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1//===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9// This is an extremely simple MachineInstr-level dead-code-elimination pass.
15#include "llvm/ADT/Statistic.h"
21#include "llvm/Pass.h"
22#include "llvm/Support/Debug.h"
25using namespace llvm;
27#define DEBUG_TYPE "dead-mi-elimination"
29STATISTIC(NumDeletes, "Number of dead instructions deleted");
31namespace {
32class DeadMachineInstructionElimImpl {
33 const MachineRegisterInfo *MRI = nullptr;
34 const TargetInstrInfo *TII = nullptr;
38 bool runImpl(MachineFunction &MF);
41 bool isDead(const MachineInstr *MI) const;
42 bool eliminateDeadMI(MachineFunction &MF);
45class DeadMachineInstructionElim : public MachineFunctionPass {
47 static char ID; // Pass identification, replacement for typeid
49 DeadMachineInstructionElim() : MachineFunctionPass(ID) {
51 }
53 bool runOnMachineFunction(MachineFunction &MF) override {
54 if (skipFunction(MF.getFunction()))
55 return false;
56 return DeadMachineInstructionElimImpl().runImpl(MF);
57 }
59 void getAnalysisUsage(AnalysisUsage &AU) const override {
60 AU.setPreservesCFG();
62 }
64} // namespace
69 if (!DeadMachineInstructionElimImpl().runImpl(MF))
73 return PA;
76char DeadMachineInstructionElim::ID = 0;
77char &llvm::DeadMachineInstructionElimID = DeadMachineInstructionElim::ID;
79INITIALIZE_PASS(DeadMachineInstructionElim, DEBUG_TYPE,
80 "Remove dead machine instructions", false, false)
82bool DeadMachineInstructionElimImpl::isDead(const MachineInstr *MI) const {
83 // Technically speaking inline asm without side effects and no defs can still
84 // be deleted. But there is so much bad inline asm code out there, we should
85 // let them be.
86 if (MI->isInlineAsm())
87 return false;
89 // Don't delete frame allocation labels.
90 if (MI->getOpcode() == TargetOpcode::LOCAL_ESCAPE)
91 return false;
93 // Don't delete instructions with side effects.
94 bool SawStore = false;
95 if (!MI->isSafeToMove(nullptr, SawStore) && !MI->isPHI())
96 return false;
98 // Examine each operand.
99 for (const MachineOperand &MO : MI->all_defs()) {
100 Register Reg = MO.getReg();
101 if (Reg.isPhysical()) {
102 // Don't delete live physreg defs, or any reserved register defs.
103 if (!LivePhysRegs.available(Reg) || MRI->isReserved(Reg))
104 return false;
105 } else {
106 if (MO.isDead()) {
107#ifndef NDEBUG
108 // Basic check on the register. All of them should be 'undef'.
109 for (auto &U : MRI->use_nodbg_operands(Reg))
110 assert(U.isUndef() && "'Undef' use on a 'dead' register is found!");
112 continue;
113 }
114 for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
115 if (&Use != MI)
116 // This def has a non-debug use. Don't delete the instruction!
117 return false;
118 }
119 }
120 }
122 // If there are no defs with uses, the instruction is dead.
123 return true;
126bool DeadMachineInstructionElimImpl::runImpl(MachineFunction &MF) {
127 MRI = &MF.getRegInfo();
129 const TargetSubtargetInfo &ST = MF.getSubtarget();
130 TII = ST.getInstrInfo();
131 LivePhysRegs.init(*ST.getRegisterInfo());
133 bool AnyChanges = eliminateDeadMI(MF);
134 while (AnyChanges && eliminateDeadMI(MF))
135 ;
136 return AnyChanges;
139bool DeadMachineInstructionElimImpl::eliminateDeadMI(MachineFunction &MF) {
140 bool AnyChanges = false;
142 // Loop over all instructions in all blocks, from bottom to top, so that it's
143 // more likely that chains of dependent but ultimately dead instructions will
144 // be cleaned up.
145 for (MachineBasicBlock *MBB : post_order(&MF)) {
148 // Now scan the instructions and delete dead ones, tracking physreg
149 // liveness as we go.
151 // If the instruction is dead, delete it!
152 if (isDead(&MI)) {
153 LLVM_DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << MI);
154 // It is possible that some DBG_VALUE instructions refer to this
155 // instruction. They will be deleted in the live debug variable
156 // analysis.
157 MI.eraseFromParent();
158 AnyChanges = true;
159 ++NumDeletes;
160 continue;
161 }
164 }
165 }
168 return AnyChanges;
unsigned const MachineRegisterInfo * MRI
aarch64 promote const
MachineBasicBlock & MBB
#define LLVM_DEBUG(X)
Definition: Debug.h:101
static bool runImpl(Function &F, const TargetLowering &TLI)
#define DEBUG_TYPE
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
A set of register units.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
Definition: Statistic.h:167
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:321
Represent the analysis usage information of a pass.
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:269
Represents analyses that only rely on functions' control flow.
Definition: Analysis.h:70
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
bool skipFunction(const Function &F) const
Optional passes call this function to check whether the pass should be skipped.
Definition: Pass.cpp:178
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:52
void clear()
Clears the set.
Definition: LivePhysRegs.h:77
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const
Returns true if register Reg and no aliasing register is in the set.
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
void init(const TargetRegisterInfo &TRI)
(re-)initializes and clears the set.
Definition: LivePhysRegs.h:70
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
A set of analyses that are preserved following a run of a transformation pass.
Definition: Analysis.h:109
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Definition: Analysis.h:115
void preserveSet()
Mark an analysis set as preserved.
Definition: Analysis.h:144
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
TargetInstrInfo - Interface to description of machine instruction set.
TargetSubtargetInfo - Generic base class for all target subtargets.
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:656
iterator_range< po_iterator< T > > post_order(const T &G)
void initializeDeadMachineInstructionElimPass(PassRegistry &)
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:419
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.