LLVM  16.0.0git
LivePhysRegs.cpp
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1 //===--- LivePhysRegs.cpp - Live Physical Register Set --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the LivePhysRegs utility for tracking liveness of
10 // physical registers across machine instructions in forward or backward order.
11 // A more detailed description can be found in the corresponding header file.
12 //
13 //===----------------------------------------------------------------------===//
14 
21 #include "llvm/Config/llvm-config.h"
22 #include "llvm/Support/Debug.h"
24 using namespace llvm;
25 
26 
27 /// Remove all registers from the set that get clobbered by the register
28 /// mask.
29 /// The clobbers set will be the list of live registers clobbered
30 /// by the regmask.
32  SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> *Clobbers) {
33  RegisterSet::iterator LRI = LiveRegs.begin();
34  while (LRI != LiveRegs.end()) {
35  if (MO.clobbersPhysReg(*LRI)) {
36  if (Clobbers)
37  Clobbers->push_back(std::make_pair(*LRI, &MO));
38  LRI = LiveRegs.erase(LRI);
39  } else
40  ++LRI;
41  }
42 }
43 
44 /// Remove defined registers and regmask kills from the set.
46  for (const MachineOperand &MOP : phys_regs_and_masks(MI)) {
47  if (MOP.isRegMask()) {
48  removeRegsInMask(MOP);
49  continue;
50  }
51 
52  if (MOP.isDef())
53  removeReg(MOP.getReg());
54  }
55 }
56 
57 /// Add uses to the set.
59  for (const MachineOperand &MOP : phys_regs_and_masks(MI)) {
60  if (!MOP.isReg() || !MOP.readsReg())
61  continue;
62  addReg(MOP.getReg());
63  }
64 }
65 
66 /// Simulates liveness when stepping backwards over an instruction(bundle):
67 /// Remove Defs, add uses. This is the recommended way of calculating liveness.
69  // Remove defined registers and regmask kills from the set.
70  removeDefs(MI);
71 
72  // Add uses to the set.
73  addUses(MI);
74 }
75 
76 /// Simulates liveness when stepping forward over an instruction(bundle): Remove
77 /// killed-uses, add defs. This is the not recommended way, because it depends
78 /// on accurate kill flags. If possible use stepBackward() instead of this
79 /// function.
81  SmallVectorImpl<std::pair<MCPhysReg, const MachineOperand*>> &Clobbers) {
82  // Remove killed registers from the set.
83  for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
84  if (O->isReg()) {
85  if (O->isDebug())
86  continue;
87  Register Reg = O->getReg();
88  if (!Reg.isPhysical())
89  continue;
90  if (O->isDef()) {
91  // Note, dead defs are still recorded. The caller should decide how to
92  // handle them.
93  Clobbers.push_back(std::make_pair(Reg, &*O));
94  } else {
95  assert(O->isUse());
96  if (O->isKill())
97  removeReg(Reg);
98  }
99  } else if (O->isRegMask()) {
100  removeRegsInMask(*O, &Clobbers);
101  }
102  }
103 
104  // Add defs to the set.
105  for (auto Reg : Clobbers) {
106  // Skip dead defs and registers clobbered by regmasks. They shouldn't
107  // be added to the set.
108  if (Reg.second->isReg() && Reg.second->isDead())
109  continue;
110  if (Reg.second->isRegMask() &&
111  MachineOperand::clobbersPhysReg(Reg.second->getRegMask(), Reg.first))
112  continue;
113  addReg(Reg.first);
114  }
115 }
116 
117 /// Print the currently live registers to OS.
119  OS << "Live Registers:";
120  if (!TRI) {
121  OS << " (uninitialized)\n";
122  return;
123  }
124 
125  if (empty()) {
126  OS << " (empty)\n";
127  return;
128  }
129 
130  for (MCPhysReg R : *this)
131  OS << " " << printReg(R, TRI);
132  OS << "\n";
133 }
134 
135 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
137  dbgs() << " " << *this;
138 }
139 #endif
140 
142  MCPhysReg Reg) const {
143  if (LiveRegs.count(Reg))
144  return false;
145  if (MRI.isReserved(Reg))
146  return false;
147  for (MCRegAliasIterator R(Reg, TRI, false); R.isValid(); ++R) {
148  if (LiveRegs.count(*R))
149  return false;
150  }
151  return true;
152 }
153 
154 /// Add live-in registers of basic block \p MBB to \p LiveRegs.
155 void LivePhysRegs::addBlockLiveIns(const MachineBasicBlock &MBB) {
156  for (const auto &LI : MBB.liveins()) {
157  MCPhysReg Reg = LI.PhysReg;
158  LaneBitmask Mask = LI.LaneMask;
160  assert(Mask.any() && "Invalid livein mask");
161  if (Mask.all() || !S.isValid()) {
162  addReg(Reg);
163  continue;
164  }
165  for (; S.isValid(); ++S) {
166  unsigned SI = S.getSubRegIndex();
167  if ((Mask & TRI->getSubRegIndexLaneMask(SI)).any())
168  addReg(S.getSubReg());
169  }
170  }
171 }
172 
173 /// Adds all callee saved registers to \p LiveRegs.
174 static void addCalleeSavedRegs(LivePhysRegs &LiveRegs,
175  const MachineFunction &MF) {
176  const MachineRegisterInfo &MRI = MF.getRegInfo();
177  for (const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); CSR && *CSR; ++CSR)
178  LiveRegs.addReg(*CSR);
179 }
180 
181 void LivePhysRegs::addPristines(const MachineFunction &MF) {
182  const MachineFrameInfo &MFI = MF.getFrameInfo();
183  if (!MFI.isCalleeSavedInfoValid())
184  return;
185  /// This function will usually be called on an empty object, handle this
186  /// as a special case.
187  if (empty()) {
188  /// Add all callee saved regs, then remove the ones that are saved and
189  /// restored.
190  addCalleeSavedRegs(*this, MF);
191  /// Remove the ones that are not saved/restored; they are pristine.
192  for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
193  removeReg(Info.getReg());
194  return;
195  }
196  /// If a callee-saved register that is not pristine is already present
197  /// in the set, we should make sure that it stays in it. Precompute the
198  /// set of pristine registers in a separate object.
199  /// Add all callee saved regs, then remove the ones that are saved+restored.
200  LivePhysRegs Pristine(*TRI);
201  addCalleeSavedRegs(Pristine, MF);
202  /// Remove the ones that are not saved/restored; they are pristine.
203  for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
204  Pristine.removeReg(Info.getReg());
205  for (MCPhysReg R : Pristine)
206  addReg(R);
207 }
208 
210  // To get the live-outs we simply merge the live-ins of all successors.
211  for (const MachineBasicBlock *Succ : MBB.successors())
212  addBlockLiveIns(*Succ);
213  if (MBB.isReturnBlock()) {
214  // Return blocks are a special case because we currently don't mark up
215  // return instructions completely: specifically, there is no explicit
216  // use for callee-saved registers. So we add all callee saved registers
217  // that are saved and restored (somewhere). This does not include
218  // callee saved registers that are unused and hence not saved and
219  // restored; they are called pristine.
220  // FIXME: PEI should add explicit markings to return instructions
221  // instead of implicitly handling them here.
222  const MachineFunction &MF = *MBB.getParent();
223  const MachineFrameInfo &MFI = MF.getFrameInfo();
224  if (MFI.isCalleeSavedInfoValid()) {
225  for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
226  if (Info.isRestored())
227  addReg(Info.getReg());
228  }
229  }
230 }
231 
233  const MachineFunction &MF = *MBB.getParent();
234  addPristines(MF);
236 }
237 
239  const MachineFunction &MF = *MBB.getParent();
240  addPristines(MF);
241  addBlockLiveIns(MBB);
242 }
243 
245  addBlockLiveIns(MBB);
246 }
247 
249  const MachineBasicBlock &MBB) {
250  const MachineFunction &MF = *MBB.getParent();
251  const MachineRegisterInfo &MRI = MF.getRegInfo();
253  LiveRegs.init(TRI);
254  LiveRegs.addLiveOutsNoPristines(MBB);
255  for (const MachineInstr &MI : llvm::reverse(MBB))
256  LiveRegs.stepBackward(MI);
257 }
258 
260  assert(MBB.livein_empty() && "Expected empty live-in list");
261  const MachineFunction &MF = *MBB.getParent();
262  const MachineRegisterInfo &MRI = MF.getRegInfo();
264  for (MCPhysReg Reg : LiveRegs) {
265  if (MRI.isReserved(Reg))
266  continue;
267  // Skip the register if we are about to add one of its super registers.
268  bool ContainsSuperReg = false;
269  for (MCSuperRegIterator SReg(Reg, &TRI); SReg.isValid(); ++SReg) {
270  if (LiveRegs.contains(*SReg) && !MRI.isReserved(*SReg)) {
271  ContainsSuperReg = true;
272  break;
273  }
274  }
275  if (ContainsSuperReg)
276  continue;
277  MBB.addLiveIn(Reg);
278  }
279 }
280 
282  const MachineFunction &MF = *MBB.getParent();
283  const MachineRegisterInfo &MRI = MF.getRegInfo();
285  const MachineFrameInfo &MFI = MF.getFrameInfo();
286 
287  // We walk through the block backwards and start with the live outs.
288  LivePhysRegs LiveRegs;
289  LiveRegs.init(TRI);
290  LiveRegs.addLiveOutsNoPristines(MBB);
291 
292  for (MachineInstr &MI : llvm::reverse(MBB)) {
293  // Recompute dead flags.
294  for (MIBundleOperands MO(MI); MO.isValid(); ++MO) {
295  if (!MO->isReg() || !MO->isDef() || MO->isDebug())
296  continue;
297 
298  Register Reg = MO->getReg();
299  if (Reg == 0)
300  continue;
301  assert(Reg.isPhysical());
302 
303  bool IsNotLive = LiveRegs.available(MRI, Reg);
304 
305  // Special-case return instructions for cases when a return is not
306  // the last instruction in the block.
307  if (MI.isReturn() && MFI.isCalleeSavedInfoValid()) {
308  for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo()) {
309  if (Info.getReg() == Reg) {
310  IsNotLive = !Info.isRestored();
311  break;
312  }
313  }
314  }
315 
316  MO->setIsDead(IsNotLive);
317  }
318 
319  // Step backward over defs.
320  LiveRegs.removeDefs(MI);
321 
322  // Recompute kill flags.
323  for (MIBundleOperands MO(MI); MO.isValid(); ++MO) {
324  if (!MO->isReg() || !MO->readsReg() || MO->isDebug())
325  continue;
326 
327  Register Reg = MO->getReg();
328  if (Reg == 0)
329  continue;
330  assert(Reg.isPhysical());
331 
332  bool IsNotLive = LiveRegs.available(MRI, Reg);
333  MO->setIsKill(IsNotLive);
334  }
335 
336  // Complete the stepbackward.
337  LiveRegs.addUses(MI);
338  }
339 }
340 
343  computeLiveIns(LiveRegs, MBB);
344  addLiveIns(MBB, LiveRegs);
345 }
llvm::LaneBitmask
Definition: LaneBitmask.h:40
llvm::SparseSet< MCPhysReg, identity< MCPhysReg > >::iterator
typename DenseT::iterator iterator
Definition: SparseSet.h:171
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
LLVM_DUMP_METHOD
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:492
llvm::LivePhysRegs::removeDefs
void removeDefs(const MachineInstr &MI)
Remove defined registers and regmask kills from the set.
Definition: LivePhysRegs.cpp:45
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::LivePhysRegs::removeReg
void removeReg(MCPhysReg Reg)
Removes a physical register, all its sub-registers, and all its super-registers from the set.
Definition: LivePhysRegs.h:91
llvm::computeLiveIns
void computeLiveIns(LivePhysRegs &LiveRegs, const MachineBasicBlock &MBB)
Computes registers live-in to MBB assuming all of its successors live-in lists are up-to-date.
Definition: LivePhysRegs.cpp:248
llvm::MCSubRegIndexIterator
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices.
Definition: MCRegisterInfo.h:610
llvm::LivePhysRegs::addReg
void addReg(MCPhysReg Reg)
Adds a physical register and all its sub-registers to the set.
Definition: LivePhysRegs.h:81
llvm::LivePhysRegs::dump
void dump() const
Dumps the currently live registers to the debug output.
Definition: LivePhysRegs.cpp:136
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::recomputeLivenessFlags
void recomputeLivenessFlags(MachineBasicBlock &MBB)
Recomputes dead and kill flags in MBB.
Definition: LivePhysRegs.cpp:281
llvm::LivePhysRegs::addLiveInsNoPristines
void addLiveInsNoPristines(const MachineBasicBlock &MBB)
Adds all live-in registers of basic block MBB but skips pristine registers.
Definition: LivePhysRegs.cpp:244
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:151
llvm::SparseSet::begin
const_iterator begin() const
Definition: SparseSet.h:174
llvm::LivePhysRegs::removeRegsInMask
void removeRegsInMask(const MachineOperand &MO, SmallVectorImpl< std::pair< MCPhysReg, const MachineOperand * >> *Clobbers=nullptr)
Removes physical registers clobbered by the regmask operand MO.
Definition: LivePhysRegs.cpp:31
llvm::LivePhysRegs
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:50
llvm::MachineBasicBlock::isReturnBlock
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
Definition: MachineBasicBlock.h:864
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
llvm::MachineBasicBlock::liveins
iterator_range< livein_iterator > liveins() const
Definition: MachineBasicBlock.h:449
llvm::addLiveIns
void addLiveIns(MachineBasicBlock &MBB, const LivePhysRegs &LiveRegs)
Adds registers contained in LiveRegs to the block live-in list of MBB.
Definition: LivePhysRegs.cpp:259
llvm::LivePhysRegs::empty
bool empty() const
Returns true if the set is empty.
Definition: LivePhysRegs.h:78
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
MachineRegisterInfo.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
addCalleeSavedRegs
static void addCalleeSavedRegs(LivePhysRegs &LiveRegs, const MachineFunction &MF)
Adds all callee saved registers to LiveRegs.
Definition: LivePhysRegs.cpp:174
llvm::TargetRegisterInfo::getSubRegIndexLaneMask
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
Definition: TargetRegisterInfo.h:380
llvm::LivePhysRegs::addLiveIns
void addLiveIns(const MachineBasicBlock &MBB)
Adds all live-in registers of basic block MBB.
Definition: LivePhysRegs.cpp:238
llvm::SparseSet::end
const_iterator end() const
Definition: SparseSet.h:175
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:930
SI
@ SI
Definition: SIInstrInfo.cpp:7966
llvm::LivePhysRegs::addLiveOuts
void addLiveOuts(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB.
Definition: LivePhysRegs.cpp:232
llvm::phys_regs_and_masks
iterator_range< filter_iterator< ConstMIBundleOperands, std::function< bool(const MachineOperand &)> > > phys_regs_and_masks(const MachineInstr &MI)
Returns an iterator range over all physical register and mask operands for MI and bundled instruction...
Definition: LiveRegUnits.h:166
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
MachineInstrBundle.h
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::MIBundleOperands
MIBundleOperands - Iterate over all operands in a bundle of machine instructions.
Definition: MachineInstrBundle.h:166
llvm::computeAndAddLiveIns
void computeAndAddLiveIns(LivePhysRegs &LiveRegs, MachineBasicBlock &MBB)
Convenience function combining computeLiveIns() and addLiveIns().
Definition: LivePhysRegs.cpp:341
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineFrameInfo::isCalleeSavedInfoValid
bool isCalleeSavedInfoValid() const
Has the callee saved info been calculated yet?
Definition: MachineFrameInfo.h:800
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:264
llvm::MachineOperand::clobbersPhysReg
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
Definition: MachineOperand.h:626
llvm::LivePhysRegs::stepBackward
void stepBackward(const MachineInstr &MI)
Simulates liveness when stepping backwards over an instruction(bundle).
Definition: LivePhysRegs.cpp:68
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::LivePhysRegs::addUses
void addUses(const MachineInstr &MI)
Add uses to the set.
Definition: LivePhysRegs.cpp:58
llvm::LivePhysRegs::available
bool available(const MachineRegisterInfo &MRI, MCPhysReg Reg) const
Returns true if register Reg and no aliasing register is in the set.
Definition: LivePhysRegs.cpp:141
llvm::MachineRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Definition: MachineRegisterInfo.cpp:623
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:21
llvm::MIBundleOperandIteratorBase::isValid
bool isValid() const
isValid - Returns true until all the operands have been visited.
Definition: MachineInstrBundle.h:136
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::LivePhysRegs::print
void print(raw_ostream &OS) const
Prints the currently live registers to OS.
Definition: LivePhysRegs.cpp:118
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:673
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:644
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:787
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:392
llvm::LivePhysRegs::init
void init(const TargetRegisterInfo &TRI)
(re-)initializes and clears the set.
Definition: LivePhysRegs.h:68
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::LivePhysRegs::stepForward
void stepForward(const MachineInstr &MI, SmallVectorImpl< std::pair< MCPhysReg, const MachineOperand * >> &Clobbers)
Simulates liveness when stepping forward over an instruction(bundle).
Definition: LivePhysRegs.cpp:80
LiveRegUnits.h
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:404
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::LivePhysRegs::addLiveOutsNoPristines
void addLiveOutsNoPristines(const MachineBasicBlock &MBB)
Adds all live-out registers of basic block MBB but skips pristine registers.
Definition: LivePhysRegs.cpp:209
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:34
uint16_t
llvm::ConstMIBundleOperands
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
Definition: MachineInstrBundle.h:185
MachineFrameInfo.h
llvm::SparseSet::count
size_type count(const KeyT &Key) const
count - Returns 1 if this set contains an element identified by Key, 0 otherwise.
Definition: SparseSet.h:240
llvm::SparseSet::erase
iterator erase(iterator I)
erase - Erases an existing element identified by a valid iterator.
Definition: SparseSet.h:288
llvm::MachineBasicBlock::livein_empty
bool livein_empty() const
Definition: MachineBasicBlock.h:448
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:106
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::reverse
auto reverse(ContainerTy &&C)
Definition: STLExtras.h:485
raw_ostream.h
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
Debug.h
llvm::MCRegAliasIterator
MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:788
LivePhysRegs.h