LLVM 17.0.0git
FunctionLoweringInfo.h
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1//===- FunctionLoweringInfo.h - Lower functions from LLVM IR ---*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements routines for translating functions from LLVM IR into
10// Machine IR.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
15#define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
16
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/IndexedMap.h"
26#include "llvm/IR/Type.h"
27#include "llvm/IR/Value.h"
29#include <cassert>
30#include <utility>
31#include <vector>
32
33namespace llvm {
34
35class Argument;
36class BasicBlock;
37class BranchProbabilityInfo;
38class LegacyDivergenceAnalysis;
39class Function;
40class Instruction;
41class MachineFunction;
42class MachineInstr;
43class MachineRegisterInfo;
44class MVT;
45class SelectionDAG;
46class TargetLowering;
47
48//===--------------------------------------------------------------------===//
49/// FunctionLoweringInfo - This contains information that is global to a
50/// function that is used when lowering a region of the function.
51///
53public:
54 const Function *Fn;
60 /// CanLowerReturn - true iff the function's return value can be lowered to
61 /// registers.
63
64 /// True if part of the CSRs will be handled via explicit copies.
66
67 /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
68 /// allocated to hold a pointer to the hidden sret parameter.
70
71 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
73
74 /// ValueMap - Since we emit code for the function a basic block at a time,
75 /// we must remember which virtual registers hold the values for
76 /// cross-basic-block values.
78
79 /// VirtReg2Value map is needed by the Divergence Analysis driven
80 /// instruction selection. It is reverted ValueMap. It is computed
81 /// in lazy style - on demand. It is used to get the Value corresponding
82 /// to the live in virtual register and is called from the
83 /// TargetLowerinInfo::isSDNodeSourceOfDivergence.
85
86 /// This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence
87 /// to get the Value corresponding to the live-in virtual register.
89
90 /// Track virtual registers created for exception pointers.
92
93 /// Helper object to track which of three possible relocation mechanisms are
94 /// used for a particular value being relocated over a statepoint.
96 enum RelocType {
97 // Value did not need to be relocated and can be used directly.
99 // Value was spilled to stack and needs filled at the gc.relocate.
101 // Value was lowered to tied def and gc.relocate should be replaced with
102 // copy from vreg.
104 // Value was lowered to tied def and gc.relocate should be replaced with
105 // SDValue kept in StatepointLoweringInfo structure. This valid for local
106 // relocates only.
109 // Payload contains either frame index of the stack slot in which the value
110 // was spilled, or virtual register which contains the re-definition.
111 union payload_t {
112 payload_t() : FI(-1) {}
113 int FI;
116 };
117
118 /// Keep track of each value which was relocated and the strategy used to
119 /// relocate that value. This information is required when visiting
120 /// gc.relocates which may appear in following blocks.
124
125 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
126 /// the entry block. This allows the allocas to be efficiently referenced
127 /// anywhere in the function.
129
130 /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
132
133 /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
134 /// function arguments that are inserted after scheduling is completed.
136
137 /// Bitvector with a bit set if corresponding argument is described in
138 /// ArgDbgValues. Using arg numbers according to Argument numbering.
140
141 /// RegFixups - Registers which need to be replaced after isel is done.
143
145
146 /// StatepointStackSlots - A list of temporary stack slots (frame indices)
147 /// used to spill values at a statepoint. We store them here to enable
148 /// reuse of the same stack slots across different statepoints in different
149 /// basic blocks.
151
152 /// MBB - The current block.
154
155 /// MBB - The current insert position inside the current block.
157
158 struct LiveOutInfo {
159 unsigned NumSignBits : 31;
160 unsigned IsValid : 1;
162
164 };
165
166 /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
167 /// for a value.
169
170 /// VisitedBBs - The set of basic blocks visited thus far by instruction
171 /// selection.
173
174 /// PHINodesToUpdate - A list of phi instructions whose operand list will
175 /// be updated after processing the current basic block.
176 /// TODO: This isn't per-function state, it's per-basic-block state. But
177 /// there's no other convenient place for it to live right now.
178 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
180
181 /// If the current MBB is a landing pad, the exception pointer and exception
182 /// selector registers are copied into these virtual registers by
183 /// SelectionDAGISel::PrepareEHLandingPad().
185
186 /// set - Initialize this FunctionLoweringInfo with the given Function
187 /// and its associated MachineFunction.
188 ///
189 void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
190
191 /// clear - Clear out all the function-specific state. This returns this
192 /// FunctionLoweringInfo to an empty state, ready to be used for a
193 /// different function.
194 void clear();
195
196 /// isExportedInst - Return true if the specified value is an instruction
197 /// exported from its block.
198 bool isExportedInst(const Value *V) const {
199 return ValueMap.count(V);
200 }
201
202 Register CreateReg(MVT VT, bool isDivergent = false);
203
204 Register CreateRegs(const Value *V);
205
206 Register CreateRegs(Type *Ty, bool isDivergent = false);
207
209 // Tokens never live in vregs.
210 if (V->getType()->isTokenTy())
211 return 0;
212 Register &R = ValueMap[V];
213 assert(R == 0 && "Already initialized this value register!");
214 assert(VirtReg2Value.empty());
215 return R = CreateRegs(V);
216 }
217
218 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
219 /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
221 if (!LiveOutRegInfo.inBounds(Reg))
222 return nullptr;
223
224 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
225 if (!LOI->IsValid)
226 return nullptr;
227
228 return LOI;
229 }
230
231 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
232 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
233 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
234 /// the larger bit width by zero extension. The bit width must be no smaller
235 /// than the LiveOutInfo's existing bit width.
236 const LiveOutInfo *GetLiveOutRegInfo(Register Reg, unsigned BitWidth);
237
238 /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
239 void AddLiveOutRegInfo(Register Reg, unsigned NumSignBits,
240 const KnownBits &Known) {
241 // Only install this information if it tells us something.
242 if (NumSignBits == 1 && Known.isUnknown())
243 return;
244
245 LiveOutRegInfo.grow(Reg);
246 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
247 LOI.NumSignBits = NumSignBits;
248 LOI.Known.One = Known.One;
249 LOI.Known.Zero = Known.Zero;
250 }
251
252 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
253 /// register based on the LiveOutInfo of its operands.
255
256 /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
257 /// called when a block is visited before all of its predecessors.
259 // PHIs with no uses have no ValueMap entry.
261 if (It == ValueMap.end())
262 return;
263
264 Register Reg = It->second;
265 if (Reg == 0)
266 return;
267
268 LiveOutRegInfo.grow(Reg);
269 LiveOutRegInfo[Reg].IsValid = false;
270 }
271
272 /// setArgumentFrameIndex - Record frame index for the byval
273 /// argument.
274 void setArgumentFrameIndex(const Argument *A, int FI);
275
276 /// getArgumentFrameIndex - Get frame index for the byval argument.
277 int getArgumentFrameIndex(const Argument *A);
278
280 const TargetRegisterClass *RC);
281
282private:
283 /// LiveOutRegInfo - Information about live out vregs.
285};
286
287} // end namespace llvm
288
289#endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
basic Basic Alias true
This file implements the BitVector class.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
This file defines the DenseMap class.
This file implements an indexed map.
unsigned Reg
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
Analysis providing branch probability information.
Implements a dense probed hash-table based set.
Definition: DenseSet.h:271
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
BranchProbabilityInfo * BPI
Register CreateRegs(const Value *V)
void clear()
clear - Clear out all the function-specific state.
DenseSet< Register > RegsWithFixups
Register DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
void setArgumentFrameIndex(const Argument *A, int FI)
setArgumentFrameIndex - Record frame index for the byval argument.
void InvalidatePHILiveOutRegInfo(const PHINode *PN)
InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be called when a block is visited b...
BitVector DescribedArgs
Bitvector with a bit set if corresponding argument is described in ArgDbgValues.
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block.
SmallPtrSet< const BasicBlock *, 4 > VisitedBBs
VisitedBBs - The set of basic blocks visited thus far by instruction selection.
DenseMap< const Instruction *, StatepointSpillMapTy > StatepointRelocationMaps
int getArgumentFrameIndex(const Argument *A)
getArgumentFrameIndex - Get frame index for the byval argument.
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
const LegacyDivergenceAnalysis * DA
bool isExportedInst(const Value *V) const
isExportedInst - Return true if the specified value is an instruction exported from its block.
void AddLiveOutRegInfo(Register Reg, unsigned NumSignBits, const KnownBits &Known)
AddLiveOutRegInfo - Adds LiveOutInfo for a register.
const LiveOutInfo * GetLiveOutRegInfo(Register Reg)
GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the register is a PHI destinat...
Register InitializeRegForValue(const Value *V)
unsigned ExceptionPointerVirtReg
If the current MBB is a landing pad, the exception pointer and exception selector registers are copie...
bool SplitCSR
True if part of the CSRs will be handled via explicit copies.
DenseMap< const Value *, Register > ValueMap
ValueMap - Since we emit code for the function a basic block at a time, we must remember which virtua...
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
SmallVector< unsigned, 50 > StatepointStackSlots
StatepointStackSlots - A list of temporary stack slots (frame indices) used to spill values at a stat...
void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG)
set - Initialize this FunctionLoweringInfo with the given Function and its associated MachineFunction...
MachineBasicBlock * MBB
MBB - The current block.
std::vector< std::pair< MachineInstr *, unsigned > > PHINodesToUpdate
PHINodesToUpdate - A list of phi instructions whose operand list will be updated after processing the...
DenseMap< const Argument *, int > ByValArgFrameIndexMap
ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
DenseMap< Register, Register > RegFixups
RegFixups - Registers which need to be replaced after isel is done.
SmallVector< MachineInstr *, 8 > ArgDbgValues
ArgDbgValues - A list of DBG_VALUE instructions created during isel for function arguments that are i...
void ComputePHILiveOutRegInfo(const PHINode *)
ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination register based on the LiveOutI...
const TargetLowering * TLI
const Value * getValueFromVirtualReg(Register Vreg)
This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence to get the Value correspondi...
DenseMap< Register, const Value * > VirtReg2Value
VirtReg2Value map is needed by the Divergence Analysis driven instruction selection.
MachineRegisterInfo * RegInfo
Register CreateReg(MVT VT, bool isDivergent=false)
CreateReg - Allocate a single virtual register for the given type.
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
DenseMap< const Value *, ISD::NodeType > PreferredExtendType
Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND) for a value.
Register getCatchPadExceptionPointerVReg(const Value *CPI, const TargetRegisterClass *RC)
DenseMap< const Value *, Register > CatchPadExceptionPointers
Track virtual registers created for exception pointers.
Machine Value Type.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1200
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isTokenTy() const
Return true if this is 'token'.
Definition: Type.h:219
See the file comment.
Definition: ValueMap.h:84
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: ValueMap.h:151
iterator find(const KeyT &Val)
Definition: ValueMap.h:155
iterator end()
Definition: ValueMap.h:135
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
@ BasicBlock
Various leaf nodes.
Definition: ISDOpcodes.h:71
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
Helper object to track which of three possible relocation mechanisms are used for a particular value ...
union llvm::FunctionLoweringInfo::StatepointRelocationRecord::payload_t payload
enum llvm::FunctionLoweringInfo::StatepointRelocationRecord::RelocType type
bool isUnknown() const
Returns true if we don't know any bits.
Definition: KnownBits.h:63