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44 #define DEBUG_TYPE "function-lowering-info"
50 if (
I->use_empty())
return false;
51 if (isa<PHINode>(
I))
return true;
53 for (
const User *U :
I->users())
54 if (cast<Instruction>(U)->
getParent() !=
BB || isa<PHINode>(U))
69 unsigned NumOfSigned = 0, NumOfUnsigned = 0;
71 if (
const auto *CI = dyn_cast<CmpInst>(U)) {
72 NumOfSigned += CI->isSigned();
73 NumOfUnsigned += CI->isUnsigned();
76 if (NumOfSigned > NumOfUnsigned)
118 CatchObjects.
insert({AI, {}}).first->second.push_back(
119 &
H.CatchObj.FrameIndex);
121 H.CatchObj.FrameIndex = INT_MAX;
136 if (
const AllocaInst *AI = dyn_cast<AllocaInst>(&
I)) {
137 Type *Ty = AI->getAllocatedType();
143 Align SpecifiedAlign = AI->getAlign();
156 if (AI->isStaticAlloca() &&
158 const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
163 if (TySize == 0) TySize = 1;
165 auto Iter = CatchObjects.
find(AI);
168 TySize, 0,
false,
true);
177 if (isa<ScalableVectorType>(Ty))
183 if (Iter != CatchObjects.
end()) {
184 for (
int *CatchObjPtr : Iter->second)
195 }
else if (
auto *Call = dyn_cast<CallBase>(&
I)) {
197 if (Call->isInlineAsm()) {
200 std::vector<TargetLowering::AsmOperandInfo> Ops =
207 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
210 if (PhysReg.first == SP)
218 if (
const auto *II = dyn_cast<IntrinsicInst>(&
I)) {
219 if (II->getIntrinsicID() == Intrinsic::vastart)
225 if (
const auto *CI = dyn_cast<CallInst>(&
I)) {
254 if (!isa<LandingPadInst>(PadInst)) {
259 if (isa<CatchSwitchInst>(PadInst)) {
261 "WinEHPrepare failed to remove PHIs from imaginary BBs");
264 if (isa<FuncletPadInst>(PadInst))
265 assert(&*
BB.begin() == PadInst &&
"WinEHPrepare failed to demote PHIs");
275 if (
BB.hasAddressTaken())
289 if (PN.getType()->isEmptyTy())
294 assert(PHIReg &&
"PHI node does not have an assigned virtual register!");
298 for (
EVT VT : ValueVTs) {
301 for (
unsigned i = 0;
i != NumRegisters; ++
i)
303 PHIReg += NumRegisters;
336 const auto *Src = KV.first.get<
const BasicBlock *>();
337 const auto *Dest = KV.second.get<
const BasicBlock *>();
343 const auto *Dest = KV.first.get<
const BasicBlock *>();
345 for (
const auto P : KV.second)
361 LiveOutRegInfo.clear();
398 for (
unsigned i = 0;
i != NumRegs; ++
i) {
400 if (!FirstReg) FirstReg = R;
418 if (!LiveOutRegInfo.inBounds(
Reg))
442 assert(ValueVTs.size() == 1 &&
443 "PHIs with non-vector integer types should have a single VT.");
444 EVT IntVT = ValueVTs[0];
454 LiveOutRegInfo.grow(DestReg);
458 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
470 "CopyToReg node was created.");
486 "Masks should have the same bit width as the type.");
490 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
505 "its CopyToReg node was created.");
536 LLVM_DEBUG(
dbgs() <<
"Argument does not have assigned frame index!\n");
547 assert(VReg &&
"null vreg in exception pointer table!");
558 P.first->getType(), ValueVTs);
559 unsigned Reg =
P.second;
560 for (
EVT VT : ValueVTs) {
562 for (
unsigned i = 0,
e = NumRegisters;
i !=
e; ++
i)
KnownBits anyext(unsigned BitWidth) const
Return known bits for an "any" extension of the value we're tracking, where we don't know anything ab...
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
This class represents an incoming formal argument to a Function.
unsigned getNumSignBits() const
Computes the number of leading bits of this APInt that are equal to its sign bit.
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block.
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG)
set - Initialize this FunctionLoweringInfo with the given Function and its associated MachineFunction...
Information about stack frame layout on the target.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
SmallVector< CxxUnwindMapEntry, 4 > CxxUnwindMap
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
virtual const TargetInstrInfo * getInstrInfo() const
SmallVector< ClrEHUnwindMapEntry, 4 > ClrEHUnwindMap
void clear()
clear - Removes all bits from the bitvector.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
DenseSet< Register > RegsWithFixups
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
SmallVector< WinEHTryBlockMapEntry, 4 > TryBlockMap
The instances of the Type class are immutable: once they are created, they are never changed.
unsigned getBitWidth() const
Return the number of bits in the APInt.
MachineBasicBlock * MBB
MBB - The current block.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo,...
BitVector DescribedArgs
Bitvector with a bit set if corresponding argument is described in ArgDbgValues.
void setHasEHFunclets(bool V)
int CreateVariableSizedObject(Align Alignment, const AllocaInst *Alloca)
Notify the MachineFrameInfo object that a variable sized object has been created.
virtual TargetStackID::Value getStackIDForScalableVectors() const
Returns the StackID that scalable vectors should be associated with.
unsigned const TargetRegisterInfo * TRI
T get() const
Returns the value of the specified pointer type.
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
const Value * getValueFromVirtualReg(Register Vreg)
This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence to get the Value correspondi...
virtual bool needsFixedCatchObjects() const
LLVM Basic Block Representation.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
This is the shared class of boolean and integer constants.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
SmallVector< unsigned, 50 > StatepointStackSlots
StatepointStackSlots - A list of temporary stack slots (frame indices) used to spill values at a stat...
TargetInstrInfo - Interface to description of machine instruction set.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
SmallVector< MachineInstr *, 8 > ArgDbgValues
ArgDbgValues - A list of DBG_VALUE instructions created during isel for function arguments that are i...
const LegacyDivergenceAnalysis * getDivergenceAnalysis() const
void ComputePHILiveOutRegInfo(const PHINode *)
ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination register based on the LiveOutI...
const LiveOutInfo * GetLiveOutRegInfo(Register Reg)
GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the register is a PHI destinat...
bool isVectorTy() const
True if this is an instance of VectorType.
const HexagonInstrInfo * TII
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
void setHasOpaqueSPAdjustment(bool B)
bool isStackRealignable() const
isStackRealignable - This method returns whether the stack can be realigned.
bool hasPersonalityFn() const
Check whether this function has a personality function.
static bool isUsedOutsideOfDefiningBlock(const Instruction *I)
isUsedOutsideOfDefiningBlock - Return true if this instruction is used by PHI nodes or outside of the...
const WasmEHFuncInfo * getWasmEHFuncInfo() const
getWasmEHFuncInfo - Return information about how the current function uses Wasm exception handling.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Register InitializeRegForValue(const Value *V)
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
unsigned getNumIncomingValues() const
Return the number of incoming edges.
virtual bool requiresUniformRegister(MachineFunction &MF, const Value *) const
Allows target to decide about the register class of the specific value that is live outside the defin...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
AttributeList getAttributes() const
Return the attribute list for this Function.
bool isIntegerTy() const
True if this is an instance of IntegerType.
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const TargetLowering * TLI
void push_back(MachineBasicBlock *MBB)
void setHasMustTailInVarArgFunc(bool B)
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Type * getReturnType() const
Returns the type of the ret val.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Module * getParent()
Get the module that this global value is contained inside of...
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
SmallVector< WinEHHandlerType, 1 > HandlerArray
This contains information for each constraint that we are lowering.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
iterator find(const_arg_type_t< KeyT > Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setHasAddressTaken()
Set this block to reflect that it potentially is the target of an indirect branch.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
DenseMap< const Value *, Register > CatchPadExceptionPointers
Track virtual registers created for exception pointers.
Register CreateRegs(const Value *V)
DenseMap< BBOrMBB, BBOrMBB > SrcToUnwindDest
DenseMap< const Argument *, int > ByValArgFrameIndexMap
ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
Class for arbitrary precision integers.
void setStackID(int ObjectIdx, uint8_t ID)
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const
Return the number of registers that this ValueType will eventually require.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setHasEHScopes(bool V)
Type * getType() const
All values are typed, get the type of this value.
static const Function * getParent(const Value *V)
Similar to CxxUnwindMapEntry, but supports SEH filters.
LLVMContext & getContext() const
All values hold a context through their type.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
bool isDivergent(const Value *V) const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
DenseMap< const Instruction *, StatepointSpillMapTy > StatepointRelocationMaps
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
unsigned const MachineRegisterInfo * MRI
MBBOrBasicBlock Handler
Holds the __except or __finally basic block.
Wrapper class representing virtual and physical registers.
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
SmallVector< SEHUnwindMapEntry, 4 > SEHUnwindMap
SmallPtrSet< const BasicBlock *, 4 > VisitedBBs
VisitedBBs - The set of basic blocks visited thus far by instruction selection.
virtual const TargetFrameLowering * getFrameLowering() const
const WinEHFuncInfo * getWinEHFuncInfo() const
getWinEHFuncInfo - Return information about how the current function uses Windows exception handling.
void clear()
clear - Clear out all the function-specific state.
constexpr unsigned BitWidth
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
void setArgumentFrameIndex(const Argument *A, int FI)
setArgumentFrameIndex - Record frame index for the byval argument.
DenseMap< Register, Register > RegFixups
RegFixups - Registers which need to be replaced after isel is done.
Constant * getPersonalityFn() const
Get the personality function associated with this function.
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
virtual const TargetLowering * getTargetLowering() const
DenseMap< BBOrMBB, SmallPtrSet< BBOrMBB, 4 > > UnwindDestToSrcs
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static KnownBits commonBits(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits common to LHS and RHS.
Align max(MaybeAlign Lhs, Align Rhs)
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
DenseMap< Register, const Value * > VirtReg2Value
VirtReg2Value map is needed by the Divergence Analysis driven instruction selection.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
static KnownBits makeConstant(const APInt &C)
Create known bits from a known constant.
ScalarTy getKnownMinSize() const
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
unsigned getBitWidth() const
Get the bit width of this value.
an instruction to allocate memory on the stack
static ISD::NodeType getPreferredExtendForValue(const Value *V)
void calculateSEHStateNumbers(const Function *ParentFn, WinEHFuncInfo &FuncInfo)
@ SIGN_EXTEND
Conversion operators.
int getArgumentFrameIndex(const Argument *A)
getArgumentFrameIndex - Get frame index for the byval argument.
void calculateWinCXXEHStateNumbers(const Function *ParentFn, WinEHFuncInfo &FuncInfo)
Analyze the IR in ParentFn and it's handlers to build WinEHFuncInfo, which describes the state number...
const LegacyDivergenceAnalysis * DA
LLVM Value Representation.
void setHasVAStart(bool B)
iterator_range< user_iterator > users()
Register CreateReg(MVT VT, bool isDivergent=false)
CreateReg - Allocate a single virtual register for the given type.
MachineRegisterInfo * RegInfo
void calculateWasmEHInfo(const Function *F, WasmEHFuncInfo &EHInfo)
bool isFuncletEHPersonality(EHPersonality Pers)
Returns true if this is a personality function that invokes handler funclets (which must return to it...
Register getCatchPadExceptionPointerVReg(const Value *CPI, const TargetRegisterClass *RC)
DenseMap< const Value *, ISD::NodeType > PreferredExtendType
Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND) for a value.
void calculateClrEHStateNumbers(const Function *Fn, WinEHFuncInfo &FuncInfo)
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...