LLVM 19.0.0git
FunctionLoweringInfo.cpp
Go to the documentation of this file.
1//===-- FunctionLoweringInfo.cpp ------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements routines for translating functions from LLVM IR into
10// Machine IR.
11//
12//===----------------------------------------------------------------------===//
13
15#include "llvm/ADT/APInt.h"
29#include "llvm/IR/DataLayout.h"
31#include "llvm/IR/Function.h"
34#include "llvm/IR/Module.h"
35#include "llvm/Support/Debug.h"
38#include <algorithm>
39using namespace llvm;
40
41#define DEBUG_TYPE "function-lowering-info"
42
43/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
44/// PHI nodes or outside of the basic block that defines it, or used by a
45/// switch or atomic instruction, which may expand to multiple basic blocks.
47 if (I->use_empty()) return false;
48 if (isa<PHINode>(I)) return true;
49 const BasicBlock *BB = I->getParent();
50 for (const User *U : I->users())
51 if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
52 return true;
53
54 return false;
55}
56
58 // For the users of the source value being used for compare instruction, if
59 // the number of signed predicate is greater than unsigned predicate, we
60 // prefer to use SIGN_EXTEND.
61 //
62 // With this optimization, we would be able to reduce some redundant sign or
63 // zero extension instruction, and eventually more machine CSE opportunities
64 // can be exposed.
65 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
66 unsigned NumOfSigned = 0, NumOfUnsigned = 0;
67 for (const Use &U : I->uses()) {
68 if (const auto *CI = dyn_cast<CmpInst>(U.getUser())) {
69 NumOfSigned += CI->isSigned();
70 NumOfUnsigned += CI->isUnsigned();
71 }
72 if (const auto *CallI = dyn_cast<CallBase>(U.getUser())) {
73 if (!CallI->isArgOperand(&U))
74 continue;
75 unsigned ArgNo = CallI->getArgOperandNo(&U);
76 NumOfUnsigned += CallI->paramHasAttr(ArgNo, Attribute::ZExt);
77 NumOfSigned += CallI->paramHasAttr(ArgNo, Attribute::SExt);
78 }
79 }
80 if (NumOfSigned > NumOfUnsigned)
81 ExtendKind = ISD::SIGN_EXTEND;
82
83 return ExtendKind;
84}
85
87 SelectionDAG *DAG) {
88 Fn = &fn;
89 MF = &mf;
91 RegInfo = &MF->getRegInfo();
93 UA = DAG->getUniformityInfo();
94
95 // Check whether the function can return without sret-demotion.
98
100 mf.getDataLayout());
102 TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext());
103
104 // If this personality uses funclets, we need to do a bit more work.
107 Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr);
108 if (isFuncletEHPersonality(Personality)) {
109 // Calculate state numbers if we haven't already.
110 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
111 if (Personality == EHPersonality::MSVC_CXX)
113 else if (isAsynchronousEHPersonality(Personality))
114 calculateSEHStateNumbers(&fn, EHInfo);
115 else if (Personality == EHPersonality::CoreCLR)
116 calculateClrEHStateNumbers(&fn, EHInfo);
117
118 // Map all BB references in the WinEH data to MBBs.
119 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
120 for (WinEHHandlerType &H : TBME.HandlerArray) {
121 if (const AllocaInst *AI = H.CatchObj.Alloca)
122 CatchObjects.insert({AI, {}}).first->second.push_back(
123 &H.CatchObj.FrameIndex);
124 else
125 H.CatchObj.FrameIndex = INT_MAX;
126 }
127 }
128 }
129
130 // Initialize the mapping of values to registers. This is only set up for
131 // instruction values that are used outside of the block that defines
132 // them.
133 const Align StackAlign = TFI->getStackAlign();
134 for (const BasicBlock &BB : *Fn) {
135 for (const Instruction &I : BB) {
136 if (const AllocaInst *AI = dyn_cast<AllocaInst>(&I)) {
137 Type *Ty = AI->getAllocatedType();
138 Align Alignment = AI->getAlign();
139
140 // Static allocas can be folded into the initial stack frame
141 // adjustment. For targets that don't realign the stack, don't
142 // do this if there is an extra alignment requirement.
143 if (AI->isStaticAlloca() &&
144 (TFI->isStackRealignable() || (Alignment <= StackAlign))) {
145 const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
146 uint64_t TySize =
148
149 TySize *= CUI->getZExtValue(); // Get total allocated size.
150 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
151 int FrameIndex = INT_MAX;
152 auto Iter = CatchObjects.find(AI);
153 if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) {
154 FrameIndex = MF->getFrameInfo().CreateFixedObject(
155 TySize, 0, /*IsImmutable=*/false, /*isAliased=*/true);
156 MF->getFrameInfo().setObjectAlignment(FrameIndex, Alignment);
157 } else {
158 FrameIndex = MF->getFrameInfo().CreateStackObject(TySize, Alignment,
159 false, AI);
160 }
161
162 // Scalable vectors and structures that contain scalable vectors may
163 // need a special StackID to distinguish them from other (fixed size)
164 // stack objects.
165 if (Ty->isScalableTy())
166 MF->getFrameInfo().setStackID(FrameIndex,
168
169 StaticAllocaMap[AI] = FrameIndex;
170 // Update the catch handler information.
171 if (Iter != CatchObjects.end()) {
172 for (int *CatchObjPtr : Iter->second)
173 *CatchObjPtr = FrameIndex;
174 }
175 } else {
176 // FIXME: Overaligned static allocas should be grouped into
177 // a single dynamic allocation instead of using a separate
178 // stack allocation for each one.
179 // Inform the Frame Information that we have variable-sized objects.
181 Alignment <= StackAlign ? Align(1) : Alignment, AI);
182 }
183 } else if (auto *Call = dyn_cast<CallBase>(&I)) {
184 // Look for inline asm that clobbers the SP register.
185 if (Call->isInlineAsm()) {
188 std::vector<TargetLowering::AsmOperandInfo> Ops =
190 *Call);
192 if (Op.Type == InlineAsm::isClobber) {
193 // Clobbers don't have SDValue operands, hence SDValue().
195 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
196 TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
197 Op.ConstraintVT);
198 if (PhysReg.first == SP)
200 }
201 }
202 }
203 // Look for calls to the @llvm.va_start intrinsic. We can omit some
204 // prologue boilerplate for variadic functions that don't examine their
205 // arguments.
206 if (const auto *II = dyn_cast<IntrinsicInst>(&I)) {
207 if (II->getIntrinsicID() == Intrinsic::vastart)
209 }
210
211 // If we have a musttail call in a variadic function, we need to ensure
212 // we forward implicit register parameters.
213 if (const auto *CI = dyn_cast<CallInst>(&I)) {
214 if (CI->isMustTailCall() && Fn->isVarArg())
216 }
217
218 // Determine if there is a call to setjmp in the machine function.
219 if (Call->hasFnAttr(Attribute::ReturnsTwice))
221 }
222
223 // Mark values used outside their block as exported, by allocating
224 // a virtual register for them.
226 if (!isa<AllocaInst>(I) || !StaticAllocaMap.count(cast<AllocaInst>(&I)))
228
229 // Decide the preferred extend type for a value. This iterates over all
230 // users and therefore isn't cheap, so don't do this at O0.
233 }
234 }
235
236 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
237 // also creates the initial PHI MachineInstrs, though none of the input
238 // operands are populated.
239 for (const BasicBlock &BB : *Fn) {
240 // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks
241 // are really data, and no instructions can live here.
242 if (BB.isEHPad()) {
243 const Instruction *PadInst = BB.getFirstNonPHI();
244 // If this is a non-landingpad EH pad, mark this function as using
245 // funclets.
246 // FIXME: SEH catchpads do not create EH scope/funclets, so we could avoid
247 // setting this in such cases in order to improve frame layout.
248 if (!isa<LandingPadInst>(PadInst)) {
249 MF->setHasEHScopes(true);
250 MF->setHasEHFunclets(true);
252 }
253 if (isa<CatchSwitchInst>(PadInst)) {
254 assert(&*BB.begin() == PadInst &&
255 "WinEHPrepare failed to remove PHIs from imaginary BBs");
256 continue;
257 }
258 if (isa<FuncletPadInst>(PadInst) &&
259 Personality != EHPersonality::Wasm_CXX)
260 assert(&*BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs");
261 }
262
264 MBBMap[&BB] = MBB;
265 MF->push_back(MBB);
266
267 // Transfer the address-taken flag. This is necessary because there could
268 // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
269 // the first one should be marked.
270 if (BB.hasAddressTaken())
271 MBB->setAddressTakenIRBlock(const_cast<BasicBlock *>(&BB));
272
273 // Mark landing pad blocks.
274 if (BB.isEHPad())
275 MBB->setIsEHPad();
276
277 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
278 // appropriate.
279 for (const PHINode &PN : BB.phis()) {
280 if (PN.use_empty())
281 continue;
282
283 // Skip empty types
284 if (PN.getType()->isEmptyTy())
285 continue;
286
287 DebugLoc DL = PN.getDebugLoc();
288 unsigned PHIReg = ValueMap[&PN];
289 assert(PHIReg && "PHI node does not have an assigned virtual register!");
290
291 SmallVector<EVT, 4> ValueVTs;
292 ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs);
293 for (EVT VT : ValueVTs) {
294 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
296 for (unsigned i = 0; i != NumRegisters; ++i)
297 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
298 PHIReg += NumRegisters;
299 }
300 }
301 }
302
303 if (isFuncletEHPersonality(Personality)) {
304 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
305
306 // Map all BB references in the WinEH data to MBBs.
307 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
308 for (WinEHHandlerType &H : TBME.HandlerArray) {
309 if (H.Handler)
310 H.Handler = MBBMap[cast<const BasicBlock *>(H.Handler)];
311 }
312 }
313 for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap)
314 if (UME.Cleanup)
315 UME.Cleanup = MBBMap[cast<const BasicBlock *>(UME.Cleanup)];
316 for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) {
317 const auto *BB = cast<const BasicBlock *>(UME.Handler);
318 UME.Handler = MBBMap[BB];
319 }
320 for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) {
321 const auto *BB = cast<const BasicBlock *>(CME.Handler);
322 CME.Handler = MBBMap[BB];
323 }
324 } else if (Personality == EHPersonality::Wasm_CXX) {
325 WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
326 calculateWasmEHInfo(&fn, EHInfo);
327
328 // Map all BB references in the Wasm EH data to MBBs.
329 DenseMap<BBOrMBB, BBOrMBB> SrcToUnwindDest;
330 for (auto &KV : EHInfo.SrcToUnwindDest) {
331 const auto *Src = cast<const BasicBlock *>(KV.first);
332 const auto *Dest = cast<const BasicBlock *>(KV.second);
333 SrcToUnwindDest[MBBMap[Src]] = MBBMap[Dest];
334 }
335 EHInfo.SrcToUnwindDest = std::move(SrcToUnwindDest);
337 for (auto &KV : EHInfo.UnwindDestToSrcs) {
338 const auto *Dest = cast<const BasicBlock *>(KV.first);
339 UnwindDestToSrcs[MBBMap[Dest]] = SmallPtrSet<BBOrMBB, 4>();
340 for (const auto P : KV.second)
341 UnwindDestToSrcs[MBBMap[Dest]].insert(
342 MBBMap[cast<const BasicBlock *>(P)]);
343 }
344 EHInfo.UnwindDestToSrcs = std::move(UnwindDestToSrcs);
345 }
346}
347
348/// clear - Clear out all the function-specific state. This returns this
349/// FunctionLoweringInfo to an empty state, ready to be used for a
350/// different function.
352 MBBMap.clear();
353 ValueMap.clear();
354 VirtReg2Value.clear();
355 StaticAllocaMap.clear();
356 LiveOutRegInfo.clear();
357 VisitedBBs.clear();
358 ArgDbgValues.clear();
360 ByValArgFrameIndexMap.clear();
361 RegFixups.clear();
365 PreferredExtendType.clear();
368}
369
370/// CreateReg - Allocate a single virtual register for the given type.
372 return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT, isDivergent));
373}
374
375/// CreateRegs - Allocate the appropriate number of virtual registers of
376/// the correctly promoted or expanded types. Assign these registers
377/// consecutive vreg numbers and return the first assigned number.
378///
379/// In the case that the given value has struct or array type, this function
380/// will assign registers for each member or element.
381///
383 SmallVector<EVT, 4> ValueVTs;
384 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
385
386 Register FirstReg;
387 for (EVT ValueVT : ValueVTs) {
388 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
389
390 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
391 for (unsigned i = 0; i != NumRegs; ++i) {
392 Register R = CreateReg(RegisterVT, isDivergent);
393 if (!FirstReg) FirstReg = R;
394 }
395 }
396 return FirstReg;
397}
398
400 return CreateRegs(V->getType(), UA && UA->isDivergent(V) &&
402}
403
405 // Tokens live in vregs only when used for convergence control.
406 if (V->getType()->isTokenTy() && !isa<ConvergenceControlInst>(V))
407 return 0;
408 Register &R = ValueMap[V];
409 assert(R == Register() && "Already initialized this value register!");
410 assert(VirtReg2Value.empty());
411 return R = CreateRegs(V);
412}
413
414/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
415/// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
416/// the register's LiveOutInfo is for a smaller bit width, it is extended to
417/// the larger bit width by zero extension. The bit width must be no smaller
418/// than the LiveOutInfo's existing bit width.
421 if (!LiveOutRegInfo.inBounds(Reg))
422 return nullptr;
423
424 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
425 if (!LOI->IsValid)
426 return nullptr;
427
428 if (BitWidth > LOI->Known.getBitWidth()) {
429 LOI->NumSignBits = 1;
430 LOI->Known = LOI->Known.anyext(BitWidth);
431 }
432
433 return LOI;
434}
435
436/// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
437/// register based on the LiveOutInfo of its operands.
439 Type *Ty = PN->getType();
440 if (!Ty->isIntegerTy() || Ty->isVectorTy())
441 return;
442
443 SmallVector<EVT, 1> ValueVTs;
444 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
445 assert(ValueVTs.size() == 1 &&
446 "PHIs with non-vector integer types should have a single VT.");
447 EVT IntVT = ValueVTs[0];
448
449 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
450 return;
451 IntVT = TLI->getRegisterType(PN->getContext(), IntVT);
452 unsigned BitWidth = IntVT.getSizeInBits();
453
454 auto It = ValueMap.find(PN);
455 if (It == ValueMap.end())
456 return;
457
458 Register DestReg = It->second;
459 if (DestReg == 0)
460 return;
461 assert(DestReg.isVirtual() && "Expected a virtual reg");
462 LiveOutRegInfo.grow(DestReg);
463 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
464
465 Value *V = PN->getIncomingValue(0);
466 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
467 DestLOI.NumSignBits = 1;
468 DestLOI.Known = KnownBits(BitWidth);
469 return;
470 }
471
472 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
473 APInt Val;
474 if (TLI->signExtendConstant(CI))
475 Val = CI->getValue().sext(BitWidth);
476 else
477 Val = CI->getValue().zext(BitWidth);
478 DestLOI.NumSignBits = Val.getNumSignBits();
479 DestLOI.Known = KnownBits::makeConstant(Val);
480 } else {
481 assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
482 "CopyToReg node was created.");
483 Register SrcReg = ValueMap[V];
484 if (!SrcReg.isVirtual()) {
485 DestLOI.IsValid = false;
486 return;
487 }
488 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
489 if (!SrcLOI) {
490 DestLOI.IsValid = false;
491 return;
492 }
493 DestLOI = *SrcLOI;
494 }
495
496 assert(DestLOI.Known.Zero.getBitWidth() == BitWidth &&
497 DestLOI.Known.One.getBitWidth() == BitWidth &&
498 "Masks should have the same bit width as the type.");
499
500 for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
501 Value *V = PN->getIncomingValue(i);
502 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
503 DestLOI.NumSignBits = 1;
504 DestLOI.Known = KnownBits(BitWidth);
505 return;
506 }
507
508 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
509 APInt Val;
510 if (TLI->signExtendConstant(CI))
511 Val = CI->getValue().sext(BitWidth);
512 else
513 Val = CI->getValue().zext(BitWidth);
514 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
515 DestLOI.Known.Zero &= ~Val;
516 DestLOI.Known.One &= Val;
517 continue;
518 }
519
520 assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
521 "its CopyToReg node was created.");
522 Register SrcReg = ValueMap[V];
523 if (!SrcReg.isVirtual()) {
524 DestLOI.IsValid = false;
525 return;
526 }
527 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
528 if (!SrcLOI) {
529 DestLOI.IsValid = false;
530 return;
531 }
532 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
533 DestLOI.Known = DestLOI.Known.intersectWith(SrcLOI->Known);
534 }
535}
536
537/// setArgumentFrameIndex - Record frame index for the byval
538/// argument. This overrides previous frame index entry for this argument,
539/// if any.
541 int FI) {
543}
544
545/// getArgumentFrameIndex - Get frame index for the byval argument.
546/// If the argument does not have any assigned frame index then 0 is
547/// returned.
549 auto I = ByValArgFrameIndexMap.find(A);
550 if (I != ByValArgFrameIndexMap.end())
551 return I->second;
552 LLVM_DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
553 return INT_MAX;
554}
555
557 const Value *CPI, const TargetRegisterClass *RC) {
559 auto I = CatchPadExceptionPointers.insert({CPI, 0});
560 Register &VReg = I.first->second;
561 if (I.second)
562 VReg = MRI.createVirtualRegister(RC);
563 assert(VReg && "null vreg in exception pointer table!");
564 return VReg;
565}
566
567const Value *
569 if (VirtReg2Value.empty()) {
570 SmallVector<EVT, 4> ValueVTs;
571 for (auto &P : ValueMap) {
572 ValueVTs.clear();
574 P.first->getType(), ValueVTs);
575 unsigned Reg = P.second;
576 for (EVT VT : ValueVTs) {
577 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
578 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
579 VirtReg2Value[Reg++] = P.first;
580 }
581 }
582 }
583 return VirtReg2Value.lookup(Vreg);
584}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements a class to represent arbitrary precision integral constant values and operations...
static const Function * getParent(const Value *V)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
#define LLVM_DEBUG(X)
Definition: Debug.h:101
static ISD::NodeType getPreferredExtendForValue(const Instruction *I)
static bool isUsedOutsideOfDefiningBlock(const Instruction *I)
isUsedOutsideOfDefiningBlock - Return true if this instruction is used by PHI nodes or outside of the...
const HexagonInstrInfo * TII
#define I(x, y, z)
Definition: MD5.cpp:58
#define H(x, y, z)
Definition: MD5.cpp:57
unsigned const TargetRegisterInfo * TRI
Module.h This file contains the declarations for the Module class.
uint64_t IntrinsicInst * II
#define P(N)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file describes how to lower LLVM code to machine code.
LLVM IR instance of the generic uniformity analysis.
Class for arbitrary precision integers.
Definition: APInt.h:77
APInt zext(unsigned width) const
Zero extend to a new width.
Definition: APInt.cpp:981
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1447
unsigned getNumSignBits() const
Computes the number of leading bits of this APInt that are equal to its sign bit.
Definition: APInt.h:1586
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:954
an instruction to allocate memory on the stack
Definition: Instructions.h:60
This class represents an incoming formal argument to a Function.
Definition: Argument.h:31
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
void clear()
clear - Removes all bits from the bitvector.
Definition: BitVector.h:335
This is the shared class of boolean and integer constants.
Definition: Constants.h:81
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:155
This class represents an Operation in the Expression.
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:504
A debug info location.
Definition: DebugLoc.h:33
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:155
iterator end()
Definition: DenseMap.h:84
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:220
Register CreateRegs(const Value *V)
SmallPtrSet< const DbgVariableRecord *, 8 > PreprocessedDVRDeclares
void clear()
clear - Clear out all the function-specific state.
DenseSet< Register > RegsWithFixups
void setArgumentFrameIndex(const Argument *A, int FI)
setArgumentFrameIndex - Record frame index for the byval argument.
BitVector DescribedArgs
Bitvector with a bit set if corresponding argument is described in ArgDbgValues.
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block.
const UniformityInfo * UA
SmallPtrSet< const BasicBlock *, 4 > VisitedBBs
VisitedBBs - The set of basic blocks visited thus far by instruction selection.
DenseMap< const Instruction *, StatepointSpillMapTy > StatepointRelocationMaps
int getArgumentFrameIndex(const Argument *A)
getArgumentFrameIndex - Get frame index for the byval argument.
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
const LiveOutInfo * GetLiveOutRegInfo(Register Reg)
GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the register is a PHI destinat...
Register InitializeRegForValue(const Value *V)
SmallPtrSet< const DbgDeclareInst *, 8 > PreprocessedDbgDeclares
Collection of dbg.declare instructions handled after argument lowering and before ISel proper.
SmallVector< unsigned, 50 > StatepointStackSlots
StatepointStackSlots - A list of temporary stack slots (frame indices) used to spill values at a stat...
void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG)
set - Initialize this FunctionLoweringInfo with the given Function and its associated MachineFunction...
MachineBasicBlock * MBB
MBB - The current block.
DenseMap< const Argument *, int > ByValArgFrameIndexMap
ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
DenseMap< Register, Register > RegFixups
RegFixups - Registers which need to be replaced after isel is done.
SmallVector< MachineInstr *, 8 > ArgDbgValues
ArgDbgValues - A list of DBG_VALUE instructions created during isel for function arguments that are i...
void ComputePHILiveOutRegInfo(const PHINode *)
ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination register based on the LiveOutI...
const TargetLowering * TLI
const Value * getValueFromVirtualReg(Register Vreg)
This method is called from TargetLowerinInfo::isSDNodeSourceOfDivergence to get the Value correspondi...
DenseMap< Register, const Value * > VirtReg2Value
VirtReg2Value map is needed by the Divergence Analysis driven instruction selection.
MachineRegisterInfo * RegInfo
Register CreateReg(MVT VT, bool isDivergent=false)
CreateReg - Allocate a single virtual register for the given type.
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
DenseMap< const Value *, ISD::NodeType > PreferredExtendType
Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND) for a value.
Register getCatchPadExceptionPointerVReg(const Value *CPI, const TargetRegisterClass *RC)
DenseMap< const Value *, Register > CatchPadExceptionPointers
Track virtual registers created for exception pointers.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:264
bool hasPersonalityFn() const
Check whether this function has a personality function.
Definition: Function.h:858
Constant * getPersonalityFn() const
Get the personality function associated with this function.
Definition: Function.cpp:1922
AttributeList getAttributes() const
Return the attribute list for this Function.
Definition: Function.h:340
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:356
Type * getReturnType() const
Returns the type of the ret val.
Definition: Function.h:207
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:215
bool isDivergent(ConstValueRefT V) const
Whether V is divergent at its definition.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:655
Machine Value Type.
void setAddressTakenIRBlock(BasicBlock *BB)
Set this block to reflect that it corresponds to an IR-level basic block with a BlockAddress.
void setIsEHPad(bool V=true)
Indicates the block is a landing pad.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setStackID(int ObjectIdx, uint8_t ID)
void setHasOpaqueSPAdjustment(bool B)
int CreateVariableSizedObject(Align Alignment, const AllocaInst *Alloca)
Notify the MachineFrameInfo object that a variable sized object has been created.
void setHasMustTailInVarArgFunc(bool B)
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
const WinEHFuncInfo * getWinEHFuncInfo() const
getWinEHFuncInfo - Return information about how the current function uses Windows exception handling.
void setHasEHFunclets(bool V)
void setExposesReturnsTwice(bool B)
setCallsSetJmp - Set a flag that indicates if there's a call to a "returns twice" function.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void push_back(MachineBasicBlock *MBB)
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
const WasmEHFuncInfo * getWasmEHFuncInfo() const
getWasmEHFuncInfo - Return information about how the current function uses Wasm exception handling.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Definition: Module.h:293
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
unsigned getNumIncomingValues() const
Return the number of incoming edges.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:227
const UniformityInfo * getUniformityInfo() const
Definition: SelectionDAG.h:495
CodeGenOptLevel getOptLevel() const
Definition: SelectionDAG.h:485
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:427
size_t size() const
Definition: SmallVector.h:91
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
Information about stack frame layout on the target.
bool isStackRealignable() const
isStackRealignable - This method returns whether the stack can be realigned.
virtual TargetStackID::Value getStackIDForScalableVectors() const
Returns the StackID that scalable vectors should be associated with.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
virtual bool requiresUniformRegister(MachineFunction &MF, const Value *) const
Allows target to decide about the register class of the specific value that is live outside the defin...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
virtual bool needsFixedCatchObjects() const
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
virtual bool signExtendConstant(const ConstantInt *C) const
Return true if this constant should be sign extended when promoting to a larger type.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo,...
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetInstrInfo * getInstrInfo() const
virtual const TargetLowering * getTargetLowering() const
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:265
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
bool isScalableTy() const
Return true if this is a type whose size is a known multiple of vscale.
bool isIntegerTy() const
True if this is an instance of IntegerType.
Definition: Type.h:228
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
See the file comment.
Definition: ValueMap.h:84
size_type count(const KeyT &Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: ValueMap.h:151
void clear()
Definition: ValueMap.h:145
iterator find(const KeyT &Val)
Definition: ValueMap.h:155
iterator end()
Definition: ValueMap.h:135
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
LLVMContext & getContext() const
All values hold a context through their type.
Definition: Value.cpp:1074
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition: TypeSize.h:168
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:785
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:776
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void calculateWinCXXEHStateNumbers(const Function *ParentFn, WinEHFuncInfo &FuncInfo)
Analyze the IR in ParentFn and it's handlers to build WinEHFuncInfo, which describes the state number...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
bool isFuncletEHPersonality(EHPersonality Pers)
Returns true if this is a personality function that invokes handler funclets (which must return to it...
void calculateSEHStateNumbers(const Function *ParentFn, WinEHFuncInfo &FuncInfo)
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:79
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:191
void calculateWasmEHInfo(const Function *F, WasmEHFuncInfo &EHInfo)
void calculateClrEHStateNumbers(const Function *Fn, WinEHFuncInfo &FuncInfo)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
MBBOrBasicBlock Handler
Definition: WinEHFuncInfo.h:82
MBBOrBasicBlock Cleanup
Definition: WinEHFuncInfo.h:42
Extended Value Type.
Definition: ValueTypes.h:34
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:358
static KnownBits makeConstant(const APInt &C)
Create known bits from a known constant.
Definition: KnownBits.h:290
unsigned getBitWidth() const
Get the bit width of this value.
Definition: KnownBits.h:40
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
Definition: KnownBits.h:300
KnownBits anyext(unsigned BitWidth) const
Return known bits for an "any" extension of the value we're tracking, where we don't know anything ab...
Definition: KnownBits.h:156
Similar to CxxUnwindMapEntry, but supports SEH filters.
Definition: WinEHFuncInfo.h:46
This contains information for each constraint that we are lowering.
DenseMap< BBOrMBB, SmallPtrSet< BBOrMBB, 4 > > UnwindDestToSrcs
DenseMap< BBOrMBB, BBOrMBB > SrcToUnwindDest
SmallVector< SEHUnwindMapEntry, 4 > SEHUnwindMap
Definition: WinEHFuncInfo.h:98
SmallVector< ClrEHUnwindMapEntry, 4 > ClrEHUnwindMap
Definition: WinEHFuncInfo.h:99
SmallVector< WinEHTryBlockMapEntry, 4 > TryBlockMap
Definition: WinEHFuncInfo.h:97
SmallVector< CxxUnwindMapEntry, 4 > CxxUnwindMap
Definition: WinEHFuncInfo.h:96
SmallVector< WinEHHandlerType, 1 > HandlerArray
Definition: WinEHFuncInfo.h:76