LLVM 24.0.0git
HexagonDisassembler.cpp
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1//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/HexagonBaseInfo.h"
10#include "MCTargetDesc/HexagonMCChecker.h"
11#include "MCTargetDesc/HexagonMCInstrInfo.h"
12#include "MCTargetDesc/HexagonMCTargetDesc.h"
13#include "TargetInfo/HexagonTargetInfo.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/MC/MCContext.h"
16#include "llvm/MC/MCDecoder.h"
17#include "llvm/MC/MCDecoderOps.h"
18#include "llvm/MC/MCDisassembler/MCDisassembler.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrInfo.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Support/Compiler.h"
26#include "llvm/Support/Endian.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/raw_ostream.h"
29#include <cassert>
30#include <cstddef>
31#include <cstdint>
32#include <memory>
33
34#define DEBUG_TYPE "hexagon-disassembler"
35
36using namespace llvm;
37using namespace llvm::MCD;
38using namespace Hexagon;
39
40using DecodeStatus = MCDisassembler::DecodeStatus;
41
42namespace {
43
44/// Hexagon disassembler for all Hexagon platforms.
45class HexagonDisassembler : public MCDisassembler {
46public:
47 std::unique_ptr<MCInstrInfo const> const MCII;
48 mutable std::unique_ptr<MCInst> CurrentBundle;
49 mutable MCInst const *CurrentExtender;
50
51 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
52 MCInstrInfo const *MCII)
53 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(nullptr),
54 CurrentExtender(nullptr) {}
55
56 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
57 ArrayRef<uint8_t> Bytes, uint64_t Address,
58 raw_ostream &CStream, bool &Complete) const;
59 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
60 ArrayRef<uint8_t> Bytes, uint64_t Address,
61 raw_ostream &CStream) const override;
62
63 DecodeStatus getInstructionBundle(MCInst &Instr, uint64_t &Size,
64 ArrayRef<uint8_t> Bytes, uint64_t Address,
65 raw_ostream &CStream) const override;
66
67 void remapInstruction(MCInst &Instr) const;
68
69 Expected<bool> onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,
70 ArrayRef<uint8_t> Bytes,
71 uint64_t Address) const override;
72
73private:
74 bool makeBundle(ArrayRef<uint8_t> Bytes, uint64_t Address,
75 uint64_t &BytesToSkip, raw_ostream &CS) const;
76
77 void resetBundle() const {
78 CurrentBundle.reset();
79 CurrentInstruction = nullptr;
80 }
81
82 mutable MCOperand *CurrentInstruction = nullptr;
83};
84
85static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
86 int64_t Value) {
87 MCInstrInfo MCII = *Disassembler.MCII;
88 if (!Disassembler.CurrentExtender ||
89 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
90 return Value;
91 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
92 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
93 int64_t Bits;
94 bool Success =
95 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
96 Bits);
97 assert(Success);
98 (void)Success;
99 uint64_t Upper26 = static_cast<uint64_t>(Bits);
100 uint64_t Operand = Upper26 | Lower6;
101 return Operand;
102}
103static HexagonDisassembler const &disassembler(const MCDisassembler *Decoder) {
104 return *static_cast<HexagonDisassembler const *>(Decoder);
105}
106template <size_t T>
107static void signedDecoder(MCInst &MI, unsigned tmp,
108 const MCDisassembler *Decoder) {
109 HexagonDisassembler const &Disassembler = disassembler(Decoder);
110 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
111 int64_t Extended = SignExtend64<32>(FullValue);
112 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
113}
114}
115
116// Forward declare these because the auto-generated code will reference them.
117// Definitions are further down.
118
119static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
120 uint64_t Address,
121 const MCDisassembler *Decoder);
122static DecodeStatus
123DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
124 uint64_t Address,
125 const MCDisassembler *Decoder);
126static DecodeStatus
127DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
128 const MCDisassembler *Decoder);
129static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
130 uint64_t Address,
131 const MCDisassembler *Decoder);
132static DecodeStatus
133DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
134 const MCDisassembler *Decoder);
135static DecodeStatus
136DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
137 uint64_t Address,
138 const MCDisassembler *Decoder);
139static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
140 uint64_t Address,
141 const MCDisassembler *Decoder);
142static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
143 uint64_t Address,
144 const MCDisassembler *Decoder);
145static DecodeStatus DecodeHlxLRRegisterClass(MCInst &Inst, unsigned RegNo,
146 uint64_t Address,
147 const MCDisassembler *Decoder);
148static DecodeStatus DecodeHlxLLRRegisterClass(MCInst &Inst, unsigned RegNo,
149 uint64_t Address,
150 const MCDisassembler *Decoder);
151static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
152 uint64_t Address,
153 const MCDisassembler *Decoder);
154static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
155 uint64_t Address,
156 const MCDisassembler *Decoder);
157static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
158 uint64_t Address,
159 const MCDisassembler *Decoder);
160static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
161 uint64_t Address,
162 const MCDisassembler *Decoder);
163static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
164 uint64_t Address,
165 const MCDisassembler *Decoder);
166static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address,
168 const MCDisassembler *Decoder);
169static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
170 uint64_t Address,
171 const MCDisassembler *Decoder);
172static DecodeStatus
173DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
174 const MCDisassembler *Decoder);
175static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
176 uint64_t Address,
177 const MCDisassembler *Decoder);
178
179static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
180 uint64_t Address,
181 const MCDisassembler *Decoder);
182static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
183 uint64_t /*Address*/,
184 const MCDisassembler *Decoder);
185static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
186 const MCDisassembler *Decoder);
187
188static DecodeStatus n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder) {
189 MCContext &Ctx = Decoder->getContext();
190 MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(-1, Ctx)));
191 return DecodeStatus::Success;
192}
193
194static DecodeStatus sgp10ConstDecoder(MCInst &MI,
195 const MCDisassembler *Decoder) {
196 MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
197 return DecodeStatus::Success;
198}
199
200#include "HexagonDepDecoders.inc"
201#include "HexagonGenDisassemblerTables.inc"
202
203static MCDisassembler *createHexagonDisassembler(const Target &T,
204 const MCSubtargetInfo &STI,
205 MCContext &Ctx) {
206 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
207}
208
209extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
214
215bool HexagonDisassembler::makeBundle(ArrayRef<uint8_t> Bytes, uint64_t Address,
216 uint64_t &BytesToSkip,
217 raw_ostream &CS) const {
218 bool Complete = false;
219 DecodeStatus Result = DecodeStatus::Success;
220
221 CurrentBundle.reset(new MCInst);
222 CurrentBundle->setOpcode(Hexagon::BUNDLE);
223 CurrentBundle->addOperand(MCOperand::createImm(0));
224 while (Result == Success && !Complete) {
225 if (Bytes.size() < HEXAGON_INSTR_SIZE)
226 return false;
227 MCInst *Inst = getContext().createMCInst();
228 Result = getSingleInstruction(*Inst, *CurrentBundle, Bytes, Address, CS,
229 Complete);
230 CurrentBundle->addOperand(MCOperand::createInst(Inst));
231 BytesToSkip += HEXAGON_INSTR_SIZE;
232 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
233 }
234 if (Result == MCDisassembler::Fail)
235 return false;
236 if (BytesToSkip > HEXAGON_MAX_PACKET_SIZE)
237 return false;
238
239 const auto ArchSTI = Hexagon_MC::getArchSubtarget(&STI);
240 const auto STI_ = (ArchSTI != nullptr) ? *ArchSTI : STI;
241 HexagonMCChecker Checker(getContext(), *MCII, STI_, *CurrentBundle,
242 *getContext().getRegisterInfo(), false);
243 if (!Checker.check())
244 return false;
245 remapInstruction(*CurrentBundle);
246 return true;
247}
248
249DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
250 ArrayRef<uint8_t> Bytes,
251 uint64_t Address,
252 raw_ostream &CS) const {
253 CommentStream = &CS;
254
255 Size = 0;
256 uint64_t BytesToSkip = 0;
257
258 if (!CurrentBundle) {
259 if (!makeBundle(Bytes, Address, BytesToSkip, CS)) {
260 Size = BytesToSkip;
261 resetBundle();
262 return MCDisassembler::Fail;
263 }
264 CurrentInstruction = (CurrentBundle->begin() + 1);
265 }
266
267 MI = *(CurrentInstruction->getInst());
268 Size = HEXAGON_INSTR_SIZE;
269 if (++CurrentInstruction == CurrentBundle->end())
270 resetBundle();
271 return MCDisassembler::Success;
272}
273
274DecodeStatus HexagonDisassembler::getInstructionBundle(MCInst &MI,
275 uint64_t &Size,
276 ArrayRef<uint8_t> Bytes,
277 uint64_t Address,
278 raw_ostream &CS) const {
279 CommentStream = &CS;
280 Size = 0;
281 uint64_t BytesToSkip = 0;
282 assert(!CurrentBundle);
283
284 if (!makeBundle(Bytes, Address, BytesToSkip, CS)) {
285 Size = BytesToSkip;
286 resetBundle();
287 return MCDisassembler::Fail;
288 }
289
290 MI = *CurrentBundle;
291 Size = HEXAGON_INSTR_SIZE * HexagonMCInstrInfo::bundleSize(MI);
292 resetBundle();
293
294 return Success;
295}
296
297void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
298 for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
299 auto &MI = const_cast<MCInst &>(*I.getInst());
300 switch (MI.getOpcode()) {
301 case Hexagon::S2_allocframe:
302 if (MI.getOperand(0).getReg() == Hexagon::R29) {
303 MI.setOpcode(Hexagon::S6_allocframe_to_raw);
304 MI.erase(MI.begin () + 1);
305 MI.erase(MI.begin ());
306 }
307 break;
308 case Hexagon::L2_deallocframe:
309 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
310 MI.getOperand(1).getReg() == Hexagon::R30) {
311 MI.setOpcode(L6_deallocframe_map_to_raw);
312 MI.erase(MI.begin () + 1);
313 MI.erase(MI.begin ());
314 }
315 break;
316 case Hexagon::L4_return:
317 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
318 MI.getOperand(1).getReg() == Hexagon::R30) {
319 MI.setOpcode(L6_return_map_to_raw);
320 MI.erase(MI.begin () + 1);
321 MI.erase(MI.begin ());
322 }
323 break;
324 case Hexagon::L4_return_t:
325 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
326 MI.getOperand(2).getReg() == Hexagon::R30) {
327 MI.setOpcode(L4_return_map_to_raw_t);
328 MI.erase(MI.begin () + 2);
329 MI.erase(MI.begin ());
330 }
331 break;
332 case Hexagon::L4_return_f:
333 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
334 MI.getOperand(2).getReg() == Hexagon::R30) {
335 MI.setOpcode(L4_return_map_to_raw_f);
336 MI.erase(MI.begin () + 2);
337 MI.erase(MI.begin ());
338 }
339 break;
340 case Hexagon::L4_return_tnew_pt:
341 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
342 MI.getOperand(2).getReg() == Hexagon::R30) {
343 MI.setOpcode(L4_return_map_to_raw_tnew_pt);
344 MI.erase(MI.begin () + 2);
345 MI.erase(MI.begin ());
346 }
347 break;
348 case Hexagon::L4_return_fnew_pt:
349 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
350 MI.getOperand(2).getReg() == Hexagon::R30) {
351 MI.setOpcode(L4_return_map_to_raw_fnew_pt);
352 MI.erase(MI.begin () + 2);
353 MI.erase(MI.begin ());
354 }
355 break;
356 case Hexagon::L4_return_tnew_pnt:
357 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
358 MI.getOperand(2).getReg() == Hexagon::R30) {
359 MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
360 MI.erase(MI.begin () + 2);
361 MI.erase(MI.begin ());
362 }
363 break;
364 case Hexagon::L4_return_fnew_pnt:
365 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
366 MI.getOperand(2).getReg() == Hexagon::R30) {
367 MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
368 MI.erase(MI.begin () + 2);
369 MI.erase(MI.begin ());
370 }
371 break;
372 }
373 }
374}
375
376DecodeStatus HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
377 ArrayRef<uint8_t> Bytes,
378 uint64_t Address,
379 raw_ostream &cs,
380 bool &Complete) const {
381 assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
382
383 uint32_t Instruction = support::endian::read32le(Bytes.data());
384
385 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
386 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
387 HexagonII::INST_PARSE_LOOP_END) {
388 if (BundleSize == 0)
389 HexagonMCInstrInfo::setInnerLoop(MCB);
390 else if (BundleSize == 1)
391 HexagonMCInstrInfo::setOuterLoop(MCB);
392 else
393 return DecodeStatus::Fail;
394 }
395
396 CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
397 MCB, HexagonMCInstrInfo::bundleSize(MCB));
398
399 DecodeStatus Result = DecodeStatus::Fail;
400 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
401 HexagonII::INST_PARSE_DUPLEX) {
402 unsigned duplexIClass;
403 uint8_t const *DecodeLow, *DecodeHigh;
404 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
405 switch (duplexIClass) {
406 default:
407 return MCDisassembler::Fail;
408 case 0:
409 DecodeLow = DecoderTableSUBINSN_L132;
410 DecodeHigh = DecoderTableSUBINSN_L132;
411 break;
412 case 1:
413 DecodeLow = DecoderTableSUBINSN_L232;
414 DecodeHigh = DecoderTableSUBINSN_L132;
415 break;
416 case 2:
417 DecodeLow = DecoderTableSUBINSN_L232;
418 DecodeHigh = DecoderTableSUBINSN_L232;
419 break;
420 case 3:
421 DecodeLow = DecoderTableSUBINSN_A32;
422 DecodeHigh = DecoderTableSUBINSN_A32;
423 break;
424 case 4:
425 DecodeLow = DecoderTableSUBINSN_L132;
426 DecodeHigh = DecoderTableSUBINSN_A32;
427 break;
428 case 5:
429 DecodeLow = DecoderTableSUBINSN_L232;
430 DecodeHigh = DecoderTableSUBINSN_A32;
431 break;
432 case 6:
433 DecodeLow = DecoderTableSUBINSN_S132;
434 DecodeHigh = DecoderTableSUBINSN_A32;
435 break;
436 case 7:
437 DecodeLow = DecoderTableSUBINSN_S232;
438 DecodeHigh = DecoderTableSUBINSN_A32;
439 break;
440 case 8:
441 DecodeLow = DecoderTableSUBINSN_S132;
442 DecodeHigh = DecoderTableSUBINSN_L132;
443 break;
444 case 9:
445 DecodeLow = DecoderTableSUBINSN_S132;
446 DecodeHigh = DecoderTableSUBINSN_L232;
447 break;
448 case 10:
449 DecodeLow = DecoderTableSUBINSN_S132;
450 DecodeHigh = DecoderTableSUBINSN_S132;
451 break;
452 case 11:
453 DecodeLow = DecoderTableSUBINSN_S232;
454 DecodeHigh = DecoderTableSUBINSN_S132;
455 break;
456 case 12:
457 DecodeLow = DecoderTableSUBINSN_S232;
458 DecodeHigh = DecoderTableSUBINSN_L132;
459 break;
460 case 13:
461 DecodeLow = DecoderTableSUBINSN_S232;
462 DecodeHigh = DecoderTableSUBINSN_L232;
463 break;
464 case 14:
465 DecodeLow = DecoderTableSUBINSN_S232;
466 DecodeHigh = DecoderTableSUBINSN_S232;
467 break;
468 }
469 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
470 MCInst *MILow = getContext().createMCInst();
471 MCInst *MIHigh = getContext().createMCInst();
472 auto TmpExtender = CurrentExtender;
473 CurrentExtender =
474 nullptr; // constant extenders in duplex must always be in slot 1
475 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
476 this, STI);
477 CurrentExtender = TmpExtender;
478 if (Result != DecodeStatus::Success)
479 return DecodeStatus::Fail;
480 Result = decodeInstruction(
481 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
482 if (Result != DecodeStatus::Success)
483 return DecodeStatus::Fail;
484 MCOperand OPLow = MCOperand::createInst(MILow);
485 MCOperand OPHigh = MCOperand::createInst(MIHigh);
486 MI.addOperand(OPLow);
487 MI.addOperand(OPHigh);
488 Complete = true;
489 } else {
490 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
491 HexagonII::INST_PARSE_PACKET_END)
492 Complete = true;
493
494 if (CurrentExtender != nullptr)
495 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
496 Address, this, STI);
497
498 if (Result != MCDisassembler::Success)
499 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,
500 STI);
501
502 if (Result != MCDisassembler::Success &&
503 STI.hasFeature(Hexagon::ExtensionHVX))
504 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
505 Address, this, STI);
506
507 }
508
509 // HLX NV instructions use the producing register directly in the encoding.
510 if (HexagonMCInstrInfo::isNewValue(*MCII, MI) &&
511 !HexagonMCInstrInfo::isHLX(*MCII, MI)) {
512 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
513 MCOperand &MCO = MI.getOperand(OpIndex);
514 assert(MCO.isReg() && "New value consumers must be registers");
515 unsigned Register =
516 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
517 if ((Register & 0x6) == 0)
518 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
519 return MCDisassembler::Fail;
520 unsigned Lookback = (Register & 0x6) >> 1;
521 unsigned Offset = 1;
522 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
523 bool PrevVector = false;
524 auto Instructions = HexagonMCInstrInfo::bundleInstructions(*CurrentBundle);
525 auto i = Instructions.end() - 1;
526 for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
527 if (i == n)
528 // Couldn't find producer
529 return MCDisassembler::Fail;
530 bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
531 if (Vector && !CurrentVector)
532 // Skip scalars when calculating distances for vectors
533 ++Lookback;
534 if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
535 ++Lookback;
536 PrevVector = CurrentVector;
537 if (Offset == Lookback)
538 break;
539 }
540 auto const &Inst = *i->getInst();
541 bool SubregBit = (Register & 0x1) != 0;
542 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
543 // If subreg bit is set we're selecting the second produced newvalue
544 MCRegister Producer =
545 SubregBit
546 ? HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg()
547 : HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
548 assert(Producer != Hexagon::NoRegister);
549 MCO.setReg(Producer);
550 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
551 MCRegister Producer =
552 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();
553
554 if (HexagonMCInstrInfo::IsVecRegPair(Producer)) {
555 const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer);
556 const unsigned ProdPairIndex =
557 Rev ? Producer - Hexagon::WR0 : Producer - Hexagon::W0;
558 if (Rev)
559 SubregBit = !SubregBit;
560 Producer = (ProdPairIndex << 1) + SubregBit + Hexagon::V0;
561 } else if (SubregBit)
562 // Hexagon PRM 10.11 New-value operands
563 // Nt[0] is reserved and should always be encoded as zero.
564 return MCDisassembler::Fail;
565 assert(Producer != Hexagon::NoRegister);
566 MCO.setReg(Producer);
567 } else
568 return MCDisassembler::Fail;
569 }
570
571 if (CurrentExtender != nullptr) {
572 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
573 ? *MI.getOperand(1).getInst()
574 : MI;
575 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
576 !HexagonMCInstrInfo::isExtended(*MCII, Inst))
577 return MCDisassembler::Fail;
578 }
579 return Result;
580}
581
582Expected<bool> HexagonDisassembler::onSymbolStart(SymbolInfoTy &Symbol,
583 uint64_t &Size,
584 ArrayRef<uint8_t> Bytes,
585 uint64_t Address) const {
586 // At the start of a symbol, force a fresh packet by resetting any
587 // in-progress bundle state. This prevents packets from straddling label
588 // boundaries when data (e.g. jump tables) appears in between.
589 Size = 0;
590 resetBundle();
591 return true;
592}
593
594static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
595 ArrayRef<MCPhysReg> Table) {
596 if (RegNo < Table.size()) {
597 Inst.addOperand(MCOperand::createReg(Table[RegNo]));
598 return MCDisassembler::Success;
599 }
600
601 return MCDisassembler::Fail;
602}
603
604static DecodeStatus
605DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
606 const MCDisassembler *Decoder) {
607 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
608}
609
610static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
611 uint64_t Address,
612 const MCDisassembler *Decoder) {
613 static const MCPhysReg IntRegDecoderTable[] = {
614 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
615 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
616 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
617 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
618 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
619 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
620 Hexagon::R30, Hexagon::R31};
621
622 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
623}
624
625static DecodeStatus
626DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo,
627 uint64_t Address,
628 const MCDisassembler *Decoder) {
629 static const MCPhysReg GeneralSubRegDecoderTable[] = {
630 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
631 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
632 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
633 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
634 };
635
636 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
637}
638
639static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
640 uint64_t /*Address*/,
641 const MCDisassembler *Decoder) {
642 static const MCPhysReg HvxVRDecoderTable[] = {
643 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
644 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
645 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
646 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
647 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
648 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
649 Hexagon::V30, Hexagon::V31};
650
651 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
652}
653
654static DecodeStatus DecodeHlxLRRegisterClass(MCInst &Inst, unsigned RegNo,
655 uint64_t /*Address*/,
656 const MCDisassembler *Decoder) {
657 static const MCPhysReg HlxLRDecoderTable[] = {
658 Hexagon::L0, Hexagon::L1, Hexagon::L2, Hexagon::L3,
659 Hexagon::L4, Hexagon::L5, Hexagon::L6, Hexagon::L7,
660 Hexagon::L8, Hexagon::L9, Hexagon::L10, Hexagon::L11,
661 Hexagon::L12, Hexagon::L13, Hexagon::L14, Hexagon::L15};
662
663 return DecodeRegisterClass(Inst, RegNo, HlxLRDecoderTable);
664}
665
666static DecodeStatus DecodeHlxLLRRegisterClass(MCInst &Inst, unsigned RegNo,
667 uint64_t /*Address*/,
668 const MCDisassembler *Decoder) {
669 static const MCPhysReg HlxLLRDecoderTable[] = {
670 Hexagon::LL0, Hexagon::LL1, Hexagon::LL2, Hexagon::LL3,
671 Hexagon::LL4, Hexagon::LL5, Hexagon::LL6, Hexagon::LL7};
672
673 if (RegNo & 1)
674 return MCDisassembler::Fail;
675
676 return DecodeRegisterClass(Inst, RegNo / 2, HlxLLRDecoderTable);
677}
678
679static DecodeStatus
680DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
681 uint64_t /*Address*/,
682 const MCDisassembler *Decoder) {
683 static const MCPhysReg DoubleRegDecoderTable[] = {
684 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
685 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
686 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
687 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
688
689 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
690}
691
692static DecodeStatus
693DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
694 uint64_t /*Address*/,
695 const MCDisassembler *Decoder) {
696 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
697 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
698 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
699
700 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
701}
702
703static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
704 uint64_t /*Address*/,
705 const MCDisassembler *Decoder) {
706 static const MCPhysReg HvxWRDecoderTable[] = {
707 Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2,
708 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4,
709 Hexagon::W5, Hexagon::WR5, Hexagon::W6, Hexagon::WR6, Hexagon::W7,
710 Hexagon::WR7, Hexagon::W8, Hexagon::WR8, Hexagon::W9, Hexagon::WR9,
711 Hexagon::W10, Hexagon::WR10, Hexagon::W11, Hexagon::WR11, Hexagon::W12,
712 Hexagon::WR12, Hexagon::W13, Hexagon::WR13, Hexagon::W14, Hexagon::WR14,
713 Hexagon::W15, Hexagon::WR15,
714 };
715
716 return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable);
717}
718
719[[maybe_unused]] // Suppress warning temporarily.
720static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo,
721 uint64_t /*Address*/,
722 const MCDisassembler *Decoder) {
723 static const MCPhysReg HvxVQRDecoderTable[] = {
724 Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3,
725 Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7};
726
727 return DecodeRegisterClass(Inst, RegNo >> 2, HvxVQRDecoderTable);
728}
729
730static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
731 uint64_t /*Address*/,
732 const MCDisassembler *Decoder) {
733 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
734 Hexagon::P2, Hexagon::P3};
735
736 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
737}
738
739static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
740 uint64_t /*Address*/,
741 const MCDisassembler *Decoder) {
742 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
743 Hexagon::Q2, Hexagon::Q3};
744
745 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
746}
747
748static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
749 uint64_t /*Address*/,
750 const MCDisassembler *Decoder) {
751 using namespace Hexagon;
752
753 static const MCPhysReg CtrlRegDecoderTable[] = {
754 /* 0 */ SA0, LC0, SA1, LC1,
755 /* 4 */ P3_0, C5, M0, M1,
756 /* 8 */ USR, PC, UGP, GP,
757 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
758 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
759 /* 20 */ 0, 0, 0, 0,
760 /* 24 */ 0, 0, 0, 0,
761 /* 28 */ VFRAMELIMIT, VSP, UTIMERLO, UTIMERHI};
762
763 if (RegNo >= std::size(CtrlRegDecoderTable))
764 return MCDisassembler::Fail;
765
766 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
767 if (CtrlRegDecoderTable[RegNo] == NoRegister)
768 return MCDisassembler::Fail;
769
770 unsigned Register = CtrlRegDecoderTable[RegNo];
771 Inst.addOperand(MCOperand::createReg(Register));
772 return MCDisassembler::Success;
773}
774
775static DecodeStatus
776DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
777 const MCDisassembler *Decoder) {
778 using namespace Hexagon;
779
780 static const MCPhysReg CtrlReg64DecoderTable[] = {
781 /* 0 */ C1_0, 0, C3_2, 0,
782 /* 4 */ C5_4, 0, C7_6, 0,
783 /* 8 */ C9_8, 0, C11_10, 0,
784 /* 12 */ CS, 0, UPCYCLE, 0,
785 /* 16 */ C17_16, 0, PKTCOUNT, 0,
786 /* 20 */ 0, 0, 0, 0,
787 /* 24 */ 0, 0, 0, 0,
788 /* 28 */ C29_28, 0, UTIMER, 0};
789
790 if (RegNo >= std::size(CtrlReg64DecoderTable))
791 return MCDisassembler::Fail;
792
793 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
794 if (CtrlReg64DecoderTable[RegNo] == NoRegister)
795 return MCDisassembler::Fail;
796
797 unsigned Register = CtrlReg64DecoderTable[RegNo];
798 Inst.addOperand(MCOperand::createReg(Register));
799 return MCDisassembler::Success;
800}
801
802static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
803 uint64_t /*Address*/,
804 const MCDisassembler *Decoder) {
805 unsigned Register = 0;
806 switch (RegNo) {
807 case 0:
808 Register = Hexagon::M0;
809 break;
810 case 1:
811 Register = Hexagon::M1;
812 break;
813 default:
814 return MCDisassembler::Fail;
815 }
816 Inst.addOperand(MCOperand::createReg(Register));
817 return MCDisassembler::Success;
818}
819
820static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
821 uint64_t /*Address*/,
822 const MCDisassembler *Decoder) {
823 HexagonDisassembler const &Disassembler = disassembler(Decoder);
824 int64_t FullValue = fullValue(Disassembler, MI, tmp);
825 assert(FullValue >= 0 && "Negative in unsigned decoder");
826 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
827 return MCDisassembler::Success;
828}
829
830static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
831 uint64_t /*Address*/,
832 const MCDisassembler *Decoder) {
833 HexagonDisassembler const &Disassembler = disassembler(Decoder);
834 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
835 tmp = SignExtend64(tmp, Bits);
836 signedDecoder<32>(MI, tmp, Decoder);
837 return MCDisassembler::Success;
838}
839
840// custom decoder for various jump/call immediates
841static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
842 const MCDisassembler *Decoder) {
843 HexagonDisassembler const &Disassembler = disassembler(Decoder);
844 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
845 // r13_2 is not extendable, so if there are no extent bits, it's r13_2
846 if (Bits == 0)
847 Bits = 15;
848 uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
849 uint32_t Extended = FullValue + Address;
850 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 0,
851 4))
852 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
853 return MCDisassembler::Success;
854}
855
856static const uint16_t SysRegDecoderTable[] = {
857 Hexagon::SGP0, Hexagon::SGP1, Hexagon::STID,
858 Hexagon::ELR, Hexagon::BADVA0, Hexagon::BADVA1,
859 Hexagon::SSR, Hexagon::CCR, Hexagon::HTID,
860 Hexagon::BADVA, Hexagon::IMASK, Hexagon::S11,
861 Hexagon::S12, Hexagon::S13, Hexagon::S14,
862 Hexagon::S15, Hexagon::EVB, Hexagon::MODECTL,
863 Hexagon::SYSCFG, Hexagon::S19, Hexagon::S20,
864 Hexagon::VID, Hexagon::S22, Hexagon::S23,
865 Hexagon::S24, Hexagon::S25, Hexagon::S26,
866 Hexagon::CFGBASE, Hexagon::DIAG, Hexagon::REV,
867 Hexagon::PCYCLELO, Hexagon::PCYCLEHI, Hexagon::ISDBST,
868 Hexagon::ISDBCFG0, Hexagon::ISDBCFG1, Hexagon::S35,
869 Hexagon::BRKPTPC0, Hexagon::BRKPTCFG0, Hexagon::BRKPTPC1,
870 Hexagon::BRKPTCFG1, Hexagon::ISDBMBXIN, Hexagon::ISDBMBXOUT,
871 Hexagon::ISDBEN, Hexagon::ISDBGPR, Hexagon::S44,
872 Hexagon::S45, Hexagon::S46, Hexagon::S47,
873 Hexagon::PMUCNT0, Hexagon::PMUCNT1, Hexagon::PMUCNT2,
874 Hexagon::PMUCNT3, Hexagon::PMUEVTCFG, Hexagon::PMUCFG,
875 Hexagon::S54, Hexagon::S55, Hexagon::S56,
876 Hexagon::S57, Hexagon::S58, Hexagon::S59,
877 Hexagon::S60, Hexagon::S61, Hexagon::S62,
878 Hexagon::S63, Hexagon::S64, Hexagon::S65,
879 Hexagon::S66, Hexagon::S67, Hexagon::S68,
880 Hexagon::S69, Hexagon::S70, Hexagon::S71,
881 Hexagon::S72, Hexagon::S73, Hexagon::S74,
882 Hexagon::S75, Hexagon::S76, Hexagon::S77,
883 Hexagon::S78, Hexagon::S79, Hexagon::S80,
884};
885
886static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo,
887 uint64_t /*Address*/,
888 const MCDisassembler *Decoder) {
889 if (RegNo >= std::size(SysRegDecoderTable))
890 return MCDisassembler::Fail;
891
892 if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister)
893 return MCDisassembler::Fail;
894
895 unsigned Register = SysRegDecoderTable[RegNo];
896 Inst.addOperand(MCOperand::createReg(Register));
897 return MCDisassembler::Success;
898}
899
900static const uint16_t SysReg64DecoderTable[] = {
901 Hexagon::SGP1_0, Hexagon::S3_2, Hexagon::S5_4, Hexagon::S7_6,
902 Hexagon::S9_8, Hexagon::S11_10, Hexagon::S13_12, Hexagon::S15_14,
903 Hexagon::S17_16, Hexagon::S19_18, Hexagon::S21_20, Hexagon::S23_22,
904 Hexagon::S25_24, Hexagon::S27_26, Hexagon::S29_28, Hexagon::S31_30,
905 Hexagon::S33_32, Hexagon::S35_34, Hexagon::S37_36, Hexagon::S39_38,
906 Hexagon::S41_40, Hexagon::S43_42, Hexagon::S45_44, Hexagon::S47_46,
907 Hexagon::S49_48, Hexagon::S51_50, Hexagon::S53_52, Hexagon::S55_54,
908 Hexagon::S57_56, Hexagon::S59_58, Hexagon::S61_60, Hexagon::S63_62,
909 Hexagon::S65_64, Hexagon::S67_66, Hexagon::S69_68, Hexagon::S71_70,
910 Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78,
911};
912
913static DecodeStatus
914DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
915 const MCDisassembler *Decoder) {
916 RegNo = RegNo >> 1;
917 if (RegNo >= std::size(SysReg64DecoderTable))
918 return MCDisassembler::Fail;
919
920 if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister)
921 return MCDisassembler::Fail;
922
923 unsigned Register = SysReg64DecoderTable[RegNo];
924 Inst.addOperand(MCOperand::createReg(Register));
925 return MCDisassembler::Success;
926}
927
928static DecodeStatus
929DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
930 const MCDisassembler *Decoder) {
931 using namespace Hexagon;
932
933 static const MCPhysReg GuestRegDecoderTable[] = {
934 /* 0 */ GELR, GSR, GOSP, G3,
935 /* 4 */ G4, G5, G6, G7,
936 /* 8 */ G8, G9, G10, G11,
937 /* 12 */ G12, G13, G14, G15,
938 /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
939 /* 20 */ G20, G21, G22, G23,
940 /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
941 /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
942 };
943
944 if (RegNo >= std::size(GuestRegDecoderTable))
945 return MCDisassembler::Fail;
946 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
947 return MCDisassembler::Fail;
948
949 unsigned Register = GuestRegDecoderTable[RegNo];
950 Inst.addOperand(MCOperand::createReg(Register));
951 return MCDisassembler::Success;
952}
953
954static DecodeStatus
955DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
956 uint64_t /*Address*/,
957 const MCDisassembler *Decoder) {
958 using namespace Hexagon;
959
960 static const MCPhysReg GuestReg64DecoderTable[] = {
961 /* 0 */ G1_0, 0, G3_2, 0,
962 /* 4 */ G5_4, 0, G7_6, 0,
963 /* 8 */ G9_8, 0, G11_10, 0,
964 /* 12 */ G13_12, 0, G15_14, 0,
965 /* 16 */ G17_16, 0, G19_18, 0,
966 /* 20 */ G21_20, 0, G23_22, 0,
967 /* 24 */ G25_24, 0, G27_26, 0,
968 /* 28 */ G29_28, 0, G31_30, 0
969 };
970
971 if (RegNo >= std::size(GuestReg64DecoderTable))
972 return MCDisassembler::Fail;
973 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
974 return MCDisassembler::Fail;
975
976 unsigned Register = GuestReg64DecoderTable[RegNo];
977 Inst.addOperand(MCOperand::createReg(Register));
978 return MCDisassembler::Success;
979}
DecodeStatus
MCDisassembler::DecodeStatus DecodeStatus
Definition AArch64Disassembler.cpp:36
Success
#define Success
Definition AArch64Disassembler.cpp:42
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
uint64_t
uint64_t uint64_t
Definition AMDGPUDisassembler.cpp:553
Decoder
uint64_t const MCDisassembler * Decoder
Definition AMDGPUDisassembler.cpp:554
LLVM_ABI
#define LLVM_ABI
Definition Compiler.h:211
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition Compiler.h:132
sgp10ConstDecoder
static DecodeStatus sgp10ConstDecoder(MCInst &MI, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:194
DecodeIntRegsLow8RegisterClass
static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:605
DecodeGuestRegsRegisterClass
static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:929
DecodeCtrRegsRegisterClass
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:748
brtargetDecoder
static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:841
DecodePredRegsRegisterClass
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:730
LLVMInitializeHexagonDisassembler
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonDisassembler()
Definition HexagonDisassembler.cpp:210
s32_0ImmDecoder
static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:830
unsignedImmDecoder
static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:820
DecodeHvxVRRegisterClass
static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:639
createHexagonDisassembler
static MCDisassembler * createHexagonDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition HexagonDisassembler.cpp:203
DecodeSysRegs64RegisterClass
static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:914
DecodeModRegsRegisterClass
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:802
SysReg64DecoderTable
static const uint16_t SysReg64DecoderTable[]
Definition HexagonDisassembler.cpp:900
DecodeHlxLRRegisterClass
static DecodeStatus DecodeHlxLRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:654
DecodeRegisterClass
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef< MCPhysReg > Table)
Definition HexagonDisassembler.cpp:594
DecodeSysRegsRegisterClass
static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:886
DecodeDoubleRegsRegisterClass
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:680
n1ConstDecoder
static DecodeStatus n1ConstDecoder(MCInst &MI, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:188
SysRegDecoderTable
static const uint16_t SysRegDecoderTable[]
Definition HexagonDisassembler.cpp:856
DecodeGeneralSubRegsRegisterClass
static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:626
DecodeHvxWRRegisterClass
static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:703
DecodeIntRegsRegisterClass
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:610
DecodeHvxQRRegisterClass
static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:739
DecodeCtrRegs64RegisterClass
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:776
DecodeGeneralDoubleLow8RegsRegisterClass
static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:693
DecodeGuestRegs64RegisterClass
static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:955
DecodeHlxLLRRegisterClass
static DecodeStatus DecodeHlxLLRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:666
DecodeHvxVQRRegisterClass
static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const MCDisassembler *Decoder)
Definition HexagonDisassembler.cpp:720
HEXAGON_MAX_PACKET_SIZE
#define HEXAGON_MAX_PACKET_SIZE
Definition HexagonMCTargetDesc.h:36
HEXAGON_INSTR_SIZE
#define HEXAGON_INSTR_SIZE
Definition HexagonMCTargetDesc.h:32
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:876
I
#define I(x, y, z)
Definition MD5.cpp:57
Register
Promote Memory to Register
Definition Mem2Reg.cpp:110
T
#define T
Definition Mips16ISelLowering.cpp:268
getContext
Func getContext().diagnose(DiagnosticInfoUnsupported(Func
IntRegDecoderTable
static constexpr unsigned IntRegDecoderTable[]
Definition SparcDisassembler.cpp:65
llvm::ArrayRef
Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition ArrayRef.h:40
llvm::ArrayRef::size
size_t size() const
Get the array size.
Definition ArrayRef.h:141
llvm::ArrayRef::data
const T * data() const
Definition ArrayRef.h:138
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition ArrayRef.h:185
llvm::Expected
Tagged union holding either a T or a Error.
Definition Error.h:485
llvm::MCConstantExpr::create
static LLVM_ABI const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition MCExpr.cpp:212
llvm::MCContext
Context object for machine code objects.
Definition MCContext.h:83
llvm::MCDisassembler
Superclass for all disassemblers.
Definition MCDisassembler.h:85
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition MCDisassembler.h:109
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition MCInst.h:188
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition MCInst.h:215
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition MCInst.h:210
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition MCInstrInfo.h:27
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition MCInst.h:40
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition MCInst.h:166
llvm::MCOperand::createReg
static MCOperand createReg(MCRegister Reg)
Definition MCInst.h:138
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition MCInst.h:145
llvm::MCOperand::setReg
void setReg(MCRegister Reg)
Set the register number.
Definition MCInst.h:79
llvm::MCOperand::isReg
bool isReg() const
Definition MCInst.h:65
llvm::MCOperand::getReg
MCRegister getReg() const
Returns the register number.
Definition MCInst.h:73
llvm::MCOperand::getInst
const MCInst * getInst() const
Definition MCInst.h:128
llvm::MCOperand::getExpr
const MCExpr * getExpr() const
Definition MCInst.h:118
llvm::MCOperand::createInst
static MCOperand createInst(const MCInst *Val)
Definition MCInst.h:173
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition MCSubtargetInfo.h:142
llvm::Register
Wrapper class representing virtual and physical registers.
Definition Register.h:20
llvm::Target
Target - Wrapper for Target specific information.
Definition TargetRegistry.h:138
llvm::Value
LLVM Value Representation.
Definition Value.h:75
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition raw_ostream.h:53
uint16_t
uint32_t
llvm::HexagonMCInstrInfo::addConstant
void addConstant(MCInst &MI, uint64_t Value, MCContext &Context)
Definition HexagonMCInstrInfo.cpp:82
llvm::HexagonMCInstrInfo::IsReverseVecRegPair
bool IsReverseVecRegPair(MCRegister VecReg)
Definition HexagonMCInstrInfo.cpp:702
llvm::HexagonMCInstrInfo::bundleSize
size_t bundleSize(MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:116
llvm::HexagonMCInstrInfo::isDuplex
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:622
llvm::HexagonMCInstrInfo::getExtentBits
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:338
llvm::HexagonMCInstrInfo::isNewValue
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn expects newly produced value.
Definition HexagonMCInstrInfo.cpp:673
llvm::HexagonMCInstrInfo::getNewValueOp
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:377
llvm::HexagonMCInstrInfo::isHLX
bool isHLX(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:648
llvm::HexagonMCInstrInfo::getExtendableOp
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:314
llvm::HexagonMCInstrInfo::IsVecRegPair
bool IsVecRegPair(MCRegister VecReg)
Definition HexagonMCInstrInfo.cpp:697
llvm::HexagonMCInstrInfo::bundleInstructions
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:103
llvm::HexagonMCInstrInfo::isExtendable
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:626
llvm::HexagonMCInstrInfo::extenderForIndex
MCInst const * extenderForIndex(MCInst const &MCB, size_t Index)
Definition HexagonMCInstrInfo.cpp:220
llvm::HexagonMCInstrInfo::isImmext
bool isImmext(MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:653
llvm::HexagonMCInstrInfo::getNewValueOperand
MCOperand const & getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:383
llvm::HexagonMCInstrInfo::hasNewValue2
bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a second value.
Definition HexagonMCInstrInfo.cpp:518
llvm::HexagonMCInstrInfo::getExtentAlignment
unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:332
llvm::HexagonMCInstrInfo::isVector
bool isVector(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:872
llvm::HexagonMCInstrInfo::getNewValueOperand2
MCOperand const & getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:409
llvm::HexagonMCInstrInfo::isExtended
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI)
Definition HexagonMCInstrInfo.cpp:632
llvm::HexagonMCInstrInfo::hasNewValue
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI)
Return whether the insn produces a value.
Definition HexagonMCInstrInfo.cpp:511
llvm::Hexagon_MC::getArchSubtarget
MCSubtargetInfo const * getArchSubtarget(MCSubtargetInfo const *STI)
Definition HexagonMCTargetDesc.cpp:561
llvm::ms_demangle::QualifierMangleMode::Result
@ Result
Definition MicrosoftDemangle.h:132
llvm::sandboxir::Instruction
friend class Instruction
Iterator for Instructions in a `BasicBlock.
Definition BasicBlock.h:73
llvm::support::endian::read32le
uint32_t read32le(const void *P)
Definition Endian.h:412
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition DefaultTargetInfo.h:21
llvm::Offset
@ Offset
Definition DWP.cpp:577
llvm::getTheHexagonTarget
Target & getTheHexagonTarget()
Definition HexagonTargetInfo.cpp:14
llvm::M1
unsigned M1(unsigned Val)
Definition VE.h:394
llvm::MCPhysReg
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition MCRegister.h:21
llvm::M0
unsigned M0(unsigned Val)
Definition VE.h:393
llvm::SignExtend64
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition MathExtras.h:572
raw_ostream.h
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition TargetRegistry.h:900
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