46 int &FrameIndex)
const {
47 unsigned Opc =
MI.getOpcode();
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
51 if ((
MI.getOperand(1).isFI()) &&
52 (
MI.getOperand(2).isImm()) &&
54 FrameIndex =
MI.getOperand(1).getIndex();
55 return MI.getOperand(0).getReg();
68 int &FrameIndex)
const {
69 unsigned Opc =
MI.getOpcode();
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
73 if ((
MI.getOperand(1).isFI()) &&
74 (
MI.getOperand(2).isImm()) &&
76 FrameIndex =
MI.getOperand(1).getIndex();
77 return MI.getOperand(0).getReg();
87 unsigned Opc = 0, ZeroReg = 0;
90 if (Mips::GPR32RegClass.
contains(DestReg)) {
91 if (Mips::GPR32RegClass.
contains(SrcReg)) {
93 Opc = Mips::MOVE16_MM;
95 Opc = Mips::OR, ZeroReg = Mips::ZERO;
96 }
else if (Mips::CCRRegClass.
contains(SrcReg))
98 else if (Mips::FGR32RegClass.
contains(SrcReg))
100 else if (Mips::HI32RegClass.
contains(SrcReg)) {
103 }
else if (Mips::LO32RegClass.
contains(SrcReg)) {
106 }
else if (Mips::HI32DSPRegClass.
contains(SrcReg))
107 Opc = Mips::MFHI_DSP;
108 else if (Mips::LO32DSPRegClass.
contains(SrcReg))
109 Opc = Mips::MFLO_DSP;
110 else if (Mips::DSPCCRegClass.
contains(SrcReg)) {
115 else if (Mips::MSACtrlRegClass.
contains(SrcReg))
118 else if (Mips::GPR32RegClass.
contains(SrcReg)) {
119 if (Mips::CCRRegClass.
contains(DestReg))
121 else if (Mips::FGR32RegClass.
contains(DestReg))
123 else if (Mips::HI32RegClass.
contains(DestReg))
124 Opc = Mips::MTHI, DestReg = 0;
125 else if (Mips::LO32RegClass.
contains(DestReg))
126 Opc = Mips::MTLO, DestReg = 0;
127 else if (Mips::HI32DSPRegClass.
contains(DestReg))
128 Opc = Mips::MTHI_DSP;
129 else if (Mips::LO32DSPRegClass.
contains(DestReg))
130 Opc = Mips::MTLO_DSP;
131 else if (Mips::DSPCCRegClass.
contains(DestReg)) {
136 }
else if (Mips::MSACtrlRegClass.
contains(DestReg)) {
143 else if (Mips::FGR32RegClass.
contains(DestReg, SrcReg))
145 else if (Mips::AFGR64RegClass.
contains(DestReg, SrcReg))
146 Opc = Mips::FMOV_D32;
147 else if (Mips::FGR64RegClass.
contains(DestReg, SrcReg))
148 Opc = Mips::FMOV_D64;
149 else if (Mips::GPR64RegClass.
contains(DestReg)) {
150 if (Mips::GPR64RegClass.
contains(SrcReg))
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
152 else if (Mips::HI64RegClass.
contains(SrcReg))
153 Opc = Mips::MFHI64, SrcReg = 0;
154 else if (Mips::LO64RegClass.
contains(SrcReg))
155 Opc = Mips::MFLO64, SrcReg = 0;
156 else if (Mips::FGR64RegClass.
contains(SrcReg))
159 else if (Mips::GPR64RegClass.
contains(SrcReg)) {
160 if (Mips::HI64RegClass.
contains(DestReg))
161 Opc = Mips::MTHI64, DestReg = 0;
162 else if (Mips::LO64RegClass.
contains(DestReg))
163 Opc = Mips::MTLO64, DestReg = 0;
164 else if (Mips::FGR64RegClass.
contains(DestReg))
167 else if (Mips::MSA128BRegClass.
contains(DestReg)) {
168 if (Mips::MSA128BRegClass.
contains(SrcReg))
172 assert(Opc &&
"Cannot copy registers");
187 switch (
MI.getOpcode()) {
192 if (
MI.getOperand(2).getReg() == Mips::ZERO)
196 if (
MI.getOperand(2).getReg() == Mips::ZERO_64)
206 switch (
MI.getOpcode()) {
224std::optional<DestSourcePair>
226 bool isDSPControlWrite =
false;
230 if (!
MI.getOperand(1).isImm() ||
MI.getOperand(1).getImm() != (1 << 4))
232 else if (isDSPControlWrite) {
246 Register SrcReg,
bool isKill,
int FI,
254 if (Mips::GPR32RegClass.hasSubClassEq(RC))
256 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
258 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
259 Opc = Mips::STORE_ACC64;
260 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
261 Opc = Mips::STORE_ACC64DSP;
262 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
263 Opc = Mips::STORE_ACC128;
264 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
265 Opc = Mips::STORE_CCOND_DSP;
266 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
268 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
270 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
283 else if (Mips::LO32RegClass.hasSubClassEq(RC))
285 else if (Mips::LO64RegClass.hasSubClassEq(RC))
287 else if (Mips::HI32RegClass.hasSubClassEq(RC))
289 else if (Mips::HI64RegClass.hasSubClassEq(RC))
291 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
297 if (Func.hasFnAttribute(
"interrupt")) {
298 if (Mips::HI32RegClass.hasSubClassEq(RC)) {
301 }
else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
303 SrcReg = Mips::K0_64;
304 }
else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
307 }
else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
309 SrcReg = Mips::K0_64;
313 assert(Opc &&
"Register class not handled!");
328 bool ReqIndirectLoad = Func.hasFnAttribute(
"interrupt") &&
329 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
330 DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
332 if (Mips::GPR32RegClass.hasSubClassEq(RC))
334 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
336 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
337 Opc = Mips::LOAD_ACC64;
338 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
339 Opc = Mips::LOAD_ACC64DSP;
340 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
341 Opc = Mips::LOAD_ACC128;
342 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
343 Opc = Mips::LOAD_CCOND_DSP;
344 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
346 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
348 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
361 else if (Mips::HI32RegClass.hasSubClassEq(RC))
363 else if (Mips::HI64RegClass.hasSubClassEq(RC))
365 else if (Mips::LO32RegClass.hasSubClassEq(RC))
367 else if (Mips::LO64RegClass.hasSubClassEq(RC))
369 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
372 assert(Opc &&
"Register class not handled!");
374 if (!ReqIndirectLoad)
382 unsigned Reg = Mips::K0;
383 unsigned LdOp = Mips::MTLO;
384 if (DestReg == Mips::HI0)
389 if (DestReg == Mips::HI0_64)
408 switch (
MI.getDesc().getOpcode()) {
412 expandRetRA(
MBB,
MI);
417 case Mips::PseudoMFHI:
418 expandPseudoMFHiLo(
MBB,
MI, Mips::MFHI);
420 case Mips::PseudoMFHI_MM:
421 expandPseudoMFHiLo(
MBB,
MI, Mips::MFHI16_MM);
423 case Mips::PseudoMFLO:
424 expandPseudoMFHiLo(
MBB,
MI, Mips::MFLO);
426 case Mips::PseudoMFLO_MM:
427 expandPseudoMFHiLo(
MBB,
MI, Mips::MFLO16_MM);
429 case Mips::PseudoMFHI64:
430 expandPseudoMFHiLo(
MBB,
MI, Mips::MFHI64);
432 case Mips::PseudoMFLO64:
433 expandPseudoMFHiLo(
MBB,
MI, Mips::MFLO64);
435 case Mips::PseudoMTLOHI:
436 expandPseudoMTLoHi(
MBB,
MI, Mips::MTLO, Mips::MTHI,
false);
438 case Mips::PseudoMTLOHI64:
439 expandPseudoMTLoHi(
MBB,
MI, Mips::MTLO64, Mips::MTHI64,
false);
441 case Mips::PseudoMTLOHI_DSP:
442 expandPseudoMTLoHi(
MBB,
MI, Mips::MTLO_DSP, Mips::MTHI_DSP,
true);
444 case Mips::PseudoMTLOHI_MM:
445 expandPseudoMTLoHi(
MBB,
MI, Mips::MTLO_MM, Mips::MTHI_MM,
false);
447 case Mips::PseudoCVT_S_W:
448 expandCvtFPInt(
MBB,
MI, Mips::CVT_S_W, Mips::MTC1,
false);
450 case Mips::PseudoCVT_D32_W:
451 Opc =
isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W;
452 expandCvtFPInt(
MBB,
MI, Opc, Mips::MTC1,
false);
454 case Mips::PseudoCVT_S_L:
455 expandCvtFPInt(
MBB,
MI, Mips::CVT_S_L, Mips::DMTC1,
true);
457 case Mips::PseudoCVT_D64_W:
458 Opc =
isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W;
459 expandCvtFPInt(
MBB,
MI, Opc, Mips::MTC1,
true);
461 case Mips::PseudoCVT_D64_L:
462 expandCvtFPInt(
MBB,
MI, Mips::CVT_D64_L, Mips::DMTC1,
true);
464 case Mips::BuildPairF64:
467 case Mips::BuildPairF64_64:
470 case Mips::ExtractElementF64:
473 case Mips::ExtractElementF64_64:
476 case Mips::MIPSeh_return32:
477 case Mips::MIPSeh_return64:
478 expandEhReturn(
MBB,
MI);
505 case Mips::BEQ:
return Mips::BNE;
506 case Mips::BEQ_MM:
return Mips::BNE_MM;
507 case Mips::BNE:
return Mips::BEQ;
508 case Mips::BNE_MM:
return Mips::BEQ_MM;
509 case Mips::BGTZ:
return Mips::BLEZ;
510 case Mips::BGEZ:
return Mips::BLTZ;
511 case Mips::BLTZ:
return Mips::BGEZ;
512 case Mips::BLEZ:
return Mips::BGTZ;
513 case Mips::BGTZ_MM:
return Mips::BLEZ_MM;
514 case Mips::BGEZ_MM:
return Mips::BLTZ_MM;
515 case Mips::BLTZ_MM:
return Mips::BGEZ_MM;
516 case Mips::BLEZ_MM:
return Mips::BGTZ_MM;
517 case Mips::BEQ64:
return Mips::BNE64;
518 case Mips::BNE64:
return Mips::BEQ64;
519 case Mips::BGTZ64:
return Mips::BLEZ64;
520 case Mips::BGEZ64:
return Mips::BLTZ64;
521 case Mips::BLTZ64:
return Mips::BGEZ64;
522 case Mips::BLEZ64:
return Mips::BGTZ64;
523 case Mips::BC1T:
return Mips::BC1F;
524 case Mips::BC1F:
return Mips::BC1T;
525 case Mips::BC1T_MM:
return Mips::BC1F_MM;
526 case Mips::BC1F_MM:
return Mips::BC1T_MM;
527 case Mips::BEQZ16_MM:
return Mips::BNEZ16_MM;
528 case Mips::BNEZ16_MM:
return Mips::BEQZ16_MM;
529 case Mips::BEQZC_MM:
return Mips::BNEZC_MM;
530 case Mips::BNEZC_MM:
return Mips::BEQZC_MM;
531 case Mips::BEQZC:
return Mips::BNEZC;
532 case Mips::BNEZC:
return Mips::BEQZC;
533 case Mips::BLEZC:
return Mips::BGTZC;
534 case Mips::BGEZC:
return Mips::BLTZC;
535 case Mips::BGEC:
return Mips::BLTC;
536 case Mips::BGTZC:
return Mips::BLEZC;
537 case Mips::BLTZC:
return Mips::BGEZC;
538 case Mips::BLTC:
return Mips::BGEC;
539 case Mips::BGEUC:
return Mips::BLTUC;
540 case Mips::BLTUC:
return Mips::BGEUC;
541 case Mips::BEQC:
return Mips::BNEC;
542 case Mips::BNEC:
return Mips::BEQC;
543 case Mips::BC1EQZ:
return Mips::BC1NEZ;
544 case Mips::BC1NEZ:
return Mips::BC1EQZ;
545 case Mips::BEQZC_MMR6:
return Mips::BNEZC_MMR6;
546 case Mips::BNEZC_MMR6:
return Mips::BEQZC_MMR6;
547 case Mips::BLEZC_MMR6:
return Mips::BGTZC_MMR6;
548 case Mips::BGEZC_MMR6:
return Mips::BLTZC_MMR6;
549 case Mips::BGEC_MMR6:
return Mips::BLTC_MMR6;
550 case Mips::BGTZC_MMR6:
return Mips::BLEZC_MMR6;
551 case Mips::BLTZC_MMR6:
return Mips::BGEZC_MMR6;
552 case Mips::BLTC_MMR6:
return Mips::BGEC_MMR6;
553 case Mips::BGEUC_MMR6:
return Mips::BLTUC_MMR6;
554 case Mips::BLTUC_MMR6:
return Mips::BGEUC_MMR6;
555 case Mips::BEQC_MMR6:
return Mips::BNEC_MMR6;
556 case Mips::BNEC_MMR6:
return Mips::BEQC_MMR6;
557 case Mips::BC1EQZC_MMR6:
return Mips::BC1NEZC_MMR6;
558 case Mips::BC1NEZC_MMR6:
return Mips::BC1EQZC_MMR6;
559 case Mips::BEQZC64:
return Mips::BNEZC64;
560 case Mips::BNEZC64:
return Mips::BEQZC64;
561 case Mips::BEQC64:
return Mips::BNEC64;
562 case Mips::BNEC64:
return Mips::BEQC64;
563 case Mips::BGEC64:
return Mips::BLTC64;
564 case Mips::BGEUC64:
return Mips::BLTUC64;
565 case Mips::BLTC64:
return Mips::BGEC64;
566 case Mips::BLTUC64:
return Mips::BGEUC64;
567 case Mips::BGTZC64:
return Mips::BLEZC64;
568 case Mips::BGEZC64:
return Mips::BLTZC64;
569 case Mips::BLTZC64:
return Mips::BGEZC64;
570 case Mips::BLEZC64:
return Mips::BGTZC64;
571 case Mips::BBIT0:
return Mips::BBIT1;
572 case Mips::BBIT1:
return Mips::BBIT0;
573 case Mips::BBIT032:
return Mips::BBIT132;
574 case Mips::BBIT132:
return Mips::BBIT032;
575 case Mips::BZ_B:
return Mips::BNZ_B;
576 case Mips::BZ_H:
return Mips::BNZ_H;
577 case Mips::BZ_W:
return Mips::BNZ_W;
578 case Mips::BZ_D:
return Mips::BNZ_D;
579 case Mips::BZ_V:
return Mips::BNZ_V;
580 case Mips::BNZ_B:
return Mips::BZ_B;
581 case Mips::BNZ_H:
return Mips::BZ_H;
582 case Mips::BNZ_W:
return Mips::BZ_W;
583 case Mips::BNZ_D:
return Mips::BZ_D;
584 case Mips::BNZ_V:
return Mips::BZ_V;
594 unsigned ADDiu = ABI.GetPtrAddiuOp();
599 if (isInt<16>(Amount)) {
605 unsigned Opc = ABI.GetPtrAdduOp();
607 Opc = ABI.GetPtrSubuOp();
620 unsigned *NewImm)
const {
625 unsigned LUi = STI.
isABI_N64() ? Mips::LUi64 : Mips::LUi;
626 unsigned ZEROReg = STI.
isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
628 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
629 bool LastInstrIsADDiu = NewImm;
642 if (Inst->Opc == LUi)
646 .
addImm(SignExtend64<16>(Inst->ImmOpnd));
649 for (++Inst; Inst != Seq.
end() - LastInstrIsADDiu; ++Inst)
651 .
addImm(SignExtend64<16>(Inst->ImmOpnd));
653 if (LastInstrIsADDiu)
654 *NewImm = Inst->ImmOpnd;
659unsigned MipsSEInstrInfo::getAnalyzableBrOpc(
unsigned Opc)
const {
660 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
661 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
662 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
663 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
664 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
665 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
666 Opc == Mips::J_MM || Opc == Mips::B_MM || Opc == Mips::BEQZC_MM ||
667 Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC ||
668 Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC ||
669 Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC ||
670 Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC ||
671 Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 ||
672 Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 ||
673 Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 ||
674 Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||
675 Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||
676 Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
677 Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 ||
678 Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 ||
679 Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 ||
680 Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 ||
681 Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 ||
682 Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 ||
683 Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0;
698 for (
auto & MO :
I->operands()) {
710MipsSEInstrInfo::compareOpndSize(
unsigned Opc,
715 unsigned DstRegSize = RI->getRegSizeInBits(*
getRegClass(Desc, 0, RI, MF));
716 unsigned SrcRegSize = RI->getRegSizeInBits(*
getRegClass(Desc, 1, RI, MF));
718 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
723 unsigned NewOpc)
const {
731 bool HasExplicitDef)
const {
745 if (HasExplicitDef) {
746 Register DstReg =
I->getOperand(0).getReg();
759 unsigned CvtOpc,
unsigned MovOpc,
763 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
766 bool DstIsLarger, SrcIsLarger;
768 std::tie(DstIsLarger, SrcIsLarger) =
785 Register DstReg =
I->getOperand(0).getReg();
786 Register SrcReg =
I->getOperand(1).getReg();
787 unsigned N =
I->getOperand(2).getImm();
790 assert(
N < 2 &&
"Invalid immediate");
791 unsigned SubIdx =
N ? Mips::sub_hi : Mips::sub_lo;
816 get(
isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)
817 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)),
827 Register DstReg =
I->getOperand(0).getReg();
828 unsigned LoReg =
I->getOperand(1).getReg(), HiReg =
I->getOperand(2).getReg();
872 get(
isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
873 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),
890 unsigned ADDU =
ABI.GetPtrAdduOp();
895 Register OffsetReg =
I->getOperand(0).getReg();
896 Register TargetReg =
I->getOperand(1).getReg();
902 if (
TM.isPositionIndependent())
static const TargetRegisterClass * getRegClass(const MachineInstr &MI, Register Reg)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ ZERO
Special weight used for cases with exact zero probability.
unsigned const TargetRegisterInfo * TRI
static bool isORCopyInst(const MachineInstr &MI)
static unsigned getUnconditionalBranch(const MipsSubtarget &STI)
static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite)
If @MI is WRDSP/RRDSP instruction return true with @isWrite set to true if it is WRDSP instruction.
static bool isMicroMips(const MCSubtargetInfo *STI)
const char LLVMTargetMachineRef TM
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Describe properties that are true of each instruction in the target description file.
unsigned short NumOperands
Wrapper class representing physical registers. Should be passed by value.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
bool ArePtrs64bit() const
const MipsSubtarget & Subtarget
MachineMemOperand * GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const
bool isZeroImm(const MachineOperand &op) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
Adjust SP by Amount bytes.
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot,...
void loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot,...
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, unsigned *NewImm) const
Emit a series of instructions to load an immediate.
bool isBranchWithImm(unsigned Opc) const override
isBranchWithImm - Return true if the branch contains an immediate operand (
MipsSEInstrInfo(const MipsSubtarget &STI)
void storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, int64_t Offset) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
const MipsRegisterInfo & getRegisterInfo() const override
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
unsigned getOppositeBranchOpc(unsigned Opc) const override
getOppositeBranchOpc - Return the inverse of the specified opcode, e.g.
bool inMicroMipsMode() const
bool isPositionIndependent() const
const MipsABIInfo & getABI() const
Wrapper class representing virtual and physical registers.
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Kill
The last use of a register.
@ Undef
Value of the register doesn't matter.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
const MipsInstrInfo * createMipsSEInstrInfo(const MipsSubtarget &STI)
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
unsigned getKillRegState(bool B)