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35 RegInfo &RI = RegInfos[R];
36 if (RI.RegClass !=
nullptr && !BadRC[R]) {
37 if (RC->LaneMask != RI.RegClass->LaneMask) {
39 RI.RegClass =
nullptr;
49 if (UnitInfos[U].
Reg != 0)
60 std::pair<uint32_t,LaneBitmask>
P = *
I;
61 UnitInfo &UI = UnitInfos[
P.first];
67 UI.Mask = RC->LaneMask;
83 MaskInfos.resize(RegMasks.
size()+1);
88 if (!(MB[
I / 32] & (1u << (
I % 32))))
93 MaskInfos[
M].Units = PU.
flip();
102 AliasInfos[U].Regs = AS;
108 std::set<RegisterId> AS;
114 if (MB[
i/32] & (1u << (
i%32)))
143 while (UMA.isValid() && UMB.isValid()) {
145 std::pair<RegisterId,LaneBitmask> PA = *UMA;
146 if (PA.second.any() && (PA.second &
RA.Mask).none()) {
151 std::pair<RegisterId,LaneBitmask>
PB = *UMB;
152 if (
PB.second.any() && (
PB.second & RB.
Mask).none()) {
157 if (PA.first ==
PB.first)
159 if (PA.first <
PB.first)
161 else if (
PB.first < PA.first)
170 bool Preserved = MB[RR.
Reg/32] & (1u << (RR.
Reg%32));
188 if ((SM & RR.
Mask).none())
190 unsigned SR =
SI.getSubReg();
191 if (!(MB[SR/32] & (1u << (SR%32))))
208 for (
unsigned w = 0, nw = NumRegs/32; w != nw; ++w) {
219 unsigned TailRegs = NumRegs % 32;
222 unsigned TW = NumRegs / 32;
223 uint32_t TailMask = (1u << TailRegs) - 1;
224 if (~BM[TW] & ~BN[TW] & TailMask)
236 const RegInfo &RI = RegInfos[R];
237 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask
250 std::pair<uint32_t,LaneBitmask>
P = *U;
251 if (
P.second.none() || (
P.second & RR.
Mask).any())
252 if (Units.
test(
P.first))
261 return T.reset(Units).none();
265 std::pair<uint32_t,LaneBitmask>
P = *U;
266 if (
P.second.none() || (
P.second & RR.
Mask).any())
267 if (!Units.
test(
P.first))
280 std::pair<uint32_t,LaneBitmask>
P = *U;
281 if (
P.second.none() || (
P.second & RR.
Mask).any())
306 Units.
reset(RG.Units);
312 T.insert(RR).intersect(*
this);
321 return RegisterAggr(PRI).insert(RR).clear(*this).makeRegRef();
353 std::pair<uint32_t,LaneBitmask>
P = *
I;
354 if (Units.
test(
P.first))
370 for (
int U = RG.Units.find_first(); U >= 0; U = RG.Units.find_next(U)) {
372 Masks[R.Reg] |= R.Mask;
374 Pos = End ? Masks.end() : Masks.begin();
375 Index = End ? Masks.size() : 0;
This is an optimization pass for GlobalISel generic memory operations.
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices.
RegisterRef makeRegRef() const
RegisterAggr & insert(RegisterRef RR)
RegisterAggr & clear(RegisterRef RR)
bool isValid() const
Returns true if this iterator is not yet at the end.
static MCRegister from(unsigned Val)
Check the provided unsigned value is a valid MCRegister.
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Reg
All possible values of the reg field in the ModR/M byte.
T get(uint32_t Idx) const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
RegisterId getRegMaskId(const uint32_t *RM) const
unsigned const TargetRegisterInfo * TRI
const BitVector & getMaskUnits(RegisterId MaskId) const
PhysicalRegisterInfo(const TargetRegisterInfo &tri, const MachineFunction &mf)
RegisterAggr(const PhysicalRegisterInfo &pri)
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static bool isRegMaskId(RegisterId R)
(vector float) vec_cmpeq(*A, *B) C
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
This class implements an extremely fast bulk output stream that can only output to a stream.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
const BitVector & getUnitAliases(uint32_t U) const
bool hasCoverOf(RegisterRef RR) const
iterator_range< regclass_iterator > regclasses() const
PassBuilder PB(Machine, PassOpts->PTO, None, &PIC)
const LaneBitmask LaneMask
Representation of each machine instruction.
bool hasAliasOf(RegisterRef RR) const
rr_iterator(const RegisterAggr &RG, bool End)
RegisterAggr & intersect(RegisterRef RR)
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.
raw_ostream & operator<<(raw_ostream &OS, const Print< RegisterRef > &P)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::set< RegisterId > getAliasSet(RegisterId Reg) const
StandardInstrumentations SI(Debug, VerifyEach)
MCSuperRegIterator enumerates all super-registers of Reg.
SI optimize exec mask operations pre RA
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
RegisterRef intersectWith(RegisterRef RR) const
bool test(unsigned Idx) const
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
MCRegUnitRootIterator enumerates the root registers of a register unit.
RegisterRef clearIn(RegisterRef RR) const
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
const uint32_t * getRegMaskBits(RegisterId R) const
bool anyCommon(const BitVector &RHS) const
Test if any common bits are set.
void print(raw_ostream &OS) const
It looks like we only need to define PPCfmarto for these because according to these instructions perform RTO on fma s src2 rnd ← FPSCR RN
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
static constexpr LaneBitmask getAll()
RegisterRef mapTo(RegisterRef RR, unsigned R) const
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
MCRegAliasIterator enumerates all registers aliasing Reg.
const TargetRegisterInfo & getTRI() const