35 RegInfo &RI = RegInfos[R];
36 if (RI.RegClass !=
nullptr && !BadRC[R]) {
37 if (RC->LaneMask != RI.RegClass->LaneMask) {
39 RI.RegClass =
nullptr;
49 if (UnitInfos[U].Reg != 0)
60 std::pair<uint32_t,LaneBitmask>
P = *
I;
61 UnitInfo &UI = UnitInfos[
P.first];
67 UI.Mask = RC->LaneMask;
81 RegMasks.
insert(Op.getRegMask());
83 MaskInfos.resize(RegMasks.
size()+1);
84 for (
uint32_t M = 1, NM = RegMasks.
size(); M <= NM; ++M) {
88 if (!(MB[
I / 32] & (1u << (
I % 32))))
93 MaskInfos[M].Units = PU.
flip();
102 AliasInfos[U].Regs = AS;
108 std::set<RegisterId> AS;
113 for (
unsigned i = 1, e = TRI.
getNumRegs(); i != e; ++i) {
114 if (MB[i/32] & (1u << (i%32)))
118 for (
const uint32_t *RM : RegMasks) {
128 for (
const uint32_t *RM : RegMasks) {
143 while (UMA.isValid() && UMB.isValid()) {
145 std::pair<RegisterId,LaneBitmask> PA = *UMA;
146 if (PA.second.any() && (PA.second &
RA.Mask).none()) {
151 std::pair<RegisterId,LaneBitmask>
PB = *UMB;
152 if (
PB.second.any() && (
PB.second & RB.
Mask).none()) {
157 if (PA.first ==
PB.first)
159 if (PA.first <
PB.first)
161 else if (
PB.first < PA.first)
170 bool Preserved = MB[RR.
Reg/32] & (1u << (RR.
Reg%32));
188 if ((SM & RR.
Mask).none())
190 unsigned SR =
SI.getSubReg();
191 if (!(MB[SR/32] & (1u << (SR%32))))
208 for (
unsigned w = 0, nw = NumRegs/32; w != nw; ++w) {
219 unsigned TailRegs = NumRegs % 32;
222 unsigned TW = NumRegs / 32;
223 uint32_t TailMask = (1u << TailRegs) - 1;
224 if (~BM[TW] & ~BN[TW] & TailMask)
236 const RegInfo &RI = RegInfos[R];
237 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask
250 std::pair<uint32_t,LaneBitmask>
P = *U;
251 if (
P.second.none() || (
P.second & RR.
Mask).any())
252 if (Units.
test(
P.first))
261 return T.reset(Units).none();
265 std::pair<uint32_t,LaneBitmask>
P = *U;
266 if (
P.second.none() || (
P.second & RR.
Mask).any())
267 if (!Units.
test(
P.first))
280 std::pair<uint32_t,LaneBitmask>
P = *U;
281 if (
P.second.none() || (
P.second & RR.
Mask).any())
306 Units.
reset(RG.Units);
312 T.insert(RR).intersect(*
this);
353 std::pair<uint32_t,LaneBitmask>
P = *
I;
354 if (Units.
test(
P.first))
372 Masks[R.Reg] |= R.Mask;
374 Pos =
End ? Masks.end() : Masks.begin();
This file implements the BitVector class.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
A common definition of LaneBitmask for use in TableGen and CodeGen.
unsigned const TargetRegisterInfo * TRI
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
bool test(unsigned Idx) const
int find_first() const
find_first - Returns the index of the first set bit, -1 if none of the bits are set.
bool anyCommon(const BitVector &RHS) const
Test if any common bits are set.
int find_next(unsigned Prev) const
find_next - Returns the index of the next set bit following the "Prev" bit.
MCRegAliasIterator enumerates all registers aliasing Reg.
MCRegUnitMaskIterator enumerates a list of register units and their associated lane masks for Reg.
MCRegUnitRootIterator enumerates the root registers of a register unit.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
iterator_range< mc_superreg_iterator > superregs_inclusive(MCRegister Reg) const
Return an iterator range over all super-registers of Reg, including Reg.
unsigned getSubRegIndex(MCRegister RegNo, MCRegister SubRegNo) const
For a given register pair, return the sub-register index if the second register is a sub-register of ...
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
static MCRegister from(unsigned Val)
Check the provided unsigned value is a valid MCRegister.
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
const LaneBitmask LaneMask
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
iterator_range< regclass_iterator > regclasses() const
virtual ArrayRef< const uint32_t * > getRegMasks() const =0
Return all the call-preserved register masks defined for this target.
LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask LaneMask) const
Transform a lanemask given for a virtual register to the corresponding lanemask before using subregis...
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, LaneBitmask Mask) const
Transforms a LaneMask computed for one subregister to the lanemask that would have been computed when...
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
raw_ostream & operator<<(raw_ostream &OS, const Print< RegisterRef > &P)
This is an optimization pass for GlobalISel generic memory operations.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
static constexpr LaneBitmask getAll()
T get(uint32_t Idx) const
const BitVector & getMaskUnits(RegisterId MaskId) const
RegisterId getRegMaskId(const uint32_t *RM) const
PhysicalRegisterInfo(const TargetRegisterInfo &tri, const MachineFunction &mf)
const TargetRegisterInfo & getTRI() const
static bool isRegMaskId(RegisterId R)
const uint32_t * getRegMaskBits(RegisterId R) const
const BitVector & getUnitAliases(uint32_t U) const
std::set< RegisterId > getAliasSet(RegisterId Reg) const
RegisterRef mapTo(RegisterRef RR, unsigned R) const
RegisterRef getRefForUnit(uint32_t U) const
rr_iterator(const RegisterAggr &RG, bool End)
RegisterAggr & insert(RegisterRef RR)
bool hasAliasOf(RegisterRef RR) const
bool hasCoverOf(RegisterRef RR) const
RegisterRef clearIn(RegisterRef RR) const
void print(raw_ostream &OS) const
RegisterRef makeRegRef() const
RegisterRef intersectWith(RegisterRef RR) const
RegisterAggr & intersect(RegisterRef RR)
RegisterAggr & clear(RegisterRef RR)