Go to the documentation of this file.
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
47 std::vector<SDValue> &OutOps)
override;
80 const unsigned Depth = 0)
const;
98 const SDLoc &
DL,
unsigned CurOp,
99 bool IsMasked,
bool IsStridedOrIndexed,
101 bool IsLoad =
false,
MVT *IndexVT =
nullptr);
134 #include "RISCVGenDAGISel.inc"
139 bool doPeepholeMergeVVMFold();
140 bool performVMergeToVAdd(
SDNode *
N);
141 bool performCombineVMergeAndVOps(
SDNode *
N,
bool IsTA);
221 #define GET_RISCVVSSEGTable_DECL
222 #define GET_RISCVVLSEGTable_DECL
223 #define GET_RISCVVLXSEGTable_DECL
224 #define GET_RISCVVSXSEGTable_DECL
225 #define GET_RISCVVLETable_DECL
226 #define GET_RISCVVSETable_DECL
227 #define GET_RISCVVLXTable_DECL
228 #define GET_RISCVVSXTable_DECL
229 #define GET_RISCVMaskedPseudosTable_DECL
230 #include "RISCVGenSearchableTables.inc"
void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
This is an optimization pass for GlobalISel generic memory operations.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal)
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
bool selectRVVSimm5(SDValue N, SDValue &Imm)
void selectVSETVLI(SDNode *Node)
bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
Represents one node in the SelectionDAG.
bool selectVSplat(SDValue N, SDValue &SplatVal)
bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val)
void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided)
bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal)
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset)
uint16_t UnmaskedTUPseudo
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
CodeGenOpt::Level OptLevel
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
bool selectShiftMask32(SDValue N, SDValue &ShAmt)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC)
mir Rename Register Operands
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
bool selectVLOp(SDValue N, SDValue &VL)
void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt)
bool selectVSplatUimm5(SDValue N, SDValue &SplatVal)
bool selectSHXADD_UWOp(SDValue N, SDValue &Val)
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided)
Primary interface to the complete machine description for the target machine.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
bool hasAllWUsers(SDNode *Node) const
bool selectVSplatSimm5(SDValue N, SDValue &SplatVal)
RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOpt::Level OptLevel)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
bool hasAllNBitUsers(SDNode *Node, unsigned Bits, const unsigned Depth=0) const
RISCVDAGToDAGISel()=delete
void PostprocessISelDAG() override
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
void selectVLSEGFF(SDNode *Node, bool IsMasked)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
bool selectZExtBits(SDValue N, SDValue &Val)
bool tryShrinkShlLogicImm(SDNode *Node)
bool selectSHXADDOp(SDValue N, SDValue &Val)
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm)
void Select(SDNode *Node) override
Main hook for targets to transform nodes into machine nodes.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Level
Code generation optimization level.
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
bool hasAllHUsers(SDNode *Node) const
bool selectSExti32(SDValue N, SDValue &Val)
void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)