LLVM  14.0.0git
RISCVISelDAGToDAG.h
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1 //===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISCV ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines an instruction selector for the RISCV target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
15 
16 #include "RISCV.h"
17 #include "RISCVTargetMachine.h"
19 
20 // RISCV-specific code to select RISCV machine instructions for
21 // SelectionDAG operations.
22 namespace llvm {
24  const RISCVSubtarget *Subtarget = nullptr;
25 
26 public:
29 
30  StringRef getPassName() const override {
31  return "RISCV DAG->DAG Pattern Instruction Selection";
32  }
33 
35  Subtarget = &MF.getSubtarget<RISCVSubtarget>();
37  }
38 
39  void PreprocessISelDAG() override;
40  void PostprocessISelDAG() override;
41 
42  void Select(SDNode *Node) override;
43 
44  bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
45  std::vector<SDValue> &OutOps) override;
46 
49 
50  bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
52  return selectShiftMask(N, Subtarget->getXLen(), ShAmt);
53  }
55  return selectShiftMask(N, 32, ShAmt);
56  }
57 
58  bool selectSExti32(SDValue N, SDValue &Val);
59  bool selectZExti32(SDValue N, SDValue &Val);
60 
61  bool hasAllNBitUsers(SDNode *Node, unsigned Bits) const;
62  bool hasAllHUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 16); }
63  bool hasAllWUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 32); }
64 
65  bool selectVLOp(SDValue N, SDValue &VL);
66 
67  bool selectVSplat(SDValue N, SDValue &SplatVal);
68  bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
69  bool selectVSplatUimm5(SDValue N, SDValue &SplatVal);
70  bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
72 
73  bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm);
74  template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) {
75  return selectRVVSimm5(N, Width, Imm);
76  }
77 
78  void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm,
79  const SDLoc &DL, unsigned CurOp,
80  bool IsMasked, bool IsStridedOrIndexed,
82  bool IsLoad = false, MVT *IndexVT = nullptr);
83 
84  void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided);
85  void selectVLSEGFF(SDNode *Node, bool IsMasked);
86  void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
87  void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided);
88  void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
89 
90  // Return the RISC-V condition code that matches the given DAG integer
91  // condition code. The CondCode must be one of those supported by the RISC-V
92  // ISA (see translateSetCCForBranch).
94  switch (CC) {
95  default:
96  llvm_unreachable("Unsupported CondCode");
97  case ISD::SETEQ:
98  return RISCVCC::COND_EQ;
99  case ISD::SETNE:
100  return RISCVCC::COND_NE;
101  case ISD::SETLT:
102  return RISCVCC::COND_LT;
103  case ISD::SETGE:
104  return RISCVCC::COND_GE;
105  case ISD::SETULT:
106  return RISCVCC::COND_LTU;
107  case ISD::SETUGE:
108  return RISCVCC::COND_GEU;
109  }
110  }
111 
112 // Include the pieces autogenerated from the target description.
113 #include "RISCVGenDAGISel.inc"
114 
115 private:
116  bool doPeepholeLoadStoreADDI(SDNode *Node);
117  bool doPeepholeSExtW(SDNode *Node);
118 };
119 
120 namespace RISCV {
121 struct VLSEGPseudo {
129 };
130 
131 struct VLXSEGPseudo {
139 };
140 
141 struct VSSEGPseudo {
148 };
149 
150 struct VSXSEGPseudo {
158 };
159 
160 struct VLEPseudo {
167 };
168 
169 struct VSEPseudo {
175 };
176 
184 };
185 
186 #define GET_RISCVVSSEGTable_DECL
187 #define GET_RISCVVLSEGTable_DECL
188 #define GET_RISCVVLXSEGTable_DECL
189 #define GET_RISCVVSXSEGTable_DECL
190 #define GET_RISCVVLETable_DECL
191 #define GET_RISCVVSETable_DECL
192 #define GET_RISCVVLXTable_DECL
193 #define GET_RISCVVSXTable_DECL
194 #include "RISCVGenSearchableTables.inc"
195 } // namespace RISCV
196 
197 } // namespace llvm
198 
199 #endif
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1374
llvm::RISCV::VLX_VSXPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:178
llvm::RISCVDAGToDAGISel::selectVLXSEG
void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
Definition: RISCVISelDAGToDAG.cpp:344
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::RISCV::VLSEGPseudo
Definition: RISCVISelDAGToDAG.h:121
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1086
llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1
bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:1747
llvm::RISCVCC::COND_GEU
@ COND_GEU
Definition: RISCVInstrInfo.h:35
llvm::RISCV::VSXSEGPseudo::IndexLMUL
uint16_t IndexLMUL
Definition: RISCVISelDAGToDAG.h:156
llvm::RISCVDAGToDAGISel::PreprocessISelDAG
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
Definition: RISCVISelDAGToDAG.cpp:44
llvm::RISCVDAGToDAGISel::selectRVVSimm5
bool selectRVVSimm5(SDValue N, SDValue &Imm)
Definition: RISCVISelDAGToDAG.h:74
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1386
llvm::RISCV::VLEPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:164
llvm::RISCV::VLX_VSXPseudo::IndexLMUL
uint16_t IndexLMUL
Definition: RISCVISelDAGToDAG.h:182
llvm::RISCV::VLXSEGPseudo
Definition: RISCVISelDAGToDAG.h:131
llvm::RISCVDAGToDAGISel::selectZExti32
bool selectZExti32(SDValue N, SDValue &Val)
Definition: RISCVISelDAGToDAG.cpp:1576
llvm::RISCV::VLSEGPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:127
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1381
llvm::RISCV::VSXSEGPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:154
llvm::RISCV::VSSEGPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:145
llvm::RISCV::VSSEGPseudo::Strided
uint16_t Strided
Definition: RISCVISelDAGToDAG.h:144
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::RISCVTargetMachine
Definition: RISCVTargetMachine.h:23
llvm::RISCVDAGToDAGISel::selectVSplat
bool selectVSplat(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:1698
llvm::RISCVDAGToDAGISel
Definition: RISCVISelDAGToDAG.h:23
llvm::RISCVDAGToDAGISel::getPassName
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
Definition: RISCVISelDAGToDAG.h:30
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::RISCV::VLX_VSXPseudo
Definition: RISCVISelDAGToDAG.h:177
llvm::RISCV::VLXSEGPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:135
llvm::RISCV::VLSEGPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:123
llvm::RISCV::VLSEGPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:126
llvm::RISCVDAGToDAGISel::selectVSSEG
void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided)
Definition: RISCVISelDAGToDAG.cpp:392
llvm::RISCV::VSSEGPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:143
llvm::RISCV::VLXSEGPseudo::IndexLMUL
uint16_t IndexLMUL
Definition: RISCVISelDAGToDAG.h:137
llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero
bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:1753
llvm::RISCVDAGToDAGISel::SelectBaseAddr
bool SelectBaseAddr(SDValue Addr, SDValue &Base)
Definition: RISCVISelDAGToDAG.cpp:1520
llvm::RISCV::VSSEGPseudo
Definition: RISCVISelDAGToDAG.h:141
llvm::RISCVDAGToDAGISel::selectShiftMask
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
Definition: RISCVISelDAGToDAG.cpp:1530
llvm::RISCV::VLX_VSXPseudo::Ordered
uint16_t Ordered
Definition: RISCVISelDAGToDAG.h:179
llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel
RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine)
Definition: RISCVISelDAGToDAG.h:27
llvm::RISCVCC::COND_LT
@ COND_LT
Definition: RISCVInstrInfo.h:32
llvm::RISCV::VLEPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:161
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1383
llvm::RISCVDAGToDAGISel::SelectAddrFI
bool SelectAddrFI(SDValue Addr, SDValue &Base)
Definition: RISCVISelDAGToDAG.cpp:1512
llvm::RISCV::VSSEGPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:147
llvm::RISCVCC::COND_LTU
@ COND_LTU
Definition: RISCVInstrInfo.h:34
llvm::RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
Definition: RISCVISelDAGToDAG.cpp:1494
llvm::RISCV::VLXSEGPseudo::Ordered
uint16_t Ordered
Definition: RISCVISelDAGToDAG.h:134
llvm::RISCVDAGToDAGISel::selectShiftMask32
bool selectShiftMask32(SDValue N, SDValue &ShAmt)
Definition: RISCVISelDAGToDAG.h:54
llvm::RISCVDAGToDAGISel::getRISCVCCForIntCC
static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC)
Definition: RISCVISelDAGToDAG.h:93
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:78
llvm::RISCV::VLX_VSXPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:183
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::RISCV::VSEPseudo::Strided
uint16_t Strided
Definition: RISCVISelDAGToDAG.h:171
llvm::RISCV::VSEPseudo
Definition: RISCVISelDAGToDAG.h:169
llvm::RISCVDAGToDAGISel::selectVLOp
bool selectVLOp(SDValue N, SDValue &VL)
Definition: RISCVISelDAGToDAG.cpp:1687
llvm::RISCVDAGToDAGISel::selectVSXSEG
void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
Definition: RISCVISelDAGToDAG.cpp:424
llvm::RISCVDAGToDAGISel::selectShiftMaskXLen
bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt)
Definition: RISCVISelDAGToDAG.h:51
llvm::RISCVDAGToDAGISel::selectVSplatUimm5
bool selectVSplatUimm5(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:1761
llvm::RISCV::VSSEGPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:146
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::RISCV::VSXSEGPseudo::NF
uint16_t NF
Definition: RISCVISelDAGToDAG.h:151
llvm::RISCVCC::COND_EQ
@ COND_EQ
Definition: RISCVInstrInfo.h:30
llvm::RISCV::VSEPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:173
llvm::RISCV::VLXSEGPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:133
llvm::RISCVDAGToDAGISel::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: RISCVISelDAGToDAG.h:34
llvm::RISCV::VLEPseudo::FF
uint16_t FF
Definition: RISCVISelDAGToDAG.h:163
llvm::RISCV::VLSEGPseudo::FF
uint16_t FF
Definition: RISCVISelDAGToDAG.h:125
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::RISCVDAGToDAGISel::selectVLSEG
void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided)
Definition: RISCVISelDAGToDAG.cpp:258
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1375
llvm::RISCV::VLSEGPseudo::Strided
uint16_t Strided
Definition: RISCVISelDAGToDAG.h:124
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1361
llvm::RISCV::VLXSEGPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:136
llvm::RISCVDAGToDAGISel::hasAllWUsers
bool hasAllWUsers(SDNode *Node) const
Definition: RISCVISelDAGToDAG.h:63
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::RISCVDAGToDAGISel::selectVSplatSimm5
bool selectVSplatSimm5(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:1742
RISCV.h
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::RISCV::VSEPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:174
SelectionDAGISel.h
llvm::RISCV::VLSEGPseudo::NF
uint16_t NF
Definition: RISCVISelDAGToDAG.h:122
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::RISCV::VSXSEGPseudo::Ordered
uint16_t Ordered
Definition: RISCVISelDAGToDAG.h:153
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::RISCV::VSEPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:170
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::RISCV::VLSEGPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:128
Node
Definition: ItaniumDemangle.h:235
llvm::RISCV::VSXSEGPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:152
llvm::RISCV::VSEPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:172
llvm::SelectionDAGISel::MF
MachineFunction * MF
Definition: SelectionDAGISel.h:45
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1384
llvm::RISCV::VLXSEGPseudo::NF
uint16_t NF
Definition: RISCVISelDAGToDAG.h:132
uint16_t
llvm::RISCV::VLX_VSXPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:180
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::RISCV::VSXSEGPseudo
Definition: RISCVISelDAGToDAG.h:150
llvm::RISCVDAGToDAGISel::PostprocessISelDAG
void PostprocessISelDAG() override
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
Definition: RISCVISelDAGToDAG.cpp:110
llvm::RISCVDAGToDAGISel::selectVLSEGFF
void selectVLSEGFF(SDNode *Node, bool IsMasked)
Definition: RISCVISelDAGToDAG.cpp:299
llvm::RISCV::VLEPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:165
llvm::RISCVSubtarget::getXLen
unsigned getXLen() const
Definition: RISCVSubtarget.h:132
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
llvm::RISCV::VLX_VSXPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:181
llvm::RISCVCC::COND_GE
@ COND_GE
Definition: RISCVInstrInfo.h:33
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:410
llvm::RISCV::VSXSEGPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:157
llvm::RISCVCC::CondCode
CondCode
Definition: RISCVInstrInfo.h:29
llvm::SelectionDAGISel
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
Definition: SelectionDAGISel.h:39
N
#define N
llvm::RISCVDAGToDAGISel::selectRVVSimm5
bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm)
Definition: RISCVISelDAGToDAG.cpp:1779
llvm::RISCV::VLEPseudo::Strided
uint16_t Strided
Definition: RISCVISelDAGToDAG.h:162
llvm::RISCVDAGToDAGISel::Select
void Select(SDNode *Node) override
Main hook for targets to transform nodes into machine nodes.
Definition: RISCVISelDAGToDAG.cpp:463
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::RISCV::VLXSEGPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:138
llvm::SelectionDAGISel::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: SelectionDAGISel.cpp:415
llvm::RISCV::VSXSEGPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:155
llvm::RISCV::VLEPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:166
llvm::RISCV::VLEPseudo
Definition: RISCVISelDAGToDAG.h:160
llvm::RISCVDAGToDAGISel::hasAllHUsers
bool hasAllHUsers(SDNode *Node) const
Definition: RISCVISelDAGToDAG.h:62
llvm::RISCVDAGToDAGISel::hasAllNBitUsers
bool hasAllNBitUsers(SDNode *Node, unsigned Bits) const
Definition: RISCVISelDAGToDAG.cpp:1605
llvm::RISCVDAGToDAGISel::selectSExti32
bool selectSExti32(SDValue N, SDValue &Val)
Definition: RISCVISelDAGToDAG.cpp:1561
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::RISCVCC::COND_NE
@ COND_NE
Definition: RISCVInstrInfo.h:31
llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands
void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)
Definition: RISCVISelDAGToDAG.cpp:213
RISCVTargetMachine.h
llvm::RISCV::VSSEGPseudo::NF
uint16_t NF
Definition: RISCVISelDAGToDAG.h:142