LLVM  17.0.0git
RISCVISelDAGToDAG.h
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1 //===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISCV ------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines an instruction selector for the RISCV target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
14 #define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
15 
16 #include "RISCV.h"
17 #include "RISCVTargetMachine.h"
19 #include "llvm/Support/KnownBits.h"
20 
21 // RISCV-specific code to select RISCV machine instructions for
22 // SelectionDAG operations.
23 namespace llvm {
25  const RISCVSubtarget *Subtarget = nullptr;
26 
27 public:
28  static char ID;
29 
30  RISCVDAGToDAGISel() = delete;
31 
35 
37  Subtarget = &MF.getSubtarget<RISCVSubtarget>();
39  }
40 
41  void PreprocessISelDAG() override;
42  void PostprocessISelDAG() override;
43 
44  void Select(SDNode *Node) override;
45 
46  bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
47  std::vector<SDValue> &OutOps) override;
48 
52 
54 
55  bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
57  return selectShiftMask(N, Subtarget->getXLen(), ShAmt);
58  }
60  return selectShiftMask(N, 32, ShAmt);
61  }
62 
63  bool selectSExti32(SDValue N, SDValue &Val);
64  bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val);
65  template <unsigned Bits> bool selectZExtBits(SDValue N, SDValue &Val) {
66  return selectZExtBits(N, Bits, Val);
67  }
68 
69  bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val);
70  template <unsigned ShAmt> bool selectSHXADDOp(SDValue N, SDValue &Val) {
71  return selectSHXADDOp(N, ShAmt, Val);
72  }
73 
74  bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val);
75  template <unsigned ShAmt> bool selectSHXADD_UWOp(SDValue N, SDValue &Val) {
76  return selectSHXADD_UWOp(N, ShAmt, Val);
77  }
78 
79  bool hasAllNBitUsers(SDNode *Node, unsigned Bits,
80  const unsigned Depth = 0) const;
81  bool hasAllHUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 16); }
82  bool hasAllWUsers(SDNode *Node) const { return hasAllNBitUsers(Node, 32); }
83 
84  bool selectVLOp(SDValue N, SDValue &VL);
85 
86  bool selectVSplat(SDValue N, SDValue &SplatVal);
87  bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
88  bool selectVSplatUimm5(SDValue N, SDValue &SplatVal);
89  bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
91 
92  bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm);
93  template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) {
94  return selectRVVSimm5(N, Width, Imm);
95  }
96 
97  void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm,
98  const SDLoc &DL, unsigned CurOp,
99  bool IsMasked, bool IsStridedOrIndexed,
101  bool IsLoad = false, MVT *IndexVT = nullptr);
102 
103  void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided);
104  void selectVLSEGFF(SDNode *Node, bool IsMasked);
105  void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
106  void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided);
107  void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered);
108 
109  void selectVSETVLI(SDNode *Node);
110 
111  // Return the RISC-V condition code that matches the given DAG integer
112  // condition code. The CondCode must be one of those supported by the RISC-V
113  // ISA (see translateSetCCForBranch).
115  switch (CC) {
116  default:
117  llvm_unreachable("Unsupported CondCode");
118  case ISD::SETEQ:
119  return RISCVCC::COND_EQ;
120  case ISD::SETNE:
121  return RISCVCC::COND_NE;
122  case ISD::SETLT:
123  return RISCVCC::COND_LT;
124  case ISD::SETGE:
125  return RISCVCC::COND_GE;
126  case ISD::SETULT:
127  return RISCVCC::COND_LTU;
128  case ISD::SETUGE:
129  return RISCVCC::COND_GEU;
130  }
131  }
132 
133 // Include the pieces autogenerated from the target description.
134 #include "RISCVGenDAGISel.inc"
135 
136 private:
137  bool doPeepholeSExtW(SDNode *Node);
138  bool doPeepholeMaskedRVV(SDNode *Node);
139  bool doPeepholeMergeVVMFold();
140  bool performVMergeToVAdd(SDNode *N);
141  bool performCombineVMergeAndVOps(SDNode *N, bool IsTA);
142 };
143 
144 namespace RISCV {
145 struct VLSEGPseudo {
154 };
155 
156 struct VLXSEGPseudo {
165 };
166 
167 struct VSSEGPseudo {
174 };
175 
176 struct VSXSEGPseudo {
184 };
185 
186 struct VLEPseudo {
194 };
195 
196 struct VSEPseudo {
202 };
203 
212 };
213 
218  uint8_t MaskOpIdx;
219 };
220 
221 #define GET_RISCVVSSEGTable_DECL
222 #define GET_RISCVVLSEGTable_DECL
223 #define GET_RISCVVLXSEGTable_DECL
224 #define GET_RISCVVSXSEGTable_DECL
225 #define GET_RISCVVLETable_DECL
226 #define GET_RISCVVSETable_DECL
227 #define GET_RISCVVLXTable_DECL
228 #define GET_RISCVVSXTable_DECL
229 #define GET_RISCVMaskedPseudosTable_DECL
230 #include "RISCVGenSearchableTables.inc"
231 } // namespace RISCV
232 
233 } // namespace llvm
234 
235 #endif
llvm::ISD::SETUGE
@ SETUGE
Definition: ISDOpcodes.h:1441
llvm::RISCV::VLX_VSXPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:205
llvm::RISCVDAGToDAGISel::selectVLXSEG
void selectVLXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
Definition: RISCVISelDAGToDAG.cpp:401
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::RISCV::VLSEGPseudo
Definition: RISCVISelDAGToDAG.h:145
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1
bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:2532
llvm::RISCVCC::COND_GEU
@ COND_GEU
Definition: RISCVInstrInfo.h:36
llvm::RISCV::VSXSEGPseudo::IndexLMUL
uint16_t IndexLMUL
Definition: RISCVISelDAGToDAG.h:182
llvm::RISCVDAGToDAGISel::PreprocessISelDAG
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
Definition: RISCVISelDAGToDAG.cpp:60
llvm::RISCVDAGToDAGISel::selectRVVSimm5
bool selectRVVSimm5(SDValue N, SDValue &Imm)
Definition: RISCVISelDAGToDAG.h:93
llvm::ISD::SETNE
@ SETNE
Definition: ISDOpcodes.h:1453
llvm::RISCV::VLEPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:191
llvm::RISCV::VLX_VSXPseudo::IndexLMUL
uint16_t IndexLMUL
Definition: RISCVISelDAGToDAG.h:210
llvm::RISCV::VLXSEGPseudo
Definition: RISCVISelDAGToDAG.h:156
llvm::RISCV::VLSEGPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:152
llvm::RISCVDAGToDAGISel::selectVSETVLI
void selectVSETVLI(SDNode *Node)
Definition: RISCVISelDAGToDAG.cpp:529
llvm::ISD::SETEQ
@ SETEQ
Definition: ISDOpcodes.h:1448
llvm::RISCVDAGToDAGISel::SelectFrameAddrRegImm
bool SelectFrameAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
Definition: RISCVISelDAGToDAG.cpp:1886
llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp
bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
Definition: RISCVISelDAGToDAG.cpp:2267
llvm::RISCV::VSXSEGPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:180
llvm::RISCV::VSSEGPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:171
llvm::RISCV::VSSEGPseudo::Strided
uint16_t Strided
Definition: RISCVISelDAGToDAG.h:170
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::RISCVTargetMachine
Definition: RISCVTargetMachine.h:24
llvm::RISCVDAGToDAGISel::selectVSplat
bool selectVSplat(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:2484
llvm::RISCVDAGToDAGISel
Definition: RISCVISelDAGToDAG.h:24
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::RISCVDAGToDAGISel::selectZExtBits
bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val)
Definition: RISCVISelDAGToDAG.cpp:2151
llvm::RISCV::RISCVMaskedPseudoInfo::UnmaskedPseudo
uint16_t UnmaskedPseudo
Definition: RISCVISelDAGToDAG.h:216
llvm::tgtok::Bits
@ Bits
Definition: TGLexer.h:50
llvm::RISCV::VLX_VSXPseudo::IsTU
uint16_t IsTU
Definition: RISCVISelDAGToDAG.h:206
llvm::RISCV::VLX_VSXPseudo
Definition: RISCVISelDAGToDAG.h:204
llvm::RISCV::VLXSEGPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:161
llvm::RISCV::VLSEGPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:147
llvm::RISCV::VLSEGPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:151
llvm::RISCVDAGToDAGISel::selectVSSEG
void selectVSSEG(SDNode *Node, bool IsMasked, bool IsStrided)
Definition: RISCVISelDAGToDAG.cpp:455
llvm::RISCV::VSSEGPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:169
llvm::RISCV::VLXSEGPseudo::IndexLMUL
uint16_t IndexLMUL
Definition: RISCVISelDAGToDAG.h:163
llvm::RISCV::VLSEGPseudo::IsTU
uint16_t IsTU
Definition: RISCVISelDAGToDAG.h:148
llvm::RISCV::VLXSEGPseudo::IsTU
uint16_t IsTU
Definition: RISCVISelDAGToDAG.h:159
llvm::RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero
bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:2538
KnownBits.h
llvm::RISCVDAGToDAGISel::SelectAddrFrameIndex
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset)
Definition: RISCVISelDAGToDAG.cpp:1874
llvm::RISCV::VSSEGPseudo
Definition: RISCVISelDAGToDAG.h:167
llvm::RISCV::RISCVMaskedPseudoInfo
Definition: RISCVISelDAGToDAG.h:214
llvm::RISCV::RISCVMaskedPseudoInfo::UnmaskedTUPseudo
uint16_t UnmaskedTUPseudo
Definition: RISCVISelDAGToDAG.h:217
llvm::RISCVDAGToDAGISel::selectShiftMask
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
Definition: RISCVISelDAGToDAG.cpp:2069
llvm::RISCV::VLX_VSXPseudo::Ordered
uint16_t Ordered
Definition: RISCVISelDAGToDAG.h:207
llvm::RISCVCC::COND_LT
@ COND_LT
Definition: RISCVInstrInfo.h:33
llvm::RISCV::VLEPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:187
llvm::ISD::SETGE
@ SETGE
Definition: ISDOpcodes.h:1450
llvm::SelectionDAGISel::OptLevel
CodeGenOpt::Level OptLevel
Definition: SelectionDAGISel.h:54
llvm::RISCV::VSSEGPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:173
llvm::RISCVCC::COND_LTU
@ COND_LTU
Definition: RISCVInstrInfo.h:35
llvm::RISCVDAGToDAGISel::ID
static char ID
Definition: RISCVISelDAGToDAG.h:28
llvm::RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand
bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
Definition: RISCVISelDAGToDAG.cpp:1856
llvm::RISCV::VLXSEGPseudo::Ordered
uint16_t Ordered
Definition: RISCVISelDAGToDAG.h:160
llvm::RISCVDAGToDAGISel::selectShiftMask32
bool selectShiftMask32(SDValue N, SDValue &ShAmt)
Definition: RISCVISelDAGToDAG.h:59
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::RISCVDAGToDAGISel::SelectAddrRegImm
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset)
Definition: RISCVISelDAGToDAG.cpp:1979
llvm::RISCVDAGToDAGISel::getRISCVCCForIntCC
static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC)
Definition: RISCVISelDAGToDAG.h:114
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::RISCV::VLX_VSXPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:211
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:672
llvm::RISCV::VSEPseudo::Strided
uint16_t Strided
Definition: RISCVISelDAGToDAG.h:198
llvm::RISCV::VSEPseudo
Definition: RISCVISelDAGToDAG.h:196
llvm::RISCVDAGToDAGISel::selectVLOp
bool selectVLOp(SDValue N, SDValue &VL)
Definition: RISCVISelDAGToDAG.cpp:2460
llvm::RISCVDAGToDAGISel::selectVSXSEG
void selectVSXSEG(SDNode *Node, bool IsMasked, bool IsOrdered)
Definition: RISCVISelDAGToDAG.cpp:487
llvm::RISCVDAGToDAGISel::selectShiftMaskXLen
bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt)
Definition: RISCVISelDAGToDAG.h:56
llvm::RISCVDAGToDAGISel::selectVSplatUimm5
bool selectVSplatUimm5(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:2546
llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp
bool selectSHXADD_UWOp(SDValue N, SDValue &Val)
Definition: RISCVISelDAGToDAG.h:75
llvm::RISCV::VSSEGPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:172
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
llvm::RISCV::VSXSEGPseudo::NF
uint16_t NF
Definition: RISCVISelDAGToDAG.h:177
llvm::RISCVCC::COND_EQ
@ COND_EQ
Definition: RISCVInstrInfo.h:31
llvm::RISCV::VSEPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:200
llvm::RISCV::VLXSEGPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:158
llvm::RISCVDAGToDAGISel::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: RISCVISelDAGToDAG.h:36
llvm::RISCV::VLEPseudo::FF
uint16_t FF
Definition: RISCVISelDAGToDAG.h:190
llvm::RISCV::VLSEGPseudo::FF
uint16_t FF
Definition: RISCVISelDAGToDAG.h:150
llvm::RISCVSubtarget
Definition: RISCVSubtarget.h:35
llvm::RISCV::RISCVMaskedPseudoInfo::MaskedPseudo
uint16_t MaskedPseudo
Definition: RISCVISelDAGToDAG.h:215
llvm::RISCVDAGToDAGISel::selectVLSEG
void selectVLSEG(SDNode *Node, bool IsMasked, bool IsStrided)
Definition: RISCVISelDAGToDAG.cpp:313
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
llvm::ISD::SETULT
@ SETULT
Definition: ISDOpcodes.h:1442
llvm::RISCV::VLSEGPseudo::Strided
uint16_t Strided
Definition: RISCVISelDAGToDAG.h:149
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1428
llvm::RISCV::VLXSEGPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:162
llvm::RISCVDAGToDAGISel::hasAllWUsers
bool hasAllWUsers(SDNode *Node) const
Definition: RISCVISelDAGToDAG.h:82
llvm::RISCV::RISCVMaskedPseudoInfo::MaskOpIdx
uint8_t MaskOpIdx
Definition: RISCVISelDAGToDAG.h:218
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::RISCVDAGToDAGISel::selectVSplatSimm5
bool selectVSplatSimm5(SDValue N, SDValue &SplatVal)
Definition: RISCVISelDAGToDAG.cpp:2527
RISCV.h
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel
RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine, CodeGenOpt::Level OptLevel)
Definition: RISCVISelDAGToDAG.h:32
llvm::RISCV::VSEPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:201
SelectionDAGISel.h
llvm::RISCV::VLSEGPseudo::NF
uint16_t NF
Definition: RISCVISelDAGToDAG.h:146
llvm::RISCV::VSXSEGPseudo::Ordered
uint16_t Ordered
Definition: RISCVISelDAGToDAG.h:179
llvm::Offset
@ Offset
Definition: DWP.cpp:406
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::RISCV::VSEPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:197
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::RISCV::VLSEGPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:153
Node
Definition: ItaniumDemangle.h:156
llvm::RISCV::VSXSEGPseudo::Masked
uint16_t Masked
Definition: RISCVISelDAGToDAG.h:178
llvm::RISCV::VSEPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:199
llvm::SelectionDAGISel::MF
MachineFunction * MF
Definition: SelectionDAGISel.h:47
llvm::ISD::SETLT
@ SETLT
Definition: ISDOpcodes.h:1451
llvm::RISCVDAGToDAGISel::hasAllNBitUsers
bool hasAllNBitUsers(SDNode *Node, unsigned Bits, const unsigned Depth=0) const
Definition: RISCVISelDAGToDAG.cpp:2310
llvm::RISCV::VLXSEGPseudo::NF
uint16_t NF
Definition: RISCVISelDAGToDAG.h:157
llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel
RISCVDAGToDAGISel()=delete
uint16_t
llvm::RISCV::VLX_VSXPseudo::Log2SEW
uint16_t Log2SEW
Definition: RISCVISelDAGToDAG.h:208
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:354
llvm::RISCV::VSXSEGPseudo
Definition: RISCVISelDAGToDAG.h:176
llvm::RISCVDAGToDAGISel::PostprocessISelDAG
void PostprocessISelDAG() override
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
Definition: RISCVISelDAGToDAG.cpp:152
llvm::RISCVDAGToDAGISel::selectVLSEGFF
void selectVLSEGFF(SDNode *Node, bool IsMasked)
Definition: RISCVISelDAGToDAG.cpp:356
llvm::RISCV::VLEPseudo::IsTU
uint16_t IsTU
Definition: RISCVISelDAGToDAG.h:188
llvm::RISCV::VLEPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:192
llvm::RISCVSubtarget::getXLen
unsigned getXLen() const
Definition: RISCVSubtarget.h:113
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::RISCV::VLX_VSXPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:209
llvm::RISCVDAGToDAGISel::selectZExtBits
bool selectZExtBits(SDValue N, SDValue &Val)
Definition: RISCVISelDAGToDAG.h:65
llvm::RISCVCC::COND_GE
@ COND_GE
Definition: RISCVInstrInfo.h:34
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::RISCVDAGToDAGISel::tryShrinkShlLogicImm
bool tryShrinkShlLogicImm(SDNode *Node)
Definition: RISCVISelDAGToDAG.cpp:599
llvm::RISCV::VSXSEGPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:183
llvm::RISCVDAGToDAGISel::selectSHXADDOp
bool selectSHXADDOp(SDValue N, SDValue &Val)
Definition: RISCVISelDAGToDAG.h:70
llvm::RISCVCC::CondCode
CondCode
Definition: RISCVInstrInfo.h:30
llvm::SelectionDAGISel
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
Definition: SelectionDAGISel.h:41
N
#define N
llvm::RISCVDAGToDAGISel::selectRVVSimm5
bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm)
Definition: RISCVISelDAGToDAG.cpp:2563
llvm::RISCV::VLEPseudo::Strided
uint16_t Strided
Definition: RISCVISelDAGToDAG.h:189
llvm::RISCVDAGToDAGISel::Select
void Select(SDNode *Node) override
Main hook for targets to transform nodes into machine nodes.
Definition: RISCVISelDAGToDAG.cpp:677
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::RISCV::VLXSEGPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:164
llvm::CodeGenOpt::Level
Level
Code generation optimization level.
Definition: CodeGen.h:57
llvm::SelectionDAGISel::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: SelectionDAGISel.cpp:381
llvm::RISCV::VSXSEGPseudo::LMUL
uint16_t LMUL
Definition: RISCVISelDAGToDAG.h:181
llvm::RISCVDAGToDAGISel::selectSHXADDOp
bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val)
Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
Definition: RISCVISelDAGToDAG.cpp:2172
llvm::RISCV::VLEPseudo::Pseudo
uint16_t Pseudo
Definition: RISCVISelDAGToDAG.h:193
llvm::RISCV::VLEPseudo
Definition: RISCVISelDAGToDAG.h:186
llvm::RISCVDAGToDAGISel::hasAllHUsers
bool hasAllHUsers(SDNode *Node) const
Definition: RISCVISelDAGToDAG.h:81
llvm::RISCVDAGToDAGISel::selectSExti32
bool selectSExti32(SDValue N, SDValue &Val)
Definition: RISCVISelDAGToDAG.cpp:2136
llvm::RISCVCC::COND_NE
@ COND_NE
Definition: RISCVInstrInfo.h:32
llvm::RISCVDAGToDAGISel::addVectorLoadStoreOperands
void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)
Definition: RISCVISelDAGToDAG.cpp:266
RISCVTargetMachine.h
llvm::RISCV::VSSEGPseudo::NF
uint16_t NF
Definition: RISCVISelDAGToDAG.h:168