#include "Target/RISCV/RISCVISelDAGToDAG.h"

Inheritance diagram for llvm::RISCVDAGToDAGISel:

Public Member Functions
	RISCVDAGToDAGISel ()=delete
	RISCVDAGToDAGISel (RISCVTargetMachine &TargetMachine, CodeGenOptLevel OptLevel)
bool	runOnMachineFunction (MachineFunction &MF) override
void	PreprocessISelDAG () override
	PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.
void	PostprocessISelDAG () override
	PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
void	Select (SDNode *Node) override
	Main hook for targets to transform nodes into machine nodes.
bool	SelectInlineAsmMemoryOperand (const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override
	SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.
bool	areOffsetsWithinAlignment (SDValue Addr, Align Alignment)
bool	SelectAddrFrameIndex (SDValue Addr, SDValue &Base, SDValue &Offset)
bool	SelectAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset)
bool	SelectAddrRegImm26 (SDValue Addr, SDValue &Base, SDValue &Offset)
	Similar to SelectAddrRegImm, except that the offset is a 26-bit signed immediate.
bool	SelectAddrRegImm9 (SDValue Addr, SDValue &Base, SDValue &Offset)
	Similar to SelectAddrRegImm, except that the offset is restricted to uimm9.
bool	SelectAddrRegImmLsb00000 (SDValue Addr, SDValue &Base, SDValue &Offset)
	Similar to SelectAddrRegImm, except that the least significant 5 bits of Offset should be all zeros.
bool	SelectAddrRegRegScale (SDValue Addr, ArrayRef< unsigned > Amounts, SDValue &Base, SDValue &Index, SDValue &Scale)
template<unsigned ShiftAmount>
bool	SelectAddrRegRegFixedScale (SDValue Addr, SDValue &Base, SDValue &Index)
template<unsigned MaxShift>
bool	SelectAddrRegRegScale (SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
bool	SelectAddrRegZextRegScale (SDValue Addr, ArrayRef< unsigned > Amounts, unsigned Bits, SDValue &Base, SDValue &Index, SDValue &Scale)
template<unsigned ShiftAmount, unsigned Bits>
bool	SelectAddrRegZextRegFixedScale (SDValue Addr, SDValue &Base, SDValue &Index)
template<unsigned MaxShift, unsigned Bits>
bool	SelectAddrRegZextRegScale (SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
bool	SelectAddrRegReg (SDValue Addr, SDValue &Base, SDValue &Offset)
bool	tryShrinkShlLogicImm (SDNode *Node)
bool	trySignedBitfieldExtract (SDNode *Node)
bool	trySignedBitfieldInsertInSign (SDNode *Node)
bool	tryUnsignedBitfieldExtract (SDNode *Node, const SDLoc &DL, MVT VT, SDValue X, unsigned Msb, unsigned Lsb)
bool	tryUnsignedBitfieldInsertInZero (SDNode *Node, const SDLoc &DL, MVT VT, SDValue X, unsigned Msb, unsigned Lsb)
bool	tryIndexedLoad (SDNode *Node)
bool	tryWideningMulAcc (SDNode *Node, const SDLoc &DL)
bool	selectShiftMask (SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
bool	selectShiftMaskXLen (SDValue N, SDValue &ShAmt)
template<unsigned Size>
bool	selectShiftMask (SDValue N, SDValue &ShAmt)
bool	selectSETCC (SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val, bool OneUse)
	RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with 0.
template<bool OneUse = false>
bool	selectSETNE (SDValue N, SDValue &Val)
template<bool OneUse = false>
bool	selectSETEQ (SDValue N, SDValue &Val)
bool	selectSExtBits (SDValue N, unsigned Bits, SDValue &Val)
template<unsigned Bits>
bool	selectSExtBits (SDValue N, SDValue &Val)
bool	selectZExtBits (SDValue N, unsigned Bits, SDValue &Val)
template<unsigned Bits>
bool	selectZExtBits (SDValue N, SDValue &Val)
bool	selectSHXADDOp (SDValue N, unsigned ShAmt, SDValue &Val)
	Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
template<unsigned ShAmt>
bool	selectSHXADDOp (SDValue N, SDValue &Val)
bool	selectSHXADD_UWOp (SDValue N, unsigned ShAmt, SDValue &Val)
	Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
template<unsigned ShAmt>
bool	selectSHXADD_UWOp (SDValue N, SDValue &Val)
bool	selectZExtImm32 (SDValue N, SDValue &Val)
bool	selectNegImm (SDValue N, SDValue &Val)
bool	selectInvLogicImm (SDValue N, SDValue &Val)
bool	orDisjoint (const SDNode *Node) const
bool	hasAllNBitUsers (SDNode *Node, unsigned Bits, const unsigned Depth=0) const
bool	hasAllBUsers (SDNode *Node) const
bool	hasAllHUsers (SDNode *Node) const
bool	hasAllWUsers (SDNode *Node) const
bool	selectSimm5Shl2 (SDValue N, SDValue &Simm5, SDValue &Shl2)
bool	selectVLOp (SDValue N, SDValue &VL)
bool	selectVSplat (SDValue N, SDValue &SplatVal)
bool	selectVSplatSimm5 (SDValue N, SDValue &SplatVal)
bool	selectVSplatUimm (SDValue N, unsigned Bits, SDValue &SplatVal)
template<unsigned Bits>
bool	selectVSplatUimmBits (SDValue N, SDValue &Val)
bool	selectVSplatSimm5Plus1 (SDValue N, SDValue &SplatVal)
bool	selectVSplatSimm5Plus1NoDec (SDValue N, SDValue &SplatVal)
bool	selectVSplatSimm5Plus1NonZero (SDValue N, SDValue &SplatVal)
bool	selectVSplatImm64Neg (SDValue N, SDValue &SplatVal)
bool	selectLow8BitsVSplat (SDValue N, SDValue &SplatVal)
bool	selectScalarFPAsInt (SDValue N, SDValue &Imm)
bool	selectRVVSimm5 (SDValue N, unsigned Width, SDValue &Imm)
template<unsigned Width>
bool	selectRVVSimm5 (SDValue N, SDValue &Imm)
bool	selectVMNOTOp (SDValue N, SDValue &Res)
bool	selectVMNOT_VLOp (SDNode *Parent, SDValue N, SDValue &Res)
void	addVectorLoadStoreOperands (SDNode Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT IndexVT=nullptr)
void	selectVLSEG (SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided)
void	selectVLSEGFF (SDNode *Node, unsigned NF, bool IsMasked)
void	selectVLXSEG (SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered)
void	selectVSSEG (SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided)
void	selectVSXSEG (SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered)
void	selectVSETVLI (SDNode *Node)
void	selectXSfmmVSET (SDNode *Node)
void	selectSF_VC_X_SE (SDNode *Node)
Public Member Functions inherited from llvm::SelectionDAGISel
	SelectionDAGISel (TargetMachine &tm, CodeGenOptLevel OL=CodeGenOptLevel::Default)
virtual	~SelectionDAGISel ()
BatchAAResults *	getBatchAA () const
	Returns a (possibly null) pointer to the current BatchAAResults.
const TargetLowering *	getTargetLowering () const
void	initializeAnalysisResults (MachineFunctionAnalysisManager &MFAM)
void	initializeAnalysisResults (MachineFunctionPass &MFP)
virtual void	emitFunctionEntryCode ()
virtual bool	IsProfitableToFold (SDValue N, SDNode U, SDNode Root) const
	IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during instruction selection that starts at Root.
bool	CheckAndMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
	CheckAndMask - The isel is trying to match something like (and X, 255).
bool	CheckOrMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
	CheckOrMask - The isel is trying to match something like (or X, 255).
virtual bool	CheckPatternPredicate (unsigned PredNo) const
	CheckPatternPredicate - This function is generated by tblgen in the target.
virtual bool	CheckNodePredicate (SDValue Op, unsigned PredNo) const
	CheckNodePredicate - This function is generated by tblgen in the target.
virtual bool	CheckNodePredicateWithOperands (SDValue Op, unsigned PredNo, ArrayRef< SDValue > Operands) const
	CheckNodePredicateWithOperands - This function is generated by tblgen in the target.
virtual bool	CheckComplexPattern (SDNode Root, SDNode Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)
virtual SDValue	RunSDNodeXForm (SDValue V, unsigned XFormNo)
virtual MVT	getValueTypeForHwMode (unsigned Index) const
void	SelectCodeCommon (SDNode NodeToMatch, const uint8_t MatcherTable, unsigned TableSize, const uint8_t *OperandLists)
virtual bool	ComplexPatternFuncMutatesDAG () const
	Return true if complex patterns for this target can mutate the DAG.
bool	mayRaiseFPException (SDNode *Node) const
	Return whether the node may raise an FP exception.
bool	isOrEquivalentToAdd (const SDNode *N) const

Static Public Member Functions
static RISCVCC::CondCode	getRISCVCCForIntCC (ISD::CondCode CC)
Static Public Member Functions inherited from llvm::SelectionDAGISel
static bool	IsLegalToFold (SDValue N, SDNode U, SDNode Root, CodeGenOptLevel OptLevel, bool IgnoreChains=false)
	IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction selection that starts at Root.
static void	InvalidateNodeId (SDNode *N)
static int	getUninvalidatedNodeId (SDNode *N)
static void	EnforceNodeIdInvariant (SDNode *N)
static int	getNumFixedFromVariadicInfo (unsigned Flags)
	getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values that should be skipped when copying from the root.

Additional Inherited Members
Public Types inherited from llvm::SelectionDAGISel
enum	BuiltinOpcodes { OPC_Scope , OPC_RecordNode , OPC_RecordChild0 , OPC_RecordChild1 , OPC_RecordChild2 , OPC_RecordChild3 , OPC_RecordChild4 , OPC_RecordChild5 , OPC_RecordChild6 , OPC_RecordChild7 , OPC_RecordMemRef , OPC_CaptureGlueInput , OPC_CaptureDeactivationSymbol , OPC_MoveChild , OPC_MoveChild0 , OPC_MoveChild1 , OPC_MoveChild2 , OPC_MoveChild3 , OPC_MoveChild4 , OPC_MoveChild5 , OPC_MoveChild6 , OPC_MoveChild7 , OPC_MoveSibling , OPC_MoveSibling0 , OPC_MoveSibling1 , OPC_MoveSibling2 , OPC_MoveSibling3 , OPC_MoveSibling4 , OPC_MoveSibling5 , OPC_MoveSibling6 , OPC_MoveSibling7 , OPC_MoveParent , OPC_CheckSame , OPC_CheckChild0Same , OPC_CheckChild1Same , OPC_CheckChild2Same , OPC_CheckChild3Same , OPC_CheckPatternPredicate , OPC_CheckPatternPredicate0 , OPC_CheckPatternPredicate1 , OPC_CheckPatternPredicate2 , OPC_CheckPatternPredicate3 , OPC_CheckPatternPredicate4 , OPC_CheckPatternPredicate5 , OPC_CheckPatternPredicate6 , OPC_CheckPatternPredicate7 , OPC_CheckPatternPredicateTwoByte , OPC_CheckPredicate , OPC_CheckPredicate0 , OPC_CheckPredicate1 , OPC_CheckPredicate2 , OPC_CheckPredicate3 , OPC_CheckPredicate4 , OPC_CheckPredicate5 , OPC_CheckPredicate6 , OPC_CheckPredicate7 , OPC_CheckPredicateWithOperands , OPC_CheckOpcode , OPC_SwitchOpcode , OPC_CheckType , OPC_CheckTypeI32 , OPC_CheckTypeI64 , OPC_CheckTypeByHwMode , OPC_CheckTypeByHwMode0 , OPC_CheckTypeRes , OPC_CheckTypeResByHwMode , OPC_SwitchType , OPC_CheckChild0Type , OPC_CheckChild1Type , OPC_CheckChild2Type , OPC_CheckChild3Type , OPC_CheckChild4Type , OPC_CheckChild5Type , OPC_CheckChild6Type , OPC_CheckChild7Type , OPC_CheckChild0TypeI32 , OPC_CheckChild1TypeI32 , OPC_CheckChild2TypeI32 , OPC_CheckChild3TypeI32 , OPC_CheckChild4TypeI32 , OPC_CheckChild5TypeI32 , OPC_CheckChild6TypeI32 , OPC_CheckChild7TypeI32 , OPC_CheckChild0TypeI64 , OPC_CheckChild1TypeI64 , OPC_CheckChild2TypeI64 , OPC_CheckChild3TypeI64 , OPC_CheckChild4TypeI64 , OPC_CheckChild5TypeI64 , OPC_CheckChild6TypeI64 , OPC_CheckChild7TypeI64 , OPC_CheckChild0TypeByHwMode , OPC_CheckChild1TypeByHwMode , OPC_CheckChild2TypeByHwMode , OPC_CheckChild3TypeByHwMode , OPC_CheckChild4TypeByHwMode , OPC_CheckChild5TypeByHwMode , OPC_CheckChild6TypeByHwMode , OPC_CheckChild7TypeByHwMode , OPC_CheckChild0TypeByHwMode0 , OPC_CheckChild1TypeByHwMode0 , OPC_CheckChild2TypeByHwMode0 , OPC_CheckChild3TypeByHwMode0 , OPC_CheckChild4TypeByHwMode0 , OPC_CheckChild5TypeByHwMode0 , OPC_CheckChild6TypeByHwMode0 , OPC_CheckChild7TypeByHwMode0 , OPC_CheckInteger , OPC_CheckChild0Integer , OPC_CheckChild1Integer , OPC_CheckChild2Integer , OPC_CheckChild3Integer , OPC_CheckChild4Integer , OPC_CheckCondCode , OPC_CheckChild2CondCode , OPC_CheckValueType , OPC_CheckComplexPat , OPC_CheckComplexPat0 , OPC_CheckComplexPat1 , OPC_CheckComplexPat2 , OPC_CheckComplexPat3 , OPC_CheckComplexPat4 , OPC_CheckComplexPat5 , OPC_CheckComplexPat6 , OPC_CheckComplexPat7 , OPC_CheckAndImm , OPC_CheckOrImm , OPC_CheckImmAllOnesV , OPC_CheckImmAllZerosV , OPC_CheckUndef , OPC_CheckFoldableChainNode , OPC_EmitInteger , OPC_EmitIntegerI8 , OPC_EmitIntegerI16 , OPC_EmitIntegerI32 , OPC_EmitIntegerI64 , OPC_EmitIntegerByHwMode , OPC_EmitIntegerByHwMode0 , OPC_EmitRegister , OPC_EmitRegisterI32 , OPC_EmitRegisterI64 , OPC_EmitRegisterByHwMode , OPC_EmitRegister2 , OPC_EmitRegisterByHwMode2 , OPC_EmitConvertToTarget , OPC_EmitConvertToTarget0 , OPC_EmitConvertToTarget1 , OPC_EmitConvertToTarget2 , OPC_EmitConvertToTarget3 , OPC_EmitConvertToTarget4 , OPC_EmitConvertToTarget5 , OPC_EmitConvertToTarget6 , OPC_EmitConvertToTarget7 , OPC_EmitMergeInputChains , OPC_EmitMergeInputChains1_0 , OPC_EmitMergeInputChains1_1 , OPC_EmitMergeInputChains1_2 , OPC_EmitCopyToReg , OPC_EmitCopyToReg0 , OPC_EmitCopyToReg1 , OPC_EmitCopyToReg2 , OPC_EmitCopyToReg3 , OPC_EmitCopyToReg4 , OPC_EmitCopyToReg5 , OPC_EmitCopyToReg6 , OPC_EmitCopyToReg7 , OPC_EmitCopyToRegTwoByte , OPC_EmitNodeXForm , OPC_EmitNode , OPC_EmitNodeByHwMode , OPC_EmitNode0 , OPC_EmitNode1 , OPC_EmitNode2 , OPC_EmitNode1None , OPC_EmitNode2None , OPC_EmitNode0Chain , OPC_EmitNode1Chain , OPC_EmitNode2Chain , OPC_MorphNodeTo , OPC_MorphNodeToByHwMode , OPC_MorphNodeTo0 , OPC_MorphNodeTo1 , OPC_MorphNodeTo2 , OPC_MorphNodeTo1None , OPC_MorphNodeTo2None , OPC_MorphNodeTo0Chain , OPC_MorphNodeTo1Chain , OPC_MorphNodeTo2Chain , OPC_MorphNodeTo1GlueInput , OPC_MorphNodeTo2GlueInput , OPC_MorphNodeTo1GlueOutput , OPC_MorphNodeTo2GlueOutput , OPC_CompleteMatch , OPC_Coverage }
enum	{ OPFL_None = 0 , OPFL_Chain = 1 , OPFL_GlueInput = 2 , OPFL_GlueOutput = 4 , OPFL_MemRefs = 8 , OPFL_Variadic0 = 1 << 4 , OPFL_Variadic1 = 2 << 4 , OPFL_Variadic2 = 3 << 4 , OPFL_Variadic3 = 4 << 4 , OPFL_Variadic4 = 5 << 4 , OPFL_Variadic5 = 6 << 4 , OPFL_Variadic6 = 7 << 4 , OPFL_Variadic7 = 8 << 4 , OPFL_VariadicInfo = 15 << 4 }
Public Attributes inherited from llvm::SelectionDAGISel
TargetMachine &	TM
const TargetLibraryInfo *	LibInfo
const LibcallLoweringInfo *	LibcallLowering
std::unique_ptr< FunctionLoweringInfo >	FuncInfo
std::unique_ptr< SwiftErrorValueTracking >	SwiftError
MachineFunction *	MF
MachineRegisterInfo *	RegInfo
SelectionDAG *	CurDAG
std::unique_ptr< SelectionDAGBuilder >	SDB
std::optional< BatchAAResults >	BatchAA
AssumptionCache *	AC = nullptr
GCFunctionInfo *	GFI = nullptr
SSPLayoutInfo *	SP = nullptr
const TargetTransformInfo *	TTI = nullptr
CodeGenOptLevel	OptLevel
const TargetInstrInfo *	TII
const TargetLowering *	TLI
bool	FastISelFailed
SmallPtrSet< const Instruction *, 4 >	ElidedArgCopyInstrs
std::unique_ptr< OptimizationRemarkEmitter >	ORE
	Current optimization remark emitter.
bool	MatchFilterFuncName = false
	True if the function currently processing is in the function printing list (i.e.
StringRef	FuncName
unsigned	HwMode
Protected Member Functions inherited from llvm::SelectionDAGISel
void	ReplaceUses (SDValue F, SDValue T)
	ReplaceUses - replace all uses of the old node F with the use of the new node T.
void	ReplaceUses (const SDValue F, const SDValue T, unsigned Num)
	ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T.
void	ReplaceUses (SDNode F, SDNode T)
	ReplaceUses - replace all uses of the old node F with the use of the new node T.
void	ReplaceNode (SDNode F, SDNode T)
	Replace all uses of `F` with `T`, then remove `F` from the DAG.
void	SelectInlineAsmMemoryOperands (std::vector< SDValue > &Ops, const SDLoc &DL)
	SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
virtual StringRef	getPatternForIndex (unsigned index)
	getPatternForIndex - Patterns selected by tablegen during ISEL
virtual StringRef	getIncludePathForIndex (unsigned index)
	getIncludePathForIndex - get the td source location of pattern instantiation
bool	shouldOptForSize (const MachineFunction *MF) const
Protected Attributes inherited from llvm::SelectionDAGISel
unsigned	DAGSize = 0
	DAGSize - Size of DAG being instruction selected.

Detailed Description

Definition at line 24 of file RISCVISelDAGToDAG.h.

Constructor & Destructor Documentation

◆ RISCVDAGToDAGISel() [1/2]

llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel ( )

delete

◆ RISCVDAGToDAGISel() [2/2]

llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel	(	RISCVTargetMachine &	TargetMachine,
		CodeGenOptLevel	OptLevel )

inlineexplicit

Definition at line 30 of file RISCVISelDAGToDAG.h.

References llvm::SelectionDAGISel::OptLevel, and llvm::SelectionDAGISel::SelectionDAGISel().

Member Function Documentation

◆ addVectorLoadStoreOperands()

void RISCVDAGToDAGISel::addVectorLoadStoreOperands	(	SDNode *	Node,
		unsigned	SEWImm,
		const SDLoc &	DL,
		unsigned	CurOp,
		bool	IsMasked,
		bool	IsStridedOrIndexed,
		SmallVectorImpl< SDValue > &	Operands,
		bool	IsLoad = false,
		MVT *	IndexVT = nullptr )

Definition at line 321 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVVType::MASK_AGNOSTIC, Operands, and selectVLOp().

Referenced by Select(), selectVLSEG(), selectVLSEGFF(), selectVLXSEG(), selectVSSEG(), and selectVSXSEG().

◆ areOffsetsWithinAlignment()

bool RISCVDAGToDAGISel::areOffsetsWithinAlignment	(	SDValue	Addr,
		Align	Alignment )

Definition at line 3572 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::cast(), llvm::SelectionDAGISel::CurDAG, llvm::SDNode::getOpcode(), llvm::User::getOperand(), llvm::isInt(), isRegImmLoadOrStore(), llvm::SDNode::users(), and llvm::Value::users().

Referenced by SelectAddrRegImm().

◆ getRISCVCCForIntCC()

RISCVCC::CondCode llvm::RISCVDAGToDAGISel::getRISCVCCForIntCC ( ISD::CondCode CC )

inlinestatic

Definition at line 206 of file RISCVISelDAGToDAG.h.

References llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, llvm::RISCVCC::COND_NE, llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, and llvm::ISD::SETULT.

◆ hasAllBUsers()

bool llvm::RISCVDAGToDAGISel::hasAllBUsers ( SDNode * Node ) const

inline

Definition at line 155 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

Referenced by Select().

◆ hasAllHUsers()

bool llvm::RISCVDAGToDAGISel::hasAllHUsers ( SDNode * Node ) const

inline

Definition at line 156 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

Referenced by Select().

◆ hasAllNBitUsers()

bool RISCVDAGToDAGISel::hasAllNBitUsers	(	SDNode *	Node,
		unsigned	Bits,
		const unsigned	Depth = 0 ) const

◆ hasAllWUsers()

bool llvm::RISCVDAGToDAGISel::hasAllWUsers ( SDNode * Node ) const

inline

Definition at line 157 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

Referenced by Select().

◆ orDisjoint()

bool RISCVDAGToDAGISel::orDisjoint ( const SDNode * Node ) const

Definition at line 4422 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::SelectionDAGISel::CurDAG, N, and llvm::ISD::OR.

Referenced by selectZExtImm32().

◆ PostprocessISelDAG()

void RISCVDAGToDAGISel::PostprocessISelDAG ( )

overridevirtual

PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 224 of file RISCVISelDAGToDAG.cpp.

References llvm::cast(), llvm::SelectionDAGISel::CurDAG, llvm::HandleSDNode::getValue(), and N.

◆ PreprocessISelDAG()

void RISCVDAGToDAGISel::PreprocessISelDAG ( )

overridevirtual

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 43 of file RISCVISelDAGToDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::ISD::ADD, llvm::ISD::ANY_EXTEND, llvm::any_of(), assert(), C(), llvm::cast(), llvm::MVT::changeVectorElementType(), llvm::ISD::Constant, llvm::SelectionDAGISel::CurDAG, llvm::dbgs(), DL, llvm::dyn_cast(), llvm::ISD::FP_EXTEND, llvm::TypeSize::getFixed(), llvm::MachinePointerInfo::getFixedStack(), llvm::RISCVMatInt::getIntMatCost(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::MVT::getVectorElementType(), llvm::MachinePointerInfo::getWithOffset(), llvm::Hi, Imm, INT64_MIN, llvm::ISD::INTRINSIC_W_CHAIN, llvm::isInt(), llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), llvm::MVT::isVector(), LLVM_DEBUG, llvm::Lo, llvm::SelectionDAGISel::MF, llvm::MachineMemOperand::MOLoad, N, Opc, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SUB, and llvm::ISD::TokenFactor.

◆ runOnMachineFunction()

bool llvm::RISCVDAGToDAGISel::runOnMachineFunction ( MachineFunction & MF )

inlineoverridevirtual

Reimplemented from llvm::SelectionDAGISel.

Definition at line 34 of file RISCVISelDAGToDAG.h.

References llvm::SelectionDAGISel::MF, and llvm::SelectionDAGISel::runOnMachineFunction().

◆ Select()

void RISCVDAGToDAGISel::Select ( SDNode * N )

overridevirtual

Main hook for targets to transform nodes into machine nodes.

Implements llvm::SelectionDAGISel.

Definition at line 1174 of file RISCVISelDAGToDAG.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, AbstractManglingParser< Derived, Alloc >::Ops, addVectorLoadStoreOperands(), llvm::ISD::AND, assert(), llvm::sampleprof::Base, llvm::bit_width(), llvm::ISD::BITCAST, llvm::APFloat::bitcastToAPInt(), buildGPRPair(), C(), CASE_VMNAND_VMSET_OPCODES, CASE_VMSLT_OPCODES, CASE_VMXOR_VMANDN_VMOR_OPCODES, llvm::cast(), llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::countr_one(), llvm::countr_zero(), llvm::SelectionDAGISel::CurDAG, llvm::dbgs(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), DL, Node::dump(), llvm::RISCVFPRndMode::DYN, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, extractGPRPair(), llvm::SDNode::getAsZExtVal(), llvm::APInt::getBitWidth(), llvm::SDValue::getConstantOperandVal(), llvm::RISCVTargetLowering::getLMUL(), getNode(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), llvm::TypeSize::getScalable(), llvm::MVT::getScalarSizeInBits(), getSegInstNF(), llvm::APInt::getSExtValue(), llvm::APInt::getSignedMinValue(), llvm::SDNode::getSimpleValueType(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::EVT::getStoreSize(), llvm::MVT::getStoreSize(), getTileReg(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), hasAllBUsers(), hasAllHUsers(), hasAllWUsers(), llvm::SDValue::hasOneUse(), llvm::Hi, I, Imm, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isa(), llvm::APInt::isAllOnes(), isApplicableToPLIOrPLUI(), llvm::MVT::isFixedLengthVector(), llvm::isInt(), llvm::SelectionDAGISel::IsLegalToFold(), llvm::isMask_64(), llvm::APFloat::isNegZero(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::APFloat::isPosZero(), llvm::isPowerOf2_64(), llvm::SelectionDAGISel::IsProfitableToFold(), llvm::MVT::isScalableVector(), llvm::isShiftedInt(), llvm::isShiftedMask_64(), llvm::APInt::isSplat(), llvm::isUInt(), llvm::APFloat::isZero(), LLVM_DEBUG, llvm_unreachable, llvm::RISCVVType::LMUL_F2, llvm::RISCVVType::LMUL_F4, llvm::RISCVVType::LMUL_F8, llvm::Lo, llvm::ISD::LOAD, llvm::Load, llvm::Log2_32(), llvm::M1(), llvm::RISCVVType::MASK_AGNOSTIC, llvm::maskTrailingOnes(), llvm::maskTrailingZeros(), llvm::MachineMemOperand::MONonTemporal, llvm::MONontemporalBit0, llvm::MONontemporalBit1, llvm::ISD::MUL, N, llvm::Offset, Opc, Operands, llvm::ISD::OR, P, llvm::ISD::POST_INC, PreferredLandingPadLabel, llvm::ISD::PREFETCH, llvm::SelectionDAGISel::ReplaceNode(), llvm::SelectionDAGISel::ReplaceUses(), llvm::report_fatal_error(), llvm::reportFatalUsageError(), llvm::RISCVFPRndMode::RNE, llvm::RISCV::RVVBitsPerBlock, llvm::ISD::SCALAR_TO_VECTOR, SelectAddrRegImm(), selectImm(), selectSF_VC_X_SE(), selectVLOp(), selectVLSEG(), selectVLSEGFF(), selectVLXSEG(), selectVSETVLI(), selectVSSEG(), selectVSXSEG(), selectXSfmmVSET(), llvm::MachineMemOperand::setFlags(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::SignExtend64(), llvm::MVT::SimpleTy, llvm::ISD::SMUL_LOHI, llvm::Splat, llvm::ISD::SPLAT_VECTOR, llvm::ISD::SRA, llvm::ISD::SRL, llvm::Store, llvm::RISCVVType::TAIL_AGNOSTIC, llvm::SelectionDAGISel::TLI, llvm::SelectionDAGISel::TM, TRI, llvm::APInt::trunc(), tryIndexedLoad(), tryShrinkShlLogicImm(), trySignedBitfieldExtract(), trySignedBitfieldInsertInSign(), tryUnsignedBitfieldExtract(), tryUnsignedBitfieldInsertInZero(), tryWideningMulAcc(), llvm::ISD::UMUL_LOHI, X, and llvm::ISD::XOR.

◆ SelectAddrFrameIndex()

bool RISCVDAGToDAGISel::SelectAddrFrameIndex	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset )

Definition at line 3448 of file RISCVISelDAGToDAG.cpp.

References llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::dyn_cast(), and llvm::Offset.

Referenced by SelectAddrRegImm(), SelectAddrRegImm9(), and SelectAddrRegImmLsb00000().

◆ SelectAddrRegImm()

bool RISCVDAGToDAGISel::SelectAddrRegImm	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset )

◆ SelectAddrRegImm26()

bool RISCVDAGToDAGISel::SelectAddrRegImm26	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset )

Similar to SelectAddrRegImm, except that the offset is a 26-bit signed immediate.

This is used by the Qualcomm Xqcilo large offset load/store instructions (qc.e.lw/qc.e.sw), whose offset field is 26 bits wide. Only matches offsets that do not fit a 12-bit signed immediate, so that offsets in the simm12 range keep using the shorter (and possibly compressible) standard load/store instructions.

Definition at line 3710 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::sampleprof::Base, llvm::cast(), llvm::SelectionDAGISel::CurDAG, DL, llvm::dyn_cast(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::isa(), llvm::isInt(), llvm::isShiftedUInt(), isWorthFoldingAdd(), llvm::maxIntN(), llvm::minIntN(), and llvm::Offset.

◆ SelectAddrRegImm9()

bool RISCVDAGToDAGISel::SelectAddrRegImm9	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset )

Similar to SelectAddrRegImm, except that the offset is restricted to uimm9.

Definition at line 3772 of file RISCVISelDAGToDAG.cpp.

References llvm::sampleprof::Base, llvm::cast(), llvm::SelectionDAGISel::CurDAG, DL, llvm::dyn_cast(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::isUInt(), llvm::Offset, and SelectAddrFrameIndex().

◆ SelectAddrRegImmLsb00000()

bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset )

Similar to SelectAddrRegImm, except that the least significant 5 bits of Offset should be all zeros.

Definition at line 3799 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::cast(), llvm::SelectionDAGISel::CurDAG, DL, llvm::dyn_cast(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::isa(), llvm::isInt(), llvm::Offset, SelectAddrFrameIndex(), and selectConstantAddr().

◆ SelectAddrRegReg()

bool RISCVDAGToDAGISel::SelectAddrRegReg	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset )

Definition at line 4030 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::sampleprof::Base, llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::isa(), and llvm::Offset.

◆ SelectAddrRegRegFixedScale()

template<unsigned ShiftAmount>

bool llvm::RISCVDAGToDAGISel::SelectAddrRegRegFixedScale	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Index )

inline

Definition at line 60 of file RISCVISelDAGToDAG.h.

References assert(), llvm::sampleprof::Base, llvm::SDNode::getAsZExtVal(), and SelectAddrRegRegScale().

◆ SelectAddrRegRegScale() [1/2]

bool RISCVDAGToDAGISel::SelectAddrRegRegScale	(	SDValue	Addr,
		ArrayRef< unsigned >	Amounts,
		SDValue &	Base,
		SDValue &	Index,
		SDValue &	Scale )

Definition at line 3924 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::dyn_cast(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getSimpleValueType(), llvm::is_contained(), llvm::isa(), llvm::isInt(), isWorthFoldingIntoRegRegScale(), N, and llvm::ISD::SHL.

Referenced by SelectAddrRegRegFixedScale(), SelectAddrRegRegScale(), and SelectAddrRegZextRegScale().

◆ SelectAddrRegRegScale() [2/2]

template<unsigned MaxShift>

bool llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Index,
		SDValue &	Scale )

inline

Definition at line 70 of file RISCVISelDAGToDAG.h.

References llvm::sampleprof::Base, and SelectAddrRegRegScale().

◆ SelectAddrRegZextRegFixedScale()

template<unsigned ShiftAmount, unsigned Bits>

bool llvm::RISCVDAGToDAGISel::SelectAddrRegZextRegFixedScale	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Index )

inline

Definition at line 82 of file RISCVISelDAGToDAG.h.

References assert(), llvm::sampleprof::Base, llvm::SDNode::getAsZExtVal(), and SelectAddrRegZextRegScale().

◆ SelectAddrRegZextRegScale() [1/2]

bool RISCVDAGToDAGISel::SelectAddrRegZextRegScale	(	SDValue	Addr,
		ArrayRef< unsigned >	Amounts,
		unsigned	Bits,
		SDValue &	Base,
		SDValue &	Index,
		SDValue &	Scale )

Definition at line 4011 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::AND, llvm::sampleprof::Base, C(), llvm::dyn_cast(), llvm::maskTrailingOnes(), and SelectAddrRegRegScale().

Referenced by SelectAddrRegZextRegFixedScale(), and SelectAddrRegZextRegScale().

◆ SelectAddrRegZextRegScale() [2/2]

template<unsigned MaxShift, unsigned Bits>

bool llvm::RISCVDAGToDAGISel::SelectAddrRegZextRegScale	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Index,
		SDValue &	Scale )

inline

Definition at line 93 of file RISCVISelDAGToDAG.h.

References llvm::sampleprof::Base, and SelectAddrRegZextRegScale().

◆ SelectInlineAsmMemoryOperand()

bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand	(	const SDValue &	Op,
		InlineAsm::ConstraintCode	ConstraintID,
		std::vector< SDValue > &	OutOps )

overridevirtual

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.

If this does not match or is not implemented, return true. The resultant operands (which will appear in the machine instruction) should be added to the OutOps vector.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 3420 of file RISCVISelDAGToDAG.cpp.

References llvm::InlineAsm::A, assert(), llvm::SelectionDAGISel::CurDAG, llvm::InlineAsm::getMemConstraintName(), llvm::InlineAsm::m, llvm::InlineAsm::o, llvm::report_fatal_error(), and SelectAddrRegImm().

◆ selectInvLogicImm()

bool RISCVDAGToDAGISel::selectInvLogicImm	(	SDValue	N,
		SDValue &	Val )

Definition at line 4493 of file RISCVISelDAGToDAG.cpp.

References llvm::all_of(), llvm::ISD::AND, llvm::cast(), llvm::SelectionDAGISel::CurDAG, Imm, llvm::isa(), llvm::isInt(), N, llvm::ISD::OR, selectImm(), and llvm::ISD::XOR.

◆ selectLow8BitsVSplat()

bool RISCVDAGToDAGISel::selectLow8BitsVSplat	(	SDValue	N,
		SDValue &	SplatVal )

Definition at line 4897 of file RISCVISelDAGToDAG.cpp.

References N, selectVSplat(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.

◆ selectNegImm()

bool RISCVDAGToDAGISel::selectNegImm	(	SDValue	N,
		SDValue &	Val )

Definition at line 4465 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::all_of(), llvm::cast(), Imm, INT64_MIN, llvm::isa(), llvm::isInt(), and N.

Referenced by selectVSplatImm64Neg().

◆ selectRVVSimm5() [1/2]

template<unsigned Width>

bool llvm::RISCVDAGToDAGISel::selectRVVSimm5	(	SDValue	N,
		SDValue &	Imm )

inline

Definition at line 179 of file RISCVISelDAGToDAG.h.

References Imm, N, and selectRVVSimm5().

◆ selectRVVSimm5() [2/2]

bool RISCVDAGToDAGISel::selectRVVSimm5	(	SDValue	N,
		unsigned	Width,
		SDValue &	Imm )

Definition at line 4959 of file RISCVISelDAGToDAG.cpp.

References C(), llvm::SelectionDAGISel::CurDAG, llvm::dyn_cast(), Imm, llvm::isInt(), N, and llvm::SignExtend64().

Referenced by selectRVVSimm5().

◆ selectScalarFPAsInt()

bool RISCVDAGToDAGISel::selectScalarFPAsInt	(	SDValue	N,
		SDValue &	Imm )

Definition at line 4923 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::ISD::BITCAST, llvm::APFloat::bitcastToAPInt(), llvm::SelectionDAGISel::CurDAG, DL, llvm::dyn_cast(), llvm::APInt::getSExtValue(), llvm::SDNode::getSimpleValueType(), llvm::ConstantFPSDNode::getValueAPF(), Imm, llvm::APFloat::isNegZero(), llvm::APFloat::isPosZero(), N, and selectImm().

◆ selectSETCC()

bool RISCVDAGToDAGISel::selectSETCC	(	SDValue	N,
		ISD::CondCode	ExpectedCCVal,
		SDValue &	Val,
		bool	OneUse )

RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with 0.

This function emits instructions that convert the seteq/setne into something that can be compared with 0. ExpectedCCVal indicates the condition code to attempt to match (e.g. ISD::SETNE).

Definition at line 4120 of file RISCVISelDAGToDAG.cpp.

References assert(), C(), llvm::cast(), llvm::SelectionDAGISel::CurDAG, DL, llvm::dyn_cast(), llvm::isInt(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), llvm::isPowerOf2_64(), llvm::Log2_64(), N, Opc, llvm::ISD::SETCC, and llvm::ISD::SIGN_EXTEND_INREG.