LLVM 20.0.0git
Public Member Functions | Static Public Member Functions | List of all members
llvm::RISCVDAGToDAGISel Class Reference

#include "Target/RISCV/RISCVISelDAGToDAG.h"

Inheritance diagram for llvm::RISCVDAGToDAGISel:
Inheritance graph
[legend]

Public Member Functions

 RISCVDAGToDAGISel ()=delete
 
 RISCVDAGToDAGISel (RISCVTargetMachine &TargetMachine, CodeGenOptLevel OptLevel)
 
bool runOnMachineFunction (MachineFunction &MF) override
 
void PreprocessISelDAG () override
 PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.
 
void PostprocessISelDAG () override
 PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
 
void Select (SDNode *Node) override
 Main hook for targets to transform nodes into machine nodes.
 
bool SelectInlineAsmMemoryOperand (const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override
 SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.
 
bool SelectAddrFrameIndex (SDValue Addr, SDValue &Base, SDValue &Offset)
 
bool SelectFrameAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset)
 
bool SelectAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset, bool IsINX=false)
 
bool SelectAddrRegImmINX (SDValue Addr, SDValue &Base, SDValue &Offset)
 
bool SelectAddrRegImmLsb00000 (SDValue Addr, SDValue &Base, SDValue &Offset)
 Similar to SelectAddrRegImm, except that the least significant 5 bits of Offset shoule be all zeros.
 
bool SelectAddrRegRegScale (SDValue Addr, unsigned MaxShiftAmount, SDValue &Base, SDValue &Index, SDValue &Scale)
 
template<unsigned MaxShift>
bool SelectAddrRegRegScale (SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
 
template<unsigned MaxShift, unsigned Bits>
bool SelectAddrRegZextRegScale (SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
 
bool SelectAddrRegReg (SDValue Addr, SDValue &Base, SDValue &Offset)
 
bool tryShrinkShlLogicImm (SDNode *Node)
 
bool trySignedBitfieldExtract (SDNode *Node)
 
bool tryIndexedLoad (SDNode *Node)
 
bool selectShiftMask (SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
 
bool selectShiftMaskXLen (SDValue N, SDValue &ShAmt)
 
bool selectShiftMask32 (SDValue N, SDValue &ShAmt)
 
bool selectSETCC (SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val)
 RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with 0.
 
bool selectSETNE (SDValue N, SDValue &Val)
 
bool selectSETEQ (SDValue N, SDValue &Val)
 
bool selectSExtBits (SDValue N, unsigned Bits, SDValue &Val)
 
template<unsigned Bits>
bool selectSExtBits (SDValue N, SDValue &Val)
 
bool selectZExtBits (SDValue N, unsigned Bits, SDValue &Val)
 
template<unsigned Bits>
bool selectZExtBits (SDValue N, SDValue &Val)
 
bool selectSHXADDOp (SDValue N, unsigned ShAmt, SDValue &Val)
 Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
 
template<unsigned ShAmt>
bool selectSHXADDOp (SDValue N, SDValue &Val)
 
bool selectSHXADD_UWOp (SDValue N, unsigned ShAmt, SDValue &Val)
 Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
 
template<unsigned ShAmt>
bool selectSHXADD_UWOp (SDValue N, SDValue &Val)
 
bool hasAllNBitUsers (SDNode *Node, unsigned Bits, const unsigned Depth=0) const
 
bool hasAllBUsers (SDNode *Node) const
 
bool hasAllHUsers (SDNode *Node) const
 
bool hasAllWUsers (SDNode *Node) const
 
bool selectSimm5Shl2 (SDValue N, SDValue &Simm5, SDValue &Shl2)
 
bool selectVLOp (SDValue N, SDValue &VL)
 
bool selectVSplat (SDValue N, SDValue &SplatVal)
 
bool selectVSplatSimm5 (SDValue N, SDValue &SplatVal)
 
bool selectVSplatUimm (SDValue N, unsigned Bits, SDValue &SplatVal)
 
template<unsigned Bits>
bool selectVSplatUimmBits (SDValue N, SDValue &Val)
 
bool selectVSplatSimm5Plus1 (SDValue N, SDValue &SplatVal)
 
bool selectVSplatSimm5Plus1NonZero (SDValue N, SDValue &SplatVal)
 
bool selectLow8BitsVSplat (SDValue N, SDValue &SplatVal)
 
bool selectFPImm (SDValue N, SDValue &Imm)
 
bool selectRVVSimm5 (SDValue N, unsigned Width, SDValue &Imm)
 
template<unsigned Width>
bool selectRVVSimm5 (SDValue N, SDValue &Imm)
 
void addVectorLoadStoreOperands (SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)
 
void selectVLSEG (SDNode *Node, bool IsMasked, bool IsStrided)
 
void selectVLSEGFF (SDNode *Node, bool IsMasked)
 
void selectVLXSEG (SDNode *Node, bool IsMasked, bool IsOrdered)
 
void selectVSSEG (SDNode *Node, bool IsMasked, bool IsStrided)
 
void selectVSXSEG (SDNode *Node, bool IsMasked, bool IsOrdered)
 
void selectVSETVLI (SDNode *Node)
 
void selectSF_VC_X_SE (SDNode *Node)
 
- Public Member Functions inherited from llvm::SelectionDAGISel
 SelectionDAGISel (TargetMachine &tm, CodeGenOptLevel OL=CodeGenOptLevel::Default)
 
virtual ~SelectionDAGISel ()
 
const TargetLoweringgetTargetLowering () const
 
void initializeAnalysisResults (MachineFunctionAnalysisManager &MFAM)
 
void initializeAnalysisResults (MachineFunctionPass &MFP)
 
virtual bool runOnMachineFunction (MachineFunction &mf)
 
virtual void emitFunctionEntryCode ()
 
virtual void PreprocessISelDAG ()
 PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.
 
virtual void PostprocessISelDAG ()
 PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
 
virtual void Select (SDNode *N)=0
 Main hook for targets to transform nodes into machine nodes.
 
virtual bool SelectInlineAsmMemoryOperand (const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps)
 SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.
 
virtual bool IsProfitableToFold (SDValue N, SDNode *U, SDNode *Root) const
 IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during instruction selection that starts at Root.
 
bool CheckAndMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
 CheckAndMask - The isel is trying to match something like (and X, 255).
 
bool CheckOrMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
 CheckOrMask - The isel is trying to match something like (or X, 255).
 
virtual bool CheckPatternPredicate (unsigned PredNo) const
 CheckPatternPredicate - This function is generated by tblgen in the target.
 
virtual bool CheckNodePredicate (SDNode *N, unsigned PredNo) const
 CheckNodePredicate - This function is generated by tblgen in the target.
 
virtual bool CheckNodePredicateWithOperands (SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const
 CheckNodePredicateWithOperands - This function is generated by tblgen in the target.
 
virtual bool CheckComplexPattern (SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)
 
virtual SDValue RunSDNodeXForm (SDValue V, unsigned XFormNo)
 
void SelectCodeCommon (SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize)
 
virtual bool ComplexPatternFuncMutatesDAG () const
 Return true if complex patterns for this target can mutate the DAG.
 
bool mayRaiseFPException (SDNode *Node) const
 Return whether the node may raise an FP exception.
 
bool isOrEquivalentToAdd (const SDNode *N) const
 

Static Public Member Functions

static RISCVCC::CondCode getRISCVCCForIntCC (ISD::CondCode CC)
 
- Static Public Member Functions inherited from llvm::SelectionDAGISel
static bool IsLegalToFold (SDValue N, SDNode *U, SDNode *Root, CodeGenOptLevel OptLevel, bool IgnoreChains=false)
 IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction selection that starts at Root.
 
static void InvalidateNodeId (SDNode *N)
 
static int getUninvalidatedNodeId (SDNode *N)
 
static void EnforceNodeIdInvariant (SDNode *N)
 
static int getNumFixedFromVariadicInfo (unsigned Flags)
 getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values that should be skipped when copying from the root.
 

Additional Inherited Members

- Public Types inherited from llvm::SelectionDAGISel
enum  BuiltinOpcodes {
  OPC_Scope , OPC_RecordNode , OPC_RecordChild0 , OPC_RecordChild1 ,
  OPC_RecordChild2 , OPC_RecordChild3 , OPC_RecordChild4 , OPC_RecordChild5 ,
  OPC_RecordChild6 , OPC_RecordChild7 , OPC_RecordMemRef , OPC_CaptureGlueInput ,
  OPC_MoveChild , OPC_MoveChild0 , OPC_MoveChild1 , OPC_MoveChild2 ,
  OPC_MoveChild3 , OPC_MoveChild4 , OPC_MoveChild5 , OPC_MoveChild6 ,
  OPC_MoveChild7 , OPC_MoveSibling , OPC_MoveSibling0 , OPC_MoveSibling1 ,
  OPC_MoveSibling2 , OPC_MoveSibling3 , OPC_MoveSibling4 , OPC_MoveSibling5 ,
  OPC_MoveSibling6 , OPC_MoveSibling7 , OPC_MoveParent , OPC_CheckSame ,
  OPC_CheckChild0Same , OPC_CheckChild1Same , OPC_CheckChild2Same , OPC_CheckChild3Same ,
  OPC_CheckPatternPredicate , OPC_CheckPatternPredicate0 , OPC_CheckPatternPredicate1 , OPC_CheckPatternPredicate2 ,
  OPC_CheckPatternPredicate3 , OPC_CheckPatternPredicate4 , OPC_CheckPatternPredicate5 , OPC_CheckPatternPredicate6 ,
  OPC_CheckPatternPredicate7 , OPC_CheckPatternPredicateTwoByte , OPC_CheckPredicate , OPC_CheckPredicate0 ,
  OPC_CheckPredicate1 , OPC_CheckPredicate2 , OPC_CheckPredicate3 , OPC_CheckPredicate4 ,
  OPC_CheckPredicate5 , OPC_CheckPredicate6 , OPC_CheckPredicate7 , OPC_CheckPredicateWithOperands ,
  OPC_CheckOpcode , OPC_SwitchOpcode , OPC_CheckType , OPC_CheckTypeI32 ,
  OPC_CheckTypeI64 , OPC_CheckTypeRes , OPC_SwitchType , OPC_CheckChild0Type ,
  OPC_CheckChild1Type , OPC_CheckChild2Type , OPC_CheckChild3Type , OPC_CheckChild4Type ,
  OPC_CheckChild5Type , OPC_CheckChild6Type , OPC_CheckChild7Type , OPC_CheckChild0TypeI32 ,
  OPC_CheckChild1TypeI32 , OPC_CheckChild2TypeI32 , OPC_CheckChild3TypeI32 , OPC_CheckChild4TypeI32 ,
  OPC_CheckChild5TypeI32 , OPC_CheckChild6TypeI32 , OPC_CheckChild7TypeI32 , OPC_CheckChild0TypeI64 ,
  OPC_CheckChild1TypeI64 , OPC_CheckChild2TypeI64 , OPC_CheckChild3TypeI64 , OPC_CheckChild4TypeI64 ,
  OPC_CheckChild5TypeI64 , OPC_CheckChild6TypeI64 , OPC_CheckChild7TypeI64 , OPC_CheckInteger ,
  OPC_CheckChild0Integer , OPC_CheckChild1Integer , OPC_CheckChild2Integer , OPC_CheckChild3Integer ,
  OPC_CheckChild4Integer , OPC_CheckCondCode , OPC_CheckChild2CondCode , OPC_CheckValueType ,
  OPC_CheckComplexPat , OPC_CheckComplexPat0 , OPC_CheckComplexPat1 , OPC_CheckComplexPat2 ,
  OPC_CheckComplexPat3 , OPC_CheckComplexPat4 , OPC_CheckComplexPat5 , OPC_CheckComplexPat6 ,
  OPC_CheckComplexPat7 , OPC_CheckAndImm , OPC_CheckOrImm , OPC_CheckImmAllOnesV ,
  OPC_CheckImmAllZerosV , OPC_CheckFoldableChainNode , OPC_EmitInteger , OPC_EmitInteger8 ,
  OPC_EmitInteger16 , OPC_EmitInteger32 , OPC_EmitInteger64 , OPC_EmitStringInteger ,
  OPC_EmitStringInteger32 , OPC_EmitRegister , OPC_EmitRegisterI32 , OPC_EmitRegisterI64 ,
  OPC_EmitRegister2 , OPC_EmitConvertToTarget , OPC_EmitConvertToTarget0 , OPC_EmitConvertToTarget1 ,
  OPC_EmitConvertToTarget2 , OPC_EmitConvertToTarget3 , OPC_EmitConvertToTarget4 , OPC_EmitConvertToTarget5 ,
  OPC_EmitConvertToTarget6 , OPC_EmitConvertToTarget7 , OPC_EmitMergeInputChains , OPC_EmitMergeInputChains1_0 ,
  OPC_EmitMergeInputChains1_1 , OPC_EmitMergeInputChains1_2 , OPC_EmitCopyToReg , OPC_EmitCopyToReg0 ,
  OPC_EmitCopyToReg1 , OPC_EmitCopyToReg2 , OPC_EmitCopyToReg3 , OPC_EmitCopyToReg4 ,
  OPC_EmitCopyToReg5 , OPC_EmitCopyToReg6 , OPC_EmitCopyToReg7 , OPC_EmitCopyToRegTwoByte ,
  OPC_EmitNodeXForm , OPC_EmitNode , OPC_EmitNode0 , OPC_EmitNode1 ,
  OPC_EmitNode2 , OPC_EmitNode0None , OPC_EmitNode1None , OPC_EmitNode2None ,
  OPC_EmitNode0Chain , OPC_EmitNode1Chain , OPC_EmitNode2Chain , OPC_MorphNodeTo ,
  OPC_MorphNodeTo0 , OPC_MorphNodeTo1 , OPC_MorphNodeTo2 , OPC_MorphNodeTo0None ,
  OPC_MorphNodeTo1None , OPC_MorphNodeTo2None , OPC_MorphNodeTo0Chain , OPC_MorphNodeTo1Chain ,
  OPC_MorphNodeTo2Chain , OPC_MorphNodeTo0GlueInput , OPC_MorphNodeTo1GlueInput , OPC_MorphNodeTo2GlueInput ,
  OPC_MorphNodeTo0GlueOutput , OPC_MorphNodeTo1GlueOutput , OPC_MorphNodeTo2GlueOutput , OPC_CompleteMatch ,
  OPC_Coverage
}
 
enum  {
  OPFL_None = 0 , OPFL_Chain = 1 , OPFL_GlueInput = 2 , OPFL_GlueOutput = 4 ,
  OPFL_MemRefs = 8 , OPFL_Variadic0 = 1<<4 , OPFL_Variadic1 = 2<<4 , OPFL_Variadic2 = 3<<4 ,
  OPFL_Variadic3 = 4<<4 , OPFL_Variadic4 = 5<<4 , OPFL_Variadic5 = 6<<4 , OPFL_Variadic6 = 7<<4 ,
  OPFL_VariadicInfo = OPFL_Variadic6
}
 
- Public Attributes inherited from llvm::SelectionDAGISel
TargetMachineTM
 
const TargetLibraryInfoLibInfo
 
std::unique_ptr< FunctionLoweringInfoFuncInfo
 
SwiftErrorValueTrackingSwiftError
 
MachineFunctionMF
 
MachineModuleInfoMMI
 
MachineRegisterInfoRegInfo
 
SelectionDAGCurDAG
 
std::unique_ptr< SelectionDAGBuilderSDB
 
AAResultsAA = nullptr
 
AssumptionCacheAC = nullptr
 
GCFunctionInfoGFI = nullptr
 
SSPLayoutInfoSP = nullptr
 
CodeGenOptLevel OptLevel
 
const TargetInstrInfoTII
 
const TargetLoweringTLI
 
bool FastISelFailed
 
SmallPtrSet< const Instruction *, 4 > ElidedArgCopyInstrs
 
std::unique_ptr< OptimizationRemarkEmitterORE
 Current optimization remark emitter.
 
bool MatchFilterFuncName = false
 True if the function currently processing is in the function printing list (i.e.
 
StringRef FuncName
 
- Protected Member Functions inherited from llvm::SelectionDAGISel
void ReplaceUses (SDValue F, SDValue T)
 ReplaceUses - replace all uses of the old node F with the use of the new node T.
 
void ReplaceUses (const SDValue *F, const SDValue *T, unsigned Num)
 ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T.
 
void ReplaceUses (SDNode *F, SDNode *T)
 ReplaceUses - replace all uses of the old node F with the use of the new node T.
 
void ReplaceNode (SDNode *F, SDNode *T)
 Replace all uses of F with T, then remove F from the DAG.
 
void SelectInlineAsmMemoryOperands (std::vector< SDValue > &Ops, const SDLoc &DL)
 SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
 
virtual StringRef getPatternForIndex (unsigned index)
 getPatternForIndex - Patterns selected by tablegen during ISEL
 
virtual StringRef getIncludePathForIndex (unsigned index)
 getIncludePathForIndex - get the td source location of pattern instantiation
 
bool shouldOptForSize (const MachineFunction *MF) const
 
- Protected Attributes inherited from llvm::SelectionDAGISel
unsigned DAGSize = 0
 DAGSize - Size of DAG being instruction selected.
 

Detailed Description

Definition at line 24 of file RISCVISelDAGToDAG.h.

Constructor & Destructor Documentation

◆ RISCVDAGToDAGISel() [1/2]

llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel ( )
delete

◆ RISCVDAGToDAGISel() [2/2]

llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel ( RISCVTargetMachine TargetMachine,
CodeGenOptLevel  OptLevel 
)
inlineexplicit

Definition at line 30 of file RISCVISelDAGToDAG.h.

Member Function Documentation

◆ addVectorLoadStoreOperands()

void RISCVDAGToDAGISel::addVectorLoadStoreOperands ( SDNode Node,
unsigned  SEWImm,
const SDLoc DL,
unsigned  CurOp,
bool  IsMasked,
bool  IsStridedOrIndexed,
SmallVectorImpl< SDValue > &  Operands,
bool  IsLoad = false,
MVT IndexVT = nullptr 
)

◆ getRISCVCCForIntCC()

static RISCVCC::CondCode llvm::RISCVDAGToDAGISel::getRISCVCCForIntCC ( ISD::CondCode  CC)
inlinestatic

◆ hasAllBUsers()

bool llvm::RISCVDAGToDAGISel::hasAllBUsers ( SDNode Node) const
inline

Definition at line 124 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

Referenced by Select().

◆ hasAllHUsers()

bool llvm::RISCVDAGToDAGISel::hasAllHUsers ( SDNode Node) const
inline

Definition at line 125 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

Referenced by Select().

◆ hasAllNBitUsers()

bool RISCVDAGToDAGISel::hasAllNBitUsers ( SDNode Node,
unsigned  Bits,
const unsigned  Depth = 0 
) const

◆ hasAllWUsers()

bool llvm::RISCVDAGToDAGISel::hasAllWUsers ( SDNode Node) const
inline

Definition at line 126 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

Referenced by Select().

◆ PostprocessISelDAG()

void RISCVDAGToDAGISel::PostprocessISelDAG ( )
overridevirtual

◆ PreprocessISelDAG()

void RISCVDAGToDAGISel::PreprocessISelDAG ( )
overridevirtual

◆ runOnMachineFunction()

bool llvm::RISCVDAGToDAGISel::runOnMachineFunction ( MachineFunction MF)
inlineoverridevirtual

◆ Select()

void RISCVDAGToDAGISel::Select ( SDNode N)
overridevirtual

Main hook for targets to transform nodes into machine nodes.

Implements llvm::SelectionDAGISel.

Definition at line 878 of file RISCVISelDAGToDAG.cpp.

References addVectorLoadStoreOperands(), llvm::ISD::AND, assert(), llvm::sampleprof::Base, llvm::bit_width(), llvm::ISD::BITCAST, llvm::APFloat::bitcastToAPInt(), llvm::RISCVISD::BuildPairF64, llvm::CallingConv::C, CASE_VMSLT_OPCODES, CASE_VMSLT_VMNAND_VMSET_OPCODES, CASE_VMXOR_VMANDN_VMOR_OPCODES, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::countr_one(), llvm::countr_zero(), llvm::SelectionDAGISel::CurDAG, llvm::dbgs(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), DL, llvm::RISCVSubtarget::expandVScale(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetMachine::getOptLevel(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), llvm::SelectionDAG::getRegister(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::TypeSize::getScalable(), llvm::MVT::getScalarSizeInBits(), llvm::APInt::getSExtValue(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::EVT::getStoreSize(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SelectionDAG::getTargetInsertSubreg(), llvm::RISCVSubtarget::getTargetLowering(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), hasAllBUsers(), hasAllHUsers(), hasAllWUsers(), llvm::SDValue::hasOneUse(), llvm::Hi, Idx, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::RISCVSubtarget::is64Bit(), llvm::MVT::isFixedLengthVector(), llvm::SelectionDAGISel::IsLegalToFold(), llvm::isMask_64(), llvm::APFloat::isNegZero(), llvm::isOneConstant(), llvm::APFloat::isPosZero(), llvm::isPowerOf2_64(), llvm::SelectionDAGISel::IsProfitableToFold(), llvm::MVT::isScalableVector(), llvm::isShiftedMask_64(), llvm::APFloat::isZero(), LLVM_DEBUG, llvm_unreachable, llvm::RISCVII::LMUL_F2, llvm::RISCVII::LMUL_F4, llvm::RISCVII::LMUL_F8, llvm::Lo, llvm::ISD::LOAD, llvm::Log2_32(), llvm::M1(), llvm::RISCVII::MASK_AGNOSTIC, llvm::MachineMemOperand::MONonTemporal, llvm::MONontemporalBit0, llvm::MONontemporalBit1, llvm::ISD::MUL, N, llvm::Offset, Operands, llvm::ISD::OR, P, llvm::ISD::POST_INC, llvm::ISD::PREFETCH, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAGISel::ReplaceNode(), llvm::SelectionDAGISel::ReplaceUses(), llvm::report_fatal_error(), llvm::RISCVFPRndMode::RNE, llvm::RISCV::RVVBitsPerBlock, selectImm(), selectSF_VC_X_SE(), selectVLOp(), selectVLSEG(), selectVLSEGFF(), selectVLXSEG(), selectVSETVLI(), selectVSSEG(), selectVSXSEG(), llvm::MachineMemOperand::setFlags(), llvm::SelectionDAG::setNodeMemRefs(), llvm::ISD::SEXTLOAD, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::MVT::SimpleTy, llvm::RISCVISD::SplitF64, llvm::ISD::SRA, llvm::ISD::SRL, llvm::RISCVII::TAIL_AGNOSTIC, llvm::SelectionDAGISel::TLI, llvm::SelectionDAGISel::TM, TRI, tryIndexedLoad(), tryShrinkShlLogicImm(), trySignedBitfieldExtract(), llvm::RISCVISD::VFMV_S_F_VL, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_S_X_VL, llvm::RISCVISD::VMV_V_X_VL, X, and llvm::ISD::XOR.

◆ SelectAddrFrameIndex()

bool RISCVDAGToDAGISel::SelectAddrFrameIndex ( SDValue  Addr,
SDValue Base,
SDValue Offset 
)

◆ SelectAddrRegImm()

bool RISCVDAGToDAGISel::SelectAddrRegImm ( SDValue  Addr,
SDValue Base,
SDValue Offset,
bool  IsINX = false 
)

◆ SelectAddrRegImmINX()

bool llvm::RISCVDAGToDAGISel::SelectAddrRegImmINX ( SDValue  Addr,
SDValue Base,
SDValue Offset 
)
inline

Definition at line 52 of file RISCVISelDAGToDAG.h.

References Addr, llvm::sampleprof::Base, llvm::Offset, and SelectAddrRegImm().

◆ SelectAddrRegImmLsb00000()

bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000 ( SDValue  Addr,
SDValue Base,
SDValue Offset 
)

◆ SelectAddrRegReg()

bool RISCVDAGToDAGISel::SelectAddrRegReg ( SDValue  Addr,
SDValue Base,
SDValue Offset 
)

Definition at line 2777 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, Addr, llvm::sampleprof::Base, and llvm::Offset.

◆ SelectAddrRegRegScale() [1/2]

template<unsigned MaxShift>
bool llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale ( SDValue  Addr,
SDValue Base,
SDValue Index,
SDValue Scale 
)
inline

Definition at line 61 of file RISCVISelDAGToDAG.h.

References Addr, llvm::sampleprof::Base, and SelectAddrRegRegScale().

◆ SelectAddrRegRegScale() [2/2]

bool RISCVDAGToDAGISel::SelectAddrRegRegScale ( SDValue  Addr,
unsigned  MaxShiftAmount,
SDValue Base,
SDValue Index,
SDValue Scale 
)

◆ SelectAddrRegZextRegScale()

template<unsigned MaxShift, unsigned Bits>
bool llvm::RISCVDAGToDAGISel::SelectAddrRegZextRegScale ( SDValue  Addr,
SDValue Base,
SDValue Index,
SDValue Scale 
)
inline

◆ selectFPImm()

bool RISCVDAGToDAGISel::selectFPImm ( SDValue  N,
SDValue Imm 
)

◆ SelectFrameAddrRegImm()

bool RISCVDAGToDAGISel::SelectFrameAddrRegImm ( SDValue  Addr,
SDValue Base,
SDValue Offset 
)

◆ SelectInlineAsmMemoryOperand()

bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand ( const SDValue Op,
InlineAsm::ConstraintCode  ConstraintID,
std::vector< SDValue > &  OutOps 
)
overridevirtual

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.

If this does not match or is not implemented, return true. The resultant operands (which will appear in the machine instruction) should be added to the OutOps vector.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 2427 of file RISCVISelDAGToDAG.cpp.

References llvm::InlineAsm::A, assert(), llvm::SelectionDAGISel::CurDAG, llvm::InlineAsm::getMemConstraintName(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::InlineAsm::m, llvm::InlineAsm::o, llvm::report_fatal_error(), and SelectAddrRegImm().

◆ selectLow8BitsVSplat()

bool RISCVDAGToDAGISel::selectLow8BitsVSplat ( SDValue  N,
SDValue SplatVal 
)

◆ selectRVVSimm5() [1/2]

template<unsigned Width>
bool llvm::RISCVDAGToDAGISel::selectRVVSimm5 ( SDValue  N,
SDValue Imm 
)
inline

Definition at line 146 of file RISCVISelDAGToDAG.h.

References N, and selectRVVSimm5().

◆ selectRVVSimm5() [2/2]

bool RISCVDAGToDAGISel::selectRVVSimm5 ( SDValue  N,
unsigned  Width,
SDValue Imm 
)

◆ selectSETCC()

bool RISCVDAGToDAGISel::selectSETCC ( SDValue  N,
ISD::CondCode  ExpectedCCVal,
SDValue Val 
)

RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with 0.

This function emits instructions that convert the seteq/setne into something that can be compared with 0. ExpectedCCVal indicates the condition code to attempt to match (e.g. ISD::SETNE).

Definition at line 2867 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), LHS, N, RHS, and llvm::ISD::SETCC.

Referenced by selectSETEQ(), and selectSETNE().

◆ selectSETEQ()

bool llvm::RISCVDAGToDAGISel::selectSETEQ ( SDValue  N,
SDValue Val 
)
inline

Definition at line 99 of file RISCVISelDAGToDAG.h.

References N, selectSETCC(), and llvm::ISD::SETEQ.

◆ selectSETNE()

bool llvm::RISCVDAGToDAGISel::selectSETNE ( SDValue  N,
SDValue Val 
)
inline

Definition at line 96 of file RISCVISelDAGToDAG.h.

References N, selectSETCC(), and llvm::ISD::SETNE.

◆ selectSExtBits() [1/2]

template<unsigned Bits>
bool llvm::RISCVDAGToDAGISel::selectSExtBits ( SDValue  N,
SDValue Val 
)
inline

Definition at line 104 of file RISCVISelDAGToDAG.h.

References N, and selectSExtBits().

◆ selectSExtBits() [2/2]

bool RISCVDAGToDAGISel::selectSExtBits ( SDValue  N,
unsigned  Bits,
SDValue Val 
)

◆ selectSF_VC_X_SE()

void RISCVDAGToDAGISel::selectSF_VC_X_SE ( SDNode Node)

◆ selectShiftMask()

bool RISCVDAGToDAGISel::selectShiftMask ( SDValue  N,
unsigned  ShiftWidth,
SDValue ShAmt 
)

◆ selectShiftMask32()

bool llvm::RISCVDAGToDAGISel::selectShiftMask32 ( SDValue  N,
SDValue ShAmt 
)
inline

Definition at line 91 of file RISCVISelDAGToDAG.h.

References N, and selectShiftMask().

◆ selectShiftMaskXLen()

bool llvm::RISCVDAGToDAGISel::selectShiftMaskXLen ( SDValue  N,
SDValue ShAmt 
)
inline

Definition at line 88 of file RISCVISelDAGToDAG.h.

References llvm::RISCVSubtarget::getXLen(), N, and selectShiftMask().

◆ selectSHXADD_UWOp() [1/2]

template<unsigned ShAmt>
bool llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp ( SDValue  N,
SDValue Val 
)
inline

Definition at line 118 of file RISCVISelDAGToDAG.h.

References N, and selectSHXADD_UWOp().

◆ selectSHXADD_UWOp() [2/2]

bool RISCVDAGToDAGISel::selectSHXADD_UWOp ( SDValue  N,
unsigned  ShAmt,
SDValue Val 
)

Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.

ShAmt contains 1, 2, or 3 and is set based on which SHXADD_UW we are trying to match.

Definition at line 3069 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::AND, llvm::countl_zero(), llvm::countr_zero(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), llvm::isShiftedMask_64(), N, and llvm::ISD::SHL.

Referenced by selectSHXADD_UWOp().

◆ selectSHXADDOp() [1/2]

template<unsigned ShAmt>
bool llvm::RISCVDAGToDAGISel::selectSHXADDOp ( SDValue  N,
SDValue Val 
)
inline

Definition at line 113 of file RISCVISelDAGToDAG.h.

References N, and selectSHXADDOp().

◆ selectSHXADDOp() [2/2]

bool RISCVDAGToDAGISel::selectSHXADDOp ( SDValue  N,
unsigned  ShAmt,
SDValue Val 
)

◆ selectSimm5Shl2()

bool RISCVDAGToDAGISel::selectSimm5Shl2 ( SDValue  N,
SDValue Simm5,
SDValue Shl2 
)

◆ selectVLOp()

bool RISCVDAGToDAGISel::selectVLOp ( SDValue  N,
SDValue VL 
)

◆ selectVLSEG()

void RISCVDAGToDAGISel::selectVLSEG ( SDNode Node,
bool  IsMasked,
bool  IsStrided 
)

◆ selectVLSEGFF()

void RISCVDAGToDAGISel::selectVLSEGFF ( SDNode Node,
bool  IsMasked 
)

◆ selectVLXSEG()

void RISCVDAGToDAGISel::selectVLXSEG ( SDNode Node,
bool  IsMasked,
bool  IsOrdered 
)

◆ selectVSETVLI()

void RISCVDAGToDAGISel::selectVSETVLI ( SDNode Node)

◆ selectVSplat()

bool RISCVDAGToDAGISel::selectVSplat ( SDValue  N,
SDValue SplatVal 
)

Definition at line 3369 of file RISCVISelDAGToDAG.cpp.

References findVSplat(), N, and llvm::Splat.

Referenced by selectLow8BitsVSplat().

◆ selectVSplatSimm5()

bool RISCVDAGToDAGISel::selectVSplatSimm5 ( SDValue  N,
SDValue SplatVal 
)

◆ selectVSplatSimm5Plus1()

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1 ( SDValue  N,
SDValue SplatVal 
)

◆ selectVSplatSimm5Plus1NonZero()

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero ( SDValue  N,
SDValue SplatVal 
)

◆ selectVSplatUimm()

bool RISCVDAGToDAGISel::selectVSplatUimm ( SDValue  N,
unsigned  Bits,
SDValue SplatVal 
)

◆ selectVSplatUimmBits()

template<unsigned Bits>
bool llvm::RISCVDAGToDAGISel::selectVSplatUimmBits ( SDValue  N,
SDValue Val 
)
inline

Definition at line 135 of file RISCVISelDAGToDAG.h.

References N, and selectVSplatUimm().

◆ selectVSSEG()

void RISCVDAGToDAGISel::selectVSSEG ( SDNode Node,
bool  IsMasked,
bool  IsStrided 
)

◆ selectVSXSEG()

void RISCVDAGToDAGISel::selectVSXSEG ( SDNode Node,
bool  IsMasked,
bool  IsOrdered 
)

◆ selectZExtBits() [1/2]

template<unsigned Bits>
bool llvm::RISCVDAGToDAGISel::selectZExtBits ( SDValue  N,
SDValue Val 
)
inline

Definition at line 108 of file RISCVISelDAGToDAG.h.

References N, and selectZExtBits().

◆ selectZExtBits() [2/2]

bool RISCVDAGToDAGISel::selectZExtBits ( SDValue  N,
unsigned  Bits,
SDValue Val 
)

◆ tryIndexedLoad()

bool RISCVDAGToDAGISel::tryIndexedLoad ( SDNode Node)

◆ tryShrinkShlLogicImm()

bool RISCVDAGToDAGISel::tryShrinkShlLogicImm ( SDNode Node)

◆ trySignedBitfieldExtract()

bool RISCVDAGToDAGISel::trySignedBitfieldExtract ( SDNode Node)

The documentation for this class was generated from the following files: