#include "Target/RISCV/RISCVISelDAGToDAG.h"

Inheritance diagram for llvm::RISCVDAGToDAGISel:

[legend]

Collaboration diagram for llvm::RISCVDAGToDAGISel:

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Public Member Functions
	RISCVDAGToDAGISel (RISCVTargetMachine &TargetMachine, CodeGenOpt::Level OptLevel)

StringRef	getPassName () const override
	getPassName - Return a nice clean name for a pass. More...

bool	runOnMachineFunction (MachineFunction &MF) override
	runOnMachineFunction - This method must be overloaded to perform the desired machine code transformation or analysis. More...

void	PreprocessISelDAG () override
	PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts. More...

void	PostprocessISelDAG () override
	PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection. More...

void	Select (SDNode *Node) override
	Main hook for targets to transform nodes into machine nodes. More...

bool	SelectInlineAsmMemoryOperand (const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
	SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint. More...

bool	SelectAddrFrameIndex (SDValue Addr, SDValue &Base, SDValue &Offset)

bool	SelectFrameAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset)

bool	SelectAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset)

bool	tryShrinkShlLogicImm (SDNode *Node)

bool	selectShiftMask (SDValue N, unsigned ShiftWidth, SDValue &ShAmt)

bool	selectShiftMaskXLen (SDValue N, SDValue &ShAmt)

bool	selectShiftMask32 (SDValue N, SDValue &ShAmt)

bool	selectSExti32 (SDValue N, SDValue &Val)

bool	selectZExti32 (SDValue N, SDValue &Val)

bool	selectSHXADDOp (SDValue N, unsigned ShAmt, SDValue &Val)
	Look for various patterns that can be done with a SHL that can be folded into a SHXADD. More...

bool	selectSH1ADDOp (SDValue N, SDValue &Val)

bool	selectSH2ADDOp (SDValue N, SDValue &Val)

bool	selectSH3ADDOp (SDValue N, SDValue &Val)

bool	hasAllNBitUsers (SDNode *Node, unsigned Bits) const

bool	hasAllHUsers (SDNode *Node) const

bool	hasAllWUsers (SDNode *Node) const

bool	selectVLOp (SDValue N, SDValue &VL)

bool	selectVSplat (SDValue N, SDValue &SplatVal)

bool	selectVSplatSimm5 (SDValue N, SDValue &SplatVal)

bool	selectVSplatUimm5 (SDValue N, SDValue &SplatVal)

bool	selectVSplatSimm5Plus1 (SDValue N, SDValue &SplatVal)

bool	selectVSplatSimm5Plus1NonZero (SDValue N, SDValue &SplatVal)

bool	selectRVVSimm5 (SDValue N, unsigned Width, SDValue &Imm)

template<unsigned Width>
bool	selectRVVSimm5 (SDValue N, SDValue &Imm)

void	addVectorLoadStoreOperands (SDNode Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT IndexVT=nullptr)

void	selectVLSEG (SDNode *Node, bool IsMasked, bool IsStrided)

void	selectVLSEGFF (SDNode *Node, bool IsMasked)

void	selectVLXSEG (SDNode *Node, bool IsMasked, bool IsOrdered)

void	selectVSSEG (SDNode *Node, bool IsMasked, bool IsStrided)

void	selectVSXSEG (SDNode *Node, bool IsMasked, bool IsOrdered)

void	selectVSETVLI (SDNode *Node)

Public Member Functions inherited from llvm::SelectionDAGISel
	SelectionDAGISel (TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default)

	~SelectionDAGISel () override

const TargetLowering *	getTargetLowering () const

void	getAnalysisUsage (AnalysisUsage &AU) const override
	getAnalysisUsage - Subclasses that override getAnalysisUsage must call this. More...

virtual void	emitFunctionEntryCode ()

virtual bool	IsProfitableToFold (SDValue N, SDNode U, SDNode Root) const
	IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during instruction selection that starts at Root. More...

bool	CheckAndMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
	CheckAndMask - The isel is trying to match something like (and X, 255). More...

bool	CheckOrMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
	CheckOrMask - The isel is trying to match something like (or X, 255). More...

virtual bool	CheckPatternPredicate (unsigned PredNo) const
	CheckPatternPredicate - This function is generated by tblgen in the target. More...

virtual bool	CheckNodePredicate (SDNode *N, unsigned PredNo) const
	CheckNodePredicate - This function is generated by tblgen in the target. More...

virtual bool	CheckNodePredicateWithOperands (SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const
	CheckNodePredicateWithOperands - This function is generated by tblgen in the target. More...

virtual bool	CheckComplexPattern (SDNode Root, SDNode Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)

virtual SDValue	RunSDNodeXForm (SDValue V, unsigned XFormNo)

void	SelectCodeCommon (SDNode NodeToMatch, const unsigned char MatcherTable, unsigned TableSize)

virtual bool	ComplexPatternFuncMutatesDAG () const
	Return true if complex patterns for this target can mutate the DAG. More...

bool	mayRaiseFPException (SDNode *Node) const
	Return whether the node may raise an FP exception. More...

bool	isOrEquivalentToAdd (const SDNode *N) const

Public Member Functions inherited from llvm::MachineFunctionPass
bool	doInitialization (Module &) override
	doInitialization - Virtual method overridden by subclasses to do any necessary initialization before any pass is run. More...

Public Member Functions inherited from llvm::FunctionPass
	FunctionPass (char &pid)

Pass *	createPrinterPass (raw_ostream &OS, const std::string &Banner) const override
	createPrinterPass - Get a function printer pass. More...

void	assignPassManager (PMStack &PMS, PassManagerType T) override
	Find appropriate Function Pass Manager or Call Graph Pass Manager in the PM Stack and add self into that manager. More...

PassManagerType	getPotentialPassManagerType () const override
	Return what kind of Pass Manager can manage this pass. More...

Public Member Functions inherited from llvm::Pass
	Pass (PassKind K, char &pid)

	Pass (const Pass &)=delete

Pass &	operator= (const Pass &)=delete

virtual	~Pass ()

PassKind	getPassKind () const

AnalysisID	getPassID () const
	getPassID - Return the PassID number that corresponds to this pass. More...

virtual bool	doFinalization (Module &)
	doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run. More...

virtual void	print (raw_ostream &OS, const Module *M) const
	print - Print out the internal state of the pass. More...

void	dump () const

virtual void	preparePassManager (PMStack &)
	Check if available pass managers are suitable for this pass or not. More...

void	setResolver (AnalysisResolver *AR)

AnalysisResolver *	getResolver () const

virtual void	releaseMemory ()
	releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed. More...

virtual void *	getAdjustedAnalysisPointer (AnalysisID ID)
	getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance. More...

virtual ImmutablePass *	getAsImmutablePass ()

virtual PMDataManager *	getAsPMDataManager ()

virtual void	verifyAnalysis () const
	verifyAnalysis() - This member can be implemented by a analysis pass to check state of analysis information. More...

virtual void	dumpPassStructure (unsigned Offset=0)

template<typename AnalysisType >
AnalysisType *	getAnalysisIfAvailable () const
	getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information that might be around, for example to update it. More...

bool	mustPreserveAnalysisID (char &AID) const
	mustPreserveAnalysisID - This method serves the same function as getAnalysisIfAvailable, but works if you just have an AnalysisID. More...

template<typename AnalysisType >
AnalysisType &	getAnalysis () const
	getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function. More...

template<typename AnalysisType >
AnalysisType &	getAnalysis (Function &F, bool *Changed=nullptr)
	getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function. More...

template<typename AnalysisType >
AnalysisType &	getAnalysisID (AnalysisID PI) const

template<typename AnalysisType >
AnalysisType &	getAnalysisID (AnalysisID PI, Function &F, bool *Changed=nullptr)

Static Public Member Functions
static RISCVCC::CondCode	getRISCVCCForIntCC (ISD::CondCode CC)

Static Public Member Functions inherited from llvm::SelectionDAGISel
static bool	IsLegalToFold (SDValue N, SDNode U, SDNode Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false)
	IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction selection that starts at Root. More...

static void	InvalidateNodeId (SDNode *N)

static int	getUninvalidatedNodeId (SDNode *N)

static void	EnforceNodeIdInvariant (SDNode *N)

static int	getNumFixedFromVariadicInfo (unsigned Flags)
	getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values that should be skipped when copying from the root. More...

Static Public Member Functions inherited from llvm::Pass
static const PassInfo *	lookupPassInfo (const void *TI)

static const PassInfo *	lookupPassInfo (StringRef Arg)

static Pass *	createPass (AnalysisID ID)

Additional Inherited Members
Public Types inherited from llvm::SelectionDAGISel
enum	BuiltinOpcodes { OPC_Scope, OPC_RecordNode, OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3, OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7, OPC_RecordMemRef, OPC_CaptureGlueInput, OPC_MoveChild, OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2, OPC_MoveChild3, OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6, OPC_MoveChild7, OPC_MoveParent, OPC_CheckSame, OPC_CheckChild0Same, OPC_CheckChild1Same, OPC_CheckChild2Same, OPC_CheckChild3Same, OPC_CheckPatternPredicate, OPC_CheckPredicate, OPC_CheckPredicateWithOperands, OPC_CheckOpcode, OPC_SwitchOpcode, OPC_CheckType, OPC_CheckTypeRes, OPC_SwitchType, OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type, OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type, OPC_CheckChild6Type, OPC_CheckChild7Type, OPC_CheckInteger, OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer, OPC_CheckChild3Integer, OPC_CheckChild4Integer, OPC_CheckCondCode, OPC_CheckChild2CondCode, OPC_CheckValueType, OPC_CheckComplexPat, OPC_CheckAndImm, OPC_CheckOrImm, OPC_CheckImmAllOnesV, OPC_CheckImmAllZerosV, OPC_CheckFoldableChainNode, OPC_EmitInteger, OPC_EmitStringInteger, OPC_EmitRegister, OPC_EmitRegister2, OPC_EmitConvertToTarget, OPC_EmitMergeInputChains, OPC_EmitMergeInputChains1_0, OPC_EmitMergeInputChains1_1, OPC_EmitMergeInputChains1_2, OPC_EmitCopyToReg, OPC_EmitCopyToReg2, OPC_EmitNodeXForm, OPC_EmitNode, OPC_EmitNode0, OPC_EmitNode1, OPC_EmitNode2, OPC_MorphNodeTo, OPC_MorphNodeTo0, OPC_MorphNodeTo1, OPC_MorphNodeTo2, OPC_CompleteMatch, OPC_Coverage }

enum	{ OPFL_None = 0, OPFL_Chain = 1, OPFL_GlueInput = 2, OPFL_GlueOutput = 4, OPFL_MemRefs = 8, OPFL_Variadic0 = 1<<4, OPFL_Variadic1 = 2<<4, OPFL_Variadic2 = 3<<4, OPFL_Variadic3 = 4<<4, OPFL_Variadic4 = 5<<4, OPFL_Variadic5 = 6<<4, OPFL_Variadic6 = 7<<4, OPFL_VariadicInfo = OPFL_Variadic6 }

Public Attributes inherited from llvm::SelectionDAGISel
TargetMachine &	TM

const TargetLibraryInfo *	LibInfo

std::unique_ptr< FunctionLoweringInfo >	FuncInfo

SwiftErrorValueTracking *	SwiftError

MachineFunction *	MF

MachineRegisterInfo *	RegInfo

SelectionDAG *	CurDAG

std::unique_ptr< SelectionDAGBuilder >	SDB

AAResults *	AA = nullptr

GCFunctionInfo *	GFI = nullptr

CodeGenOpt::Level	OptLevel

const TargetInstrInfo *	TII

const TargetLowering *	TLI

bool	FastISelFailed

SmallPtrSet< const Instruction *, 4 >	ElidedArgCopyInstrs

bool	UseInstrRefDebugInfo = false

std::unique_ptr< OptimizationRemarkEmitter >	ORE
	Current optimization remark emitter. More...

Static Public Attributes inherited from llvm::SelectionDAGISel
static char	ID = 0

Protected Member Functions inherited from llvm::SelectionDAGISel
void	ReplaceUses (SDValue F, SDValue T)
	ReplaceUses - replace all uses of the old node F with the use of the new node T. More...

void	ReplaceUses (const SDValue F, const SDValue T, unsigned Num)
	ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T. More...

void	ReplaceUses (SDNode F, SDNode T)
	ReplaceUses - replace all uses of the old node F with the use of the new node T. More...

void	ReplaceNode (SDNode F, SDNode T)
	Replace all uses of `F` with `T`, then remove `F` from the DAG. More...

void	SelectInlineAsmMemoryOperands (std::vector< SDValue > &Ops, const SDLoc &DL)
	SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen. More...

virtual StringRef	getPatternForIndex (unsigned index)
	getPatternForIndex - Patterns selected by tablegen during ISEL More...

virtual StringRef	getIncludePathForIndex (unsigned index)
	getIncludePathForIndex - get the td source location of pattern instantiation More...

bool	shouldOptForSize (const MachineFunction *MF) const

Protected Member Functions inherited from llvm::MachineFunctionPass
	MachineFunctionPass (char &ID)

virtual MachineFunctionProperties	getRequiredProperties () const

virtual MachineFunctionProperties	getSetProperties () const

virtual MachineFunctionProperties	getClearedProperties () const

Protected Member Functions inherited from llvm::FunctionPass
bool	skipFunction (const Function &F) const
	Optional passes call this function to check whether the pass should be skipped. More...

Protected Attributes inherited from llvm::SelectionDAGISel
unsigned	DAGSize = 0
	DAGSize - Size of DAG being instruction selected. More...

Detailed Description

Definition at line 23 of file RISCVISelDAGToDAG.h.

Constructor & Destructor Documentation

◆ RISCVDAGToDAGISel()

llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel	(	RISCVTargetMachine &	TargetMachine,
		CodeGenOpt::Level	OptLevel
	)

inlineexplicit

Definition at line 27 of file RISCVISelDAGToDAG.h.

Member Function Documentation

◆ addVectorLoadStoreOperands()

void RISCVDAGToDAGISel::addVectorLoadStoreOperands	(	SDNode *	Node,
		unsigned	SEWImm,
		const SDLoc &	DL,
		unsigned	CurOp,
		bool	IsMasked,
		bool	IsStridedOrIndexed,
		SmallVectorImpl< SDValue > &	Operands,
		bool	IsLoad = `false`,
		MVT *	IndexVT = `nullptr`
	)

Definition at line 249 of file RISCVISelDAGToDAG.cpp.

◆ getPassName()

StringRef llvm::RISCVDAGToDAGISel::getPassName ( ) const

inlineoverridevirtual

getPassName - Return a nice clean name for a pass.

This usually implemented in terms of the name that is registered by one of the Registration templates, but can be overloaded directly.

Reimplemented from llvm::Pass.

Definition at line 31 of file RISCVISelDAGToDAG.h.

◆ getRISCVCCForIntCC()

static RISCVCC::CondCode llvm::RISCVDAGToDAGISel::getRISCVCCForIntCC ( ISD::CondCode CC )

inlinestatic

Definition at line 110 of file RISCVISelDAGToDAG.h.

References llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, llvm::RISCVCC::COND_NE, llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, and llvm::ISD::SETULT.

◆ hasAllHUsers()

bool llvm::RISCVDAGToDAGISel::hasAllHUsers ( SDNode * Node ) const

inline

Definition at line 77 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

◆ hasAllNBitUsers()

bool RISCVDAGToDAGISel::hasAllNBitUsers	(	SDNode *	Node,
		unsigned	Bits
	)		const

Definition at line 2218 of file RISCVISelDAGToDAG.cpp.

Referenced by hasAllHUsers(), and hasAllWUsers().

◆ hasAllWUsers()

bool llvm::RISCVDAGToDAGISel::hasAllWUsers ( SDNode * Node ) const

inline

Definition at line 78 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

◆ PostprocessISelDAG()

void RISCVDAGToDAGISel::PostprocessISelDAG ( )

overridevirtual

PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 135 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAG::allnodes_begin(), llvm::SelectionDAG::allnodes_end(), llvm::SelectionDAGISel::CurDAG, llvm::NVPTXISD::Dummy, llvm::SelectionDAG::getRoot(), N, llvm::SelectionDAG::RemoveDeadNodes(), and llvm::SelectionDAG::setRoot().

◆ PreprocessISelDAG()

void RISCVDAGToDAGISel::PreprocessISelDAG ( )

overridevirtual

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 43 of file RISCVISelDAGToDAG.cpp.

◆ runOnMachineFunction()

bool llvm::RISCVDAGToDAGISel::runOnMachineFunction ( MachineFunction & MF )

inlineoverridevirtual

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformation or analysis.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 35 of file RISCVISelDAGToDAG.h.

References llvm::MachineFunction::getSubtarget(), llvm::SelectionDAGISel::MF, and llvm::SelectionDAGISel::runOnMachineFunction().

◆ Select()

void RISCVDAGToDAGISel::Select ( SDNode * N )

overridevirtual

Main hook for targets to transform nodes into machine nodes.

Implements llvm::SelectionDAGISel.

Definition at line 660 of file RISCVISelDAGToDAG.cpp.

◆ SelectAddrFrameIndex()

bool RISCVDAGToDAGISel::SelectAddrFrameIndex	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset
	)

Definition at line 1838 of file RISCVISelDAGToDAG.cpp.

References Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), and llvm::RISCVSubtarget::getXLenVT().

Referenced by SelectAddrRegImm(), and SelectFrameAddrRegImm().

◆ SelectAddrRegImm()

bool RISCVDAGToDAGISel::SelectAddrRegImm	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset
	)

◆ SelectFrameAddrRegImm()

bool RISCVDAGToDAGISel::SelectFrameAddrRegImm	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset
	)

Definition at line 1850 of file RISCVISelDAGToDAG.cpp.

References Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::isBaseWithConstantOffset(), and SelectAddrFrameIndex().

◆ SelectInlineAsmMemoryOperand()

bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand	(	const SDValue &	Op,
		unsigned	ConstraintID,
		std::vector< SDValue > &	OutOps
	)

overridevirtual

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.

If this does not match or is not implemented, return true. The resultant operands (which will appear in the machine instruction) should be added to the OutOps vector.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 1820 of file RISCVISelDAGToDAG.cpp.

References llvm::InlineAsm::Constraint_A, and llvm::InlineAsm::Constraint_m.

◆ selectRVVSimm5() [1/2]

template<unsigned Width>

bool llvm::RISCVDAGToDAGISel::selectRVVSimm5	(	SDValue	N,
		SDValue &	Imm
	)

inline

Definition at line 89 of file RISCVISelDAGToDAG.h.

References llvm::RISCVMatInt::Imm, N, and selectRVVSimm5().

◆ selectRVVSimm5() [2/2]

bool RISCVDAGToDAGISel::selectRVVSimm5	(	SDValue	N,
		unsigned	Width,
		SDValue &	Imm
	)

Definition at line 2419 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVMatInt::Imm, N, and llvm::SignExtend64().

Referenced by selectRVVSimm5().

◆ selectSExti32()

bool RISCVDAGToDAGISel::selectSExti32	(	SDValue	N,
		SDValue &	Val
	)

Definition at line 2079 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAGISel::CurDAG, llvm::MVT::getSizeInBits(), llvm::MVT::i32, N, and llvm::ISD::SIGN_EXTEND_INREG.

◆ selectSH1ADDOp()

bool llvm::RISCVDAGToDAGISel::selectSH1ADDOp	(	SDValue	N,
		SDValue &	Val
	)

inline

Definition at line 66 of file RISCVISelDAGToDAG.h.

References N, and selectSHXADDOp().

◆ selectSH2ADDOp()

bool llvm::RISCVDAGToDAGISel::selectSH2ADDOp	(	SDValue	N,
		SDValue &	Val
	)

inline

Definition at line 69 of file RISCVISelDAGToDAG.h.

References N, and selectSHXADDOp().

◆ selectSH3ADDOp()

bool llvm::RISCVDAGToDAGISel::selectSH3ADDOp	(	SDValue	N,
		SDValue &	Val
	)

inline

Definition at line 72 of file RISCVISelDAGToDAG.h.

References N, and selectSHXADDOp().

◆ selectShiftMask()

bool RISCVDAGToDAGISel::selectShiftMask	(	SDValue	N,
		unsigned	ShiftWidth,
		SDValue &	ShAmt
	)

Definition at line 2033 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::AND, assert(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAGISel::CurDAG, DL, llvm::APInt::getBitWidth(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getRegister(), llvm::MVT::i64, llvm::RISCVMatInt::Imm, llvm::isPowerOf2_32(), llvm::APInt::isSubsetOf(), N, llvm::ISD::SUB, and llvm::KnownBits::Zero.

Referenced by selectShiftMask32(), and selectShiftMaskXLen().

◆ selectShiftMask32()

bool llvm::RISCVDAGToDAGISel::selectShiftMask32	(	SDValue	N,
		SDValue &	ShAmt
	)

inline

Definition at line 58 of file RISCVISelDAGToDAG.h.

References N, and selectShiftMask().

◆ selectShiftMaskXLen()

bool llvm::RISCVDAGToDAGISel::selectShiftMaskXLen	(	SDValue	N,
		SDValue &	ShAmt
	)

inline

Definition at line 55 of file RISCVISelDAGToDAG.h.

References llvm::RISCVSubtarget::getXLen(), N, and selectShiftMask().

◆ selectSHXADDOp()

bool RISCVDAGToDAGISel::selectSHXADDOp	(	SDValue	N,
		unsigned	ShAmt,
		SDValue &	Val
	)

Look for various patterns that can be done with a SHL that can be folded into a SHXADD.

ShAmt contains 1, 2, or 3 and is set based on which SHXADD we are trying to match.

Definition at line 2115 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::AND, C1, llvm::countLeadingZeros(), llvm::countTrailingZeros(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLen(), llvm::SDValue::hasOneUse(), llvm::isShiftedMask_64(), llvm::BitmaskEnumDetail::Mask(), N, llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by selectSH1ADDOp(), selectSH2ADDOp(), and selectSH3ADDOp().

◆ selectVLOp()

bool RISCVDAGToDAGISel::selectVLOp	(	SDValue	N,
		SDValue &	VL
	)

Definition at line 2318 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, getReg(), llvm::SelectionDAG::getTargetConstant(), N, and llvm::RISCV::VLMaxSentinel.

◆ selectVLSEG()

void RISCVDAGToDAGISel::selectVLSEG	(	SDNode *	Node,
		bool	IsMasked,
		bool	IsStrided
	)

Definition at line 296 of file RISCVISelDAGToDAG.cpp.

◆ selectVLSEGFF()

void RISCVDAGToDAGISel::selectVLSEGFF	(	SDNode *	Node,
		bool	IsMasked
	)

Definition at line 339 of file RISCVISelDAGToDAG.cpp.

◆ selectVLXSEG()

void RISCVDAGToDAGISel::selectVLXSEG	(	SDNode *	Node,
		bool	IsMasked,
		bool	IsOrdered
	)

Definition at line 384 of file RISCVISelDAGToDAG.cpp.

◆ selectVSETVLI()

void RISCVDAGToDAGISel::selectVSETVLI ( SDNode * Node )

Definition at line 512 of file RISCVISelDAGToDAG.cpp.

◆ selectVSplat()

bool RISCVDAGToDAGISel::selectVSplat	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 2342 of file RISCVISelDAGToDAG.cpp.

References N, and llvm::RISCVISD::VMV_V_X_VL.

◆ selectVSplatSimm5()

bool RISCVDAGToDAGISel::selectVSplatSimm5	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 2383 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, llvm::RISCVMatInt::Imm, N, and selectVSplatSimmHelper().

◆ selectVSplatSimm5Plus1()

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 2388 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, llvm::RISCVMatInt::Imm, N, and selectVSplatSimmHelper().

◆ selectVSplatSimm5Plus1NonZero()

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 2394 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, llvm::RISCVMatInt::Imm, N, and selectVSplatSimmHelper().

◆ selectVSplatUimm5()

bool RISCVDAGToDAGISel::selectVSplatUimm5	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 2402 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), N, and llvm::RISCVISD::VMV_V_X_VL.

◆ selectVSSEG()

void RISCVDAGToDAGISel::selectVSSEG	(	SDNode *	Node,
		bool	IsMasked,
		bool	IsStrided
	)

Definition at line 438 of file RISCVISelDAGToDAG.cpp.

◆ selectVSXSEG()

void RISCVDAGToDAGISel::selectVSXSEG	(	SDNode *	Node,
		bool	IsMasked,
		bool	IsOrdered
	)

Definition at line 470 of file RISCVISelDAGToDAG.cpp.

◆ selectZExti32()

bool RISCVDAGToDAGISel::selectZExti32	(	SDValue	N,
		SDValue &	Val
	)

Definition at line 2094 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::AND, llvm::SelectionDAGISel::CurDAG, llvm::APInt::getHighBitsSet(), llvm::MVT::getSizeInBits(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), and N.

◆ tryShrinkShlLogicImm()

bool RISCVDAGToDAGISel::tryShrinkShlLogicImm ( SDNode * Node )

Definition at line 582 of file RISCVISelDAGToDAG.cpp.

The documentation for this class was generated from the following files:

lib/Target/RISCV/RISCVISelDAGToDAG.h
lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Public Member Functions

Static Public Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ RISCVDAGToDAGISel()

Member Function Documentation

◆ addVectorLoadStoreOperands()

◆ getPassName()

◆ getRISCVCCForIntCC()

◆ hasAllHUsers()

◆ hasAllNBitUsers()

◆ hasAllWUsers()

◆ PostprocessISelDAG()

◆ PreprocessISelDAG()

◆ runOnMachineFunction()

◆ Select()

◆ SelectAddrFrameIndex()

◆ SelectAddrRegImm()

◆ SelectFrameAddrRegImm()

◆ SelectInlineAsmMemoryOperand()

◆ selectRVVSimm5() [1/2]

◆ selectRVVSimm5() [2/2]

◆ selectSExti32()

◆ selectSH1ADDOp()

◆ selectSH2ADDOp()

◆ selectSH3ADDOp()

◆ selectShiftMask()

◆ selectShiftMask32()

◆ selectShiftMaskXLen()

◆ selectSHXADDOp()

◆ selectVLOp()

◆ selectVLSEG()

◆ selectVLSEGFF()

◆ selectVLXSEG()

◆ selectVSETVLI()

◆ selectVSplat()

◆ selectVSplatSimm5()

◆ selectVSplatSimm5Plus1()

◆ selectVSplatSimm5Plus1NonZero()

◆ selectVSplatUimm5()

◆ selectVSSEG()

◆ selectVSXSEG()

◆ selectZExti32()

◆ tryShrinkShlLogicImm()