LLVM
16.0.0git
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#include "Target/RISCV/RISCVISelDAGToDAG.h"
Public Member Functions | |
RISCVDAGToDAGISel (RISCVTargetMachine &TargetMachine, CodeGenOpt::Level OptLevel) | |
StringRef | getPassName () const override |
getPassName - Return a nice clean name for a pass. More... | |
bool | runOnMachineFunction (MachineFunction &MF) override |
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformation or analysis. More... | |
void | PreprocessISelDAG () override |
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts. More... | |
void | PostprocessISelDAG () override |
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection. More... | |
void | Select (SDNode *Node) override |
Main hook for targets to transform nodes into machine nodes. More... | |
bool | SelectInlineAsmMemoryOperand (const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override |
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint. More... | |
bool | SelectAddrFrameIndex (SDValue Addr, SDValue &Base, SDValue &Offset) |
bool | SelectFrameAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset) |
bool | SelectAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset) |
bool | tryShrinkShlLogicImm (SDNode *Node) |
bool | selectShiftMask (SDValue N, unsigned ShiftWidth, SDValue &ShAmt) |
bool | selectShiftMaskXLen (SDValue N, SDValue &ShAmt) |
bool | selectShiftMask32 (SDValue N, SDValue &ShAmt) |
bool | selectSExti32 (SDValue N, SDValue &Val) |
bool | selectZExti32 (SDValue N, SDValue &Val) |
bool | selectSHXADDOp (SDValue N, unsigned ShAmt, SDValue &Val) |
Look for various patterns that can be done with a SHL that can be folded into a SHXADD. More... | |
bool | selectSH1ADDOp (SDValue N, SDValue &Val) |
bool | selectSH2ADDOp (SDValue N, SDValue &Val) |
bool | selectSH3ADDOp (SDValue N, SDValue &Val) |
bool | hasAllNBitUsers (SDNode *Node, unsigned Bits) const |
bool | hasAllHUsers (SDNode *Node) const |
bool | hasAllWUsers (SDNode *Node) const |
bool | selectVLOp (SDValue N, SDValue &VL) |
bool | selectVSplat (SDValue N, SDValue &SplatVal) |
bool | selectVSplatSimm5 (SDValue N, SDValue &SplatVal) |
bool | selectVSplatUimm5 (SDValue N, SDValue &SplatVal) |
bool | selectVSplatSimm5Plus1 (SDValue N, SDValue &SplatVal) |
bool | selectVSplatSimm5Plus1NonZero (SDValue N, SDValue &SplatVal) |
bool | selectRVVSimm5 (SDValue N, unsigned Width, SDValue &Imm) |
template<unsigned Width> | |
bool | selectRVVSimm5 (SDValue N, SDValue &Imm) |
void | addVectorLoadStoreOperands (SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr) |
void | selectVLSEG (SDNode *Node, bool IsMasked, bool IsStrided) |
void | selectVLSEGFF (SDNode *Node, bool IsMasked) |
void | selectVLXSEG (SDNode *Node, bool IsMasked, bool IsOrdered) |
void | selectVSSEG (SDNode *Node, bool IsMasked, bool IsStrided) |
void | selectVSXSEG (SDNode *Node, bool IsMasked, bool IsOrdered) |
void | selectVSETVLI (SDNode *Node) |
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SelectionDAGISel (TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default) | |
~SelectionDAGISel () override | |
const TargetLowering * | getTargetLowering () const |
void | getAnalysisUsage (AnalysisUsage &AU) const override |
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this. More... | |
virtual void | emitFunctionEntryCode () |
virtual bool | IsProfitableToFold (SDValue N, SDNode *U, SDNode *Root) const |
IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during instruction selection that starts at Root. More... | |
bool | CheckAndMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const |
CheckAndMask - The isel is trying to match something like (and X, 255). More... | |
bool | CheckOrMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const |
CheckOrMask - The isel is trying to match something like (or X, 255). More... | |
virtual bool | CheckPatternPredicate (unsigned PredNo) const |
CheckPatternPredicate - This function is generated by tblgen in the target. More... | |
virtual bool | CheckNodePredicate (SDNode *N, unsigned PredNo) const |
CheckNodePredicate - This function is generated by tblgen in the target. More... | |
virtual bool | CheckNodePredicateWithOperands (SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const |
CheckNodePredicateWithOperands - This function is generated by tblgen in the target. More... | |
virtual bool | CheckComplexPattern (SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result) |
virtual SDValue | RunSDNodeXForm (SDValue V, unsigned XFormNo) |
void | SelectCodeCommon (SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize) |
virtual bool | ComplexPatternFuncMutatesDAG () const |
Return true if complex patterns for this target can mutate the DAG. More... | |
bool | mayRaiseFPException (SDNode *Node) const |
Return whether the node may raise an FP exception. More... | |
bool | isOrEquivalentToAdd (const SDNode *N) const |
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bool | doInitialization (Module &) override |
doInitialization - Virtual method overridden by subclasses to do any necessary initialization before any pass is run. More... | |
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FunctionPass (char &pid) | |
Pass * | createPrinterPass (raw_ostream &OS, const std::string &Banner) const override |
createPrinterPass - Get a function printer pass. More... | |
void | assignPassManager (PMStack &PMS, PassManagerType T) override |
Find appropriate Function Pass Manager or Call Graph Pass Manager in the PM Stack and add self into that manager. More... | |
PassManagerType | getPotentialPassManagerType () const override |
Return what kind of Pass Manager can manage this pass. More... | |
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Pass (PassKind K, char &pid) | |
Pass (const Pass &)=delete | |
Pass & | operator= (const Pass &)=delete |
virtual | ~Pass () |
PassKind | getPassKind () const |
AnalysisID | getPassID () const |
getPassID - Return the PassID number that corresponds to this pass. More... | |
virtual bool | doFinalization (Module &) |
doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run. More... | |
virtual void | print (raw_ostream &OS, const Module *M) const |
print - Print out the internal state of the pass. More... | |
void | dump () const |
virtual void | preparePassManager (PMStack &) |
Check if available pass managers are suitable for this pass or not. More... | |
void | setResolver (AnalysisResolver *AR) |
AnalysisResolver * | getResolver () const |
virtual void | releaseMemory () |
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed. More... | |
virtual void * | getAdjustedAnalysisPointer (AnalysisID ID) |
getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance. More... | |
virtual ImmutablePass * | getAsImmutablePass () |
virtual PMDataManager * | getAsPMDataManager () |
virtual void | verifyAnalysis () const |
verifyAnalysis() - This member can be implemented by a analysis pass to check state of analysis information. More... | |
virtual void | dumpPassStructure (unsigned Offset=0) |
template<typename AnalysisType > | |
AnalysisType * | getAnalysisIfAvailable () const |
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information that might be around, for example to update it. More... | |
bool | mustPreserveAnalysisID (char &AID) const |
mustPreserveAnalysisID - This method serves the same function as getAnalysisIfAvailable, but works if you just have an AnalysisID. More... | |
template<typename AnalysisType > | |
AnalysisType & | getAnalysis () const |
getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function. More... | |
template<typename AnalysisType > | |
AnalysisType & | getAnalysis (Function &F, bool *Changed=nullptr) |
getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function. More... | |
template<typename AnalysisType > | |
AnalysisType & | getAnalysisID (AnalysisID PI) const |
template<typename AnalysisType > | |
AnalysisType & | getAnalysisID (AnalysisID PI, Function &F, bool *Changed=nullptr) |
Static Public Member Functions | |
static RISCVCC::CondCode | getRISCVCCForIntCC (ISD::CondCode CC) |
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static bool | IsLegalToFold (SDValue N, SDNode *U, SDNode *Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false) |
IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction selection that starts at Root. More... | |
static void | InvalidateNodeId (SDNode *N) |
static int | getUninvalidatedNodeId (SDNode *N) |
static void | EnforceNodeIdInvariant (SDNode *N) |
static int | getNumFixedFromVariadicInfo (unsigned Flags) |
getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values that should be skipped when copying from the root. More... | |
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static const PassInfo * | lookupPassInfo (const void *TI) |
static const PassInfo * | lookupPassInfo (StringRef Arg) |
static Pass * | createPass (AnalysisID ID) |
Definition at line 23 of file RISCVISelDAGToDAG.h.
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inlineexplicit |
Definition at line 27 of file RISCVISelDAGToDAG.h.
void RISCVDAGToDAGISel::addVectorLoadStoreOperands | ( | SDNode * | Node, |
unsigned | SEWImm, | ||
const SDLoc & | DL, | ||
unsigned | CurOp, | ||
bool | IsMasked, | ||
bool | IsStridedOrIndexed, | ||
SmallVectorImpl< SDValue > & | Operands, | ||
bool | IsLoad = false , |
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MVT * | IndexVT = nullptr |
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) |
Definition at line 249 of file RISCVISelDAGToDAG.cpp.
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inlineoverridevirtual |
getPassName - Return a nice clean name for a pass.
This usually implemented in terms of the name that is registered by one of the Registration templates, but can be overloaded directly.
Reimplemented from llvm::Pass.
Definition at line 31 of file RISCVISelDAGToDAG.h.
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inlinestatic |
Definition at line 110 of file RISCVISelDAGToDAG.h.
References llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, llvm::RISCVCC::COND_NE, llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, and llvm::ISD::SETULT.
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inline |
Definition at line 77 of file RISCVISelDAGToDAG.h.
References hasAllNBitUsers().
bool RISCVDAGToDAGISel::hasAllNBitUsers | ( | SDNode * | Node, |
unsigned | Bits | ||
) | const |
Definition at line 2218 of file RISCVISelDAGToDAG.cpp.
Referenced by hasAllHUsers(), and hasAllWUsers().
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inline |
Definition at line 78 of file RISCVISelDAGToDAG.h.
References hasAllNBitUsers().
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overridevirtual |
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
Reimplemented from llvm::SelectionDAGISel.
Definition at line 135 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAG::allnodes_begin(), llvm::SelectionDAG::allnodes_end(), llvm::SelectionDAGISel::CurDAG, llvm::NVPTXISD::Dummy, llvm::SelectionDAG::getRoot(), N, llvm::SelectionDAG::RemoveDeadNodes(), and llvm::SelectionDAG::setRoot().
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overridevirtual |
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.
Reimplemented from llvm::SelectionDAGISel.
Definition at line 43 of file RISCVISelDAGToDAG.cpp.
References Align, llvm::SelectionDAG::allnodes_begin(), llvm::SelectionDAG::allnodes_end(), assert(), llvm::SelectionDAGISel::CurDAG, llvm::dbgs(), DL, llvm::TypeSize::Fixed(), llvm::SelectionDAGISel::FuncInfo, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MachinePointerInfo::getWithOffset(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_W_CHAIN, llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), LLVM_DEBUG, llvm::SelectionDAGISel::MF, llvm::MachineMemOperand::MOLoad, N, llvm::MVT::Other, llvm::SelectionDAG::RemoveDeadNodes(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SPLAT_VECTOR, llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, llvm::SelectionDAGISel::TLI, llvm::ISD::TokenFactor, llvm::RISCVISD::VFMV_V_F_VL, and llvm::RISCVISD::VMV_V_X_VL.
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inlineoverridevirtual |
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformation or analysis.
Reimplemented from llvm::SelectionDAGISel.
Definition at line 35 of file RISCVISelDAGToDAG.h.
References llvm::MachineFunction::getSubtarget(), llvm::SelectionDAGISel::MF, and llvm::SelectionDAGISel::runOnMachineFunction().
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overridevirtual |
Main hook for targets to transform nodes into machine nodes.
Implements llvm::SelectionDAGISel.
Definition at line 660 of file RISCVISelDAGToDAG.cpp.
Definition at line 1838 of file RISCVISelDAGToDAG.cpp.
References Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), and llvm::RISCVSubtarget::getXLenVT().
Referenced by SelectAddrRegImm(), and SelectFrameAddrRegImm().
Definition at line 1943 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::ADD, llvm::RISCVISD::ADD_LO, Addr, assert(), llvm::sampleprof::Base, llvm::commonAlignment(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValueType(), llvm::SelectionDAG::isBaseWithConstantOffset(), isWorthFoldingAdd(), SelectAddrFrameIndex(), and selectConstantAddr().
Definition at line 1850 of file RISCVISelDAGToDAG.cpp.
References Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::isBaseWithConstantOffset(), and SelectAddrFrameIndex().
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overridevirtual |
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.
If this does not match or is not implemented, return true. The resultant operands (which will appear in the machine instruction) should be added to the OutOps vector.
Reimplemented from llvm::SelectionDAGISel.
Definition at line 1820 of file RISCVISelDAGToDAG.cpp.
References llvm::InlineAsm::Constraint_A, and llvm::InlineAsm::Constraint_m.
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inline |
Definition at line 89 of file RISCVISelDAGToDAG.h.
References llvm::RISCVMatInt::Imm, N, and selectRVVSimm5().
Definition at line 2419 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVMatInt::Imm, N, and llvm::SignExtend64().
Referenced by selectRVVSimm5().
Definition at line 2079 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAGISel::CurDAG, llvm::MVT::getSizeInBits(), llvm::MVT::i32, N, and llvm::ISD::SIGN_EXTEND_INREG.
Definition at line 66 of file RISCVISelDAGToDAG.h.
References N, and selectSHXADDOp().
Definition at line 69 of file RISCVISelDAGToDAG.h.
References N, and selectSHXADDOp().
Definition at line 72 of file RISCVISelDAGToDAG.h.
References N, and selectSHXADDOp().
Definition at line 2033 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::AND, assert(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAGISel::CurDAG, DL, llvm::APInt::getBitWidth(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getRegister(), llvm::MVT::i64, llvm::RISCVMatInt::Imm, llvm::isPowerOf2_32(), llvm::APInt::isSubsetOf(), N, llvm::ISD::SUB, and llvm::KnownBits::Zero.
Referenced by selectShiftMask32(), and selectShiftMaskXLen().
Definition at line 58 of file RISCVISelDAGToDAG.h.
References N, and selectShiftMask().
Definition at line 55 of file RISCVISelDAGToDAG.h.
References llvm::RISCVSubtarget::getXLen(), N, and selectShiftMask().
Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
ShAmt
contains 1, 2, or 3 and is set based on which SHXADD we are trying to match.
Definition at line 2115 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::AND, C1, llvm::countLeadingZeros(), llvm::countTrailingZeros(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLen(), llvm::SDValue::hasOneUse(), llvm::isShiftedMask_64(), llvm::BitmaskEnumDetail::Mask(), N, llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by selectSH1ADDOp(), selectSH2ADDOp(), and selectSH3ADDOp().
Definition at line 2318 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, getReg(), llvm::SelectionDAG::getTargetConstant(), N, and llvm::RISCV::VLMaxSentinel.
void RISCVDAGToDAGISel::selectVLSEG | ( | SDNode * | Node, |
bool | IsMasked, | ||
bool | IsStrided | ||
) |
Definition at line 296 of file RISCVISelDAGToDAG.cpp.
void RISCVDAGToDAGISel::selectVLSEGFF | ( | SDNode * | Node, |
bool | IsMasked | ||
) |
Definition at line 339 of file RISCVISelDAGToDAG.cpp.
void RISCVDAGToDAGISel::selectVLXSEG | ( | SDNode * | Node, |
bool | IsMasked, | ||
bool | IsOrdered | ||
) |
Definition at line 384 of file RISCVISelDAGToDAG.cpp.
void RISCVDAGToDAGISel::selectVSETVLI | ( | SDNode * | Node | ) |
Definition at line 512 of file RISCVISelDAGToDAG.cpp.
Definition at line 2342 of file RISCVISelDAGToDAG.cpp.
References N, and llvm::RISCVISD::VMV_V_X_VL.
Definition at line 2383 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, llvm::RISCVMatInt::Imm, N, and selectVSplatSimmHelper().
Definition at line 2388 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, llvm::RISCVMatInt::Imm, N, and selectVSplatSimmHelper().
Definition at line 2394 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, llvm::RISCVMatInt::Imm, N, and selectVSplatSimmHelper().
Definition at line 2402 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), N, and llvm::RISCVISD::VMV_V_X_VL.
void RISCVDAGToDAGISel::selectVSSEG | ( | SDNode * | Node, |
bool | IsMasked, | ||
bool | IsStrided | ||
) |
Definition at line 438 of file RISCVISelDAGToDAG.cpp.
void RISCVDAGToDAGISel::selectVSXSEG | ( | SDNode * | Node, |
bool | IsMasked, | ||
bool | IsOrdered | ||
) |
Definition at line 470 of file RISCVISelDAGToDAG.cpp.
Definition at line 2094 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::SelectionDAGISel::CurDAG, llvm::APInt::getHighBitsSet(), llvm::MVT::getSizeInBits(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), and N.
bool RISCVDAGToDAGISel::tryShrinkShlLogicImm | ( | SDNode * | Node | ) |
Definition at line 582 of file RISCVISelDAGToDAG.cpp.