llvm::RISCVDAGToDAGISel Class Reference

#include "Target/RISCV/RISCVISelDAGToDAG.h"

Inheritance diagram for llvm::RISCVDAGToDAGISel:

Public Member Functions
	RISCVDAGToDAGISel ()=delete
	RISCVDAGToDAGISel (RISCVTargetMachine &TargetMachine, CodeGenOpt::Level OptLevel)
bool	runOnMachineFunction (MachineFunction &MF) override
	runOnMachineFunction - This method must be overloaded to perform the desired machine code transformation or analysis.
void	PreprocessISelDAG () override
	PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.
void	PostprocessISelDAG () override
	PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
void	Select (SDNode *Node) override
	Main hook for targets to transform nodes into machine nodes.
bool	SelectInlineAsmMemoryOperand (const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override
	SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.
bool	SelectAddrFrameIndex (SDValue Addr, SDValue &Base, SDValue &Offset)
bool	SelectFrameAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset)
bool	SelectAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset, bool IsINX=false)
bool	SelectAddrRegImmINX (SDValue Addr, SDValue &Base, SDValue &Offset)
bool	SelectAddrRegRegScale (SDValue Addr, unsigned MaxShiftAmount, SDValue &Base, SDValue &Index, SDValue &Scale)
template<unsigned MaxShift>
bool	SelectAddrRegRegScale (SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
template<unsigned MaxShift, unsigned Bits>
bool	SelectAddrRegZextRegScale (SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale)
bool	tryShrinkShlLogicImm (SDNode *Node)
bool	trySignedBitfieldExtract (SDNode *Node)
bool	tryIndexedLoad (SDNode *Node)
bool	selectShiftMask (SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
bool	selectShiftMaskXLen (SDValue N, SDValue &ShAmt)
bool	selectShiftMask32 (SDValue N, SDValue &ShAmt)
bool	selectSETCC (SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val)
	RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with 0.
bool	selectSETNE (SDValue N, SDValue &Val)
bool	selectSETEQ (SDValue N, SDValue &Val)
bool	selectSExtBits (SDValue N, unsigned Bits, SDValue &Val)
template<unsigned Bits>
bool	selectSExtBits (SDValue N, SDValue &Val)
bool	selectZExtBits (SDValue N, unsigned Bits, SDValue &Val)
template<unsigned Bits>
bool	selectZExtBits (SDValue N, SDValue &Val)
bool	selectSHXADDOp (SDValue N, unsigned ShAmt, SDValue &Val)
	Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
template<unsigned ShAmt>
bool	selectSHXADDOp (SDValue N, SDValue &Val)
bool	selectSHXADD_UWOp (SDValue N, unsigned ShAmt, SDValue &Val)
	Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
template<unsigned ShAmt>
bool	selectSHXADD_UWOp (SDValue N, SDValue &Val)
bool	hasAllNBitUsers (SDNode *Node, unsigned Bits, const unsigned Depth=0) const
bool	hasAllHUsers (SDNode *Node) const
bool	hasAllWUsers (SDNode *Node) const
bool	selectSimm5Shl2 (SDValue N, SDValue &Simm5, SDValue &Shl2)
bool	selectVLOp (SDValue N, SDValue &VL)
bool	selectVSplat (SDValue N, SDValue &SplatVal)
bool	selectVSplatSimm5 (SDValue N, SDValue &SplatVal)
bool	selectVSplatUimm5 (SDValue N, SDValue &SplatVal)
bool	selectVSplatSimm5Plus1 (SDValue N, SDValue &SplatVal)
bool	selectVSplatSimm5Plus1NonZero (SDValue N, SDValue &SplatVal)
bool	selectFPImm (SDValue N, SDValue &Imm)
bool	selectRVVSimm5 (SDValue N, unsigned Width, SDValue &Imm)
template<unsigned Width>
bool	selectRVVSimm5 (SDValue N, SDValue &Imm)
void	addVectorLoadStoreOperands (SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr)
void	selectVLSEG (SDNode *Node, bool IsMasked, bool IsStrided)
void	selectVLSEGFF (SDNode *Node, bool IsMasked)
void	selectVLXSEG (SDNode *Node, bool IsMasked, bool IsOrdered)
void	selectVSSEG (SDNode *Node, bool IsMasked, bool IsStrided)
void	selectVSXSEG (SDNode *Node, bool IsMasked, bool IsOrdered)
void	selectVSETVLI (SDNode *Node)
Public Member Functions inherited from llvm::SelectionDAGISel
	SelectionDAGISel (char &ID, TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default)
	~SelectionDAGISel () override
const TargetLowering *	getTargetLowering () const
void	getAnalysisUsage (AnalysisUsage &AU) const override
	getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
bool	runOnMachineFunction (MachineFunction &MF) override
	runOnMachineFunction - This method must be overloaded to perform the desired machine code transformation or analysis.
virtual void	emitFunctionEntryCode ()
virtual void	PreprocessISelDAG ()
	PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.
virtual void	PostprocessISelDAG ()
	PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
virtual void	Select (SDNode *N)=0
	Main hook for targets to transform nodes into machine nodes.
virtual bool	SelectInlineAsmMemoryOperand (const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps)
	SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.
virtual bool	IsProfitableToFold (SDValue N, SDNode *U, SDNode *Root) const
	IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during instruction selection that starts at Root.
bool	CheckAndMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
	CheckAndMask - The isel is trying to match something like (and X, 255).
bool	CheckOrMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const
	CheckOrMask - The isel is trying to match something like (or X, 255).
virtual bool	CheckPatternPredicate (unsigned PredNo) const
	CheckPatternPredicate - This function is generated by tblgen in the target.
virtual bool	CheckNodePredicate (SDNode *N, unsigned PredNo) const
	CheckNodePredicate - This function is generated by tblgen in the target.
virtual bool	CheckNodePredicateWithOperands (SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const
	CheckNodePredicateWithOperands - This function is generated by tblgen in the target.
virtual bool	CheckComplexPattern (SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result)
virtual SDValue	RunSDNodeXForm (SDValue V, unsigned XFormNo)
void	SelectCodeCommon (SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize)
virtual bool	ComplexPatternFuncMutatesDAG () const
	Return true if complex patterns for this target can mutate the DAG.
bool	mayRaiseFPException (SDNode *Node) const
	Return whether the node may raise an FP exception.
bool	isOrEquivalentToAdd (const SDNode *N) const
Public Member Functions inherited from llvm::MachineFunctionPass
bool	doInitialization (Module &) override
	doInitialization - Virtual method overridden by subclasses to do any necessary initialization before any pass is run.
Public Member Functions inherited from llvm::FunctionPass
	FunctionPass (char &pid)
Pass *	createPrinterPass (raw_ostream &OS, const std::string &Banner) const override
	createPrinterPass - Get a function printer pass.
virtual bool	runOnFunction (Function &F)=0
	runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass.
void	assignPassManager (PMStack &PMS, PassManagerType T) override
	Find appropriate Function Pass Manager or Call Graph Pass Manager in the PM Stack and add self into that manager.
PassManagerType	getPotentialPassManagerType () const override
	Return what kind of Pass Manager can manage this pass.
Public Member Functions inherited from llvm::Pass
	Pass (PassKind K, char &pid)
	Pass (const Pass &)=delete
Pass &	operator= (const Pass &)=delete
virtual	~Pass ()
PassKind	getPassKind () const
virtual StringRef	getPassName () const
	getPassName - Return a nice clean name for a pass.
AnalysisID	getPassID () const
	getPassID - Return the PassID number that corresponds to this pass.
virtual bool	doInitialization (Module &)
	doInitialization - Virtual method overridden by subclasses to do any necessary initialization before any pass is run.
virtual bool	doFinalization (Module &)
	doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run.
virtual void	print (raw_ostream &OS, const Module *M) const
	print - Print out the internal state of the pass.
void	dump () const
virtual Pass *	createPrinterPass (raw_ostream &OS, const std::string &Banner) const =0
	createPrinterPass - Get a Pass appropriate to print the IR this pass operates on (Module, Function or MachineFunction).
virtual void	assignPassManager (PMStack &, PassManagerType)
	Each pass is responsible for assigning a pass manager to itself.
virtual void	preparePassManager (PMStack &)
	Check if available pass managers are suitable for this pass or not.
virtual PassManagerType	getPotentialPassManagerType () const
	Return what kind of Pass Manager can manage this pass.
void	setResolver (AnalysisResolver *AR)
AnalysisResolver *	getResolver () const
virtual void	getAnalysisUsage (AnalysisUsage &) const
	getAnalysisUsage - This function should be overriden by passes that need analysis information to do their job.
virtual void	releaseMemory ()
	releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed.
virtual void *	getAdjustedAnalysisPointer (AnalysisID ID)
	getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance.
virtual ImmutablePass *	getAsImmutablePass ()
virtual PMDataManager *	getAsPMDataManager ()
virtual void	verifyAnalysis () const
	verifyAnalysis() - This member can be implemented by a analysis pass to check state of analysis information.
virtual void	dumpPassStructure (unsigned Offset=0)
template<typename AnalysisType >
AnalysisType *	getAnalysisIfAvailable () const
	getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information that might be around, for example to update it.
bool	mustPreserveAnalysisID (char &AID) const
	mustPreserveAnalysisID - This method serves the same function as getAnalysisIfAvailable, but works if you just have an AnalysisID.
template<typename AnalysisType >
AnalysisType &	getAnalysis () const
	getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function.
template<typename AnalysisType >
AnalysisType &	getAnalysis (Function &F, bool *Changed=nullptr)
	getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function.
template<typename AnalysisType >
AnalysisType &	getAnalysisID (AnalysisID PI) const
template<typename AnalysisType >
AnalysisType &	getAnalysisID (AnalysisID PI, Function &F, bool *Changed=nullptr)

Static Public Member Functions
static RISCVCC::CondCode	getRISCVCCForIntCC (ISD::CondCode CC)
Static Public Member Functions inherited from llvm::SelectionDAGISel
static bool	IsLegalToFold (SDValue N, SDNode *U, SDNode *Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false)
	IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction selection that starts at Root.
static void	InvalidateNodeId (SDNode *N)
static int	getUninvalidatedNodeId (SDNode *N)
static void	EnforceNodeIdInvariant (SDNode *N)
static int	getNumFixedFromVariadicInfo (unsigned Flags)
	getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values that should be skipped when copying from the root.
Static Public Member Functions inherited from llvm::Pass
static const PassInfo *	lookupPassInfo (const void *TI)
static const PassInfo *	lookupPassInfo (StringRef Arg)
static Pass *	createPass (AnalysisID ID)

Static Public Attributes
static char	ID = 0

Additional Inherited Members
Public Types inherited from llvm::SelectionDAGISel
enum	BuiltinOpcodes {   OPC_Scope , OPC_RecordNode , OPC_RecordChild0 , OPC_RecordChild1 ,   OPC_RecordChild2 , OPC_RecordChild3 , OPC_RecordChild4 , OPC_RecordChild5 ,   OPC_RecordChild6 , OPC_RecordChild7 , OPC_RecordMemRef , OPC_CaptureGlueInput ,   OPC_MoveChild , OPC_MoveChild0 , OPC_MoveChild1 , OPC_MoveChild2 ,   OPC_MoveChild3 , OPC_MoveChild4 , OPC_MoveChild5 , OPC_MoveChild6 ,   OPC_MoveChild7 , OPC_MoveParent , OPC_CheckSame , OPC_CheckChild0Same ,   OPC_CheckChild1Same , OPC_CheckChild2Same , OPC_CheckChild3Same , OPC_CheckPatternPredicate ,   OPC_CheckPredicate , OPC_CheckPredicateWithOperands , OPC_CheckOpcode , OPC_SwitchOpcode ,   OPC_CheckType , OPC_CheckTypeRes , OPC_SwitchType , OPC_CheckChild0Type ,   OPC_CheckChild1Type , OPC_CheckChild2Type , OPC_CheckChild3Type , OPC_CheckChild4Type ,   OPC_CheckChild5Type , OPC_CheckChild6Type , OPC_CheckChild7Type , OPC_CheckInteger ,   OPC_CheckChild0Integer , OPC_CheckChild1Integer , OPC_CheckChild2Integer , OPC_CheckChild3Integer ,   OPC_CheckChild4Integer , OPC_CheckCondCode , OPC_CheckChild2CondCode , OPC_CheckValueType ,   OPC_CheckComplexPat , OPC_CheckAndImm , OPC_CheckOrImm , OPC_CheckImmAllOnesV ,   OPC_CheckImmAllZerosV , OPC_CheckFoldableChainNode , OPC_EmitInteger , OPC_EmitStringInteger ,   OPC_EmitRegister , OPC_EmitRegister2 , OPC_EmitConvertToTarget , OPC_EmitMergeInputChains ,   OPC_EmitMergeInputChains1_0 , OPC_EmitMergeInputChains1_1 , OPC_EmitMergeInputChains1_2 , OPC_EmitCopyToReg ,   OPC_EmitCopyToReg2 , OPC_EmitNodeXForm , OPC_EmitNode , OPC_EmitNode0 ,   OPC_EmitNode1 , OPC_EmitNode2 , OPC_MorphNodeTo , OPC_MorphNodeTo0 ,   OPC_MorphNodeTo1 , OPC_MorphNodeTo2 , OPC_CompleteMatch , OPC_Coverage }
enum	{   OPFL_None = 0 , OPFL_Chain = 1 , OPFL_GlueInput = 2 , OPFL_GlueOutput = 4 ,   OPFL_MemRefs = 8 , OPFL_Variadic0 = 1<<4 , OPFL_Variadic1 = 2<<4 , OPFL_Variadic2 = 3<<4 ,   OPFL_Variadic3 = 4<<4 , OPFL_Variadic4 = 5<<4 , OPFL_Variadic5 = 6<<4 , OPFL_Variadic6 = 7<<4 ,   OPFL_VariadicInfo = OPFL_Variadic6 }
Public Attributes inherited from llvm::SelectionDAGISel
TargetMachine &	TM
const TargetLibraryInfo *	LibInfo
std::unique_ptr< FunctionLoweringInfo >	FuncInfo
SwiftErrorValueTracking *	SwiftError
MachineFunction *	MF
MachineRegisterInfo *	RegInfo
SelectionDAG *	CurDAG
std::unique_ptr< SelectionDAGBuilder >	SDB
AAResults *	AA = nullptr
AssumptionCache *	AC = nullptr
GCFunctionInfo *	GFI = nullptr
CodeGenOpt::Level	OptLevel
const TargetInstrInfo *	TII
const TargetLowering *	TLI
bool	FastISelFailed
SmallPtrSet< const Instruction *, 4 >	ElidedArgCopyInstrs
std::unique_ptr< OptimizationRemarkEmitter >	ORE
	Current optimization remark emitter.
Protected Member Functions inherited from llvm::SelectionDAGISel
void	ReplaceUses (SDValue F, SDValue T)
	ReplaceUses - replace all uses of the old node F with the use of the new node T.
void	ReplaceUses (const SDValue *F, const SDValue *T, unsigned Num)
	ReplaceUses - replace all uses of the old nodes F with the use of the new nodes T.
void	ReplaceUses (SDNode *F, SDNode *T)
	ReplaceUses - replace all uses of the old node F with the use of the new node T.
void	ReplaceNode (SDNode *F, SDNode *T)
	Replace all uses of F with T, then remove F from the DAG.
void	SelectInlineAsmMemoryOperands (std::vector< SDValue > &Ops, const SDLoc &DL)
	SelectInlineAsmMemoryOperands - Calls to this are automatically generated by tblgen.
virtual StringRef	getPatternForIndex (unsigned index)
	getPatternForIndex - Patterns selected by tablegen during ISEL
virtual StringRef	getIncludePathForIndex (unsigned index)
	getIncludePathForIndex - get the td source location of pattern instantiation
bool	shouldOptForSize (const MachineFunction *MF) const
Protected Member Functions inherited from llvm::MachineFunctionPass
	MachineFunctionPass (char &ID)
virtual bool	runOnMachineFunction (MachineFunction &MF)=0
	runOnMachineFunction - This method must be overloaded to perform the desired machine code transformation or analysis.
void	getAnalysisUsage (AnalysisUsage &AU) const override
	getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual MachineFunctionProperties	getRequiredProperties () const
virtual MachineFunctionProperties	getSetProperties () const
virtual MachineFunctionProperties	getClearedProperties () const
Protected Member Functions inherited from llvm::FunctionPass
bool	skipFunction (const Function &F) const
	Optional passes call this function to check whether the pass should be skipped.
Protected Attributes inherited from llvm::SelectionDAGISel
unsigned	DAGSize = 0
	DAGSize - Size of DAG being instruction selected.

Detailed Description

Definition at line 24 of file RISCVISelDAGToDAG.h.

Constructor & Destructor Documentation

RISCVDAGToDAGISel() [1/2]

llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel ( )

delete

RISCVDAGToDAGISel() [2/2]

llvm::RISCVDAGToDAGISel::RISCVDAGToDAGISel ( RISCVTargetMachine &  TargetMachine, CodeGenOpt::Level  OptLevel  )

inlineexplicit

Definition at line 32 of file RISCVISelDAGToDAG.h.

Member Function Documentation

addVectorLoadStoreOperands()

void RISCVDAGToDAGISel::addVectorLoadStoreOperands	(	SDNode *	Node,
		unsigned	SEWImm,
		const SDLoc &	DL,
		unsigned	CurOp,
		bool	IsMasked,
		bool	IsStridedOrIndexed,
		SmallVectorImpl< SDValue > &	Operands,
		bool	IsLoad = false,
		MVT *	IndexVT = nullptr
	)

Definition at line 266 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::RISCVSubtarget::getXLenVT(), Log2SEW, Operands, and selectVLOp().

Referenced by Select(), selectVLSEG(), selectVLSEGFF(), selectVLXSEG(), selectVSSEG(), and selectVSXSEG().

getRISCVCCForIntCC()

static RISCVCC::CondCode llvm::RISCVDAGToDAGISel::getRISCVCCForIntCC ( ISD::CondCode  CC )

inlinestatic

Definition at line 158 of file RISCVISelDAGToDAG.h.

References CC, llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, llvm::RISCVCC::COND_NE, llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, and llvm::ISD::SETULT.

hasAllHUsers()

bool llvm::RISCVDAGToDAGISel::hasAllHUsers ( SDNode *  Node ) const

inline

Definition at line 122 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

Referenced by Select().

hasAllNBitUsers()

bool RISCVDAGToDAGISel::hasAllNBitUsers	(	SDNode *	Node,
		unsigned	Bits,
		const unsigned	Depth = 0
	)		const

Definition at line 2722 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::bit_width(), llvm::Depth, llvm::User::getOperand(), llvm::RISCVSubtarget::getXLen(), hasAllNBitUsers(), llvm::Log2_32(), llvm::SelectionDAG::MaxRecursionDepth, llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRL, llvm::ISD::SUB, and llvm::ISD::XOR.

Referenced by hasAllHUsers(), hasAllNBitUsers(), and hasAllWUsers().

hasAllWUsers()

bool llvm::RISCVDAGToDAGISel::hasAllWUsers ( SDNode *  Node ) const

inline

Definition at line 123 of file RISCVISelDAGToDAG.h.

References hasAllNBitUsers().

Referenced by Select().

PostprocessISelDAG()

void RISCVDAGToDAGISel::PostprocessISelDAG ( )

overridevirtual

PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 152 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAG::allnodes_begin(), llvm::SelectionDAG::allnodes_end(), llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getRoot(), N, llvm::SelectionDAG::RemoveDeadNodes(), and llvm::SelectionDAG::setRoot().

PreprocessISelDAG()

void RISCVDAGToDAGISel::PreprocessISelDAG ( )

overridevirtual

PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 60 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAG::allnodes_begin(), llvm::SelectionDAG::allnodes_end(), assert(), llvm::SelectionDAGISel::CurDAG, llvm::dbgs(), DL, llvm::TypeSize::Fixed(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MachinePointerInfo::getWithOffset(), llvm::RISCVSubtarget::getXLenVT(), llvm::Hi, llvm::ISD::INTRINSIC_W_CHAIN, llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), LLVM_DEBUG, llvm::Lo, llvm::SelectionDAGISel::MF, llvm::MachineMemOperand::MOLoad, N, llvm::SelectionDAG::RemoveDeadNodes(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SPLAT_VECTOR, llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, llvm::SelectionDAGISel::TLI, llvm::ISD::TokenFactor, llvm::RISCVISD::VFMV_V_F_VL, and llvm::RISCVISD::VMV_V_X_VL.

runOnMachineFunction()

bool llvm::RISCVDAGToDAGISel::runOnMachineFunction ( MachineFunction &  MF )

inlineoverridevirtual

runOnMachineFunction - This method must be overloaded to perform the desired machine code transformation or analysis.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 36 of file RISCVISelDAGToDAG.h.

References llvm::MachineFunction::getSubtarget(), llvm::SelectionDAGISel::MF, and llvm::SelectionDAGISel::runOnMachineFunction().

Select()

void RISCVDAGToDAGISel::Select ( SDNode *  N )

overridevirtual

Main hook for targets to transform nodes into machine nodes.

Implements llvm::SelectionDAGISel.

Definition at line 802 of file RISCVISelDAGToDAG.cpp.

References addVectorLoadStoreOperands(), llvm::ISD::AND, assert(), llvm::bit_width(), llvm::ISD::BITCAST, llvm::APFloat::bitcastToAPInt(), llvm::CallingConv::C, CASE_VMSLT_OPCODES, CASE_VMSLT_VMNAND_VMSET_OPCODES, CASE_VMXOR_VMANDN_VMOR_OPCODES, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::countr_one(), llvm::countr_zero(), llvm::SelectionDAGISel::CurDAG, llvm::dbgs(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetMachine::getOptLevel(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), llvm::SelectionDAG::getRegister(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::MVT::getScalarSizeInBits(), llvm::APInt::getSExtValue(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getStoreSize(), llvm::EVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SelectionDAG::getTargetInsertSubreg(), llvm::RISCVSubtarget::getTargetLowering(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), hasAllHUsers(), hasAllWUsers(), llvm::SDValue::hasOneUse(), llvm::RISCVSubtarget::hasStdExtZhinxOrZhinxmin(), llvm::Hi, Idx, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::RISCVSubtarget::is64Bit(), llvm::MVT::isFixedLengthVector(), llvm::SelectionDAGISel::IsLegalToFold(), llvm::isMask_64(), llvm::APFloat::isNegZero(), llvm::isOneConstant(), llvm::APFloat::isPosZero(), llvm::SelectionDAGISel::IsProfitableToFold(), llvm::MVT::isScalableVector(), llvm::isShiftedMask_64(), llvm::APFloat::isZero(), LLVM_DEBUG, llvm_unreachable, llvm::RISCVII::LMUL_F2, llvm::RISCVII::LMUL_F4, llvm::RISCVII::LMUL_F8, llvm::Lo, llvm::ISD::LOAD, llvm::Log2_32(), Log2SEW, llvm::M1(), llvm::ISD::MUL, Operands, llvm::ISD::OR, P, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAGISel::ReplaceNode(), llvm::SelectionDAGISel::ReplaceUses(), llvm::report_fatal_error(), selectImm(), selectVLOp(), selectVLSEG(), selectVLSEGFF(), selectVLXSEG(), selectVSETVLI(), selectVSSEG(), selectVSXSEG(), llvm::SelectionDAG::setNodeMemRefs(), SEW, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::MVT::SimpleTy, llvm::RISCVISD::SplitF64, llvm::ISD::SRA, llvm::ISD::SRL, llvm::SelectionDAGISel::TLI, llvm::SelectionDAGISel::TM, TRI, tryIndexedLoad(), tryShrinkShlLogicImm(), trySignedBitfieldExtract(), llvm::RISCVISD::VFMV_S_F_VL, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_S_X_VL, llvm::RISCVISD::VMV_V_X_VL, X, and llvm::ISD::XOR.

SelectAddrFrameIndex()

bool RISCVDAGToDAGISel::SelectAddrFrameIndex	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset
	)

Definition at line 2152 of file RISCVISelDAGToDAG.cpp.

References Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::RISCVSubtarget::getXLenVT(), and llvm::Offset.

Referenced by SelectAddrRegImm(), and SelectFrameAddrRegImm().

SelectAddrRegImm()

bool RISCVDAGToDAGISel::SelectAddrRegImm	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset,
		bool	IsINX = false
	)

Definition at line 2311 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::RISCVISD::ADD_LO, Addr, assert(), llvm::sampleprof::Base, llvm::commonAlignment(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValueType(), llvm::SelectionDAG::isBaseWithConstantOffset(), isWorthFoldingAdd(), llvm::Offset, SelectAddrFrameIndex(), and selectConstantAddr().

Referenced by SelectAddrRegImmINX(), and SelectInlineAsmMemoryOperand().

SelectAddrRegImmINX()

bool llvm::RISCVDAGToDAGISel::SelectAddrRegImmINX ( SDValue  Addr, SDValue &  Base, SDValue &  Offset  )

inline

Definition at line 53 of file RISCVISelDAGToDAG.h.

References Addr, llvm::sampleprof::Base, llvm::Offset, and SelectAddrRegImm().

SelectAddrRegRegScale() [1/2]

template<unsigned MaxShift>

bool llvm::RISCVDAGToDAGISel::SelectAddrRegRegScale ( SDValue  Addr, SDValue &  Base, SDValue &  Index, SDValue &  Scale  )

inline

Definition at line 61 of file RISCVISelDAGToDAG.h.

References Addr, llvm::sampleprof::Base, and SelectAddrRegRegScale().

SelectAddrRegRegScale() [2/2]

bool RISCVDAGToDAGISel::SelectAddrRegRegScale	(	SDValue	Addr,
		unsigned	MaxShiftAmount,
		SDValue &	Base,
		SDValue &	Index,
		SDValue &	Scale
	)

Definition at line 2257 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), N, and llvm::ISD::SHL.

Referenced by SelectAddrRegRegScale(), and SelectAddrRegZextRegScale().

SelectAddrRegZextRegScale()

template<unsigned MaxShift, unsigned Bits>

bool llvm::RISCVDAGToDAGISel::SelectAddrRegZextRegScale ( SDValue  Addr, SDValue &  Base, SDValue &  Index, SDValue &  Scale  )

inline

Definition at line 67 of file RISCVISelDAGToDAG.h.

References Addr, llvm::ISD::AND, llvm::sampleprof::Base, llvm::CallingConv::C, and SelectAddrRegRegScale().

selectFPImm()

bool RISCVDAGToDAGISel::selectFPImm	(	SDValue	N,
		SDValue &	Imm
	)

Definition at line 3000 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::APFloat::bitcastToAPInt(), llvm::SelectionDAGISel::CurDAG, DL, llvm::APInt::getSExtValue(), llvm::SDNode::getSimpleValueType(), llvm::ConstantFPSDNode::getValueAPF(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::is64Bit(), llvm::APFloat::isNegZero(), llvm::APFloat::isPosZero(), N, selectImm(), and llvm::SelectionDAGISel::TLI.

SelectFrameAddrRegImm()

bool RISCVDAGToDAGISel::SelectFrameAddrRegImm	(	SDValue	Addr,
		SDValue &	Base,
		SDValue &	Offset
	)

Definition at line 2164 of file RISCVISelDAGToDAG.cpp.

References Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::Offset, and SelectAddrFrameIndex().

SelectInlineAsmMemoryOperand()

bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand ( const SDValue &  Op, unsigned  ConstraintID, std::vector< SDValue > &  OutOps  )

overridevirtual

SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.

If this does not match or is not implemented, return true. The resultant operands (which will appear in the machine instruction) should be added to the OutOps vector.

Reimplemented from llvm::SelectionDAGISel.

Definition at line 2126 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::InlineAsm::Constraint_A, llvm::InlineAsm::Constraint_m, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), and SelectAddrRegImm().

selectRVVSimm5() [1/2]

template<unsigned Width>

bool llvm::RISCVDAGToDAGISel::selectRVVSimm5 ( SDValue  N, SDValue &  Imm  )

inline

Definition at line 137 of file RISCVISelDAGToDAG.h.

References N, and selectRVVSimm5().

selectRVVSimm5() [2/2]

bool RISCVDAGToDAGISel::selectRVVSimm5	(	SDValue	N,
		unsigned	Width,
		SDValue &	Imm
	)

Definition at line 3026 of file RISCVISelDAGToDAG.cpp.

References llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), N, and llvm::SignExtend64().

Referenced by selectRVVSimm5().

selectSETCC()

bool RISCVDAGToDAGISel::selectSETCC	(	SDValue	N,
		ISD::CondCode	ExpectedCCVal,
		SDValue &	Val
	)

RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with 0.

This function emits instructions that convert the seteq/setne into something that can be compared with 0. When Equal is false, we match setne. When Equal is true, we match seteq.

Definition at line 2475 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), LHS, N, RHS, and llvm::ISD::SETCC.

Referenced by selectSETEQ(), and selectSETNE().

selectSETEQ()

bool llvm::RISCVDAGToDAGISel::selectSETEQ ( SDValue  N, SDValue &  Val  )

inline

Definition at line 97 of file RISCVISelDAGToDAG.h.

References N, selectSETCC(), and llvm::ISD::SETEQ.

selectSETNE()

bool llvm::RISCVDAGToDAGISel::selectSETNE ( SDValue  N, SDValue &  Val  )

inline

Definition at line 94 of file RISCVISelDAGToDAG.h.

References N, selectSETCC(), and llvm::ISD::SETNE.

selectSExtBits() [1/2]

template<unsigned Bits>

bool llvm::RISCVDAGToDAGISel::selectSExtBits ( SDValue  N, SDValue &  Val  )

inline

Definition at line 102 of file RISCVISelDAGToDAG.h.

References N, and selectSExtBits().

selectSExtBits() [2/2]

bool RISCVDAGToDAGISel::selectSExtBits	(	SDValue	N,
		unsigned	Bits,
		SDValue &	Val
	)

Definition at line 2534 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAGISel::CurDAG, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getSizeInBits(), N, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::SRA.

Referenced by selectSExtBits().

selectShiftMask()

bool RISCVDAGToDAGISel::selectShiftMask	(	SDValue	N,
		unsigned	ShiftWidth,
		SDValue &	ShAmt
	)

Definition at line 2403 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAGISel::CurDAG, DL, llvm::APInt::getBitWidth(), llvm::SDValue::getConstantOperandAPInt(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::isPowerOf2_32(), llvm::APInt::isSubsetOf(), N, llvm::ISD::SUB, and llvm::KnownBits::Zero.

Referenced by selectShiftMask32(), and selectShiftMaskXLen().

selectShiftMask32()

bool llvm::RISCVDAGToDAGISel::selectShiftMask32 ( SDValue  N, SDValue &  ShAmt  )

inline

Definition at line 89 of file RISCVISelDAGToDAG.h.

References N, and selectShiftMask().

selectShiftMaskXLen()

bool llvm::RISCVDAGToDAGISel::selectShiftMaskXLen ( SDValue  N, SDValue &  ShAmt  )

inline

Definition at line 86 of file RISCVISelDAGToDAG.h.

References llvm::RISCVSubtarget::getXLen(), N, and selectShiftMask().

selectSHXADD_UWOp() [1/2]

template<unsigned ShAmt>

bool llvm::RISCVDAGToDAGISel::selectSHXADD_UWOp ( SDValue  N, SDValue &  Val  )

inline

Definition at line 116 of file RISCVISelDAGToDAG.h.

References N, and selectSHXADD_UWOp().

selectSHXADD_UWOp() [2/2]

bool RISCVDAGToDAGISel::selectSHXADD_UWOp	(	SDValue	N,
		unsigned	ShAmt,
		SDValue &	Val
	)

Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.

ShAmt contains 1, 2, or 3 and is set based on which SHXADD_UW we are trying to match.

Definition at line 2679 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::AND, llvm::countl_zero(), llvm::countr_zero(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), llvm::isShiftedMask_64(), N, and llvm::ISD::SHL.

Referenced by selectSHXADD_UWOp().

selectSHXADDOp() [1/2]

template<unsigned ShAmt>

bool llvm::RISCVDAGToDAGISel::selectSHXADDOp ( SDValue  N, SDValue &  Val  )

inline

Definition at line 111 of file RISCVISelDAGToDAG.h.

References N, and selectSHXADDOp().

selectSHXADDOp() [2/2]

bool RISCVDAGToDAGISel::selectSHXADDOp	(	SDValue	N,
		unsigned	ShAmt,
		SDValue &	Val
	)

Look for various patterns that can be done with a SHL that can be folded into a SHXADD.

ShAmt contains 1, 2, or 3 and is set based on which SHXADD we are trying to match.

Definition at line 2584 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::AND, llvm::bit_width(), llvm::countr_zero(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLen(), llvm::SDValue::hasOneUse(), llvm::isShiftedMask_64(), N, llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by selectSHXADDOp().

selectSimm5Shl2()

bool RISCVDAGToDAGISel::selectSimm5Shl2	(	SDValue	N,
		SDValue &	Simm5,
		SDValue &	Shl2
	)

Definition at line 2873 of file RISCVISelDAGToDAG.cpp.

References llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), N, and llvm::Offset.

selectVLOp()

bool RISCVDAGToDAGISel::selectVLOp	(	SDValue	N,
		SDValue &	VL
	)

Definition at line 2897 of file RISCVISelDAGToDAG.cpp.

References llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, getReg(), llvm::SelectionDAG::getTargetConstant(), N, and llvm::RISCV::VLMaxSentinel.

Referenced by addVectorLoadStoreOperands(), and Select().

selectVLSEG()

void RISCVDAGToDAGISel::selectVLSEG	(	SDNode *	Node,
		bool	IsMasked,
		bool	IsStrided
	)

Definition at line 313 of file RISCVISelDAGToDAG.cpp.

References addVectorLoadStoreOperands(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::RISCVTargetLowering::getSubregIndexByMVT(), llvm::SelectionDAG::getTargetExtractSubreg(), I, isAllUndef(), llvm::Log2_32(), Log2SEW, Merge, Operands, P, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAGISel::ReplaceUses(), and llvm::SelectionDAG::setNodeMemRefs().

Referenced by Select().

selectVLSEGFF()

void RISCVDAGToDAGISel::selectVLSEGFF	(	SDNode *	Node,
		bool	IsMasked
	)

Definition at line 356 of file RISCVISelDAGToDAG.cpp.

References addVectorLoadStoreOperands(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::RISCVTargetLowering::getSubregIndexByMVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::RISCVSubtarget::getXLenVT(), I, isAllUndef(), llvm::Log2_32(), Log2SEW, Operands, P, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAGISel::ReplaceUses(), and llvm::SelectionDAG::setNodeMemRefs().

Referenced by Select().

selectVLXSEG()

void RISCVDAGToDAGISel::selectVLXSEG	(	SDNode *	Node,
		bool	IsMasked,
		bool	IsOrdered
	)

Definition at line 401 of file RISCVISelDAGToDAG.cpp.

References addVectorLoadStoreOperands(), assert(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::RISCVTargetLowering::getSubregIndexByMVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::MVT::getVectorElementCount(), I, llvm::RISCVSubtarget::is64Bit(), isAllUndef(), llvm::Log2_32(), Log2SEW, Operands, P, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAGISel::ReplaceUses(), llvm::report_fatal_error(), and llvm::SelectionDAG::setNodeMemRefs().

Referenced by Select().

selectVSETVLI()

void RISCVDAGToDAGISel::selectVSETVLI

(

SDNode *

Node

)

Definition at line 529 of file RISCVISelDAGToDAG.cpp.

References assert(), llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::RISCVVType::decodeVSEW(), DL, llvm::RISCVVType::encodeVTYPE(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructions(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::Offset, llvm::SelectionDAGISel::ReplaceNode(), SEW, and VLMul.

Referenced by Select().

selectVSplat()

bool RISCVDAGToDAGISel::selectVSplat	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 2921 of file RISCVISelDAGToDAG.cpp.

References assert(), N, and llvm::RISCVISD::VMV_V_X_VL.

selectVSplatSimm5()

bool RISCVDAGToDAGISel::selectVSplatSimm5	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 2964 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, N, and selectVSplatSimmHelper().

selectVSplatSimm5Plus1()

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 2969 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, N, and selectVSplatSimmHelper().

selectVSplatSimm5Plus1NonZero()

bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 2975 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, N, and selectVSplatSimmHelper().

selectVSplatUimm5()

bool RISCVDAGToDAGISel::selectVSplatUimm5	(	SDValue	N,
		SDValue &	SplatVal
	)

Definition at line 2983 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), N, and llvm::RISCVISD::VMV_V_X_VL.

selectVSSEG()

void RISCVDAGToDAGISel::selectVSSEG	(	SDNode *	Node,
		bool	IsMasked,
		bool	IsStrided
	)

Definition at line 455 of file RISCVISelDAGToDAG.cpp.

References addVectorLoadStoreOperands(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::Log2_32(), Log2SEW, Operands, P, llvm::SelectionDAGISel::ReplaceNode(), and llvm::SelectionDAG::setNodeMemRefs().

Referenced by Select().

selectVSXSEG()

void RISCVDAGToDAGISel::selectVSXSEG	(	SDNode *	Node,
		bool	IsMasked,
		bool	IsOrdered
	)

Definition at line 487 of file RISCVISelDAGToDAG.cpp.

References addVectorLoadStoreOperands(), assert(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorElementCount(), llvm::RISCVSubtarget::is64Bit(), llvm::Log2_32(), Log2SEW, Operands, P, llvm::SelectionDAGISel::ReplaceNode(), llvm::report_fatal_error(), and llvm::SelectionDAG::setNodeMemRefs().

Referenced by Select().

selectZExtBits() [1/2]

template<unsigned Bits>

bool llvm::RISCVDAGToDAGISel::selectZExtBits ( SDValue  N, SDValue &  Val  )

inline

Definition at line 106 of file RISCVISelDAGToDAG.h.

References N, and selectZExtBits().

selectZExtBits() [2/2]

bool RISCVDAGToDAGISel::selectZExtBits	(	SDValue	N,
		unsigned	Bits,
		SDValue &	Val
	)

Definition at line 2563 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::AND, llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::APInt::getBitsSetFrom(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::MaskedValueIsZero(), and N.

Referenced by selectZExtBits().

tryIndexedLoad()

bool RISCVDAGToDAGISel::tryIndexedLoad

(

SDNode *

Node

)

Definition at line 731 of file RISCVISelDAGToDAG.cpp.

References llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::LSBaseSDNode::getAddressingMode(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getMachineNode(), llvm::MemSDNode::getMemoryVT(), llvm::LoadSDNode::getOffset(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::Offset, llvm::ISD::POST_DEC, llvm::ISD::POST_INC, llvm::ISD::PRE_DEC, llvm::ISD::PRE_INC, llvm::SelectionDAGISel::ReplaceNode(), llvm::SelectionDAG::setNodeMemRefs(), llvm::ISD::UNINDEXED, and llvm::ISD::ZEXTLOAD.

Referenced by Select().

tryShrinkShlLogicImm()

bool RISCVDAGToDAGISel::tryShrinkShlLogicImm

(

SDNode *

Node

)

Definition at line 586 of file RISCVISelDAGToDAG.cpp.

References llvm::ISD::AND, assert(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::SelectionDAG::getTargetConstant(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm_unreachable, llvm::ISD::OR, llvm::SelectionDAGISel::ReplaceNode(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::XOR.

Referenced by Select().

trySignedBitfieldExtract()

bool RISCVDAGToDAGISel::trySignedBitfieldExtract

(

SDNode *

Node

)

Definition at line 664 of file RISCVISelDAGToDAG.cpp.

References llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), llvm::SelectionDAGISel::ReplaceNode(), llvm::ISD::SHL, and llvm::ISD::SIGN_EXTEND_INREG.

Referenced by Select().

Member Data Documentation

ID

char RISCVDAGToDAGISel::ID = 0

static

Definition at line 28 of file RISCVISelDAGToDAG.h.

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The documentation for this class was generated from the following files:

• lib/Target/RISCV/RISCVISelDAGToDAG.h
• lib/Target/RISCV/RISCVISelDAGToDAG.cpp