#include "Target/RISCV/RISCVISelDAGToDAG.h"
Public Member Functions | |
| RISCVDAGToDAGISel ()=delete | |
| RISCVDAGToDAGISel (RISCVTargetMachine &TargetMachine, CodeGenOpt::Level OptLevel) | |
| bool | runOnMachineFunction (MachineFunction &MF) override |
| runOnMachineFunction - This method must be overloaded to perform the desired machine code transformation or analysis. More... | |
| void | PreprocessISelDAG () override |
| PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts. More... | |
| void | PostprocessISelDAG () override |
| PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection. More... | |
| void | Select (SDNode *Node) override |
| Main hook for targets to transform nodes into machine nodes. More... | |
| bool | SelectInlineAsmMemoryOperand (const SDValue &Op, unsigned ConstraintID, std::vector< SDValue > &OutOps) override |
| SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint. More... | |
| bool | SelectAddrFrameIndex (SDValue Addr, SDValue &Base, SDValue &Offset) |
| bool | SelectFrameAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset) |
| bool | SelectAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset) |
| bool | tryShrinkShlLogicImm (SDNode *Node) |
| bool | selectShiftMask (SDValue N, unsigned ShiftWidth, SDValue &ShAmt) |
| bool | selectShiftMaskXLen (SDValue N, SDValue &ShAmt) |
| bool | selectShiftMask32 (SDValue N, SDValue &ShAmt) |
| bool | selectSExti32 (SDValue N, SDValue &Val) |
| bool | selectZExtBits (SDValue N, unsigned Bits, SDValue &Val) |
| template<unsigned Bits> | |
| bool | selectZExtBits (SDValue N, SDValue &Val) |
| bool | selectSHXADDOp (SDValue N, unsigned ShAmt, SDValue &Val) |
| Look for various patterns that can be done with a SHL that can be folded into a SHXADD. More... | |
| template<unsigned ShAmt> | |
| bool | selectSHXADDOp (SDValue N, SDValue &Val) |
| bool | selectSHXADD_UWOp (SDValue N, unsigned ShAmt, SDValue &Val) |
| Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW. More... | |
| template<unsigned ShAmt> | |
| bool | selectSHXADD_UWOp (SDValue N, SDValue &Val) |
| bool | hasAllNBitUsers (SDNode *Node, unsigned Bits, const unsigned Depth=0) const |
| bool | hasAllHUsers (SDNode *Node) const |
| bool | hasAllWUsers (SDNode *Node) const |
| bool | selectVLOp (SDValue N, SDValue &VL) |
| bool | selectVSplat (SDValue N, SDValue &SplatVal) |
| bool | selectVSplatSimm5 (SDValue N, SDValue &SplatVal) |
| bool | selectVSplatUimm5 (SDValue N, SDValue &SplatVal) |
| bool | selectVSplatSimm5Plus1 (SDValue N, SDValue &SplatVal) |
| bool | selectVSplatSimm5Plus1NonZero (SDValue N, SDValue &SplatVal) |
| bool | selectRVVSimm5 (SDValue N, unsigned Width, SDValue &Imm) |
| template<unsigned Width> | |
| bool | selectRVVSimm5 (SDValue N, SDValue &Imm) |
| void | addVectorLoadStoreOperands (SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr) |
| void | selectVLSEG (SDNode *Node, bool IsMasked, bool IsStrided) |
| void | selectVLSEGFF (SDNode *Node, bool IsMasked) |
| void | selectVLXSEG (SDNode *Node, bool IsMasked, bool IsOrdered) |
| void | selectVSSEG (SDNode *Node, bool IsMasked, bool IsStrided) |
| void | selectVSXSEG (SDNode *Node, bool IsMasked, bool IsOrdered) |
| void | selectVSETVLI (SDNode *Node) |
 Public Member Functions inherited from llvm::SelectionDAGISel | |
| SelectionDAGISel (char &ID, TargetMachine &tm, CodeGenOpt::Level OL=CodeGenOpt::Default) | |
| ~SelectionDAGISel () override | |
| const TargetLowering * | getTargetLowering () const |
| void | getAnalysisUsage (AnalysisUsage &AU) const override |
| getAnalysisUsage - Subclasses that override getAnalysisUsage must call this. More... | |
| virtual void | emitFunctionEntryCode () |
| virtual bool | IsProfitableToFold (SDValue N, SDNode *U, SDNode *Root) const |
| IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during instruction selection that starts at Root. More... | |
| bool | CheckAndMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const |
| CheckAndMask - The isel is trying to match something like (and X, 255). More... | |
| bool | CheckOrMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const |
| CheckOrMask - The isel is trying to match something like (or X, 255). More... | |
| virtual bool | CheckPatternPredicate (unsigned PredNo) const |
| CheckPatternPredicate - This function is generated by tblgen in the target. More... | |
| virtual bool | CheckNodePredicate (SDNode *N, unsigned PredNo) const |
| CheckNodePredicate - This function is generated by tblgen in the target. More... | |
| virtual bool | CheckNodePredicateWithOperands (SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const |
| CheckNodePredicateWithOperands - This function is generated by tblgen in the target. More... | |
| virtual bool | CheckComplexPattern (SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result) |
| virtual SDValue | RunSDNodeXForm (SDValue V, unsigned XFormNo) |
| void | SelectCodeCommon (SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize) |
| virtual bool | ComplexPatternFuncMutatesDAG () const |
| Return true if complex patterns for this target can mutate the DAG. More... | |
| bool | mayRaiseFPException (SDNode *Node) const |
| Return whether the node may raise an FP exception. More... | |
| bool | isOrEquivalentToAdd (const SDNode *N) const |
| Public Member Functions inherited from llvm::MachineFunctionPass | |
| bool | doInitialization (Module &) override |
| doInitialization - Virtual method overridden by subclasses to do any necessary initialization before any pass is run. More... | |
| Public Member Functions inherited from llvm::FunctionPass | |
| FunctionPass (char &pid) | |
| Pass * | createPrinterPass (raw_ostream &OS, const std::string &Banner) const override |
| createPrinterPass - Get a function printer pass. More... | |
| void | assignPassManager (PMStack &PMS, PassManagerType T) override |
| Find appropriate Function Pass Manager or Call Graph Pass Manager in the PM Stack and add self into that manager. More... | |
| PassManagerType | getPotentialPassManagerType () const override |
| Return what kind of Pass Manager can manage this pass. More... | |
| Public Member Functions inherited from llvm::Pass | |
| Pass (PassKind K, char &pid) | |
| Pass (const Pass &)=delete | |
| Pass & | operator= (const Pass &)=delete |
| virtual | ~Pass () |
| PassKind | getPassKind () const |
| virtual StringRef | getPassName () const |
| getPassName - Return a nice clean name for a pass. More... | |
| AnalysisID | getPassID () const |
| getPassID - Return the PassID number that corresponds to this pass. More... | |
| virtual bool | doFinalization (Module &) |
| doFinalization - Virtual method overriden by subclasses to do any necessary clean up after all passes have run. More... | |
| virtual void | print (raw_ostream &OS, const Module *M) const |
| print - Print out the internal state of the pass. More... | |
| void | dump () const |
| virtual void | preparePassManager (PMStack &) |
| Check if available pass managers are suitable for this pass or not. More... | |
| void | setResolver (AnalysisResolver *AR) |
| AnalysisResolver * | getResolver () const |
| virtual void | releaseMemory () |
| releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memory when it is no longer needed. More... | |
| virtual void * | getAdjustedAnalysisPointer (AnalysisID ID) |
| getAdjustedAnalysisPointer - This method is used when a pass implements an analysis interface through multiple inheritance. More... | |
| virtual ImmutablePass * | getAsImmutablePass () |
| virtual PMDataManager * | getAsPMDataManager () |
| virtual void | verifyAnalysis () const |
| verifyAnalysis() - This member can be implemented by a analysis pass to check state of analysis information. More... | |
| virtual void | dumpPassStructure (unsigned Offset=0) |
| template<typename AnalysisType > | |
| AnalysisType * | getAnalysisIfAvailable () const |
| getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information that might be around, for example to update it. More... | |
| bool | mustPreserveAnalysisID (char &AID) const |
| mustPreserveAnalysisID - This method serves the same function as getAnalysisIfAvailable, but works if you just have an AnalysisID. More... | |
| template<typename AnalysisType > | |
| AnalysisType & | getAnalysis () const |
| getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function. More... | |
| template<typename AnalysisType > | |
| AnalysisType & | getAnalysis (Function &F, bool *Changed=nullptr) |
| getAnalysis<AnalysisType>() - This function is used by subclasses to get to the analysis information that they claim to use by overriding the getAnalysisUsage function. More... | |
| template<typename AnalysisType > | |
| AnalysisType & | getAnalysisID (AnalysisID PI) const |
| template<typename AnalysisType > | |
| AnalysisType & | getAnalysisID (AnalysisID PI, Function &F, bool *Changed=nullptr) |
Static Public Member Functions | |
| static RISCVCC::CondCode | getRISCVCCForIntCC (ISD::CondCode CC) |
| Static Public Member Functions inherited from llvm::SelectionDAGISel | |
| static bool | IsLegalToFold (SDValue N, SDNode *U, SDNode *Root, CodeGenOpt::Level OptLevel, bool IgnoreChains=false) |
| IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction selection that starts at Root. More... | |
| static void | InvalidateNodeId (SDNode *N) |
| static int | getUninvalidatedNodeId (SDNode *N) |
| static void | EnforceNodeIdInvariant (SDNode *N) |
| static int | getNumFixedFromVariadicInfo (unsigned Flags) |
| getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values that should be skipped when copying from the root. More... | |
| Static Public Member Functions inherited from llvm::Pass | |
| static const PassInfo * | lookupPassInfo (const void *TI) |
| static const PassInfo * | lookupPassInfo (StringRef Arg) |
| static Pass * | createPass (AnalysisID ID) |
Static Public Attributes | |
| static char | ID = 0 |
Detailed Description
Definition at line 24 of file RISCVISelDAGToDAG.h.
Constructor & Destructor Documentation
◆ RISCVDAGToDAGISel() [1/2]
|
delete |
◆ RISCVDAGToDAGISel() [2/2]
|
inlineexplicit |
Definition at line 32 of file RISCVISelDAGToDAG.h.
Member Function Documentation
◆ addVectorLoadStoreOperands()
| void RISCVDAGToDAGISel::addVectorLoadStoreOperands | ( | SDNode * | Node, |
| unsigned | SEWImm, | ||
| const SDLoc & | DL, | ||
| unsigned | CurOp, | ||
| bool | IsMasked, | ||
| bool | IsStridedOrIndexed, | ||
| SmallVectorImpl< SDValue > & | Operands, | ||
| bool | IsLoad = false, |
||
| MVT * | IndexVT = nullptr |
||
| ) |
Definition at line 266 of file RISCVISelDAGToDAG.cpp.
◆ getRISCVCCForIntCC()
|
inlinestatic |
Definition at line 114 of file RISCVISelDAGToDAG.h.
References CC, llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, llvm::RISCVCC::COND_NE, llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, and llvm::ISD::SETULT.
◆ hasAllHUsers()
|
inline |
Definition at line 81 of file RISCVISelDAGToDAG.h.
References hasAllNBitUsers().
◆ hasAllNBitUsers()
| bool RISCVDAGToDAGISel::hasAllNBitUsers | ( | SDNode * | Node, |
| unsigned | Bits, | ||
| const unsigned | Depth = 0 |
||
| ) | const |
Definition at line 2310 of file RISCVISelDAGToDAG.cpp.
Referenced by hasAllHUsers(), and hasAllWUsers().
◆ hasAllWUsers()
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inline |
Definition at line 82 of file RISCVISelDAGToDAG.h.
References hasAllNBitUsers().
◆ PostprocessISelDAG()
|
overridevirtual |
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
Reimplemented from llvm::SelectionDAGISel.
Definition at line 152 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAG::allnodes_begin(), llvm::SelectionDAG::allnodes_end(), llvm::SelectionDAGISel::CurDAG, llvm::NVPTXISD::Dummy, llvm::SelectionDAG::getRoot(), N, llvm::SelectionDAG::RemoveDeadNodes(), and llvm::SelectionDAG::setRoot().
◆ PreprocessISelDAG()
|
overridevirtual |
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.
Reimplemented from llvm::SelectionDAGISel.
Definition at line 60 of file RISCVISelDAGToDAG.cpp.
References Align, llvm::SelectionDAG::allnodes_begin(), llvm::SelectionDAG::allnodes_end(), assert(), llvm::SelectionDAGISel::CurDAG, llvm::dbgs(), DL, llvm::TypeSize::Fixed(), llvm::SelectionDAGISel::FuncInfo, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MachinePointerInfo::getWithOffset(), llvm::RISCVSubtarget::getXLenVT(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_W_CHAIN, llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), LLVM_DEBUG, llvm::SelectionDAGISel::MF, llvm::MachineMemOperand::MOLoad, N, llvm::MVT::Other, llvm::SelectionDAG::RemoveDeadNodes(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SPLAT_VECTOR, llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, llvm::SelectionDAGISel::TLI, llvm::ISD::TokenFactor, llvm::RISCVISD::VFMV_V_F_VL, and llvm::RISCVISD::VMV_V_X_VL.
◆ runOnMachineFunction()
|
inlineoverridevirtual |
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformation or analysis.
Reimplemented from llvm::SelectionDAGISel.
Definition at line 36 of file RISCVISelDAGToDAG.h.
References llvm::MachineFunction::getSubtarget(), llvm::SelectionDAGISel::MF, and llvm::SelectionDAGISel::runOnMachineFunction().
◆ Select()
|
overridevirtual |
Main hook for targets to transform nodes into machine nodes.
Implements llvm::SelectionDAGISel.
Definition at line 677 of file RISCVISelDAGToDAG.cpp.
◆ SelectAddrFrameIndex()
Definition at line 1874 of file RISCVISelDAGToDAG.cpp.
References Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::RISCVSubtarget::getXLenVT(), and llvm::Offset.
Referenced by SelectAddrRegImm(), and SelectFrameAddrRegImm().
◆ SelectAddrRegImm()
Definition at line 1979 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::ADD, llvm::RISCVISD::ADD_LO, Addr, assert(), llvm::sampleprof::Base, llvm::commonAlignment(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValueType(), llvm::SelectionDAG::isBaseWithConstantOffset(), isWorthFoldingAdd(), llvm::Offset, SelectAddrFrameIndex(), and selectConstantAddr().
◆ SelectFrameAddrRegImm()
Definition at line 1886 of file RISCVISelDAGToDAG.cpp.
References Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::Offset, and SelectAddrFrameIndex().
◆ SelectInlineAsmMemoryOperand()
|
overridevirtual |
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.
If this does not match or is not implemented, return true. The resultant operands (which will appear in the machine instruction) should be added to the OutOps vector.
Reimplemented from llvm::SelectionDAGISel.
Definition at line 1856 of file RISCVISelDAGToDAG.cpp.
References llvm::InlineAsm::Constraint_A, and llvm::InlineAsm::Constraint_m.
◆ selectRVVSimm5() [1/2]
|
inline |
Definition at line 93 of file RISCVISelDAGToDAG.h.
References llvm::RISCVMatInt::Imm, N, and selectRVVSimm5().
◆ selectRVVSimm5() [2/2]
Definition at line 2563 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVMatInt::Imm, N, and llvm::SignExtend64().
Referenced by selectRVVSimm5().
◆ selectSExti32()
Definition at line 2136 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAGISel::CurDAG, llvm::MVT::getSizeInBits(), llvm::MVT::i32, N, and llvm::ISD::SIGN_EXTEND_INREG.
◆ selectShiftMask()
Definition at line 2069 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAGISel::CurDAG, DL, llvm::APInt::getBitWidth(), llvm::SDValue::getConstantOperandAPInt(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::MVT::i64, llvm::RISCVMatInt::Imm, llvm::isPowerOf2_32(), llvm::APInt::isSubsetOf(), N, llvm::ISD::SUB, and llvm::KnownBits::Zero.
Referenced by selectShiftMask32(), and selectShiftMaskXLen().
◆ selectShiftMask32()
Definition at line 59 of file RISCVISelDAGToDAG.h.
References N, and selectShiftMask().
◆ selectShiftMaskXLen()
Definition at line 56 of file RISCVISelDAGToDAG.h.
References llvm::RISCVSubtarget::getXLen(), N, and selectShiftMask().
◆ selectSHXADD_UWOp() [1/2]
|
inline |
Definition at line 75 of file RISCVISelDAGToDAG.h.
References N, and selectSHXADD_UWOp().
◆ selectSHXADD_UWOp() [2/2]
Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
ShAmt contains 1, 2, or 3 and is set based on which SHXADD_UW we are trying to match.
Definition at line 2267 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::countLeadingZeros(), llvm::countTrailingZeros(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), llvm::isShiftedMask_64(), llvm::BitmaskEnumDetail::Mask(), N, and llvm::ISD::SHL.
Referenced by selectSHXADD_UWOp().
◆ selectSHXADDOp() [1/2]
|
inline |
Definition at line 70 of file RISCVISelDAGToDAG.h.
References N, and selectSHXADDOp().
◆ selectSHXADDOp() [2/2]
Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
ShAmt contains 1, 2, or 3 and is set based on which SHXADD we are trying to match.
Definition at line 2172 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::bit_width(), C1, llvm::countTrailingZeros(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLen(), llvm::SDValue::hasOneUse(), llvm::isShiftedMask_64(), llvm::BitmaskEnumDetail::Mask(), N, llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by selectSHXADDOp().
◆ selectVLOp()
Definition at line 2460 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, getReg(), llvm::SelectionDAG::getTargetConstant(), N, and llvm::RISCV::VLMaxSentinel.
◆ selectVLSEG()
| void RISCVDAGToDAGISel::selectVLSEG | ( | SDNode * | Node, |
| bool | IsMasked, | ||
| bool | IsStrided | ||
| ) |
Definition at line 313 of file RISCVISelDAGToDAG.cpp.
◆ selectVLSEGFF()
| void RISCVDAGToDAGISel::selectVLSEGFF | ( | SDNode * | Node, |
| bool | IsMasked | ||
| ) |
Definition at line 356 of file RISCVISelDAGToDAG.cpp.
◆ selectVLXSEG()
| void RISCVDAGToDAGISel::selectVLXSEG | ( | SDNode * | Node, |
| bool | IsMasked, | ||
| bool | IsOrdered | ||
| ) |
Definition at line 401 of file RISCVISelDAGToDAG.cpp.
◆ selectVSETVLI()
| void RISCVDAGToDAGISel::selectVSETVLI | ( | SDNode * | Node | ) |
Definition at line 529 of file RISCVISelDAGToDAG.cpp.
◆ selectVSplat()
Definition at line 2484 of file RISCVISelDAGToDAG.cpp.
References assert(), N, and llvm::RISCVISD::VMV_V_X_VL.
◆ selectVSplatSimm5()
Definition at line 2527 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, llvm::RISCVMatInt::Imm, N, and selectVSplatSimmHelper().
◆ selectVSplatSimm5Plus1()
Definition at line 2532 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, llvm::RISCVMatInt::Imm, N, and selectVSplatSimmHelper().
◆ selectVSplatSimm5Plus1NonZero()
Definition at line 2538 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, llvm::RISCVMatInt::Imm, N, and selectVSplatSimmHelper().
◆ selectVSplatUimm5()
Definition at line 2546 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), N, and llvm::RISCVISD::VMV_V_X_VL.
◆ selectVSSEG()
| void RISCVDAGToDAGISel::selectVSSEG | ( | SDNode * | Node, |
| bool | IsMasked, | ||
| bool | IsStrided | ||
| ) |
Definition at line 455 of file RISCVISelDAGToDAG.cpp.
◆ selectVSXSEG()
| void RISCVDAGToDAGISel::selectVSXSEG | ( | SDNode * | Node, |
| bool | IsMasked, | ||
| bool | IsOrdered | ||
| ) |
Definition at line 487 of file RISCVISelDAGToDAG.cpp.
◆ selectZExtBits() [1/2]
|
inline |
Definition at line 65 of file RISCVISelDAGToDAG.h.
References llvm::tgtok::Bits, N, and selectZExtBits().
◆ selectZExtBits() [2/2]
Definition at line 2151 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::tgtok::Bits, llvm::SelectionDAGISel::CurDAG, llvm::APInt::getBitsSetFrom(), llvm::MVT::getSizeInBits(), llvm::BitmaskEnumDetail::Mask(), llvm::SelectionDAG::MaskedValueIsZero(), and N.
Referenced by selectZExtBits().
◆ tryShrinkShlLogicImm()
| bool RISCVDAGToDAGISel::tryShrinkShlLogicImm | ( | SDNode * | Node | ) |
Definition at line 599 of file RISCVISelDAGToDAG.cpp.
Member Data Documentation
◆ ID
|
static |
Definition at line 28 of file RISCVISelDAGToDAG.h.
The documentation for this class was generated from the following files:
- lib/Target/RISCV/RISCVISelDAGToDAG.h
- lib/Target/RISCV/RISCVISelDAGToDAG.cpp
