RISCVOptWInstrs.cpp File Reference

#include "RISCV.h"
#include "RISCVMachineFunctionInfo.h"
#include "RISCVSubtarget.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/TargetInstrInfo.h"

Go to the source code of this file.

Macros
#define	DEBUG_TYPE   "riscv-opt-w-instrs"
#define	RISCV_OPT_W_INSTRS_NAME   "RISC-V Optimize W Instructions"

Functions
	STATISTIC (NumRemovedSExtW, "Number of removed sign-extensions")
	STATISTIC (NumTransformedToWInstrs, "Number of instructions transformed to W-ops")
	STATISTIC (NumTransformedToNonWInstrs, "Number of instructions transformed to non-W-ops")
	INITIALIZE_PASS (RISCVOptWInstrs, DEBUG_TYPE, RISCV_OPT_W_INSTRS_NAME, false, false) FunctionPass *llvm
static bool	vectorPseudoHasAllNBitUsers (const MachineOperand &UserOp, unsigned Bits)
static bool	hasAllNBitUsers (const MachineInstr &OrigMI, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI, unsigned OrigBits)
static bool	hasAllWUsers (const MachineInstr &OrigMI, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI)
static bool	isSignExtendingOpW (const MachineInstr &MI, unsigned OpNo)
static bool	isSignExtendedW (Register SrcReg, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI, SmallPtrSetImpl< MachineInstr * > &FixableDef)
static unsigned	getWOp (unsigned Opcode)

Variables
static cl::opt< bool >	DisableSExtWRemoval ("riscv-disable-sextw-removal", cl::desc("Disable removal of sext.w"), cl::init(false), cl::Hidden)
static cl::opt< bool >	DisableStripWSuffix ("riscv-disable-strip-w-suffix", cl::desc("Disable strip W suffix"), cl::init(false), cl::Hidden)

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "riscv-opt-w-instrs"

Definition at line 45 of file RISCVOptWInstrs.cpp.

RISCV_OPT_W_INSTRS_NAME

#define RISCV_OPT_W_INSTRS_NAME   "RISC-V Optimize W Instructions"

Definition at line 46 of file RISCVOptWInstrs.cpp.

Referenced by INITIALIZE_PASS().

Function Documentation

getWOp()

unsigned getWOp ( unsigned Opcode )

static

Definition at line 679 of file RISCVOptWInstrs.cpp.

References llvm_unreachable.

hasAllNBitUsers()

bool hasAllNBitUsers ( const MachineInstr & OrigMI, const RISCVSubtarget & ST, const MachineRegisterInfo & MRI, unsigned OrigBits )

static

Definition at line 120 of file RISCVOptWInstrs.cpp.

References llvm::alignDown(), llvm::bit_width(), llvm::SmallVectorImpl< T >::emplace_back(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::SmallSet< T, N, C >::insert(), llvm::Register::isVirtual(), llvm::Log2_32(), MI, MRI, OpIdx, P, llvm::SmallVectorImpl< T >::pop_back_val(), and vectorPseudoHasAllNBitUsers().

Referenced by hasAllWUsers().

hasAllWUsers()

bool hasAllWUsers ( const MachineInstr & OrigMI, const RISCVSubtarget & ST, const MachineRegisterInfo & MRI )

static

Definition at line 374 of file RISCVOptWInstrs.cpp.

References hasAllNBitUsers(), and MRI.

Referenced by isSignExtendedW().

INITIALIZE_PASS()

INITIALIZE_PASS	(	RISCVOptWInstrs	,
		DEBUG_TYPE	,
		RISCV_OPT_W_INSTRS_NAME	,
		false	,
		false	)

Definition at line 87 of file RISCVOptWInstrs.cpp.

References llvm::createRISCVOptWInstrsPass(), DEBUG_TYPE, and RISCV_OPT_W_INSTRS_NAME.

isSignExtendedW()

bool isSignExtendedW ( Register SrcReg, const RISCVSubtarget & ST, const MachineRegisterInfo & MRI, SmallPtrSetImpl< MachineInstr * > & FixableDef )

static

Definition at line 435 of file RISCVOptWInstrs.cpp.

References assert(), B(), llvm::BitWidth, D(), llvm::dyn_cast(), llvm::dyn_cast_if_present(), E(), llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::MachineFunction::front(), llvm::MachineOperand::getGlobal(), llvm::MachineFunction::getInfo(), llvm::MachineInstr::getOperand(), llvm::MachineFunction::getRegInfo(), hasAllWUsers(), I, II, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SmallSet< T, N, C >::insert(), llvm::MachineInstr::isCall(), llvm::MachineOperand::isGlobal(), llvm::isInt(), llvm::MachineRegisterInfo::isLiveIn(), llvm::RISCVMachineFunctionInfo::isSExt32Register(), isSignExtendingOpW(), llvm::Register::isVirtual(), MBB, MI, MRI, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), Reg, and llvm::SignExtend64().

isSignExtendingOpW()

bool isSignExtendingOpW ( const MachineInstr & MI, unsigned OpNo )

static

Definition at line 381 of file RISCVOptWInstrs.cpp.

References assert(), llvm::RISCVII::IsSignExtendingOpWMask, llvm::isUInt(), and MI.

Referenced by isSignExtendedW().

STATISTIC() [1/3]

STATISTIC	(	NumRemovedSExtW	,
		"Number of removed sign-extensions"	)

STATISTIC() [2/3]

STATISTIC	(	NumTransformedToNonWInstrs	,
		"Number of instructions transformed to non-W-ops"	)

STATISTIC() [3/3]

STATISTIC	(	NumTransformedToWInstrs	,
		"Number of instructions transformed to W-ops"	)

vectorPseudoHasAllNBitUsers()

bool vectorPseudoHasAllNBitUsers ( const MachineOperand & UserOp, unsigned Bits )

static

Definition at line 94 of file RISCVOptWInstrs.cpp.

References assert(), llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), llvm::RISCV::getRVVMCOpcode(), llvm::RISCVII::getSEWOpNum(), llvm::RISCV::getVectorLowDemandedScalarBits(), llvm::RISCVII::getVLOpNum(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVLOp(), and MI.

Referenced by hasAllNBitUsers().

Variable Documentation

DisableSExtWRemoval

cl::opt< bool > DisableSExtWRemoval("riscv-disable-sextw-removal", cl::desc("Disable removal of sext.w"), cl::init(false), cl::Hidden) ( "riscv-disable-sextw-removal" , cl::desc("Disable removal of sext.w") , cl::init(false) , cl::Hidden  )

static

DisableStripWSuffix

cl::opt< bool > DisableStripWSuffix("riscv-disable-strip-w-suffix", cl::desc("Disable strip W suffix"), cl::init(false), cl::Hidden) ( "riscv-disable-strip-w-suffix" , cl::desc("Disable strip W suffix") , cl::init(false) , cl::Hidden  )

static