Go to the source code of this file.
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| STATISTIC (NumRemovedSExtW, "Number of removed sign-extensions") |
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| STATISTIC (NumTransformedToWInstrs, "Number of instructions transformed to W-ops") |
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| INITIALIZE_PASS (RISCVOptWInstrs, DEBUG_TYPE, RISCV_OPT_W_INSTRS_NAME, false, false) FunctionPass *llvm |
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static bool | hasAllNBitUsers (const MachineInstr &OrigMI, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI, unsigned OrigBits) |
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static bool | hasAllWUsers (const MachineInstr &OrigMI, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI) |
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static bool | isSignExtendingOpW (const MachineInstr &MI, const MachineRegisterInfo &MRI) |
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static bool | isSignExtendedW (Register SrcReg, const RISCVSubtarget &ST, const MachineRegisterInfo &MRI, SmallPtrSetImpl< MachineInstr * > &FixableDef) |
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static unsigned | getWOp (unsigned Opcode) |
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◆ DEBUG_TYPE
#define DEBUG_TYPE "riscv-opt-w-instrs" |
◆ RISCV_OPT_W_INSTRS_NAME
#define RISCV_OPT_W_INSTRS_NAME "RISC-V Optimize W Instructions" |
◆ getWOp()
◆ hasAllNBitUsers()
Definition at line 83 of file RISCVOptWInstrs.cpp.
References llvm::bit_width(), llvm::SmallVectorBase< Size_T >::empty(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::SmallSet< T, N, C >::insert(), llvm::Log2_32(), MI, MRI, P, llvm::SmallVectorImpl< T >::pop_back_val(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by hasAllWUsers().
◆ hasAllWUsers()
◆ INITIALIZE_PASS()
◆ isSignExtendedW()
Definition at line 341 of file RISCVOptWInstrs.cpp.
References B, llvm::BitWidth, D, E, llvm::SmallVectorBase< Size_T >::empty(), llvm::MachineFunction::front(), llvm::MachineOperand::getGlobal(), llvm::MachineFunction::getInfo(), getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineFunction::getRegInfo(), hasAllWUsers(), I, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::MachineBasicBlock::instr_begin(), llvm::MachineInstr::isCall(), llvm::MachineOperand::isGlobal(), llvm::MachineRegisterInfo::isLiveIn(), llvm::RISCVMachineFunctionInfo::isSExt32Register(), isSignExtendingOpW(), llvm::Register::isVirtual(), MBB, MI, MRI, llvm::SmallVectorImpl< T >::pop_back_val(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().
◆ isSignExtendingOpW()
◆ STATISTIC() [1/2]
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NumRemovedSExtW |
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"Number of removed sign-extensions" |
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◆ STATISTIC() [2/2]
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NumTransformedToWInstrs |
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"Number of instructions transformed to W-ops" |
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◆ DisableSExtWRemoval
cl::opt< bool > DisableSExtWRemoval("riscv-disable-sextw-removal", cl::desc("Disable removal of sext.w"), cl::init(false), cl::Hidden) |
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"riscv-disable-sextw-removal" |
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cl::desc("Disable removal of sext.w") |
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cl::init(false) |
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cl::Hidden |
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◆ DisableStripWSuffix
cl::opt< bool > DisableStripWSuffix("riscv-disable-strip-w-suffix", cl::desc("Disable strip W suffix"), cl::init(false), cl::Hidden) |
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"riscv-disable-strip-w-suffix" |
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cl::desc("Disable strip W suffix") |
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cl::init(false) |
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cl::Hidden |
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