LLVM 22.0.0git
RISCVVLOptimizer.cpp File Reference

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "riscv-vl-optimizer"
#define PASS_NAME   "RISC-V VL Optimizer"
#define VSEG_CASES(Prefix, EEW)
#define VSSEG_CASES(EEW)
#define VSSSEG_CASES(EEW)
#define VSUXSEG_CASES(EEW)
#define VSOXSEG_CASES(EEW)

Functions

static LLVM_ATTRIBUTE_UNUSED raw_ostreamoperator<< (raw_ostream &OS, const OperandInfo &OI)
static LLVM_ATTRIBUTE_UNUSED raw_ostreamoperator<< (raw_ostream &OS, const std::optional< OperandInfo > &OI)
static std::pair< unsigned, boolgetEMULEqualsEEWDivSEWTimesLMUL (unsigned Log2EEW, const MachineInstr &MI)
 Return EMUL = (EEW / SEW) * LMUL where EEW comes from Log2EEW and LMUL and SEW are from the TSFlags of MI.
static unsigned getIntegerExtensionOperandEEW (unsigned Factor, const MachineInstr &MI, const MachineOperand &MO)
 Dest has EEW=SEW.
static std::optional< unsignedgetOperandLog2EEW (const MachineOperand &MO)
static std::optional< OperandInfo > getOperandInfo (const MachineOperand &MO)
static bool isTupleInsertInstr (const MachineInstr &MI)
 Return true if MI is an instruction used for assembling registers for segmented store instructions, namely, RISCVISD::TUPLE_INSERT.
static bool isSupportedInstr (const MachineInstr &MI)
 Return true if this optimization should consider MI for VL reduction.
static bool isVectorOpUsedAsScalarOp (const MachineOperand &MO)
 Return true if MO is a vector operand but is used as a scalar operand.
static bool isSegmentedStoreInstr (const MachineInstr &MI)
static bool isPhysical (const MachineOperand &MO)

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "riscv-vl-optimizer"

Definition at line 38 of file RISCVVLOptimizer.cpp.

◆ PASS_NAME

#define PASS_NAME   "RISC-V VL Optimizer"

Definition at line 39 of file RISCVVLOptimizer.cpp.

◆ VSEG_CASES

#define VSEG_CASES ( Prefix,
EEW )
Value:
RISCV::Prefix##SEG2E##EEW##_V: \
case RISCV::Prefix##SEG3E##EEW##_V: \
case RISCV::Prefix##SEG4E##EEW##_V: \
case RISCV::Prefix##SEG5E##EEW##_V: \
case RISCV::Prefix##SEG6E##EEW##_V: \
case RISCV::Prefix##SEG7E##EEW##_V: \
case RISCV::Prefix##SEG8E##EEW##_V

Definition at line 220 of file RISCVVLOptimizer.cpp.

◆ VSOXSEG_CASES

#define VSOXSEG_CASES ( EEW)
Value:
VSEG_CASES(VSOX, I##EEW)
#define I(x, y, z)
Definition MD5.cpp:58
#define VSEG_CASES(Prefix, EEW)

Definition at line 231 of file RISCVVLOptimizer.cpp.

Referenced by getOperandLog2EEW(), and isSegmentedStoreInstr().

◆ VSSEG_CASES

#define VSSEG_CASES ( EEW)
Value:
VSEG_CASES(VS, EEW)

Definition at line 228 of file RISCVVLOptimizer.cpp.

Referenced by getOperandLog2EEW(), and isSegmentedStoreInstr().

◆ VSSSEG_CASES

#define VSSSEG_CASES ( EEW)
Value:
VSEG_CASES(VSS, EEW)

Definition at line 229 of file RISCVVLOptimizer.cpp.

Referenced by getOperandLog2EEW(), and isSegmentedStoreInstr().

◆ VSUXSEG_CASES

#define VSUXSEG_CASES ( EEW)
Value:
VSEG_CASES(VSUX, I##EEW)

Definition at line 230 of file RISCVVLOptimizer.cpp.

Referenced by getOperandLog2EEW(), and isSegmentedStoreInstr().

Function Documentation

◆ getEMULEqualsEEWDivSEWTimesLMUL()

std::pair< unsigned, bool > getEMULEqualsEEWDivSEWTimesLMUL ( unsigned Log2EEW,
const MachineInstr & MI )
static

Return EMUL = (EEW / SEW) * LMUL where EEW comes from Log2EEW and LMUL and SEW are from the TSFlags of MI.

Definition at line 178 of file RISCVVLOptimizer.cpp.

References llvm::RISCVVType::decodeVLMUL(), llvm::RISCVII::getLMul(), llvm::RISCVII::getSEWOpNum(), and MI.

Referenced by getOperandInfo().

◆ getIntegerExtensionOperandEEW()

unsigned getIntegerExtensionOperandEEW ( unsigned Factor,
const MachineInstr & MI,
const MachineOperand & MO )
static

Dest has EEW=SEW.

Source EEW=SEW/Factor (i.e. F2 => EEW/2). SEW comes from TSFlags of MI.

Definition at line 204 of file RISCVVLOptimizer.cpp.

References llvm::MachineOperand::getOperandNo(), llvm::RISCVII::getSEWOpNum(), llvm::Log2_32(), and MI.

Referenced by getOperandLog2EEW().

◆ getOperandInfo()

◆ getOperandLog2EEW()

◆ isPhysical()

◆ isSegmentedStoreInstr()

bool isSegmentedStoreInstr ( const MachineInstr & MI)
static

◆ isSupportedInstr()

bool isSupportedInstr ( const MachineInstr & MI)
static

Return true if this optimization should consider MI for VL reduction.

This white-list approach simplifies this optimization for instructions that may have more complex semantics with relation to how it uses VL.

Definition at line 894 of file RISCVVLOptimizer.cpp.

References isTupleInsertInstr(), MI, and llvm::RVV.

◆ isTupleInsertInstr()

bool isTupleInsertInstr ( const MachineInstr & MI)
static

Return true if MI is an instruction used for assembling registers for segmented store instructions, namely, RISCVISD::TUPLE_INSERT.

Currently it's lowered to INSERT_SUBREG.

Definition at line 1451 of file RISCVVLOptimizer.cpp.

References assert(), llvm::RISCVVType::decodeVLMUL(), llvm::RISCVRI::getLMul(), llvm::RISCVRI::getNF(), llvm::RISCVRI::isVRegClass(), MI, MRI, llvm::RISCV::RVVBitsPerBlock, TRI, and llvm::TargetRegisterClass::TSFlags.

Referenced by isSupportedInstr().

◆ isVectorOpUsedAsScalarOp()

bool isVectorOpUsedAsScalarOp ( const MachineOperand & MO)
static

Return true if MO is a vector operand but is used as a scalar operand.

Definition at line 1303 of file RISCVVLOptimizer.cpp.

References llvm::MachineOperand::getOperandNo(), llvm::MachineOperand::getParent(), MI, and llvm::RVV.

◆ operator<<() [1/2]

LLVM_ATTRIBUTE_UNUSED raw_ostream & operator<< ( raw_ostream & OS,
const OperandInfo & OI )
static

Definition at line 160 of file RISCVVLOptimizer.cpp.

◆ operator<<() [2/2]

LLVM_ATTRIBUTE_UNUSED raw_ostream & operator<< ( raw_ostream & OS,
const std::optional< OperandInfo > & OI )
static

Definition at line 166 of file RISCVVLOptimizer.cpp.