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SparcISelLowering.h
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1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that Sparc uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
15 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H
16 
17 #include "Sparc.h"
19 
20 namespace llvm {
21  class SparcSubtarget;
22 
23  namespace SPISD {
24  enum NodeType : unsigned {
26  CMPICC, // Compare two GPR operands, set icc+xcc.
27  CMPFCC, // Compare two FP operands, set fcc.
28  BRICC, // Branch to dest on icc condition
29  BRXCC, // Branch to dest on xcc condition (64-bit only).
30  BRFCC, // Branch to dest on fcc condition
31  SELECT_ICC, // Select between two values using the current ICC flags.
32  SELECT_XCC, // Select between two values using the current XCC flags.
33  SELECT_FCC, // Select between two values using the current FCC flags.
34 
35  Hi, Lo, // Hi/Lo operations, typically on a global address.
36 
37  FTOI, // FP to Int within a FP register.
38  ITOF, // Int to FP within a FP register.
39  FTOX, // FP to Int64 within a FP register.
40  XTOF, // Int64 to FP within a FP register.
41 
42  CALL, // A call instruction.
43  RET_FLAG, // Return with a flag operand.
44  GLOBAL_BASE_REG, // Global base reg for PIC.
45  FLUSHW, // FLUSH register windows to stack.
46 
47  TAIL_CALL, // Tail call
48 
49  TLS_ADD, // For Thread Local Storage (TLS).
52  };
53  }
54 
56  const SparcSubtarget *Subtarget;
57  public:
59  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
60 
61  bool useSoftFloat() const override;
62 
63  /// computeKnownBitsForTargetNode - Determine which of the bits specified
64  /// in Mask are known to be either zero or one and return them in the
65  /// KnownZero/KnownOne bitsets.
67  KnownBits &Known,
68  const APInt &DemandedElts,
69  const SelectionDAG &DAG,
70  unsigned Depth = 0) const override;
71 
74  MachineBasicBlock *MBB) const override;
75 
76  const char *getTargetNodeName(unsigned Opcode) const override;
77 
78  ConstraintType getConstraintType(StringRef Constraint) const override;
81  const char *constraint) const override;
83  std::string &Constraint,
84  std::vector<SDValue> &Ops,
85  SelectionDAG &DAG) const override;
86 
87  std::pair<unsigned, const TargetRegisterClass *>
89  StringRef Constraint, MVT VT) const override;
90 
91  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
92  MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
93  return MVT::i32;
94  }
95 
96  Register getRegisterByName(const char* RegName, LLT VT,
97  const MachineFunction &MF) const override;
98 
99  /// If a physical register, this returns the register that receives the
100  /// exception address on entry to an EH pad.
101  Register
102  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
103  return SP::I0;
104  }
105 
106  /// If a physical register, this returns the register that receives the
107  /// exception typeid on entry to a landing pad.
108  Register
109  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
110  return SP::I1;
111  }
112 
113  /// Override to support customized stack guard loading.
114  bool useLoadStackGuardNode() const override;
115  void insertSSPDeclarations(Module &M) const override;
116 
117  /// getSetCCResultType - Return the ISD::SETCC ValueType
119  EVT VT) const override;
120 
121  SDValue
122  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
124  const SDLoc &dl, SelectionDAG &DAG,
125  SmallVectorImpl<SDValue> &InVals) const override;
127  bool isVarArg,
129  const SDLoc &dl, SelectionDAG &DAG,
130  SmallVectorImpl<SDValue> &InVals) const;
132  bool isVarArg,
134  const SDLoc &dl, SelectionDAG &DAG,
135  SmallVectorImpl<SDValue> &InVals) const;
136 
137  SDValue
139  SmallVectorImpl<SDValue> &InVals) const override;
141  SmallVectorImpl<SDValue> &InVals) const;
143  SmallVectorImpl<SDValue> &InVals) const;
144 
145  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
147  const SmallVectorImpl<SDValue> &OutVals,
148  const SDLoc &dl, SelectionDAG &DAG) const override;
150  bool IsVarArg,
152  const SmallVectorImpl<SDValue> &OutVals,
153  const SDLoc &DL, SelectionDAG &DAG) const;
155  bool IsVarArg,
157  const SmallVectorImpl<SDValue> &OutVals,
158  const SDLoc &DL, SelectionDAG &DAG) const;
159 
164 
165  SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const;
166  SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF,
167  SelectionDAG &DAG) const;
169 
171  const SDLoc &DL, SelectionDAG &DAG) const;
173  const char *LibFuncName,
174  unsigned numArgs) const;
175  SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC,
176  const SDLoc &DL, SelectionDAG &DAG) const;
177 
179 
180  SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const;
181 
183  SelectionDAG &DAG) const;
184 
185  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
186 
188  CallLoweringInfo &CLI,
189  MachineFunction &MF) const;
190 
191  bool ShouldShrinkFPConstant(EVT VT) const override {
192  // Do not shrink FP constpool if VT == MVT::f128.
193  // (ldd, call _Q_fdtoq) is more expensive than two ldds.
194  return VT != MVT::f128;
195  }
196 
197  bool shouldInsertFencesForAtomic(const Instruction *I) const override {
198  // FIXME: We insert fences for each atomics and generate
199  // sub-optimal code for PSO/TSO. (Approximately nobody uses any
200  // mode but TSO, which makes this even more silly)
201  return true;
202  }
203 
205 
208  SelectionDAG &DAG) const override;
209 
211  unsigned BROpcode) const;
212  };
213 } // end namespace llvm
214 
215 #endif // SPARC_ISELLOWERING_H
llvm::SPISD::GLOBAL_BASE_REG
@ GLOBAL_BASE_REG
Definition: SparcISelLowering.h:44
llvm::SPISD::TLS_ADD
@ TLS_ADD
Definition: SparcISelLowering.h:49
llvm::SPISD::ITOF
@ ITOF
Definition: SparcISelLowering.h:38
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1090
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::SparcTargetLowering::LowerConstantPool
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Definition: SparcISelLowering.cpp:2064
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4395
llvm::SparcTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: SparcISelLowering.cpp:3404
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:189
llvm::SparcTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: SparcISelLowering.cpp:1064
llvm::SparcTargetLowering::useLoadStackGuardNode
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
Definition: SparcISelLowering.cpp:3485
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
llvm::SparcTargetLowering::LowerINTRINSIC_WO_CHAIN
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
Definition: SparcISelLowering.cpp:3059
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::SparcTargetLowering::LowerF128_LibCallArg
SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg, const SDLoc &DL, SelectionDAG &DAG) const
Definition: SparcISelLowering.cpp:2179
llvm::SparcTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: SparcISelLowering.h:102
llvm::SparcTargetLowering::LowerReturn_32
SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const
Definition: SparcISelLowering.cpp:206
llvm::SPISD::BRXCC
@ BRXCC
Definition: SparcISelLowering.h:29
llvm::SparcTargetLowering
Definition: SparcISelLowering.h:55
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:848
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1620
llvm::SparcTargetLowering::EmitInstrWithCustomInserter
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
Definition: SparcISelLowering.cpp:3169
llvm::SPISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: SparcISelLowering.h:25
I1
@ I1
Definition: DXILOpLowering.cpp:37
llvm::SPISD::BRFCC
@ BRFCC
Definition: SparcISelLowering.h:30
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::SPISD::FLUSHW
@ FLUSHW
Definition: SparcISelLowering.h:45
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:186
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
TargetLowering.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::SPISD::Hi
@ Hi
Definition: SparcISelLowering.h:35
llvm::SparcTargetLowering::LowerReturn_64
SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const
Definition: SparcISelLowering.cpp:291
llvm::SparcTargetLowering::LowerFormalArguments_64
SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
Definition: SparcISelLowering.cpp:576
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3395
llvm::SparcTargetLowering::makeAddress
SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const
Definition: SparcISelLowering.cpp:2000
llvm::SparcTargetLowering::SparcTargetLowering
SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI)
Definition: SparcISelLowering.cpp:1454
llvm::SparcTargetLowering::bitcastConstantFPToInt
SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL, SelectionDAG &DAG) const
Definition: SparcISelLowering.cpp:3134
llvm::SPISD::FTOX
@ FTOX
Definition: SparcISelLowering.h:39
llvm::SparcTargetLowering::LowerCall_32
SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
Definition: SparcISelLowering.cpp:745
llvm::Instruction
Definition: Instruction.h:42
llvm::SparcSubtarget
Definition: SparcSubtarget.h:31
llvm::SPISD::RET_FLAG
@ RET_FLAG
Definition: SparcISelLowering.h:43
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::SPISD::CMPFCC
@ CMPFCC
Definition: SparcISelLowering.h:27
llvm::SparcTargetLowering::getScalarShiftAmountTy
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
Definition: SparcISelLowering.h:92
llvm::SparcTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: SparcISelLowering.cpp:1878
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::SPISD::SELECT_ICC
@ SELECT_ICC
Definition: SparcISelLowering.h:31
llvm::SparcTargetLowering::PerformBITCASTCombine
SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const
Definition: SparcISelLowering.cpp:3145
llvm::SparcTargetLowering::computeKnownBitsForTargetNode
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
computeKnownBitsForTargetNode - Determine which of the bits specified in Mask are known to be either ...
Definition: SparcISelLowering.cpp:1918
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::ConstantFPSDNode
Definition: SelectionDAGNodes.h:1613
llvm::SPISD::XTOF
@ XTOF
Definition: SparcISelLowering.h:40
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::SPISD::TLS_LD
@ TLS_LD
Definition: SparcISelLowering.h:50
llvm::SparcTargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: SparcISelLowering.cpp:685
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetLowering::AsmOperandInfo
This contains information for each constraint that we are lowering.
Definition: TargetLowering.h:4422
llvm::SparcTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: SparcISelLowering.cpp:3157
llvm::SparcTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: SparcISelLowering.cpp:367
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3985
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::SPISD::TAIL_CALL
@ TAIL_CALL
Definition: SparcISelLowering.h:47
llvm::SPISD::BRICC
@ BRICC
Definition: SparcISelLowering.h:28
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
info
lazy value info
Definition: LazyValueInfo.cpp:58
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::SparcTargetLowering::shouldExpandAtomicRMWInIR
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: SparcISelLowering.cpp:1400
llvm::SparcTargetLowering::useSoftFloat
bool useSoftFloat() const override
Definition: SparcISelLowering.cpp:1874
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::SparcTargetLowering::insertSSPDeclarations
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
Definition: SparcISelLowering.cpp:3492
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1287
llvm::SparcTargetLowering::getRegForInlineAsmConstraint
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Definition: SparcISelLowering.cpp:3330
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:727
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:312
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::SPISD::CMPICC
@ CMPICC
Definition: SparcISelLowering.h:26
llvm::SPISD::Lo
@ Lo
Definition: SparcISelLowering.h:35
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1734
llvm::KnownBits
Definition: KnownBits.h:23
llvm::SparcTargetLowering::getConstraintType
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
Definition: SparcISelLowering.cpp:3254
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:249
llvm::SparcTargetLowering::withTargetFlags
SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const
Definition: SparcISelLowering.cpp:1961
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:344
llvm::SparcTargetLowering::LowerF128Op
SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, const char *LibFuncName, unsigned numArgs) const
Definition: SparcISelLowering.cpp:2206
llvm::SparcTargetLowering::shouldInsertFencesForAtomic
bool shouldInsertFencesForAtomic(const Instruction *I) const override
Whether AtomicExpandPass should automatically insert fences and reduce ordering for this atomic.
Definition: SparcISelLowering.h:197
Sparc.h
llvm::TargetLowering::ConstraintWeight
ConstraintWeight
Definition: TargetLowering.h:4405
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:137
llvm::SparcTargetLowering::LowerBlockAddress
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
Definition: SparcISelLowering.cpp:2069
llvm::SparcTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: SparcISelLowering.cpp:3073
llvm::SPISD::SELECT_XCC
@ SELECT_XCC
Definition: SparcISelLowering.h:32
llvm::SparcTargetLowering::expandSelectCC
MachineBasicBlock * expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, unsigned BROpcode) const
Definition: SparcISelLowering.cpp:3192
llvm::SparcTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: SparcISelLowering.h:109
llvm::SparcTargetLowering::LowerF128Compare
SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC, const SDLoc &DL, SelectionDAG &DAG) const
Definition: SparcISelLowering.cpp:2260
llvm::SparcTargetLowering::LowerCall_64
SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const
Definition: SparcISelLowering.cpp:1138
llvm::MVT::f128
@ f128
Definition: MachineValueType.h:58
N
#define N
llvm::SparcTargetLowering::LowerAsmOperandForConstraint
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
Definition: SparcISelLowering.cpp:3298
llvm::SparcTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
Definition: SparcISelLowering.cpp:1907
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
RegName
#define RegName(no)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SparcTargetLowering::LowerGlobalTLSAddress
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Definition: SparcISelLowering.cpp:2074
llvm::SPISD::SELECT_FCC
@ SELECT_FCC
Definition: SparcISelLowering.h:33
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::SparcTargetLowering::LowerGlobalAddress
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
Definition: SparcISelLowering.cpp:2059
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::SparcTargetLowering::LowerFormalArguments_32
SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const
LowerFormalArguments32 - V8 uses a very simple ABI, where all values are passed in either one or two ...
Definition: SparcISelLowering.cpp:381
llvm::SparcTargetLowering::IsEligibleForTailCallOptimization
bool IsEligibleForTailCallOptimization(CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization.
Definition: SparcISelLowering.cpp:715
llvm::SPISD::FTOI
@ FTOI
Definition: SparcISelLowering.h:37
llvm::SPISD::TLS_CALL
@ TLS_CALL
Definition: SparcISelLowering.h:51
llvm::SPISD::CALL
@ CALL
Definition: SparcISelLowering.h:42
llvm::SparcTargetLowering::makeHiLoPair
SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, SelectionDAG &DAG) const
Definition: SparcISelLowering.cpp:1988
llvm::SparcTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: SparcISelLowering.cpp:195
llvm::SparcTargetLowering::getSingleConstraintMatchWeight
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
Definition: SparcISelLowering.cpp:3271
llvm::SPISD::NodeType
NodeType
Definition: SparcISelLowering.h:24
llvm::SparcTargetLowering::ShouldShrinkFPConstant
bool ShouldShrinkFPConstant(EVT VT) const override
If true, then instruction selection should seek to shrink the FP constant of the specified type to a ...
Definition: SparcISelLowering.h:191
llvm::SparcTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: SparcISelLowering.cpp:3409
llvm::LLT
Definition: LowLevelTypeImpl.h:39