LLVM  13.0.0git
ARMCallLowering.cpp
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1 //===- llvm/lib/Target/ARM/ARMCallLowering.cpp - Call lowering ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "ARMCallLowering.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMISelLowering.h"
18 #include "ARMSubtarget.h"
19 #include "Utils/ARMBaseInfo.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/Analysis.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/Type.h"
41 #include "llvm/IR/Value.h"
42 #include "llvm/Support/Casting.h"
45 #include <algorithm>
46 #include <cassert>
47 #include <cstdint>
48 #include <utility>
49 
50 using namespace llvm;
51 
53  : CallLowering(&TLI) {}
54 
55 static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
56  Type *T) {
57  if (T->isArrayTy())
58  return isSupportedType(DL, TLI, T->getArrayElementType());
59 
60  if (T->isStructTy()) {
61  // For now we only allow homogeneous structs that we can manipulate with
62  // G_MERGE_VALUES and G_UNMERGE_VALUES
63  auto StructT = cast<StructType>(T);
64  for (unsigned i = 1, e = StructT->getNumElements(); i != e; ++i)
65  if (StructT->getElementType(i) != StructT->getElementType(0))
66  return false;
67  return isSupportedType(DL, TLI, StructT->getElementType(0));
68  }
69 
70  EVT VT = TLI.getValueType(DL, T, true);
71  if (!VT.isSimple() || VT.isVector() ||
72  !(VT.isInteger() || VT.isFloatingPoint()))
73  return false;
74 
75  unsigned VTSize = VT.getSimpleVT().getSizeInBits();
76 
77  if (VTSize == 64)
78  // FIXME: Support i64 too
79  return VT.isFloatingPoint();
80 
81  return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
82 }
83 
84 namespace {
85 
86 /// Helper class for values going out through an ABI boundary (used for handling
87 /// function return values and call parameters).
88 struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
89  ARMOutgoingValueHandler(MachineIRBuilder &MIRBuilder,
91  CCAssignFn *AssignFn)
92  : OutgoingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
93 
94  Register getStackAddress(uint64_t Size, int64_t Offset,
95  MachinePointerInfo &MPO,
96  ISD::ArgFlagsTy Flags) override {
97  assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
98  "Unsupported size");
99 
100  LLT p0 = LLT::pointer(0, 32);
101  LLT s32 = LLT::scalar(32);
102  auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP));
103 
104  auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
105 
106  auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
107 
108  MPO = MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
109  return AddrReg.getReg(0);
110  }
111 
112  void assignValueToReg(Register ValVReg, Register PhysReg,
113  CCValAssign &VA) override {
114  assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
115  assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
116 
117  assert(VA.getValVT().getSizeInBits() <= 64 && "Unsupported value size");
118  assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size");
119 
120  Register ExtReg = extendRegister(ValVReg, VA);
121  MIRBuilder.buildCopy(PhysReg, ExtReg);
122  MIB.addUse(PhysReg, RegState::Implicit);
123  }
124 
125  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
126  MachinePointerInfo &MPO, CCValAssign &VA) override {
127  assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
128  "Unsupported size");
129 
130  Register ExtReg = extendRegister(ValVReg, VA);
131  auto MMO = MIRBuilder.getMF().getMachineMemOperand(
133  Align(1));
134  MIRBuilder.buildStore(ExtReg, Addr, *MMO);
135  }
136 
137  unsigned assignCustomValue(const CallLowering::ArgInfo &Arg,
138  ArrayRef<CCValAssign> VAs) override {
139  assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
140 
141  CCValAssign VA = VAs[0];
142  assert(VA.needsCustom() && "Value doesn't need custom handling");
143 
144  // Custom lowering for other types, such as f16, is currently not supported
145  if (VA.getValVT() != MVT::f64)
146  return 0;
147 
148  CCValAssign NextVA = VAs[1];
149  assert(NextVA.needsCustom() && "Value doesn't need custom handling");
150  assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
151 
152  assert(VA.getValNo() == NextVA.getValNo() &&
153  "Values belong to different arguments");
154 
155  assert(VA.isRegLoc() && "Value should be in reg");
156  assert(NextVA.isRegLoc() && "Value should be in reg");
157 
160  MIRBuilder.buildUnmerge(NewRegs, Arg.Regs[0]);
161 
162  bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
163  if (!IsLittle)
164  std::swap(NewRegs[0], NewRegs[1]);
165 
166  assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
167  assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
168 
169  return 1;
170  }
171 
172  bool assignArg(unsigned ValNo, MVT ValVT, MVT LocVT,
173  CCValAssign::LocInfo LocInfo,
175  CCState &State) override {
176  if (AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State))
177  return true;
178 
179  StackSize =
180  std::max(StackSize, static_cast<uint64_t>(State.getNextStackOffset()));
181  return false;
182  }
183 
184  MachineInstrBuilder &MIB;
185  uint64_t StackSize = 0;
186 };
187 
188 } // end anonymous namespace
189 
190 /// Lower the return value for the already existing \p Ret. This assumes that
191 /// \p MIRBuilder's insertion point is correct.
192 bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
193  const Value *Val, ArrayRef<Register> VRegs,
194  MachineInstrBuilder &Ret) const {
195  if (!Val)
196  // Nothing to do here.
197  return true;
198 
199  auto &MF = MIRBuilder.getMF();
200  const auto &F = MF.getFunction();
201 
202  const auto &DL = MF.getDataLayout();
203  auto &TLI = *getTLI<ARMTargetLowering>();
204  if (!isSupportedType(DL, TLI, Val->getType()))
205  return false;
206 
207  ArgInfo OrigRetInfo(VRegs, Val->getType());
208  setArgFlags(OrigRetInfo, AttributeList::ReturnIndex, DL, F);
209 
210  SmallVector<ArgInfo, 4> SplitRetInfos;
211  splitToValueTypes(OrigRetInfo, SplitRetInfos, DL, F.getCallingConv());
212 
213  CCAssignFn *AssignFn =
214  TLI.CCAssignFnForReturn(F.getCallingConv(), F.isVarArg());
215 
216  ARMOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret,
217  AssignFn);
218  return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler,
219  F.getCallingConv(), F.isVarArg());
220 }
221 
223  const Value *Val, ArrayRef<Register> VRegs,
224  FunctionLoweringInfo &FLI) const {
225  assert(!Val == VRegs.empty() && "Return value without a vreg");
226 
227  auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
228  unsigned Opcode = ST.getReturnOpcode();
229  auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
230 
231  if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
232  return false;
233 
234  MIRBuilder.insertInstr(Ret);
235  return true;
236 }
237 
238 namespace {
239 
240 /// Helper class for values coming in through an ABI boundary (used for handling
241 /// formal arguments and call return values).
242 struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
243  ARMIncomingValueHandler(MachineIRBuilder &MIRBuilder,
245  : IncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
246 
247  Register getStackAddress(uint64_t Size, int64_t Offset,
248  MachinePointerInfo &MPO,
249  ISD::ArgFlagsTy Flags) override {
250  assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
251  "Unsupported size");
252 
253  auto &MFI = MIRBuilder.getMF().getFrameInfo();
254 
255  // Byval is assumed to be writable memory, but other stack passed arguments
256  // are not.
257  const bool IsImmutable = !Flags.isByVal();
258 
259  int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
260  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
261 
262  return MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI)
263  .getReg(0);
264  }
265 
266  void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
267  MachinePointerInfo &MPO, CCValAssign &VA) override {
268  assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
269  "Unsupported size");
270 
271  if (VA.getLocInfo() == CCValAssign::SExt ||
272  VA.getLocInfo() == CCValAssign::ZExt) {
273  // If the value is zero- or sign-extended, its size becomes 4 bytes, so
274  // that's what we should load.
275  Size = 4;
276  assert(MRI.getType(ValVReg).isScalar() && "Only scalars supported atm");
277 
278  auto LoadVReg = buildLoad(LLT::scalar(32), Addr, Size, MPO);
279  MIRBuilder.buildTrunc(ValVReg, LoadVReg);
280  } else {
281  // If the value is not extended, a simple load will suffice.
282  buildLoad(ValVReg, Addr, Size, MPO);
283  }
284  }
285 
286  MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, uint64_t Size,
287  MachinePointerInfo &MPO) {
288  MachineFunction &MF = MIRBuilder.getMF();
289 
291  inferAlignFromPtrInfo(MF, MPO));
292  return MIRBuilder.buildLoad(Res, Addr, *MMO);
293  }
294 
295  void assignValueToReg(Register ValVReg, Register PhysReg,
296  CCValAssign &VA) override {
297  assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
298  assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");
299 
300  uint64_t ValSize = VA.getValVT().getFixedSizeInBits();
301  uint64_t LocSize = VA.getLocVT().getFixedSizeInBits();
302 
303  assert(ValSize <= 64 && "Unsupported value size");
304  assert(LocSize <= 64 && "Unsupported location size");
305 
306  markPhysRegUsed(PhysReg);
307  if (ValSize == LocSize) {
308  MIRBuilder.buildCopy(ValVReg, PhysReg);
309  } else {
310  assert(ValSize < LocSize && "Extensions not supported");
311 
312  // We cannot create a truncating copy, nor a trunc of a physical register.
313  // Therefore, we need to copy the content of the physical register into a
314  // virtual one and then truncate that.
315  auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg);
316  MIRBuilder.buildTrunc(ValVReg, PhysRegToVReg);
317  }
318  }
319 
320  unsigned assignCustomValue(const ARMCallLowering::ArgInfo &Arg,
321  ArrayRef<CCValAssign> VAs) override {
322  assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");
323 
324  CCValAssign VA = VAs[0];
325  assert(VA.needsCustom() && "Value doesn't need custom handling");
326 
327  // Custom lowering for other types, such as f16, is currently not supported
328  if (VA.getValVT() != MVT::f64)
329  return 0;
330 
331  CCValAssign NextVA = VAs[1];
332  assert(NextVA.needsCustom() && "Value doesn't need custom handling");
333  assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");
334 
335  assert(VA.getValNo() == NextVA.getValNo() &&
336  "Values belong to different arguments");
337 
338  assert(VA.isRegLoc() && "Value should be in reg");
339  assert(NextVA.isRegLoc() && "Value should be in reg");
340 
343 
344  assignValueToReg(NewRegs[0], VA.getLocReg(), VA);
345  assignValueToReg(NewRegs[1], NextVA.getLocReg(), NextVA);
346 
347  bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle();
348  if (!IsLittle)
349  std::swap(NewRegs[0], NewRegs[1]);
350 
351  MIRBuilder.buildMerge(Arg.Regs[0], NewRegs);
352 
353  return 1;
354  }
355 
356  /// Marking a physical register as used is different between formal
357  /// parameters, where it's a basic block live-in, and call returns, where it's
358  /// an implicit-def of the call instruction.
359  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
360 };
361 
362 struct FormalArgHandler : public ARMIncomingValueHandler {
363  FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
364  CCAssignFn AssignFn)
365  : ARMIncomingValueHandler(MIRBuilder, MRI, AssignFn) {}
366 
367  void markPhysRegUsed(unsigned PhysReg) override {
368  MIRBuilder.getMRI()->addLiveIn(PhysReg);
369  MIRBuilder.getMBB().addLiveIn(PhysReg);
370  }
371 };
372 
373 } // end anonymous namespace
374 
376  const Function &F,
378  FunctionLoweringInfo &FLI) const {
379  auto &TLI = *getTLI<ARMTargetLowering>();
380  auto Subtarget = TLI.getSubtarget();
381 
382  if (Subtarget->isThumb1Only())
383  return false;
384 
385  // Quick exit if there aren't any args
386  if (F.arg_empty())
387  return true;
388 
389  if (F.isVarArg())
390  return false;
391 
392  auto &MF = MIRBuilder.getMF();
393  auto &MBB = MIRBuilder.getMBB();
394  const auto &DL = MF.getDataLayout();
395 
396  for (auto &Arg : F.args()) {
397  if (!isSupportedType(DL, TLI, Arg.getType()))
398  return false;
399  if (Arg.hasPassPointeeByValueCopyAttr())
400  return false;
401  }
402 
403  CCAssignFn *AssignFn =
404  TLI.CCAssignFnForCall(F.getCallingConv(), F.isVarArg());
405 
406  FormalArgHandler ArgHandler(MIRBuilder, MIRBuilder.getMF().getRegInfo(),
407  AssignFn);
408 
409  SmallVector<ArgInfo, 8> SplitArgInfos;
410  unsigned Idx = 0;
411  for (auto &Arg : F.args()) {
412  ArgInfo OrigArgInfo(VRegs[Idx], Arg.getType());
413 
414  setArgFlags(OrigArgInfo, Idx + AttributeList::FirstArgIndex, DL, F);
415  splitToValueTypes(OrigArgInfo, SplitArgInfos, DL, F.getCallingConv());
416 
417  Idx++;
418  }
419 
420  if (!MBB.empty())
421  MIRBuilder.setInstr(*MBB.begin());
422 
423  if (!handleAssignments(MIRBuilder, SplitArgInfos, ArgHandler,
424  F.getCallingConv(), F.isVarArg()))
425  return false;
426 
427  // Move back to the end of the basic block.
428  MIRBuilder.setMBB(MBB);
429  return true;
430 }
431 
432 namespace {
433 
434 struct CallReturnHandler : public ARMIncomingValueHandler {
435  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
436  MachineInstrBuilder MIB, CCAssignFn *AssignFn)
437  : ARMIncomingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
438 
439  void markPhysRegUsed(unsigned PhysReg) override {
440  MIB.addDef(PhysReg, RegState::Implicit);
441  }
442 
444 };
445 
446 // FIXME: This should move to the ARMSubtarget when it supports all the opcodes.
447 unsigned getCallOpcode(const MachineFunction &MF, const ARMSubtarget &STI,
448  bool isDirect) {
449  if (isDirect)
450  return STI.isThumb() ? ARM::tBL : ARM::BL;
451 
452  if (STI.isThumb())
453  return gettBLXrOpcode(MF);
454 
455  if (STI.hasV5TOps())
456  return getBLXOpcode(MF);
457 
458  if (STI.hasV4TOps())
459  return ARM::BX_CALL;
460 
461  return ARM::BMOVPCRX_CALL;
462 }
463 } // end anonymous namespace
464 
466  MachineFunction &MF = MIRBuilder.getMF();
467  const auto &TLI = *getTLI<ARMTargetLowering>();
468  const auto &DL = MF.getDataLayout();
469  const auto &STI = MF.getSubtarget<ARMSubtarget>();
470  const TargetRegisterInfo *TRI = STI.getRegisterInfo();
472 
473  if (STI.genLongCalls())
474  return false;
475 
476  if (STI.isThumb1Only())
477  return false;
478 
479  auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
480 
481  // Create the call instruction so we can add the implicit uses of arg
482  // registers, but don't insert it yet.
483  bool IsDirect = !Info.Callee.isReg();
484  auto CallOpcode = getCallOpcode(MF, STI, IsDirect);
485  auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode);
486 
487  bool IsThumb = STI.isThumb();
488  if (IsThumb)
489  MIB.add(predOps(ARMCC::AL));
490 
491  MIB.add(Info.Callee);
492  if (!IsDirect) {
493  auto CalleeReg = Info.Callee.getReg();
494  if (CalleeReg && !Register::isPhysicalRegister(CalleeReg)) {
495  unsigned CalleeIdx = IsThumb ? 2 : 0;
496  MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass(
497  MF, *TRI, MRI, *STI.getInstrInfo(), *STI.getRegBankInfo(),
498  *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx));
499  }
500  }
501 
502  MIB.addRegMask(TRI->getCallPreservedMask(MF, Info.CallConv));
503 
504  SmallVector<ArgInfo, 8> ArgInfos;
505  for (auto Arg : Info.OrigArgs) {
506  if (!isSupportedType(DL, TLI, Arg.Ty))
507  return false;
508 
509  if (Arg.Flags[0].isByVal())
510  return false;
511 
512  splitToValueTypes(Arg, ArgInfos, DL, Info.CallConv);
513  }
514 
515  auto ArgAssignFn = TLI.CCAssignFnForCall(Info.CallConv, Info.IsVarArg);
516  ARMOutgoingValueHandler ArgHandler(MIRBuilder, MRI, MIB, ArgAssignFn);
517  if (!handleAssignments(MIRBuilder, ArgInfos, ArgHandler, Info.CallConv,
518  Info.IsVarArg))
519  return false;
520 
521  // Now we can add the actual call instruction to the correct basic block.
522  MIRBuilder.insertInstr(MIB);
523 
524  if (!Info.OrigRet.Ty->isVoidTy()) {
525  if (!isSupportedType(DL, TLI, Info.OrigRet.Ty))
526  return false;
527 
528  ArgInfos.clear();
529  splitToValueTypes(Info.OrigRet, ArgInfos, DL, Info.CallConv);
530  auto RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv, Info.IsVarArg);
531  CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
532  if (!handleAssignments(MIRBuilder, ArgInfos, RetHandler, Info.CallConv,
533  Info.IsVarArg))
534  return false;
535  }
536 
537  // We now know the size of the stack - update the ADJCALLSTACKDOWN
538  // accordingly.
539  CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
540 
541  MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
542  .addImm(ArgHandler.StackSize)
543  .addImm(0)
544  .add(predOps(ARMCC::AL));
545 
546  return true;
547 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:153
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:929
i
i
Definition: README.txt:29
ARMSubtarget.h
llvm::CCValAssign::ZExt
@ ZExt
Definition: CallingConvLower.h:38
ValueTypes.h
LowLevelType.h
llvm::ARMSubtarget::genLongCalls
bool genLongCalls() const
Definition: ARMSubtarget.h:711
llvm::MVT::getStoreSize
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
Definition: MachineValueType.h:1014
llvm::ARMSubtarget::hasV5TOps
bool hasV5TOps() const
Definition: ARMSubtarget.h:597
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:132
llvm
Definition: AllocatorList.h:23
llvm::MVT::getFixedSizeInBits
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
Definition: MachineValueType.h:1000
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
ARMCallLowering.h
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:225
llvm::Function
Definition: Function.h:61
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::MachineIRBuilder::getMRI
MachineRegisterInfo * getMRI()
Getter for MRI.
Definition: MachineIRBuilder.h:288
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:430
MachineBasicBlock.h
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::ARMTargetLowering
Definition: ARMISelLowering.h:361
llvm::CallLowering::OutgoingValueHandler
Definition: CallLowering.h:244
llvm::ARMSubtarget::getInstrInfo
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:553
T
#define T
Definition: Mips16ISelLowering.cpp:341
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:40
llvm::MachineIRBuilder::setInstr
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
Definition: MachineIRBuilder.h:341
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
MachineIRBuilder.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
F
#define F(x, y, z)
Definition: MD5.cpp:56
MachineRegisterInfo.h
llvm::EVT::isSimple
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:124
llvm::getBLXOpcode
unsigned getBLXOpcode(const MachineFunction &MF)
Definition: ARMBaseInstrInfo.cpp:6517
MachineValueType.h
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:117
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::MachineIRBuilder::buildLoad
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
Definition: MachineIRBuilder.h:840
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:83
llvm::MachineIRBuilder::setMBB
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
Definition: MachineIRBuilder.h:332
llvm::CCValAssign::getLocReg
Register getLocReg() const
Definition: CallingConvLower.h:150
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:61
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MVT::f64
@ f64
Definition: MachineValueType.h:53
llvm::CallLowering::handleAssignments
bool handleAssignments(MachineIRBuilder &MIRBuilder, SmallVectorImpl< ArgInfo > &Args, ValueHandler &Handler, CallingConv::ID CallConv, bool IsVarArg, Register ThisReturnReg=Register()) const
Invoke Handler::assignArg on each of the given Args and then use Handler to move them to the assigned...
Definition: CallLowering.cpp:454
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
Utils.h
ARMBaseInfo.h
llvm::EVT::isInteger
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:139
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:270
llvm::CallLowering::IncomingValueHandler
Definition: CallLowering.h:230
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:26
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:47
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:155
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::CCValAssign::isRegLoc
bool isRegLoc() const
Definition: CallingConvLower.h:145
Type.h
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:95
llvm::ARMCallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: ARMCallLowering.cpp:375
LowLevelTypeImpl.h
llvm::ARMSubtarget::getRegBankInfo
const RegisterBankInfo * getRegBankInfo() const override
Definition: ARMSubtarget.cpp:139
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:50
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:388
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:35
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:220
llvm::ARMSubtarget::isThumb1Only
bool isThumb1Only() const
Definition: ARMSubtarget.h:802
llvm::CCValAssign::SExt
@ SExt
Definition: CallingConvLower.h:37
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:70
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:37
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:600
Analysis.h
getCallOpcode
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall)
Definition: AArch64CallLowering.cpp:767
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:53
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:815
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:295
std::swap
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
Definition: BitVector.h:840
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:571
ARMBaseInstrInfo.h
llvm::gettBLXrOpcode
unsigned gettBLXrOpcode(const MachineFunction &MF)
Definition: ARMBaseInstrInfo.cpp:6522
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:188
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::LLT::isScalar
bool isScalar() const
Definition: LowLevelTypeImpl.h:92
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:375
llvm::CCValAssign::getValNo
unsigned getValNo() const
Definition: CallingConvLower.h:142
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:33
llvm::EVT::isVector
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:149
llvm::ARMSubtarget::getRegisterInfo
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:565
DataLayout.h
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:45
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:238
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ARMCallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: ARMCallLowering.cpp:465
llvm::ARMSubtarget::hasV4TOps
bool hasV4TOps() const
Definition: ARMSubtarget.h:596
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition: MachineOperand.cpp:970
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:367
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:137
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::MachineIRBuilder::buildTrunc
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
Definition: MachineIRBuilder.cpp:737
CallingConvLower.h
MachineFrameInfo.h
Casting.h
Function.h
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:264
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:95
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:585
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
ARMISelLowering.h
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:196
SmallVector.h
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:995
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
MachineInstrBuilder.h
llvm::CCValAssign::getValVT
MVT getValVT() const
Definition: CallingConvLower.h:143
llvm::DstOp
Definition: MachineIRBuilder.h:58
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:48
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:350
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:260
llvm::MachineIRBuilder::buildMerge
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
Definition: MachineIRBuilder.cpp:588
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:240
MachineMemOperand.h
MachineOperand.h
isSupportedType
static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI, Type *T)
Definition: ARMCallLowering.cpp:55
DerivedTypes.h
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:540
llvm::TargetLoweringBase::getValueType
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
Definition: TargetLowering.h:1382
llvm::ARMCallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
Definition: ARMCallLowering.cpp:222
MachineFunction.h
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:43
Value.h
llvm::CallLowering
Definition: CallLowering.h:43
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1008
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
TargetRegisterInfo.h
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:390
llvm::EVT::isFloatingPoint
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:134
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:471
llvm::CCValAssign::needsCustom
bool needsCustom() const
Definition: CallingConvLower.h:148
llvm::ARMSubtarget::isThumb
bool isThumb() const
Definition: ARMSubtarget.h:800
llvm::EVT::getSimpleVT
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:281
llvm::ARMCallLowering::ARMCallLowering
ARMCallLowering(const ARMTargetLowering &TLI)
Definition: ARMCallLowering.cpp:52
llvm::LLT
Definition: LowLevelTypeImpl.h:40
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:150