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61 if (
T->isStructTy()) {
64 auto StructT = cast<StructType>(
T);
65 for (
unsigned i = 1,
e = StructT->getNumElements();
i !=
e; ++
i)
66 if (StructT->getElementType(
i) != StructT->getElementType(0))
82 return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32;
92 : OutgoingValueHandler(MIRBuilder,
MRI), MIB(MIB) {}
97 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
102 auto SPReg = MIRBuilder.buildCopy(p0,
Register(ARM::SP));
104 auto OffsetReg = MIRBuilder.buildConstant(s32, Offset);
106 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg);
109 return AddrReg.getReg(0);
120 Register ExtReg = extendRegister(ValVReg, VA);
121 MIRBuilder.buildCopy(PhysReg, ExtReg);
127 Register ExtReg = extendRegister(ValVReg, VA);
128 auto MMO = MIRBuilder.getMF().getMachineMemOperand(
130 MIRBuilder.buildStore(ExtReg,
Addr, *MMO);
136 assert(
Arg.Regs.size() == 1 &&
"Can't handle multple regs yet");
150 "Values belong to different arguments");
157 MIRBuilder.buildUnmerge(NewRegs,
Arg.Regs[0]);
159 bool IsLittle = MIRBuilder.getMF().getSubtarget<
ARMSubtarget>().isLittle();
165 assignValueToReg(NewRegs[0], VA.
getLocReg(), VA);
166 assignValueToReg(NewRegs[1], NextVA.
getLocReg(), NextVA);
170 assignValueToReg(NewRegs[0], VA.
getLocReg(), VA);
171 assignValueToReg(NewRegs[1], NextVA.
getLocReg(), NextVA);
189 auto &MF = MIRBuilder.
getMF();
190 const auto &
F = MF.getFunction();
192 const auto &
DL = MF.getDataLayout();
193 auto &TLI = *getTLI<ARMTargetLowering>();
204 TLI.CCAssignFnForReturn(
F.getCallingConv(),
F.isVarArg());
206 OutgoingValueAssigner RetAssigner(AssignFn);
207 ARMOutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(),
Ret);
209 MIRBuilder,
F.getCallingConv(),
216 assert(!Val == VRegs.
empty() &&
"Return value without a vreg");
219 unsigned Opcode =
ST.getReturnOpcode();
222 if (!lowerReturnVal(MIRBuilder, Val, VRegs,
Ret))
236 : IncomingValueHandler(MIRBuilder,
MRI) {}
241 assert((Size == 1 || Size == 2 || Size == 4 || Size == 8) &&
248 const bool IsImmutable = !Flags.
isByVal();
250 int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
270 buildLoad(ValVReg,
Addr, MemTy, MPO);
291 assert(ValSize <= 64 &&
"Unsupported value size");
292 assert(LocSize <= 64 &&
"Unsupported location size");
294 markPhysRegUsed(PhysReg);
295 if (ValSize == LocSize) {
298 assert(ValSize < LocSize &&
"Extensions not supported");
304 MIRBuilder.
buildTrunc(ValVReg, PhysRegToVReg);
308 unsigned assignCustomValue(ARMCallLowering::ArgInfo &
Arg,
311 assert(
Arg.Regs.size() == 1 &&
"Can't handle multple regs yet");
325 "Values belong to different arguments");
333 assignValueToReg(NewRegs[0], VA.
getLocReg(), VA);
334 assignValueToReg(NewRegs[1], NextVA.
getLocReg(), NextVA);
348 virtual void markPhysRegUsed(
unsigned PhysReg) = 0;
355 void markPhysRegUsed(
unsigned PhysReg)
override {
367 auto &TLI = *getTLI<ARMTargetLowering>();
368 auto Subtarget = TLI.getSubtarget();
370 if (Subtarget->isThumb1Only())
380 auto &MF = MIRBuilder.
getMF();
384 for (
auto &
Arg :
F.args()) {
387 if (
Arg.hasPassPointeeByValueCopyAttr())
392 TLI.CCAssignFnForCall(
F.getCallingConv(),
F.isVarArg());
399 for (
auto &
Arg :
F.args()) {
400 ArgInfo OrigArgInfo(VRegs[Idx],
Arg.getType(), Idx);
412 MIRBuilder,
F.getCallingConv(),
428 void markPhysRegUsed(
unsigned PhysReg)
override {
439 return STI.isThumb() ? ARM::tBL :
ARM::BL;
450 return ARM::BMOVPCRX_CALL;
456 const auto &TLI = *getTLI<ARMTargetLowering>();
462 if (STI.genLongCalls())
468 auto CallSeqStart = MIRBuilder.
buildInstr(ARM::ADJCALLSTACKDOWN);
472 bool IsDirect = !
Info.Callee.isReg();
476 bool IsThumb = STI.isThumb();
480 MIB.add(
Info.Callee);
482 auto CalleeReg =
Info.Callee.getReg();
484 unsigned CalleeIdx = IsThumb ? 2 : 0;
487 *MIB.getInstr(), MIB->getDesc(),
Info.Callee, CalleeIdx));
494 for (
auto Arg :
Info.OrigArgs) {
498 if (
Arg.Flags[0].isByVal())
504 auto ArgAssignFn = TLI.CCAssignFnForCall(
Info.CallConv,
Info.IsVarArg);
506 ARMOutgoingValueHandler ArgHandler(MIRBuilder,
MRI, MIB);
508 MIRBuilder,
Info.CallConv,
Info.IsVarArg))
514 if (!
Info.OrigRet.Ty->isVoidTy()) {
520 auto RetAssignFn = TLI.CCAssignFnForReturn(
Info.CallConv,
Info.IsVarArg);
524 MIRBuilder,
Info.CallConv,
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
A parsed version of the target data layout string in and methods for querying it.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MachineInstrBuilder & add(const MachineOperand &MO) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
const ARMBaseInstrInfo * getInstrInfo() const override
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
void setInstr(MachineInstr &MI)
Set the insertion point to before MI.
unsigned const TargetRegisterInfo * TRI
bool empty() const
empty - Check if the array is empty.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
unsigned getBLXOpcode(const MachineFunction &MF)
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
CCValAssign - Represent assignment of one arg/retval to a location.
MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert Res = G_LOAD Addr, MMO.
void setMBB(MachineBasicBlock &MBB)
Set the insertion point to the end of MBB.
Register getLocReg() const
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
bool isInteger() const
Return true if this is an integer or a vector integer type.
MachineFunction & getMF()
Getter for the function we currently build.
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
Analysis containing CSE Info
LocInfo getLocInfo() const
Register getReg(unsigned Idx) const
Get the register for the operand index.
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
const RegisterBankInfo * getRegBankInfo() const override
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
@ Implicit
Not emitted register (e.g. carry, or temporary result).
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Helper class to build MachineInstr.
bool isThumb1Only() const
This class contains a discriminated union of information about pointers in memory operands,...
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned gettBLXrOpcode(const MachineFunction &MF)
print Print MemDeps of function
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
unsigned getValNo() const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool isVector() const
Return true if this is a vector value type.
const ARMBaseRegisterInfo * getRegisterInfo() const override
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Type * getType() const
All values are typed, get the type of this value.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Helper struct shared between Function Specialization and SCCP Solver.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
@ MOLoad
The memory access reads data.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_TRUNC Op.
MachineRegisterInfo & MRI
uint64_t StackOffset
Stack offset for next argument.
MachineIRBuilder & MIRBuilder
@ MOStore
The memory access writes data.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef< Register > Ops)
Build and insert Res = G_MERGE_VALUES Op0, ...
static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI, Type *T)
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, MachineInstrBuilder &MIB)
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
LLVM Value Representation.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, ArrayRef< Register > ThisReturnRegs=None) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
ARMCallLowering(const ARMTargetLowering &TLI)
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const