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21 #define GET_TARGET_REGBANK_IMPL
22 #include "ARMGenRegisterBank.inc"
49 unsigned Start,
unsigned Length,
58 "Wrong mapping for GPR");
61 "Wrong mapping for SPR");
64 "Wrong mapping for DPR");
100 "Wrong value mapping for 3 GPR ops instruction");
103 "Wrong value mapping for 3 GPR ops instruction");
106 "Wrong value mapping for 3 GPR ops instruction");
110 "Wrong value mapping for 3 SPR ops instruction");
113 "Wrong value mapping for 3 SPR ops instruction");
116 "Wrong value mapping for 3 SPR ops instruction");
120 "Wrong value mapping for 3 DPR ops instruction");
123 "Wrong value mapping for 3 DPR ops instruction");
126 "Wrong value mapping for 3 DPR ops instruction");
140 static auto InitializeRegisterBankOnce = [&]() {
143 assert(&ARM::GPRRegBank == &RBGPR &&
"The order in RegBanks is messed up");
147 "Subclass not added?");
149 "Subclass not added?");
151 "Subclass not added?");
153 "Subclass not added?");
155 "Subclass not added?");
157 "Subclass not added?");
159 "Subclass not added?");
161 ARM::tGPREven_and_GPRnoip_and_tcGPRRegClassID)) &&
162 "Subclass not added?");
164 "Subclass not added?");
165 assert(RBGPR.
getSize() == 32 &&
"GPRs should hold up to 32-bit");
173 llvm::call_once(InitializeRegisterBankFlag, InitializeRegisterBankOnce);
181 switch (RC.
getID()) {
183 case GPRwithAPSRRegClassID:
184 case GPRnoipRegClassID:
185 case GPRnopcRegClassID:
186 case GPRnoip_and_GPRnopcRegClassID:
188 case GPRspRegClassID:
189 case GPRnoip_and_tcGPRRegClassID:
190 case tcGPRRegClassID:
192 case tGPREvenRegClassID:
193 case tGPROddRegClassID:
194 case tGPR_and_tGPREvenRegClassID:
195 case tGPR_and_tGPROddRegClassID:
196 case tGPREven_and_tcGPRRegClassID:
197 case tGPREven_and_GPRnoip_and_tcGPRRegClassID:
198 case tGPROdd_and_tcGPRRegClassID:
201 case SPR_8RegClassID:
203 case DPR_8RegClassID:
216 auto Opc =
MI.getOpcode();
226 using namespace TargetOpcode;
230 unsigned NumOperands =
MI.getNumOperands();
408 "Mismatched operand sizes for G_FCMP");
411 assert((Size == 32 || Size == 64) &&
"Unsupported size for G_FCMP");
417 FPRValueMapping, FPRValueMapping});
420 case G_MERGE_VALUES: {
435 case G_UNMERGE_VALUES: {
462 if (Size > 32 && Size != 64)
475 for (
unsigned i = 0;
i < NumOperands;
i++) {
476 for (
const auto &Mapping : OperandsMapping[
i]) {
478 (Mapping.RegBank->getID() != ARM::FPRRegBankID ||
480 "Trying to use floating point register bank on target without vfp");
unsigned getID() const
Return the register class ID number.
This is an optimization pass for GlobalISel generic memory operations.
const InstructionMapping & getInstrMappingImpl(const MachineInstr &MI) const
Try to get the mapping of MI.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool isValid() const
Check whether this object is valid.
unsigned const TargetRegisterInfo * TRI
const PartialMapping * BreakDown
How the value is broken down between the different register banks.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
This class implements the register bank concept.
TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Helper struct that represents how a value is partially mapped into a register.
static void checkPartialMappings()
MachineOperand class - Representation of each machine instruction operand.
static bool checkValueMapping(const RegisterBankInfo::ValueMapping &VM, RegisterBankInfo::PartialMapping *BreakDown)
unsigned getID() const
Get the identifier of this register bank.
unsigned StartIdx
Number of bits at which this partial mapping starts in the original value.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
static bool checkPartMapping(const RegisterBankInfo::PartialMapping &PM, unsigned Start, unsigned Length, unsigned RegBankID)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
Helper class that represents how the value of an instruction may be mapped and what is the related co...
static void checkValueMappings()
RegisterBankInfo::PartialMapping PartMappings[]
static const unsigned DefaultMappingID
Identifier used when the related instruction mapping instance is generated by target independent code...
const ValueMapping * getOperandsMapping(Iterator Begin, Iterator End) const
Get the uniquely generated array of ValueMapping for the elements of between Begin and End.
bool covers(const TargetRegisterClass &RC) const
Check whether this register bank covers RC.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Register getReg() const
getReg - Returns the register number.
const RegisterBank * RegBank
Register bank where the partial value lives.
const InstructionMapping & getInstructionMapping(unsigned ID, unsigned Cost, const ValueMapping *OperandsMapping, unsigned NumOperands) const
Method to get a uniquely generated InstructionMapping.
Helper struct that represents how a value is mapped through different register banks.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
RegisterBankInfo::ValueMapping ValueMappings[]
unsigned Length
Length of this mapping in bits.
unsigned const MachineRegisterInfo * MRI
const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override
Get the mapping of the different operands of MI on the register bank.
void call_once(once_flag &flag, Function &&F, Args &&... ArgList)
Execute the function specified as a parameter once.
ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
unsigned getSize() const
Get the maximal size in bits that fits in this register bank.
const InstructionMapping & getInvalidInstructionMapping() const
Method to get a uniquely generated invalid InstructionMapping.
const RegisterBank & getRegBankFromRegClass(const TargetRegisterClass &RC, LLT) const override
Get a register bank that covers RC.
unsigned NumBreakDowns
Number of partial mapping to break down this value.
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.