20#include "llvm/IR/IntrinsicsARM.h"
23#define DEBUG_TYPE "arm-isel"
29#define GET_GLOBALISEL_PREDICATE_BITSET
30#include "ARMGenGlobalISel.inc"
31#undef GET_GLOBALISEL_PREDICATE_BITSET
53 bool insertComparison(CmpConstants Helper, InsertInfo
I,
unsigned ResReg,
55 unsigned PrevRes)
const;
58 void putConstant(InsertInfo
I,
unsigned DestReg,
unsigned Constant)
const;
67 unsigned ExpectedSize,
unsigned ExpectedRegBankID)
const;
71 unsigned ExpectedRegBankID)
const;
122 unsigned ConstPoolLoad;
123 unsigned MOV_ga_pcrel;
124 unsigned LDRLIT_ga_pcrel;
125 unsigned LDRLIT_ga_abs;
134 unsigned selectSimpleExtOpc(
unsigned Opc,
unsigned Size)
const;
138 unsigned selectLoadStoreOpCode(
unsigned Opc,
unsigned RegBank,
139 unsigned Size)
const;
142 int OpIdx = -1)
const;
144 int OpIdx = -1)
const;
146 int OpIdx = -1)
const;
148#define GET_GLOBALISEL_PREDICATES_DECL
149#include "ARMGenGlobalISel.inc"
150#undef GET_GLOBALISEL_PREDICATES_DECL
154#define GET_GLOBALISEL_TEMPORARIES_DECL
155#include "ARMGenGlobalISel.inc"
156#undef GET_GLOBALISEL_TEMPORARIES_DECL
165 return new ARMInstructionSelector(
TM, STI, RBI);
169#define GET_GLOBALISEL_IMPL
170#include "ARMGenGlobalISel.inc"
171#undef GET_GLOBALISEL_IMPL
176 :
TII(*STI.getInstrInfo()),
TRI(*STI.getRegisterInfo()),
TM(
TM), RBI(RBI),
177 STI(STI), Opcodes(STI),
179#include
"ARMGenGlobalISel.inc"
182#include
"ARMGenGlobalISel.inc"
192 assert(RegBank &&
"Can't get reg bank for virtual register");
194 const unsigned Size =
MRI.getType(Reg).getSizeInBits();
196 RegBank->
getID() == ARM::FPRRegBankID) &&
197 "Unsupported reg bank");
199 if (RegBank->
getID() == ARM::FPRRegBankID) {
201 return &ARM::SPRRegClass;
203 return &ARM::DPRRegClass;
204 else if (
Size == 128)
205 return &ARM::QPRRegClass;
210 return &ARM::GPRRegClass;
216 Register DstReg =
I.getOperand(0).getReg();
238 assert(
TII.getSubtarget().hasVFP2Base() &&
"Can't select merge without VFP");
244 assert(
MRI.getType(VReg0).getSizeInBits() == 64 &&
246 "Unsupported operand for G_MERGE_VALUES");
249 assert(
MRI.getType(VReg1).getSizeInBits() == 32 &&
251 "Unsupported operand for G_MERGE_VALUES");
254 assert(
MRI.getType(VReg2).getSizeInBits() == 32 &&
256 "Unsupported operand for G_MERGE_VALUES");
269 assert(
TII.getSubtarget().hasVFP2Base() &&
270 "Can't select unmerge without VFP");
276 assert(
MRI.getType(VReg0).getSizeInBits() == 32 &&
278 "Unsupported operand for G_UNMERGE_VALUES");
281 assert(
MRI.getType(VReg1).getSizeInBits() == 32 &&
283 "Unsupported operand for G_UNMERGE_VALUES");
286 assert(
MRI.getType(VReg2).getSizeInBits() == 64 &&
288 "Unsupported operand for G_UNMERGE_VALUES");
296ARMInstructionSelector::OpcodeCache::OpcodeCache(
const ARMSubtarget &STI) {
299 using namespace TargetOpcode;
301#define STORE_OPCODE(VAR, OPC) VAR = isThumb ? ARM::t2##OPC : ARM::OPC
315 STORE16 =
isThumb ? ARM::t2STRHi12 : ARM::STRH;
316 LOAD16 =
isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
334 ConstPoolLoad =
isThumb ? ARM::t2LDRpci : ARM::LDRi12;
336 LDRLIT_ga_pcrel =
isThumb ? ARM::tLDRLIT_ga_pcrel : ARM::LDRLIT_ga_pcrel;
337 LDRLIT_ga_abs =
isThumb ? ARM::tLDRLIT_ga_abs : ARM::LDRLIT_ga_abs;
341unsigned ARMInstructionSelector::selectSimpleExtOpc(
unsigned Opc,
342 unsigned Size)
const {
343 using namespace TargetOpcode;
349 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16;
352 return Size == 8 ? Opcodes.ZEXT8 : Opcodes.ZEXT16;
357unsigned ARMInstructionSelector::selectLoadStoreOpCode(
unsigned Opc,
359 unsigned Size)
const {
360 bool isStore = Opc == TargetOpcode::G_STORE;
362 if (RegBank == ARM::GPRRegBankID) {
366 return isStore ? Opcodes.STORE8 : Opcodes.LOAD8;
368 return isStore ? Opcodes.STORE16 : Opcodes.LOAD16;
370 return isStore ? Opcodes.STORE32 : Opcodes.LOAD32;
376 if (RegBank == ARM::FPRRegBankID) {
379 return isStore ? ARM::VSTRS : ARM::VLDRS;
381 return isStore ? ARM::VSTRD : ARM::VLDRD;
393static std::pair<ARMCC::CondCodes, ARMCC::CondCodes>
461 CmpConstants(
unsigned CmpOpcode,
unsigned FlagsOpcode,
unsigned SelectOpcode,
462 unsigned OpRegBank,
unsigned OpSize)
494void ARMInstructionSelector::putConstant(
InsertInfo I,
unsigned DestReg,
496 (void)
BuildMI(
I.MBB,
I.InsertBefore,
I.DbgLoc,
TII.get(Opcodes.MOVi))
504 unsigned LHSReg,
unsigned RHSReg,
505 unsigned ExpectedSize,
506 unsigned ExpectedRegBankID)
const {
507 return MRI.getType(LHSReg) ==
MRI.getType(RHSReg) &&
508 validReg(
MRI, LHSReg, ExpectedSize, ExpectedRegBankID) &&
509 validReg(
MRI, RHSReg, ExpectedSize, ExpectedRegBankID);
513 unsigned ExpectedSize,
514 unsigned ExpectedRegBankID)
const {
515 if (
MRI.getType(Reg).getSizeInBits() != ExpectedSize) {
528bool ARMInstructionSelector::selectCmp(CmpConstants Helper,
531 const InsertInfo
I(MIB);
533 auto ResReg = MIB.
getReg(0);
534 if (!validReg(
MRI, ResReg, 1, ARM::GPRRegBankID))
545 auto LHSReg = MIB.
getReg(2);
546 auto RHSReg = MIB.
getReg(3);
547 if (!validOpRegPair(
MRI, LHSReg, RHSReg, Helper.OperandSize,
548 Helper.OperandRegBankID))
552 auto ZeroReg =
MRI.createVirtualRegister(&ARM::GPRRegClass);
553 putConstant(
I, ZeroReg, 0);
557 if (!insertComparison(Helper,
I, ResReg, ARMConds.first, LHSReg, RHSReg,
562 auto IntermediateRes =
MRI.createVirtualRegister(&ARM::GPRRegClass);
563 if (!insertComparison(Helper,
I, IntermediateRes, ARMConds.first, LHSReg,
566 if (!insertComparison(Helper,
I, ResReg, ARMConds.second, LHSReg, RHSReg,
575bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo
I,
578 unsigned LHSReg,
unsigned RHSReg,
579 unsigned PrevRes)
const {
582 BuildMI(
I.MBB,
I.InsertBefore,
I.DbgLoc,
TII.get(Helper.ComparisonOpcode))
590 if (Helper.ReadFlagsOpcode != ARM::INSTRUCTION_LIST_END) {
591 auto ReadI =
BuildMI(
I.MBB,
I.InsertBefore,
I.DbgLoc,
592 TII.get(Helper.ReadFlagsOpcode))
599 auto Mov1I =
BuildMI(
I.MBB,
I.InsertBefore,
I.DbgLoc,
600 TII.get(Helper.SelectResultOpcode))
619 if (GV->isThreadLocal()) {
630 const Align Alignment(4);
632 auto addOpsForConstantPoolLoad = [&MF, Alignment, PtrTy](
635 assert((MIB->getOpcode() == ARM::LDRi12 ||
636 MIB->getOpcode() == ARM::t2LDRpci) &&
637 "Unsupported instruction");
638 auto ConstPool = MF.getConstantPool();
643 ? ConstPool->getConstantPoolIndex(
645 : ConstPool->getConstantPoolIndex(GV, Alignment);
646 MIB.addConstantPoolIndex(CPIndex, 0, 0)
647 .addMemOperand(MF.getMachineMemOperand(
650 if (MIB->getOpcode() == ARM::LDRi12)
656 MIB.addMemOperand(MF.getMachineMemOperand(
658 TM.getProgramPointerSize(), Alignment));
661 if (
TM.isPositionIndependent()) {
669 bool UseOpcodeThatLoads =
Indirect && !STI.isThumb();
675 ? (UseOpcodeThatLoads ? (
unsigned)ARM::MOV_ga_pcrel_ldr
676 : Opcodes.MOV_ga_pcrel)
677 : (UseOpcodeThatLoads ? (
unsigned)ARM::LDRLIT_ga_pcrel_ldr
678 : Opcodes.LDRLIT_ga_pcrel);
679 MIB->setDesc(
TII.get(Opc));
686 MIB->getOperand(1).setTargetFlags(TargetFlags);
689 if (!UseOpcodeThatLoads) {
690 auto ResultReg = MIB.getReg(0);
691 auto AddressReg =
MRI.createVirtualRegister(&ARM::GPRRegClass);
693 MIB->getOperand(0).setReg(AddressReg);
695 auto InsertBefore = std::next(MIB->getIterator());
696 auto MIBLoad =
BuildMI(
MBB, InsertBefore, MIB->getDebugLoc(),
697 TII.get(Opcodes.LOAD32))
702 addGOTMemOperand(MIBLoad);
707 addGOTMemOperand(MIB);
715 if (STI.
isROPI() && isReadOnly) {
716 unsigned Opc = UseMovt ? Opcodes.MOV_ga_pcrel : Opcodes.LDRLIT_ga_pcrel;
717 MIB->setDesc(
TII.get(Opc));
720 if (STI.
isRWPI() && !isReadOnly) {
721 auto Offset =
MRI.createVirtualRegister(&ARM::GPRRegClass);
724 OffsetMIB =
BuildMI(
MBB, *MIB, MIB->getDebugLoc(),
729 OffsetMIB =
BuildMI(
MBB, *MIB, MIB->getDebugLoc(),
731 addOpsForConstantPoolLoad(OffsetMIB, GV,
true);
737 MIB->setDesc(
TII.get(Opcodes.ADDrr));
738 MIB->removeOperand(1);
749 MIB->setDesc(
TII.get(Opcodes.MOVi32imm));
752 MIB->setDesc(
TII.get(Opcodes.ConstPoolLoad));
753 MIB->removeOperand(1);
754 addOpsForConstantPoolLoad(MIB, GV,
false);
758 MIB->setDesc(
TII.get(Opcodes.MOVi32imm));
760 MIB->setDesc(
TII.get(Opcodes.LDRLIT_ga_abs));
776 auto CondReg = MIB.
getReg(1);
777 assert(validReg(
MRI, CondReg, 1, ARM::GPRRegBankID) &&
778 "Unsupported types for select operation");
779 auto CmpI =
BuildMI(
MBB, InsertBefore, DbgLoc,
TII.get(Opcodes.TSTri))
788 auto ResReg = MIB.
getReg(0);
789 auto TrueReg = MIB.
getReg(2);
790 auto FalseReg = MIB.
getReg(3);
791 assert(validOpRegPair(
MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) &&
792 validOpRegPair(
MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) &&
793 "Unsupported types for select operation");
794 auto Mov1I =
BuildMI(
MBB, InsertBefore, DbgLoc,
TII.get(Opcodes.MOVCCr))
806bool ARMInstructionSelector::selectShift(
unsigned ShiftOpc,
808 assert(!STI.isThumb() &&
"Unsupported subtarget");
815void ARMInstructionSelector::renderVFPF32Imm(
819 OpIdx == -1 &&
"Expected G_FCONSTANT");
823 assert(FPImmEncoding != -1 &&
"Invalid immediate value");
825 NewInstBuilder.
addImm(FPImmEncoding);
828void ARMInstructionSelector::renderVFPF64Imm(
831 OpIdx == -1 &&
"Expected G_FCONSTANT");
835 assert(FPImmEncoding != -1 &&
"Invalid immediate value");
837 NewInstBuilder.
addImm(FPImmEncoding);
843 assert(
MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
844 "Expected G_CONSTANT");
845 int64_t CVal =
MI.getOperand(1).getCImm()->getSExtValue();
850 assert(
I.getParent() &&
"Instruction should be in a basic block!");
851 assert(
I.getParent()->getParent() &&
"Instruction should be in a function!");
853 auto &
MBB = *
I.getParent();
855 auto &
MRI = MF.getRegInfo();
864 using namespace TargetOpcode;
866 if (selectImpl(
I, *CoverageInfo))
872 switch (
I.getOpcode()) {
877 assert(
MRI.getType(
I.getOperand(0).getReg()).getSizeInBits() <= 32 &&
878 "Unsupported destination size for extension");
880 LLT SrcTy =
MRI.getType(
I.getOperand(1).getReg());
885 I.setDesc(
TII.get(Opcodes.AND));
889 Register SExtResult =
I.getOperand(0).getReg();
892 Register AndResult =
MRI.createVirtualRegister(&ARM::GPRRegClass);
893 I.getOperand(0).setReg(AndResult);
895 auto InsertBefore = std::next(
I.getIterator());
910 unsigned NewOpc = selectSimpleExtOpc(
I.getOpcode(), SrcSize);
911 if (NewOpc ==
I.getOpcode())
913 I.setDesc(
TII.get(NewOpc));
927 auto SrcReg =
I.getOperand(1).getReg();
928 auto DstReg =
I.getOperand(0).getReg();
933 if (SrcRegBank.getID() == ARM::FPRRegBankID) {
937 assert(
I.getOpcode() == G_TRUNC &&
"Unsupported operand for G_ANYEXT");
938 assert(DstRegBank.getID() == ARM::GPRRegBankID &&
939 "Unsupported combination of register banks");
940 assert(
MRI.getType(SrcReg).getSizeInBits() == 64 &&
"Unsupported size");
941 assert(
MRI.getType(DstReg).getSizeInBits() <= 32 &&
"Unsupported size");
943 Register IgnoredBits =
MRI.createVirtualRegister(&ARM::GPRRegClass);
944 auto InsertBefore = std::next(
I.getIterator());
946 BuildMI(
MBB, InsertBefore,
I.getDebugLoc(),
TII.get(ARM::VMOVRRD))
958 if (SrcRegBank.getID() != DstRegBank.getID()) {
960 dbgs() <<
"G_TRUNC/G_ANYEXT operands on different register banks\n");
964 if (SrcRegBank.getID() != ARM::GPRRegBankID) {
965 LLVM_DEBUG(
dbgs() <<
"G_TRUNC/G_ANYEXT on non-GPR not supported yet\n");
969 I.setDesc(
TII.get(COPY));
973 if (!
MRI.getType(
I.getOperand(0).getReg()).isPointer()) {
979 auto &Val =
I.getOperand(1);
981 if (!Val.getCImm()->isZero()) {
985 Val.ChangeToImmediate(0);
987 assert(Val.isImm() &&
"Unexpected operand for G_CONSTANT");
988 if (Val.getImm() != 0) {
994 assert(!STI.isThumb() &&
"Unsupported subtarget");
995 I.setDesc(
TII.get(ARM::MOVi));
1001 unsigned Size =
MRI.getType(
I.getOperand(0).getReg()).getSizeInBits() / 8;
1004 assert((
Size == 4 ||
Size == 8) &&
"Unsupported FP constant type");
1005 auto LoadOpcode =
Size == 4 ? ARM::VLDRS : ARM::VLDRD;
1007 auto ConstPool = MF.getConstantPool();
1009 ConstPool->getConstantPoolIndex(
I.getOperand(1).getFPImm(), Alignment);
1022 auto SrcReg =
I.getOperand(1).getReg();
1023 auto DstReg =
I.getOperand(0).getReg();
1028 if (SrcRegBank.getID() != DstRegBank.getID()) {
1031 <<
"G_INTTOPTR/G_PTRTOINT operands on different register banks\n");
1035 if (SrcRegBank.getID() != ARM::GPRRegBankID) {
1037 dbgs() <<
"G_INTTOPTR/G_PTRTOINT on non-GPR not supported yet\n");
1041 I.setDesc(
TII.get(COPY));
1045 return selectSelect(MIB,
MRI);
1047 CmpConstants Helper(Opcodes.CMPrr, ARM::INSTRUCTION_LIST_END,
1048 Opcodes.MOVCCi, ARM::GPRRegBankID, 32);
1049 return selectCmp(Helper, MIB,
MRI);
1054 Register OpReg =
I.getOperand(2).getReg();
1055 unsigned Size =
MRI.getType(OpReg).getSizeInBits();
1057 if (
Size == 64 && !STI.hasFP64()) {
1058 LLVM_DEBUG(
dbgs() <<
"Subtarget only supports single precision");
1066 CmpConstants Helper(
Size == 32 ? ARM::VCMPS : ARM::VCMPD, ARM::FMSTAT,
1067 Opcodes.MOVCCi, ARM::FPRRegBankID,
Size);
1068 return selectCmp(Helper, MIB,
MRI);
1071 return selectShift(ARM_AM::ShiftOpc::lsr, MIB);
1073 return selectShift(ARM_AM::ShiftOpc::asr, MIB);
1075 return selectShift(ARM_AM::ShiftOpc::lsl, MIB);
1078 I.setDesc(
TII.get(Opcodes.ADDrr));
1084 I.setDesc(
TII.get(Opcodes.ADDri));
1087 case G_GLOBAL_VALUE:
1088 return selectGlobal(MIB,
MRI);
1091 const auto &
MemOp = **
I.memoperands_begin();
1092 if (
MemOp.isAtomic()) {
1100 LLT ValTy =
MRI.getType(Reg);
1104 "Don't know how to load/store 64-bit value without VFP");
1106 const auto NewOpc = selectLoadStoreOpCode(
I.getOpcode(), RegBank, ValSize);
1107 if (NewOpc == G_LOAD || NewOpc == G_STORE)
1110 I.setDesc(
TII.get(NewOpc));
1112 if (NewOpc == ARM::LDRH || NewOpc == ARM::STRH)
1118 case G_MERGE_VALUES: {
1123 case G_UNMERGE_VALUES: {
1129 if (!validReg(
MRI,
I.getOperand(0).getReg(), 1, ARM::GPRRegBankID)) {
1130 LLVM_DEBUG(
dbgs() <<
"Unsupported condition register for G_BRCOND");
1136 BuildMI(*
I.getParent(),
I,
I.getDebugLoc(),
TII.get(Opcodes.TSTri))
1137 .
addReg(
I.getOperand(0).getReg())
1145 BuildMI(*
I.getParent(),
I,
I.getDebugLoc(),
TII.get(Opcodes.Bcc))
1146 .
add(
I.getOperand(1))
1150 I.eraseFromParent();
1156 Register DstReg =
I.getOperand(0).getReg();
unsigned const MachineRegisterInfo * MRI
static bool isStore(int Opcode)
static bool isThumb(const MCSubtargetInfo &STI)
static std::pair< ARMCC::CondCodes, ARMCC::CondCodes > getComparePreds(CmpInst::Predicate Pred)
static bool selectMergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
#define GET_GLOBALISEL_PREDICATES_INIT
#define GET_GLOBALISEL_TEMPORARIES_INIT
static bool selectUnmergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
#define STORE_OPCODE(VAR, OPC)
This file declares the targeting of the RegisterBankInfo class for ARM.
static const Function * getParent(const Value *V)
const HexagonInstrInfo * TII
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
static StringRef getName(Value *V)
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static ARMConstantPoolConstant * Create(const Constant *C, unsigned ID)
This class provides the information for the target register banks.
bool isTargetMachO() const
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
const ARMTargetLowering * getTargetLowering() const override
bool isTargetDarwin() const
bool isGVInGOT(const GlobalValue *GV) const
Returns the constant pool modifier needed to access the GV.
bool isReadOnly(const GlobalValue *GV) const
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ FCMP_OEQ
0 0 0 1 True if ordered and equal
@ FCMP_TRUE
1 1 1 1 Always true (always folded)
@ ICMP_SLT
signed less than
@ ICMP_SLE
signed less or equal
@ FCMP_OLT
0 1 0 0 True if ordered and less than
@ FCMP_ULE
1 1 0 1 True if unordered, less than, or equal
@ FCMP_OGT
0 0 1 0 True if ordered and greater than
@ FCMP_OGE
0 0 1 1 True if ordered and greater than or equal
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_SGT
signed greater than
@ FCMP_ULT
1 1 0 0 True if unordered or less than
@ FCMP_ONE
0 1 1 0 True if ordered and operands are unequal
@ FCMP_UEQ
1 0 0 1 True if unordered or equal
@ ICMP_ULT
unsigned less than
@ FCMP_UGT
1 0 1 0 True if unordered or greater than
@ FCMP_OLE
0 1 0 1 True if ordered and less than or equal
@ FCMP_ORD
0 1 1 1 True if ordered (no nans)
@ ICMP_SGE
signed greater or equal
@ FCMP_UNE
1 1 1 0 True if unordered or not equal
@ ICMP_ULE
unsigned less or equal
@ FCMP_UGE
1 0 1 1 True if unordered, greater than, or equal
@ FCMP_FALSE
0 0 0 0 Always false (always folded)
@ FCMP_UNO
1 0 0 0 True if unordered: isnan(X) | isnan(Y)
const APFloat & getValueAPF() const
This is an important base class in LLVM.
virtual bool select(MachineInstr &I)=0
Select the (possibly generic) instruction I to only use target-specific opcodes.
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
Instructions::iterator instr_iterator
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Register getReg(unsigned Idx) const
Get the register for the operand index.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
const MachineBasicBlock * getParent() const
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
const MachineOperand & getOperand(unsigned i) const
@ MOLoad
The memory access reads data.
const GlobalValue * getGlobal() const
Register getReg() const
getReg - Returns the register number.
const ConstantFP * getFPImm() const
unsigned getPredicate() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Holds all the information related to register banks.
static const TargetRegisterClass * constrainGenericRegister(Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI)
Constrain the (possibly generic) virtual register Reg to RC.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
This class implements the register bank concept.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ SBREL
Section Relative (Windows TLS)
@ MO_NONLAZY
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which,...
@ MO_SBREL
MO_SBREL - On a symbol operand, this represents a static base relative relocation.
@ MO_GOT
MO_GOT - On a symbol operand, this represents a GOT relative relocation.
int getFP32Imm(const APInt &Imm)
getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.
int getFP64Imm(const APInt &Imm)
getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI)
bool constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI)
Mutate the newly-selected instruction I to constrain its (possibly generic) virtual register operands...
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
Implement std::hash so that hash_code can be used in STL containers.
CmpConstants(unsigned CmpOpcode, unsigned FlagsOpcode, unsigned SelectOpcode, unsigned OpRegBank, unsigned OpSize)
const unsigned OperandRegBankID
const unsigned ReadFlagsOpcode
const unsigned SelectResultOpcode
const unsigned ComparisonOpcode
const unsigned OperandSize
const MachineBasicBlock::instr_iterator InsertBefore
InsertInfo(MachineInstrBuilder &MIB)
This struct is a compact representation of a valid (non-zero power of two) alignment.
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.