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ARMFrameLowering.cpp
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1 //===- ARMFrameLowering.cpp - ARM Frame Information -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the ARM implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 //
13 // This file contains the ARM implementation of TargetFrameLowering class.
14 //
15 // On ARM, stack frames are structured as follows:
16 //
17 // The stack grows downward.
18 //
19 // All of the individual frame areas on the frame below are optional, i.e. it's
20 // possible to create a function so that the particular area isn't present
21 // in the frame.
22 //
23 // At function entry, the "frame" looks as follows:
24 //
25 // | | Higher address
26 // |-----------------------------------|
27 // | |
28 // | arguments passed on the stack |
29 // | |
30 // |-----------------------------------| <- sp
31 // | | Lower address
32 //
33 //
34 // After the prologue has run, the frame has the following general structure.
35 // Technically the last frame area (VLAs) doesn't get created until in the
36 // main function body, after the prologue is run. However, it's depicted here
37 // for completeness.
38 //
39 // | | Higher address
40 // |-----------------------------------|
41 // | |
42 // | arguments passed on the stack |
43 // | |
44 // |-----------------------------------| <- (sp at function entry)
45 // | |
46 // | varargs from registers |
47 // | |
48 // |-----------------------------------|
49 // | |
50 // | prev_lr |
51 // | prev_fp |
52 // | (a.k.a. "frame record") |
53 // | |
54 // |- - - - - - - - - - - - - - - - - -| <- fp (r7 or r11)
55 // | |
56 // | callee-saved gpr registers |
57 // | |
58 // |-----------------------------------|
59 // | |
60 // | callee-saved fp/simd regs |
61 // | |
62 // |-----------------------------------|
63 // |.empty.space.to.make.part.below....|
64 // |.aligned.in.case.it.needs.more.than| (size of this area is unknown at
65 // |.the.standard.8-byte.alignment.....| compile time; if present)
66 // |-----------------------------------|
67 // | |
68 // | local variables of fixed size |
69 // | including spill slots |
70 // |-----------------------------------| <- base pointer (not defined by ABI,
71 // |.variable-sized.local.variables....| LLVM chooses r6)
72 // |.(VLAs)............................| (size of this area is unknown at
73 // |...................................| compile time)
74 // |-----------------------------------| <- sp
75 // | | Lower address
76 //
77 //
78 // To access the data in a frame, at-compile time, a constant offset must be
79 // computable from one of the pointers (fp, bp, sp) to access it. The size
80 // of the areas with a dotted background cannot be computed at compile-time
81 // if they are present, making it required to have all three of fp, bp and
82 // sp to be set up to be able to access all contents in the frame areas,
83 // assuming all of the frame areas are non-empty.
84 //
85 // For most functions, some of the frame areas are empty. For those functions,
86 // it may not be necessary to set up fp or bp:
87 // * A base pointer is definitely needed when there are both VLAs and local
88 // variables with more-than-default alignment requirements.
89 // * A frame pointer is definitely needed when there are local variables with
90 // more-than-default alignment requirements.
91 //
92 // In some cases when a base pointer is not strictly needed, it is generated
93 // anyway when offsets from the frame pointer to access local variables become
94 // so large that the offset can't be encoded in the immediate fields of loads
95 // or stores.
96 //
97 // The frame pointer might be chosen to be r7 or r11, depending on the target
98 // architecture and operating system. See ARMSubtarget::getFramePointerReg for
99 // details.
100 //
101 // Outgoing function arguments must be at the bottom of the stack frame when
102 // calling another function. If we do not have variable-sized stack objects, we
103 // can allocate a "reserved call frame" area at the bottom of the local
104 // variable area, large enough for all outgoing calls. If we do have VLAs, then
105 // the stack pointer must be decremented and incremented around each call to
106 // make space for the arguments below the VLAs.
107 //
108 //===----------------------------------------------------------------------===//
109 
110 #include "ARMFrameLowering.h"
111 #include "ARMBaseInstrInfo.h"
112 #include "ARMBaseRegisterInfo.h"
113 #include "ARMConstantPoolValue.h"
114 #include "ARMMachineFunctionInfo.h"
115 #include "ARMSubtarget.h"
118 #include "Utils/ARMBaseInfo.h"
119 #include "llvm/ADT/BitVector.h"
120 #include "llvm/ADT/STLExtras.h"
121 #include "llvm/ADT/SmallPtrSet.h"
122 #include "llvm/ADT/SmallVector.h"
138 #include "llvm/IR/Attributes.h"
139 #include "llvm/IR/CallingConv.h"
140 #include "llvm/IR/DebugLoc.h"
141 #include "llvm/IR/Function.h"
142 #include "llvm/MC/MCAsmInfo.h"
143 #include "llvm/MC/MCContext.h"
144 #include "llvm/MC/MCDwarf.h"
145 #include "llvm/MC/MCInstrDesc.h"
146 #include "llvm/MC/MCRegisterInfo.h"
147 #include "llvm/Support/CodeGen.h"
149 #include "llvm/Support/Compiler.h"
150 #include "llvm/Support/Debug.h"
152 #include "llvm/Support/MathExtras.h"
156 #include <algorithm>
157 #include <cassert>
158 #include <cstddef>
159 #include <cstdint>
160 #include <iterator>
161 #include <utility>
162 #include <vector>
163 
164 #define DEBUG_TYPE "arm-frame-lowering"
165 
166 using namespace llvm;
167 
168 static cl::opt<bool>
169 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
170  cl::desc("Align ARM NEON spills in prolog and epilog"));
171 
174  unsigned NumAlignedDPRCS2Regs);
175 
177  : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, Align(4)),
178  STI(sti) {}
179 
181  // iOS always has a FP for backtracking, force other targets to keep their FP
182  // when doing FastISel. The emitted code is currently superior, and in cases
183  // like test-suite's lencod FastISel isn't quite correct when FP is eliminated.
184  return MF.getSubtarget<ARMSubtarget>().useFastISel();
185 }
186 
187 /// Returns true if the target can safely skip saving callee-saved registers
188 /// for noreturn nounwind functions.
190  assert(MF.getFunction().hasFnAttribute(Attribute::NoReturn) &&
191  MF.getFunction().hasFnAttribute(Attribute::NoUnwind) &&
192  !MF.getFunction().hasFnAttribute(Attribute::UWTable));
193 
194  // Frame pointer and link register are not treated as normal CSR, thus we
195  // can always skip CSR saves for nonreturning functions.
196  return true;
197 }
198 
199 /// hasFP - Return true if the specified function should have a dedicated frame
200 /// pointer register. This is true if the function has variable sized allocas
201 /// or if frame pointer elimination is disabled.
203  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
204  const MachineFrameInfo &MFI = MF.getFrameInfo();
205 
206  // ABI-required frame pointer.
208  return true;
209 
210  // Frame pointer required for use within this function.
211  return (RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
212  MFI.isFrameAddressTaken());
213 }
214 
215 /// isFPReserved - Return true if the frame pointer register should be
216 /// considered a reserved register on the scope of the specified function.
218  return hasFP(MF) || MF.getSubtarget<ARMSubtarget>().createAAPCSFrameChain();
219 }
220 
221 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
222 /// not required, we reserve argument space for call sites in the function
223 /// immediately on entry to the current function. This eliminates the need for
224 /// add/sub sp brackets around call sites. Returns true if the call frame is
225 /// included as part of the stack frame.
227  const MachineFrameInfo &MFI = MF.getFrameInfo();
228  unsigned CFSize = MFI.getMaxCallFrameSize();
229  // It's not always a good idea to include the call frame as part of the
230  // stack frame. ARM (especially Thumb) has small immediate offset to
231  // address the stack frame. So a large call frame can cause poor codegen
232  // and may even makes it impossible to scavenge a register.
233  if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
234  return false;
235 
236  return !MFI.hasVarSizedObjects();
237 }
238 
239 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
240 /// call frame pseudos can be simplified. Unlike most targets, having a FP
241 /// is not sufficient here since we still may reference some objects via SP
242 /// even when FP is available in Thumb2 mode.
243 bool
246 }
247 
248 // Returns how much of the incoming argument stack area we should clean up in an
249 // epilogue. For the C calling convention this will be 0, for guaranteed tail
250 // call conventions it can be positive (a normal return or a tail call to a
251 // function that uses less stack space for arguments) or negative (for a tail
252 // call to a function that needs more stack space than us for arguments).
256  bool IsTailCallReturn = false;
257  if (MBB.end() != MBBI) {
258  unsigned RetOpcode = MBBI->getOpcode();
259  IsTailCallReturn = RetOpcode == ARM::TCRETURNdi ||
260  RetOpcode == ARM::TCRETURNri;
261  }
263 
264  int ArgumentPopSize = 0;
265  if (IsTailCallReturn) {
266  MachineOperand &StackAdjust = MBBI->getOperand(1);
267 
268  // For a tail-call in a callee-pops-arguments environment, some or all of
269  // the stack may actually be in use for the call's arguments, this is
270  // calculated during LowerCall and consumed here...
271  ArgumentPopSize = StackAdjust.getImm();
272  } else {
273  // ... otherwise the amount to pop is *all* of the argument space,
274  // conveniently stored in the MachineFunctionInfo by
275  // LowerFormalArguments. This will, of course, be zero for the C calling
276  // convention.
277  ArgumentPopSize = AFI->getArgumentStackToRestore();
278  }
279 
280  return ArgumentPopSize;
281 }
282 
283 static bool needsWinCFI(const MachineFunction &MF) {
284  const Function &F = MF.getFunction();
285  return MF.getTarget().getMCAsmInfo()->usesWindowsCFI() &&
286  F.needsUnwindTableEntry();
287 }
288 
289 // Given a load or a store instruction, generate an appropriate unwinding SEH
290 // code on Windows.
292  const TargetInstrInfo &TII,
293  unsigned Flags) {
294  unsigned Opc = MBBI->getOpcode();
296  MachineFunction &MF = *MBB->getParent();
297  DebugLoc DL = MBBI->getDebugLoc();
299  const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>();
300  const ARMBaseRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
301 
302  Flags |= MachineInstr::NoMerge;
303 
304  switch (Opc) {
305  default:
306  report_fatal_error("No SEH Opcode for instruction " + TII.getName(Opc));
307  break;
308  case ARM::t2ADDri: // add.w r11, sp, #xx
309  case ARM::t2ADDri12: // add.w r11, sp, #xx
310  case ARM::t2MOVTi16: // movt r4, #xx
311  case ARM::tBL: // bl __chkstk
312  // These are harmless if used for just setting up a frame pointer,
313  // but that frame pointer can't be relied upon for unwinding, unless
314  // set up with SEH_SaveSP.
315  MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))
316  .addImm(/*Wide=*/1)
317  .setMIFlags(Flags);
318  break;
319 
320  case ARM::t2MOVi16: { // mov(w) r4, #xx
321  bool Wide = MBBI->getOperand(1).getImm() >= 256;
322  if (!Wide) {
323  MachineInstrBuilder NewInstr =
324  BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags());
325  NewInstr.add(MBBI->getOperand(0));
326  NewInstr.add(t1CondCodeOp(/*isDead=*/true));
327  for (unsigned i = 1, NumOps = MBBI->getNumOperands(); i != NumOps; ++i)
328  NewInstr.add(MBBI->getOperand(i));
329  MachineBasicBlock::iterator NewMBBI = MBB->insertAfter(MBBI, NewInstr);
330  MBB->erase(MBBI);
331  MBBI = NewMBBI;
332  }
333  MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)).addImm(Wide).setMIFlags(Flags);
334  break;
335  }
336 
337  case ARM::tBLXr: // blx r12 (__chkstk)
338  MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))
339  .addImm(/*Wide=*/0)
340  .setMIFlags(Flags);
341  break;
342 
343  case ARM::t2MOVi32imm: // movw+movt
344  // This pseudo instruction expands into two mov instructions. If the
345  // second operand is a symbol reference, this will stay as two wide
346  // instructions, movw+movt. If they're immediates, the first one can
347  // end up as a narrow mov though.
348  // As two SEH instructions are appended here, they won't get interleaved
349  // between the two final movw/movt instructions, but it doesn't make any
350  // practical difference.
351  MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))
352  .addImm(/*Wide=*/1)
353  .setMIFlags(Flags);
354  MBB->insertAfter(MBBI, MIB);
355  MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop))
356  .addImm(/*Wide=*/1)
357  .setMIFlags(Flags);
358  break;
359 
360  case ARM::t2LDMIA_RET:
361  case ARM::t2LDMIA_UPD:
362  case ARM::t2STMDB_UPD: {
363  unsigned Mask = 0;
364  bool Wide = false;
365  for (unsigned i = 4, NumOps = MBBI->getNumOperands(); i != NumOps; ++i) {
366  const MachineOperand &MO = MBBI->getOperand(i);
367  if (!MO.isReg() || MO.isImplicit())
368  continue;
369  unsigned Reg = RegInfo->getSEHRegNum(MO.getReg());
370  if (Reg == 15)
371  Reg = 14;
372  if (Reg >= 8 && Reg <= 13)
373  Wide = true;
374  else if (Opc == ARM::t2LDMIA_UPD && Reg == 14)
375  Wide = true;
376  Mask |= 1 << Reg;
377  }
378  if (!Wide) {
379  unsigned NewOpc;
380  switch (Opc) {
381  case ARM::t2LDMIA_RET:
382  NewOpc = ARM::tPOP_RET;
383  break;
384  case ARM::t2LDMIA_UPD:
385  NewOpc = ARM::tPOP;
386  break;
387  case ARM::t2STMDB_UPD:
388  NewOpc = ARM::tPUSH;
389  break;
390  default:
391  llvm_unreachable("");
392  }
393  MachineInstrBuilder NewInstr =
394  BuildMI(MF, DL, TII.get(NewOpc)).setMIFlags(MBBI->getFlags());
395  for (unsigned i = 2, NumOps = MBBI->getNumOperands(); i != NumOps; ++i)
396  NewInstr.add(MBBI->getOperand(i));
397  MachineBasicBlock::iterator NewMBBI = MBB->insertAfter(MBBI, NewInstr);
398  MBB->erase(MBBI);
399  MBBI = NewMBBI;
400  }
401  unsigned SEHOpc =
402  (Opc == ARM::t2LDMIA_RET) ? ARM::SEH_SaveRegs_Ret : ARM::SEH_SaveRegs;
403  MIB = BuildMI(MF, DL, TII.get(SEHOpc))
404  .addImm(Mask)
405  .addImm(Wide ? 1 : 0)
406  .setMIFlags(Flags);
407  break;
408  }
409  case ARM::VSTMDDB_UPD:
410  case ARM::VLDMDIA_UPD: {
411  int First = -1, Last = 0;
412  for (unsigned i = 4, NumOps = MBBI->getNumOperands(); i != NumOps; ++i) {
413  const MachineOperand &MO = MBBI->getOperand(i);
414  unsigned Reg = RegInfo->getSEHRegNum(MO.getReg());
415  if (First == -1)
416  First = Reg;
417  Last = Reg;
418  }
419  MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveFRegs))
420  .addImm(First)
421  .addImm(Last)
422  .setMIFlags(Flags);
423  break;
424  }
425  case ARM::tSUBspi:
426  case ARM::tADDspi:
427  MIB = BuildMI(MF, DL, TII.get(ARM::SEH_StackAlloc))
428  .addImm(MBBI->getOperand(2).getImm() * 4)
429  .addImm(/*Wide=*/0)
430  .setMIFlags(Flags);
431  break;
432  case ARM::t2SUBspImm:
433  case ARM::t2SUBspImm12:
434  case ARM::t2ADDspImm:
435  case ARM::t2ADDspImm12:
436  MIB = BuildMI(MF, DL, TII.get(ARM::SEH_StackAlloc))
437  .addImm(MBBI->getOperand(2).getImm())
438  .addImm(/*Wide=*/1)
439  .setMIFlags(Flags);
440  break;
441 
442  case ARM::tMOVr:
443  if (MBBI->getOperand(1).getReg() == ARM::SP &&
444  (Flags & MachineInstr::FrameSetup)) {
445  unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
446  MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveSP))
447  .addImm(Reg)
448  .setMIFlags(Flags);
449  } else if (MBBI->getOperand(0).getReg() == ARM::SP &&
450  (Flags & MachineInstr::FrameDestroy)) {
451  unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
452  MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveSP))
453  .addImm(Reg)
454  .setMIFlags(Flags);
455  } else {
456  report_fatal_error("No SEH Opcode for MOV");
457  }
458  break;
459 
460  case ARM::tBX_RET:
461  case ARM::TCRETURNri:
462  MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop_Ret))
463  .addImm(/*Wide=*/0)
464  .setMIFlags(Flags);
465  break;
466 
467  case ARM::TCRETURNdi:
468  MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop_Ret))
469  .addImm(/*Wide=*/1)
470  .setMIFlags(Flags);
471  break;
472  }
473  return MBB->insertAfter(MBBI, MIB);
474 }
475 
478  if (MBBI == MBB.begin())
480  return std::prev(MBBI);
481 }
482 
485  const MachineBasicBlock::iterator &End,
486  const ARMBaseInstrInfo &TII, unsigned MIFlags) {
487  if (Start.isValid())
488  Start = std::next(Start);
489  else
490  Start = MBB.begin();
491 
492  for (auto MI = Start; MI != End;) {
493  auto Next = std::next(MI);
494  // Check if this instruction already has got a SEH opcode added. In that
495  // case, don't do this generic mapping.
496  if (Next != End && isSEHInstruction(*Next)) {
497  MI = std::next(Next);
498  while (MI != End && isSEHInstruction(*MI))
499  ++MI;
500  continue;
501  }
502  insertSEH(MI, TII, MIFlags);
503  MI = Next;
504  }
505 }
506 
509  const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg,
510  unsigned SrcReg, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags,
511  ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
512  if (isARM)
513  emitARMRegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
514  Pred, PredReg, TII, MIFlags);
515  else
516  emitT2RegPlusImmediate(MBB, MBBI, dl, DestReg, SrcReg, NumBytes,
517  Pred, PredReg, TII, MIFlags);
518 }
519 
520 static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB,
522  const ARMBaseInstrInfo &TII, int NumBytes,
523  unsigned MIFlags = MachineInstr::NoFlags,
525  unsigned PredReg = 0) {
526  emitRegPlusImmediate(isARM, MBB, MBBI, dl, TII, ARM::SP, ARM::SP, NumBytes,
527  MIFlags, Pred, PredReg);
528 }
529 
530 static int sizeOfSPAdjustment(const MachineInstr &MI) {
531  int RegSize;
532  switch (MI.getOpcode()) {
533  case ARM::VSTMDDB_UPD:
534  RegSize = 8;
535  break;
536  case ARM::STMDB_UPD:
537  case ARM::t2STMDB_UPD:
538  RegSize = 4;
539  break;
540  case ARM::t2STR_PRE:
541  case ARM::STR_PRE_IMM:
542  return 4;
543  default:
544  llvm_unreachable("Unknown push or pop like instruction");
545  }
546 
547  int count = 0;
548  // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
549  // pred) so the list starts at 4.
550  for (int i = MI.getNumOperands() - 1; i >= 4; --i)
551  count += RegSize;
552  return count;
553 }
554 
556  size_t StackSizeInBytes) {
557  const MachineFrameInfo &MFI = MF.getFrameInfo();
558  const Function &F = MF.getFunction();
559  unsigned StackProbeSize = (MFI.getStackProtectorIndex() > 0) ? 4080 : 4096;
560  if (F.hasFnAttribute("stack-probe-size"))
561  F.getFnAttribute("stack-probe-size")
562  .getValueAsString()
563  .getAsInteger(0, StackProbeSize);
564  return (StackSizeInBytes >= StackProbeSize) &&
565  !F.hasFnAttribute("no-stack-arg-probe");
566 }
567 
568 namespace {
569 
570 struct StackAdjustingInsts {
571  struct InstInfo {
573  unsigned SPAdjust;
574  bool BeforeFPSet;
575  };
576 
578 
579  void addInst(MachineBasicBlock::iterator I, unsigned SPAdjust,
580  bool BeforeFPSet = false) {
581  InstInfo Info = {I, SPAdjust, BeforeFPSet};
582  Insts.push_back(Info);
583  }
584 
585  void addExtraBytes(const MachineBasicBlock::iterator I, unsigned ExtraBytes) {
586  auto Info =
587  llvm::find_if(Insts, [&](InstInfo &Info) { return Info.I == I; });
588  assert(Info != Insts.end() && "invalid sp adjusting instruction");
589  Info->SPAdjust += ExtraBytes;
590  }
591 
592  void emitDefCFAOffsets(MachineBasicBlock &MBB, const DebugLoc &dl,
593  const ARMBaseInstrInfo &TII, bool HasFP) {
594  MachineFunction &MF = *MBB.getParent();
595  unsigned CFAOffset = 0;
596  for (auto &Info : Insts) {
597  if (HasFP && !Info.BeforeFPSet)
598  return;
599 
600  CFAOffset += Info.SPAdjust;
601  unsigned CFIIndex = MF.addFrameInst(
602  MCCFIInstruction::cfiDefCfaOffset(nullptr, CFAOffset));
603  BuildMI(MBB, std::next(Info.I), dl,
604  TII.get(TargetOpcode::CFI_INSTRUCTION))
605  .addCFIIndex(CFIIndex)
607  }
608  }
609 };
610 
611 } // end anonymous namespace
612 
613 /// Emit an instruction sequence that will align the address in
614 /// register Reg by zero-ing out the lower bits. For versions of the
615 /// architecture that support Neon, this must be done in a single
616 /// instruction, since skipAlignedDPRCS2Spills assumes it is done in a
617 /// single instruction. That function only gets called when optimizing
618 /// spilling of D registers on a core with the Neon instruction set
619 /// present.
621  const TargetInstrInfo &TII,
624  const DebugLoc &DL, const unsigned Reg,
625  const Align Alignment,
626  const bool MustBeSingleInstruction) {
627  const ARMSubtarget &AST = MF.getSubtarget<ARMSubtarget>();
628  const bool CanUseBFC = AST.hasV6T2Ops() || AST.hasV7Ops();
629  const unsigned AlignMask = Alignment.value() - 1U;
630  const unsigned NrBitsToZero = Log2(Alignment);
631  assert(!AFI->isThumb1OnlyFunction() && "Thumb1 not supported");
632  if (!AFI->isThumbFunction()) {
633  // if the BFC instruction is available, use that to zero the lower
634  // bits:
635  // bfc Reg, #0, log2(Alignment)
636  // otherwise use BIC, if the mask to zero the required number of bits
637  // can be encoded in the bic immediate field
638  // bic Reg, Reg, Alignment-1
639  // otherwise, emit
640  // lsr Reg, Reg, log2(Alignment)
641  // lsl Reg, Reg, log2(Alignment)
642  if (CanUseBFC) {
643  BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
645  .addImm(~AlignMask)
646  .add(predOps(ARMCC::AL));
647  } else if (AlignMask <= 255) {
648  BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
650  .addImm(AlignMask)
652  .add(condCodeOp());
653  } else {
654  assert(!MustBeSingleInstruction &&
655  "Shouldn't call emitAligningInstructions demanding a single "
656  "instruction to be emitted for large stack alignment for a target "
657  "without BFC.");
658  BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
660  .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero))
662  .add(condCodeOp());
663  BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
665  .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero))
667  .add(condCodeOp());
668  }
669  } else {
670  // Since this is only reached for Thumb-2 targets, the BFC instruction
671  // should always be available.
672  assert(CanUseBFC);
673  BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)
675  .addImm(~AlignMask)
676  .add(predOps(ARMCC::AL));
677  }
678 }
679 
680 /// We need the offset of the frame pointer relative to other MachineFrameInfo
681 /// offsets which are encoded relative to SP at function begin.
682 /// See also emitPrologue() for how the FP is set up.
683 /// Unfortunately we cannot determine this value in determineCalleeSaves() yet
684 /// as assignCalleeSavedSpillSlots() hasn't run at this point. Instead we use
685 /// this to produce a conservative estimate that we check in an assert() later.
686 static int getMaxFPOffset(const ARMSubtarget &STI, const ARMFunctionInfo &AFI,
687  const MachineFunction &MF) {
688  // For Thumb1, push.w isn't available, so the first push will always push
689  // r7 and lr onto the stack first.
690  if (AFI.isThumb1OnlyFunction())
691  return -AFI.getArgRegsSaveSize() - (2 * 4);
692  // This is a conservative estimation: Assume the frame pointer being r7 and
693  // pc("r15") up to r8 getting spilled before (= 8 registers).
694  int MaxRegBytes = 8 * 4;
695  if (STI.splitFramePointerPush(MF)) {
696  // Here, r11 can be stored below all of r4-r15 (3 registers more than
697  // above), plus d8-d15.
698  MaxRegBytes = 11 * 4 + 8 * 8;
699  }
700  int FPCXTSaveSize =
701  (STI.hasV8_1MMainlineOps() && AFI.isCmseNSEntryFunction()) ? 4 : 0;
702  return -FPCXTSaveSize - AFI.getArgRegsSaveSize() - MaxRegBytes;
703 }
704 
706  MachineBasicBlock &MBB) const {
708  MachineFrameInfo &MFI = MF.getFrameInfo();
710  MachineModuleInfo &MMI = MF.getMMI();
711  MCContext &Context = MMI.getContext();
712  const TargetMachine &TM = MF.getTarget();
713  const MCRegisterInfo *MRI = Context.getRegisterInfo();
714  const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();
715  const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
716  assert(!AFI->isThumb1OnlyFunction() &&
717  "This emitPrologue does not support Thumb1!");
718  bool isARM = !AFI->isThumbFunction();
719  Align Alignment = STI.getFrameLowering()->getStackAlign();
720  unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
721  unsigned NumBytes = MFI.getStackSize();
722  const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
723  int FPCXTSaveSize = 0;
724  bool NeedsWinCFI = needsWinCFI(MF);
725 
726  // Debug location must be unknown since the first debug location is used
727  // to determine the end of the prologue.
728  DebugLoc dl;
729 
730  Register FramePtr = RegInfo->getFrameRegister(MF);
731 
732  // Determine the sizes of each callee-save spill areas and record which frame
733  // belongs to which callee-save spill areas.
734  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
735  int FramePtrSpillFI = 0;
736  int D8SpillFI = 0;
737 
738  // All calls are tail calls in GHC calling conv, and functions have no
739  // prologue/epilogue.
741  return;
742 
743  StackAdjustingInsts DefCFAOffsetCandidates;
744  bool HasFP = hasFP(MF);
745 
746  if (!AFI->hasStackFrame() &&
747  (!STI.isTargetWindows() || !WindowsRequiresStackProbe(MF, NumBytes))) {
748  if (NumBytes != 0) {
749  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
751  DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes, true);
752  }
753  if (!NeedsWinCFI)
754  DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
755  if (NeedsWinCFI && MBBI != MBB.begin()) {
757  BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_PrologEnd))
759  MF.setHasWinCFI(true);
760  }
761  return;
762  }
763 
764  // Determine spill area sizes.
765  if (STI.splitFramePointerPush(MF)) {
766  for (const CalleeSavedInfo &I : CSI) {
767  Register Reg = I.getReg();
768  int FI = I.getFrameIdx();
769  switch (Reg) {
770  case ARM::R11:
771  case ARM::LR:
772  if (Reg == FramePtr)
773  FramePtrSpillFI = FI;
774  GPRCS2Size += 4;
775  break;
776  case ARM::R0:
777  case ARM::R1:
778  case ARM::R2:
779  case ARM::R3:
780  case ARM::R4:
781  case ARM::R5:
782  case ARM::R6:
783  case ARM::R7:
784  case ARM::R8:
785  case ARM::R9:
786  case ARM::R10:
787  case ARM::R12:
788  GPRCS1Size += 4;
789  break;
790  case ARM::FPCXTNS:
791  FPCXTSaveSize = 4;
792  break;
793  default:
794  // This is a DPR. Exclude the aligned DPRCS2 spills.
795  if (Reg == ARM::D8)
796  D8SpillFI = FI;
797  if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
798  DPRCSSize += 8;
799  }
800  }
801  } else {
802  for (const CalleeSavedInfo &I : CSI) {
803  Register Reg = I.getReg();
804  int FI = I.getFrameIdx();
805  switch (Reg) {
806  case ARM::R8:
807  case ARM::R9:
808  case ARM::R10:
809  case ARM::R11:
810  case ARM::R12:
811  if (STI.splitFramePushPop(MF)) {
812  GPRCS2Size += 4;
813  break;
814  }
816  case ARM::R0:
817  case ARM::R1:
818  case ARM::R2:
819  case ARM::R3:
820  case ARM::R4:
821  case ARM::R5:
822  case ARM::R6:
823  case ARM::R7:
824  case ARM::LR:
825  if (Reg == FramePtr)
826  FramePtrSpillFI = FI;
827  GPRCS1Size += 4;
828  break;
829  case ARM::FPCXTNS:
830  FPCXTSaveSize = 4;
831  break;
832  default:
833  // This is a DPR. Exclude the aligned DPRCS2 spills.
834  if (Reg == ARM::D8)
835  D8SpillFI = FI;
836  if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())
837  DPRCSSize += 8;
838  }
839  }
840  }
841 
842  MachineBasicBlock::iterator LastPush = MBB.end(), GPRCS1Push, GPRCS2Push;
843 
844  // Move past the PAC computation.
845  if (AFI->shouldSignReturnAddress())
846  LastPush = MBBI++;
847 
848  // Move past FPCXT area.
849  if (FPCXTSaveSize > 0) {
850  LastPush = MBBI++;
851  DefCFAOffsetCandidates.addInst(LastPush, FPCXTSaveSize, true);
852  }
853 
854  // Allocate the vararg register save area.
855  if (ArgRegsSaveSize) {
856  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
858  LastPush = std::prev(MBBI);
859  DefCFAOffsetCandidates.addInst(LastPush, ArgRegsSaveSize, true);
860  }
861 
862  // Move past area 1.
863  if (GPRCS1Size > 0) {
864  GPRCS1Push = LastPush = MBBI++;
865  DefCFAOffsetCandidates.addInst(LastPush, GPRCS1Size, true);
866  }
867 
868  // Determine starting offsets of spill areas.
869  unsigned FPCXTOffset = NumBytes - ArgRegsSaveSize - FPCXTSaveSize;
870  unsigned GPRCS1Offset = FPCXTOffset - GPRCS1Size;
871  unsigned GPRCS2Offset = GPRCS1Offset - GPRCS2Size;
872  Align DPRAlign = DPRCSSize ? std::min(Align(8), Alignment) : Align(4);
873  unsigned DPRGapSize = GPRCS1Size + FPCXTSaveSize + ArgRegsSaveSize;
874  if (!STI.splitFramePointerPush(MF)) {
875  DPRGapSize += GPRCS2Size;
876  }
877  DPRGapSize %= DPRAlign.value();
878 
879  unsigned DPRCSOffset;
880  if (STI.splitFramePointerPush(MF)) {
881  DPRCSOffset = GPRCS1Offset - DPRGapSize - DPRCSSize;
882  GPRCS2Offset = DPRCSOffset - GPRCS2Size;
883  } else {
884  DPRCSOffset = GPRCS2Offset - DPRGapSize - DPRCSSize;
885  }
886  int FramePtrOffsetInPush = 0;
887  if (HasFP) {
888  int FPOffset = MFI.getObjectOffset(FramePtrSpillFI);
889  assert(getMaxFPOffset(STI, *AFI, MF) <= FPOffset &&
890  "Max FP estimation is wrong");
891  FramePtrOffsetInPush = FPOffset + ArgRegsSaveSize + FPCXTSaveSize;
892  AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
893  NumBytes);
894  }
895  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
896  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
897  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
898 
899  // Move past area 2.
900  if (GPRCS2Size > 0 && !STI.splitFramePointerPush(MF)) {
901  GPRCS2Push = LastPush = MBBI++;
902  DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size);
903  }
904 
905  // Prolog/epilog inserter assumes we correctly align DPRs on the stack, so our
906  // .cfi_offset operations will reflect that.
907  if (DPRGapSize) {
908  assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs");
909  if (LastPush != MBB.end() &&
910  tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, DPRGapSize))
911  DefCFAOffsetCandidates.addExtraBytes(LastPush, DPRGapSize);
912  else {
913  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRGapSize,
915  DefCFAOffsetCandidates.addInst(std::prev(MBBI), DPRGapSize);
916  }
917  }
918 
919  // Move past area 3.
920  if (DPRCSSize > 0) {
921  // Since vpush register list cannot have gaps, there may be multiple vpush
922  // instructions in the prologue.
923  while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
924  DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(*MBBI));
925  LastPush = MBBI++;
926  }
927  }
928 
929  // Move past the aligned DPRCS2 area.
930  if (AFI->getNumAlignedDPRCS2Regs() > 0) {
932  // The code inserted by emitAlignedDPRCS2Spills realigns the stack, and
933  // leaves the stack pointer pointing to the DPRCS2 area.
934  //
935  // Adjust NumBytes to represent the stack slots below the DPRCS2 area.
936  NumBytes += MFI.getObjectOffset(D8SpillFI);
937  } else
938  NumBytes = DPRCSOffset;
939 
940  if (GPRCS2Size > 0 && STI.splitFramePointerPush(MF)) {
941  GPRCS2Push = LastPush = MBBI++;
942  DefCFAOffsetCandidates.addInst(LastPush, GPRCS2Size);
943  }
944 
945  bool NeedsWinCFIStackAlloc = NeedsWinCFI;
946  if (STI.splitFramePointerPush(MF) && HasFP)
947  NeedsWinCFIStackAlloc = false;
948 
949  if (STI.isTargetWindows() && WindowsRequiresStackProbe(MF, NumBytes)) {
950  uint32_t NumWords = NumBytes >> 2;
951 
952  if (NumWords < 65536) {
953  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
954  .addImm(NumWords)
956  .add(predOps(ARMCC::AL));
957  } else {
958  // Split into two instructions here, instead of using t2MOVi32imm,
959  // to allow inserting accurate SEH instructions (including accurate
960  // instruction size for each of them).
961  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
962  .addImm(NumWords & 0xffff)
964  .add(predOps(ARMCC::AL));
965  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), ARM::R4)
966  .addReg(ARM::R4)
967  .addImm(NumWords >> 16)
969  .add(predOps(ARMCC::AL));
970  }
971 
972  switch (TM.getCodeModel()) {
973  case CodeModel::Tiny:
974  llvm_unreachable("Tiny code model not available on ARM.");
975  case CodeModel::Small:
976  case CodeModel::Medium:
977  case CodeModel::Kernel:
978  BuildMI(MBB, MBBI, dl, TII.get(ARM::tBL))
980  .addExternalSymbol("__chkstk")
983  break;
984  case CodeModel::Large:
985  BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
986  .addExternalSymbol("__chkstk")
988 
989  BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
991  .addReg(ARM::R12, RegState::Kill)
994  break;
995  }
996 
997  MachineInstrBuilder Instr, SEH;
998  Instr = BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP)
999  .addReg(ARM::SP, RegState::Kill)
1002  .add(predOps(ARMCC::AL))
1003  .add(condCodeOp());
1004  if (NeedsWinCFIStackAlloc) {
1005  SEH = BuildMI(MF, dl, TII.get(ARM::SEH_StackAlloc))
1006  .addImm(NumBytes)
1007  .addImm(/*Wide=*/1)
1009  MBB.insertAfter(Instr, SEH);
1010  }
1011  NumBytes = 0;
1012  }
1013 
1014  if (NumBytes) {
1015  // Adjust SP after all the callee-save spills.
1016  if (AFI->getNumAlignedDPRCS2Regs() == 0 &&
1017  tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, NumBytes))
1018  DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);
1019  else {
1020  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
1022  DefCFAOffsetCandidates.addInst(std::prev(MBBI), NumBytes);
1023  }
1024 
1025  if (HasFP && isARM)
1026  // Restore from fp only in ARM mode: e.g. sub sp, r7, #24
1027  // Note it's not safe to do this in Thumb2 mode because it would have
1028  // taken two instructions:
1029  // mov sp, r7
1030  // sub sp, #24
1031  // If an interrupt is taken between the two instructions, then sp is in
1032  // an inconsistent state (pointing to the middle of callee-saved area).
1033  // The interrupt handler can end up clobbering the registers.
1034  AFI->setShouldRestoreSPFromFP(true);
1035  }
1036 
1037  // Set FP to point to the stack slot that contains the previous FP.
1038  // For iOS, FP is R7, which has now been stored in spill area 1.
1039  // Otherwise, if this is not iOS, all the callee-saved registers go
1040  // into spill area 1, including the FP in R11. In either case, it
1041  // is in area one and the adjustment needs to take place just after
1042  // that push.
1043  // FIXME: The above is not necessary true when PACBTI is enabled.
1044  // AAPCS requires use of R11, and PACBTI gets in the way of regular pushes,
1045  // so FP ends up on area two.
1046  MachineBasicBlock::iterator AfterPush;
1047  if (HasFP) {
1048  AfterPush = std::next(GPRCS1Push);
1049  unsigned PushSize = sizeOfSPAdjustment(*GPRCS1Push);
1050  int FPOffset = PushSize + FramePtrOffsetInPush;
1051  if (STI.splitFramePointerPush(MF)) {
1052  AfterPush = std::next(GPRCS2Push);
1053  emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush, dl, TII,
1054  FramePtr, ARM::SP, 0, MachineInstr::FrameSetup);
1055  } else {
1056  emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, AfterPush, dl, TII,
1057  FramePtr, ARM::SP, FPOffset,
1059  }
1060  if (!NeedsWinCFI) {
1061  if (FramePtrOffsetInPush + PushSize != 0) {
1062  unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
1063  nullptr, MRI->getDwarfRegNum(FramePtr, true),
1064  FPCXTSaveSize + ArgRegsSaveSize - FramePtrOffsetInPush));
1065  BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1066  .addCFIIndex(CFIIndex)
1068  } else {
1069  unsigned CFIIndex =
1071  nullptr, MRI->getDwarfRegNum(FramePtr, true)));
1072  BuildMI(MBB, AfterPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1073  .addCFIIndex(CFIIndex)
1075  }
1076  }
1077  }
1078 
1079  // Emit a SEH opcode indicating the prologue end. The rest of the prologue
1080  // instructions below don't need to be replayed to unwind the stack.
1081  if (NeedsWinCFI && MBBI != MBB.begin()) {
1083  if (HasFP && STI.splitFramePointerPush(MF))
1084  End = AfterPush;
1086  BuildMI(MBB, End, dl, TII.get(ARM::SEH_PrologEnd))
1088  MF.setHasWinCFI(true);
1089  }
1090 
1091  // Now that the prologue's actual instructions are finalised, we can insert
1092  // the necessary DWARF cf instructions to describe the situation. Start by
1093  // recording where each register ended up:
1094  if (GPRCS1Size > 0 && !NeedsWinCFI) {
1095  MachineBasicBlock::iterator Pos = std::next(GPRCS1Push);
1096  int CFIIndex;
1097  for (const auto &Entry : CSI) {
1098  Register Reg = Entry.getReg();
1099  int FI = Entry.getFrameIdx();
1100  switch (Reg) {
1101  case ARM::R8:
1102  case ARM::R9:
1103  case ARM::R10:
1104  case ARM::R11:
1105  case ARM::R12:
1106  if (STI.splitFramePushPop(MF))
1107  break;
1109  case ARM::R0:
1110  case ARM::R1:
1111  case ARM::R2:
1112  case ARM::R3:
1113  case ARM::R4:
1114  case ARM::R5:
1115  case ARM::R6:
1116  case ARM::R7:
1117  case ARM::LR:
1119  nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
1120  BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1121  .addCFIIndex(CFIIndex)
1123  break;
1124  }
1125  }
1126  }
1127 
1128  if (GPRCS2Size > 0 && !NeedsWinCFI) {
1129  MachineBasicBlock::iterator Pos = std::next(GPRCS2Push);
1130  for (const auto &Entry : CSI) {
1131  Register Reg = Entry.getReg();
1132  int FI = Entry.getFrameIdx();
1133  switch (Reg) {
1134  case ARM::R8:
1135  case ARM::R9:
1136  case ARM::R10:
1137  case ARM::R11:
1138  case ARM::R12:
1139  if (STI.splitFramePushPop(MF)) {
1140  unsigned DwarfReg = MRI->getDwarfRegNum(
1141  Reg == ARM::R12 ? ARM::RA_AUTH_CODE : Reg, true);
1142  unsigned Offset = MFI.getObjectOffset(FI);
1143  unsigned CFIIndex = MF.addFrameInst(
1144  MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
1145  BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1146  .addCFIIndex(CFIIndex)
1148  }
1149  break;
1150  }
1151  }
1152  }
1153 
1154  if (DPRCSSize > 0 && !NeedsWinCFI) {
1155  // Since vpush register list cannot have gaps, there may be multiple vpush
1156  // instructions in the prologue.
1157  MachineBasicBlock::iterator Pos = std::next(LastPush);
1158  for (const auto &Entry : CSI) {
1159  Register Reg = Entry.getReg();
1160  int FI = Entry.getFrameIdx();
1161  if ((Reg >= ARM::D0 && Reg <= ARM::D31) &&
1162  (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
1163  unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
1164  unsigned Offset = MFI.getObjectOffset(FI);
1165  unsigned CFIIndex = MF.addFrameInst(
1166  MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
1167  BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
1168  .addCFIIndex(CFIIndex)
1170  }
1171  }
1172  }
1173 
1174  // Now we can emit descriptions of where the canonical frame address was
1175  // throughout the process. If we have a frame pointer, it takes over the job
1176  // half-way through, so only the first few .cfi_def_cfa_offset instructions
1177  // actually get emitted.
1178  if (!NeedsWinCFI)
1179  DefCFAOffsetCandidates.emitDefCFAOffsets(MBB, dl, TII, HasFP);
1180 
1181  if (STI.isTargetELF() && hasFP(MF))
1183  AFI->getFramePtrSpillOffset());
1184 
1185  AFI->setFPCXTSaveAreaSize(FPCXTSaveSize);
1186  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1187  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1188  AFI->setDPRCalleeSavedGapSize(DPRGapSize);
1189  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1190 
1191  // If we need dynamic stack realignment, do it here. Be paranoid and make
1192  // sure if we also have VLAs, we have a base pointer for frame access.
1193  // If aligned NEON registers were spilled, the stack has already been
1194  // realigned.
1195  if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->hasStackRealignment(MF)) {
1196  Align MaxAlign = MFI.getMaxAlign();
1197  assert(!AFI->isThumb1OnlyFunction());
1198  if (!AFI->isThumbFunction()) {
1199  emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::SP, MaxAlign,
1200  false);
1201  } else {
1202  // We cannot use sp as source/dest register here, thus we're using r4 to
1203  // perform the calculations. We're emitting the following sequence:
1204  // mov r4, sp
1205  // -- use emitAligningInstructions to produce best sequence to zero
1206  // -- out lower bits in r4
1207  // mov sp, r4
1208  // FIXME: It will be better just to find spare register here.
1209  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
1210  .addReg(ARM::SP, RegState::Kill)
1211  .add(predOps(ARMCC::AL));
1212  emitAligningInstructions(MF, AFI, TII, MBB, MBBI, dl, ARM::R4, MaxAlign,
1213  false);
1214  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
1216  .add(predOps(ARMCC::AL));
1217  }
1218 
1219  AFI->setShouldRestoreSPFromFP(true);
1220  }
1221 
1222  // If we need a base pointer, set it up here. It's whatever the value
1223  // of the stack pointer is at this point. Any variable size objects
1224  // will be allocated after this, so we can still use the base pointer
1225  // to reference locals.
1226  // FIXME: Clarify FrameSetup flags here.
1227  if (RegInfo->hasBasePointer(MF)) {
1228  if (isARM)
1229  BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister())
1230  .addReg(ARM::SP)
1231  .add(predOps(ARMCC::AL))
1232  .add(condCodeOp());
1233  else
1234  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister())
1235  .addReg(ARM::SP)
1236  .add(predOps(ARMCC::AL));
1237  }
1238 
1239  // If the frame has variable sized objects then the epilogue must restore
1240  // the sp from fp. We can assume there's an FP here since hasFP already
1241  // checks for hasVarSizedObjects.
1242  if (MFI.hasVarSizedObjects())
1243  AFI->setShouldRestoreSPFromFP(true);
1244 }
1245 
1247  MachineBasicBlock &MBB) const {
1248  MachineFrameInfo &MFI = MF.getFrameInfo();
1250  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1251  const ARMBaseInstrInfo &TII =
1252  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
1253  assert(!AFI->isThumb1OnlyFunction() &&
1254  "This emitEpilogue does not support Thumb1!");
1255  bool isARM = !AFI->isThumbFunction();
1256 
1257  // Amount of stack space we reserved next to incoming args for either
1258  // varargs registers or stack arguments in tail calls made by this function.
1259  unsigned ReservedArgStack = AFI->getArgRegsSaveSize();
1260 
1261  // How much of the stack used by incoming arguments this function is expected
1262  // to restore in this particular epilogue.
1263  int IncomingArgStackToRestore = getArgumentStackToRestore(MF, MBB);
1264  int NumBytes = (int)MFI.getStackSize();
1265  Register FramePtr = RegInfo->getFrameRegister(MF);
1266 
1267  // All calls are tail calls in GHC calling conv, and functions have no
1268  // prologue/epilogue.
1270  return;
1271 
1272  // First put ourselves on the first (from top) terminator instructions.
1274  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1275 
1276  MachineBasicBlock::iterator RangeStart;
1277  if (!AFI->hasStackFrame()) {
1278  if (MF.hasWinCFI()) {
1279  BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_EpilogStart))
1281  RangeStart = initMBBRange(MBB, MBBI);
1282  }
1283 
1284  if (NumBytes + IncomingArgStackToRestore != 0)
1285  emitSPUpdate(isARM, MBB, MBBI, dl, TII,
1286  NumBytes + IncomingArgStackToRestore,
1288  } else {
1289  // Unwind MBBI to point to first LDR / VLDRD.
1290  if (MBBI != MBB.begin()) {
1291  do {
1292  --MBBI;
1293  } while (MBBI != MBB.begin() &&
1294  MBBI->getFlag(MachineInstr::FrameDestroy));
1295  if (!MBBI->getFlag(MachineInstr::FrameDestroy))
1296  ++MBBI;
1297  }
1298 
1299  if (MF.hasWinCFI()) {
1300  BuildMI(MBB, MBBI, dl, TII.get(ARM::SEH_EpilogStart))
1302  RangeStart = initMBBRange(MBB, MBBI);
1303  }
1304 
1305  // Move SP to start of FP callee save spill area.
1306  NumBytes -= (ReservedArgStack +
1307  AFI->getFPCXTSaveAreaSize() +
1310  AFI->getDPRCalleeSavedGapSize() +
1311  AFI->getDPRCalleeSavedAreaSize());
1312 
1313  // Reset SP based on frame pointer only if the stack frame extends beyond
1314  // frame pointer stack slot or target is ELF and the function has FP.
1315  if (AFI->shouldRestoreSPFromFP()) {
1316  NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1317  if (NumBytes) {
1318  if (isARM)
1319  emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1320  ARMCC::AL, 0, TII,
1322  else {
1323  // It's not possible to restore SP from FP in a single instruction.
1324  // For iOS, this looks like:
1325  // mov sp, r7
1326  // sub sp, #24
1327  // This is bad, if an interrupt is taken after the mov, sp is in an
1328  // inconsistent state.
1329  // Use the first callee-saved register as a scratch register.
1330  assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
1331  "No scratch register to restore SP from FP!");
1332  emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
1334  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
1335  .addReg(ARM::R4)
1336  .add(predOps(ARMCC::AL))
1338  }
1339  } else {
1340  // Thumb2 or ARM.
1341  if (isARM)
1342  BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1343  .addReg(FramePtr)
1344  .add(predOps(ARMCC::AL))
1345  .add(condCodeOp())
1347  else
1348  BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
1349  .addReg(FramePtr)
1350  .add(predOps(ARMCC::AL))
1352  }
1353  } else if (NumBytes &&
1354  !tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
1355  emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes,
1357 
1358  // Increment past our save areas.
1360  MBBI++;
1361 
1362  if (MBBI != MBB.end() && AFI->getDPRCalleeSavedAreaSize()) {
1363  MBBI++;
1364  // Since vpop register list cannot have gaps, there may be multiple vpop
1365  // instructions in the epilogue.
1366  while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VLDMDIA_UPD)
1367  MBBI++;
1368  }
1369  if (AFI->getDPRCalleeSavedGapSize()) {
1370  assert(AFI->getDPRCalleeSavedGapSize() == 4 &&
1371  "unexpected DPR alignment gap");
1372  emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedGapSize(),
1374  }
1375 
1377  MBBI++;
1378  if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
1379 
1380  if (ReservedArgStack || IncomingArgStackToRestore) {
1381  assert((int)ReservedArgStack + IncomingArgStackToRestore >= 0 &&
1382  "attempting to restore negative stack amount");
1383  emitSPUpdate(isARM, MBB, MBBI, dl, TII,
1384  ReservedArgStack + IncomingArgStackToRestore,
1386  }
1387 
1388  // Validate PAC, It should have been already popped into R12. For CMSE entry
1389  // function, the validation instruction is emitted during expansion of the
1390  // tBXNS_RET, since the validation must use the value of SP at function
1391  // entry, before saving, resp. after restoring, FPCXTNS.
1392  if (AFI->shouldSignReturnAddress() && !AFI->isCmseNSEntryFunction())
1393  BuildMI(MBB, MBBI, DebugLoc(), STI.getInstrInfo()->get(ARM::t2AUT));
1394  }
1395 
1396  if (MF.hasWinCFI()) {
1398  BuildMI(MBB, MBB.end(), dl, TII.get(ARM::SEH_EpilogEnd))
1400  }
1401 }
1402 
1403 /// getFrameIndexReference - Provide a base+offset reference to an FI slot for
1404 /// debug info. It's the same as what we use for resolving the code-gen
1405 /// references for now. FIXME: This can go wrong when references are
1406 /// SP-relative and simple call frames aren't used.
1408  int FI,
1409  Register &FrameReg) const {
1410  return StackOffset::getFixed(ResolveFrameIndexReference(MF, FI, FrameReg, 0));
1411 }
1412 
1414  int FI, Register &FrameReg,
1415  int SPAdj) const {
1416  const MachineFrameInfo &MFI = MF.getFrameInfo();
1417  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
1418  MF.getSubtarget().getRegisterInfo());
1419  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1420  int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize();
1421  int FPOffset = Offset - AFI->getFramePtrSpillOffset();
1422  bool isFixed = MFI.isFixedObjectIndex(FI);
1423 
1424  FrameReg = ARM::SP;
1425  Offset += SPAdj;
1426 
1427  // SP can move around if there are allocas. We may also lose track of SP
1428  // when emergency spilling inside a non-reserved call frame setup.
1429  bool hasMovingSP = !hasReservedCallFrame(MF);
1430 
1431  // When dynamically realigning the stack, use the frame pointer for
1432  // parameters, and the stack/base pointer for locals.
1433  if (RegInfo->hasStackRealignment(MF)) {
1434  assert(hasFP(MF) && "dynamic stack realignment without a FP!");
1435  if (isFixed) {
1436  FrameReg = RegInfo->getFrameRegister(MF);
1437  Offset = FPOffset;
1438  } else if (hasMovingSP) {
1439  assert(RegInfo->hasBasePointer(MF) &&
1440  "VLAs and dynamic stack alignment, but missing base pointer!");
1441  FrameReg = RegInfo->getBaseRegister();
1442  Offset -= SPAdj;
1443  }
1444  return Offset;
1445  }
1446 
1447  // If there is a frame pointer, use it when we can.
1448  if (hasFP(MF) && AFI->hasStackFrame()) {
1449  // Use frame pointer to reference fixed objects. Use it for locals if
1450  // there are VLAs (and thus the SP isn't reliable as a base).
1451  if (isFixed || (hasMovingSP && !RegInfo->hasBasePointer(MF))) {
1452  FrameReg = RegInfo->getFrameRegister(MF);
1453  return FPOffset;
1454  } else if (hasMovingSP) {
1455  assert(RegInfo->hasBasePointer(MF) && "missing base pointer!");
1456  if (AFI->isThumb2Function()) {
1457  // Try to use the frame pointer if we can, else use the base pointer
1458  // since it's available. This is handy for the emergency spill slot, in
1459  // particular.
1460  if (FPOffset >= -255 && FPOffset < 0) {
1461  FrameReg = RegInfo->getFrameRegister(MF);
1462  return FPOffset;
1463  }
1464  }
1465  } else if (AFI->isThumbFunction()) {
1466  // Prefer SP to base pointer, if the offset is suitably aligned and in
1467  // range as the effective range of the immediate offset is bigger when
1468  // basing off SP.
1469  // Use add <rd>, sp, #<imm8>
1470  // ldr <rd>, [sp, #<imm8>]
1471  if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020)
1472  return Offset;
1473  // In Thumb2 mode, the negative offset is very limited. Try to avoid
1474  // out of range references. ldr <rt>,[<rn>, #-<imm8>]
1475  if (AFI->isThumb2Function() && FPOffset >= -255 && FPOffset < 0) {
1476  FrameReg = RegInfo->getFrameRegister(MF);
1477  return FPOffset;
1478  }
1479  } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
1480  // Otherwise, use SP or FP, whichever is closer to the stack slot.
1481  FrameReg = RegInfo->getFrameRegister(MF);
1482  return FPOffset;
1483  }
1484  }
1485  // Use the base pointer if we have one.
1486  // FIXME: Maybe prefer sp on Thumb1 if it's legal and the offset is cheaper?
1487  // That can happen if we forced a base pointer for a large call frame.
1488  if (RegInfo->hasBasePointer(MF)) {
1489  FrameReg = RegInfo->getBaseRegister();
1490  Offset -= SPAdj;
1491  }
1492  return Offset;
1493 }
1494 
1495 void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
1498  unsigned StmOpc, unsigned StrOpc,
1499  bool NoGap, bool (*Func)(unsigned, bool),
1500  unsigned NumAlignedDPRCS2Regs,
1501  unsigned MIFlags) const {
1502  MachineFunction &MF = *MBB.getParent();
1503  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1505 
1506  DebugLoc DL;
1507 
1508  using RegAndKill = std::pair<unsigned, bool>;
1509 
1511  unsigned i = CSI.size();
1512  while (i != 0) {
1513  unsigned LastReg = 0;
1514  for (; i != 0; --i) {
1515  Register Reg = CSI[i-1].getReg();
1516  if (!(Func)(Reg, STI.splitFramePushPop(MF))) continue;
1517 
1518  // D-registers in the aligned area DPRCS2 are NOT spilled here.
1519  if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1520  continue;
1521 
1522  const MachineRegisterInfo &MRI = MF.getRegInfo();
1523  bool isLiveIn = MRI.isLiveIn(Reg);
1524  if (!isLiveIn && !MRI.isReserved(Reg))
1525  MBB.addLiveIn(Reg);
1526  // If NoGap is true, push consecutive registers and then leave the rest
1527  // for other instructions. e.g.
1528  // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11}
1529  if (NoGap && LastReg && LastReg != Reg-1)
1530  break;
1531  LastReg = Reg;
1532  // Do not set a kill flag on values that are also marked as live-in. This
1533  // happens with the @llvm-returnaddress intrinsic and with arguments
1534  // passed in callee saved registers.
1535  // Omitting the kill flags is conservatively correct even if the live-in
1536  // is not used after all.
1537  Regs.push_back(std::make_pair(Reg, /*isKill=*/!isLiveIn));
1538  }
1539 
1540  if (Regs.empty())
1541  continue;
1542 
1543  llvm::sort(Regs, [&](const RegAndKill &LHS, const RegAndKill &RHS) {
1544  return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first);
1545  });
1546 
1547  if (Regs.size() > 1 || StrOpc== 0) {
1548  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
1549  .addReg(ARM::SP)
1550  .setMIFlags(MIFlags)
1551  .add(predOps(ARMCC::AL));
1552  for (unsigned i = 0, e = Regs.size(); i < e; ++i)
1553  MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
1554  } else if (Regs.size() == 1) {
1555  BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP)
1556  .addReg(Regs[0].first, getKillRegState(Regs[0].second))
1557  .addReg(ARM::SP)
1558  .setMIFlags(MIFlags)
1559  .addImm(-4)
1560  .add(predOps(ARMCC::AL));
1561  }
1562  Regs.clear();
1563 
1564  // Put any subsequent vpush instructions before this one: they will refer to
1565  // higher register numbers so need to be pushed first in order to preserve
1566  // monotonicity.
1567  if (MI != MBB.begin())
1568  --MI;
1569  }
1570 }
1571 
1572 void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
1575  unsigned LdmOpc, unsigned LdrOpc,
1576  bool isVarArg, bool NoGap,
1577  bool (*Func)(unsigned, bool),
1578  unsigned NumAlignedDPRCS2Regs) const {
1579  MachineFunction &MF = *MBB.getParent();
1580  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1583  bool hasPAC = AFI->shouldSignReturnAddress();
1584  DebugLoc DL;
1585  bool isTailCall = false;
1586  bool isInterrupt = false;
1587  bool isTrap = false;
1588  bool isCmseEntry = false;
1589  if (MBB.end() != MI) {
1590  DL = MI->getDebugLoc();
1591  unsigned RetOpcode = MI->getOpcode();
1592  isTailCall = (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNri);
1593  isInterrupt =
1594  RetOpcode == ARM::SUBS_PC_LR || RetOpcode == ARM::t2SUBS_PC_LR;
1595  isTrap =
1596  RetOpcode == ARM::TRAP || RetOpcode == ARM::TRAPNaCl ||
1597  RetOpcode == ARM::tTRAP;
1598  isCmseEntry = (RetOpcode == ARM::tBXNS || RetOpcode == ARM::tBXNS_RET);
1599  }
1600 
1602  unsigned i = CSI.size();
1603  while (i != 0) {
1604  unsigned LastReg = 0;
1605  bool DeleteRet = false;
1606  for (; i != 0; --i) {
1607  CalleeSavedInfo &Info = CSI[i-1];
1608  Register Reg = Info.getReg();
1609  if (!(Func)(Reg, STI.splitFramePushPop(MF))) continue;
1610 
1611  // The aligned reloads from area DPRCS2 are not inserted here.
1612  if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
1613  continue;
1614  if (Reg == ARM::LR && !isTailCall && !isVarArg && !isInterrupt &&
1615  !isCmseEntry && !isTrap && AFI->getArgumentStackToRestore() == 0 &&
1616  STI.hasV5TOps() && MBB.succ_empty() && !hasPAC &&
1617  !STI.splitFramePointerPush(MF)) {
1618  Reg = ARM::PC;
1619  // Fold the return instruction into the LDM.
1620  DeleteRet = true;
1621  LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
1622  // We 'restore' LR into PC so it is not live out of the return block:
1623  // Clear Restored bit.
1624  Info.setRestored(false);
1625  }
1626 
1627  // If NoGap is true, pop consecutive registers and then leave the rest
1628  // for other instructions. e.g.
1629  // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11}
1630  if (NoGap && LastReg && LastReg != Reg-1)
1631  break;
1632 
1633  LastReg = Reg;
1634  Regs.push_back(Reg);
1635  }
1636 
1637  if (Regs.empty())
1638  continue;
1639 
1640  llvm::sort(Regs, [&](unsigned LHS, unsigned RHS) {
1642  });
1643 
1644  if (Regs.size() > 1 || LdrOpc == 0) {
1645  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1646  .addReg(ARM::SP)
1647  .add(predOps(ARMCC::AL))
1649  for (unsigned i = 0, e = Regs.size(); i < e; ++i)
1650  MIB.addReg(Regs[i], getDefRegState(true));
1651  if (DeleteRet) {
1652  if (MI != MBB.end()) {
1653  MIB.copyImplicitOps(*MI);
1654  MI->eraseFromParent();
1655  }
1656  }
1657  MI = MIB;
1658  } else if (Regs.size() == 1) {
1659  // If we adjusted the reg to PC from LR above, switch it back here. We
1660  // only do that for LDM.
1661  if (Regs[0] == ARM::PC)
1662  Regs[0] = ARM::LR;
1663  MachineInstrBuilder MIB =
1664  BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
1665  .addReg(ARM::SP, RegState::Define)
1666  .addReg(ARM::SP)
1668  // ARM mode needs an extra reg0 here due to addrmode2. Will go away once
1669  // that refactoring is complete (eventually).
1670  if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) {
1671  MIB.addReg(0);
1673  } else
1674  MIB.addImm(4);
1675  MIB.add(predOps(ARMCC::AL));
1676  }
1677  Regs.clear();
1678 
1679  // Put any subsequent vpop instructions after this one: they will refer to
1680  // higher register numbers so need to be popped afterwards.
1681  if (MI != MBB.end())
1682  ++MI;
1683  }
1684 }
1685 
1686 /// Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers
1687 /// starting from d8. Also insert stack realignment code and leave the stack
1688 /// pointer pointing to the d8 spill slot.
1691  unsigned NumAlignedDPRCS2Regs,
1693  const TargetRegisterInfo *TRI) {
1694  MachineFunction &MF = *MBB.getParent();
1696  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1697  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1698  MachineFrameInfo &MFI = MF.getFrameInfo();
1699 
1700  // Mark the D-register spill slots as properly aligned. Since MFI computes
1701  // stack slot layout backwards, this can actually mean that the d-reg stack
1702  // slot offsets can be wrong. The offset for d8 will always be correct.
1703  for (const CalleeSavedInfo &I : CSI) {
1704  unsigned DNum = I.getReg() - ARM::D8;
1705  if (DNum > NumAlignedDPRCS2Regs - 1)
1706  continue;
1707  int FI = I.getFrameIdx();
1708  // The even-numbered registers will be 16-byte aligned, the odd-numbered
1709  // registers will be 8-byte aligned.
1710  MFI.setObjectAlignment(FI, DNum % 2 ? Align(8) : Align(16));
1711 
1712  // The stack slot for D8 needs to be maximally aligned because this is
1713  // actually the point where we align the stack pointer. MachineFrameInfo
1714  // computes all offsets relative to the incoming stack pointer which is a
1715  // bit weird when realigning the stack. Any extra padding for this
1716  // over-alignment is not realized because the code inserted below adjusts
1717  // the stack pointer by numregs * 8 before aligning the stack pointer.
1718  if (DNum == 0)
1719  MFI.setObjectAlignment(FI, MFI.getMaxAlign());
1720  }
1721 
1722  // Move the stack pointer to the d8 spill slot, and align it at the same
1723  // time. Leave the stack slot address in the scratch register r4.
1724  //
1725  // sub r4, sp, #numregs * 8
1726  // bic r4, r4, #align - 1
1727  // mov sp, r4
1728  //
1729  bool isThumb = AFI->isThumbFunction();
1730  assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1731  AFI->setShouldRestoreSPFromFP(true);
1732 
1733  // sub r4, sp, #numregs * 8
1734  // The immediate is <= 64, so it doesn't need any special encoding.
1735  unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
1736  BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1737  .addReg(ARM::SP)
1738  .addImm(8 * NumAlignedDPRCS2Regs)
1739  .add(predOps(ARMCC::AL))
1740  .add(condCodeOp());
1741 
1742  Align MaxAlign = MF.getFrameInfo().getMaxAlign();
1743  // We must set parameter MustBeSingleInstruction to true, since
1744  // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform
1745  // stack alignment. Luckily, this can always be done since all ARM
1746  // architecture versions that support Neon also support the BFC
1747  // instruction.
1748  emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);
1749 
1750  // mov sp, r4
1751  // The stack pointer must be adjusted before spilling anything, otherwise
1752  // the stack slots could be clobbered by an interrupt handler.
1753  // Leave r4 live, it is used below.
1754  Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
1755  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1756  .addReg(ARM::R4)
1757  .add(predOps(ARMCC::AL));
1758  if (!isThumb)
1759  MIB.add(condCodeOp());
1760 
1761  // Now spill NumAlignedDPRCS2Regs registers starting from d8.
1762  // r4 holds the stack slot address.
1763  unsigned NextReg = ARM::D8;
1764 
1765  // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
1766  // The writeback is only needed when emitting two vst1.64 instructions.
1767  if (NumAlignedDPRCS2Regs >= 6) {
1768  unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1769  &ARM::QQPRRegClass);
1770  MBB.addLiveIn(SupReg);
1771  BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4)
1773  .addImm(16)
1774  .addReg(NextReg)
1775  .addReg(SupReg, RegState::ImplicitKill)
1776  .add(predOps(ARMCC::AL));
1777  NextReg += 4;
1778  NumAlignedDPRCS2Regs -= 4;
1779  }
1780 
1781  // We won't modify r4 beyond this point. It currently points to the next
1782  // register to be spilled.
1783  unsigned R4BaseReg = NextReg;
1784 
1785  // 16-byte aligned vst1.64 with 4 d-regs, no writeback.
1786  if (NumAlignedDPRCS2Regs >= 4) {
1787  unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1788  &ARM::QQPRRegClass);
1789  MBB.addLiveIn(SupReg);
1790  BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1791  .addReg(ARM::R4)
1792  .addImm(16)
1793  .addReg(NextReg)
1794  .addReg(SupReg, RegState::ImplicitKill)
1795  .add(predOps(ARMCC::AL));
1796  NextReg += 4;
1797  NumAlignedDPRCS2Regs -= 4;
1798  }
1799 
1800  // 16-byte aligned vst1.64 with 2 d-regs.
1801  if (NumAlignedDPRCS2Regs >= 2) {
1802  unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1803  &ARM::QPRRegClass);
1804  MBB.addLiveIn(SupReg);
1805  BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1806  .addReg(ARM::R4)
1807  .addImm(16)
1808  .addReg(SupReg)
1809  .add(predOps(ARMCC::AL));
1810  NextReg += 2;
1811  NumAlignedDPRCS2Regs -= 2;
1812  }
1813 
1814  // Finally, use a vanilla vstr.64 for the odd last register.
1815  if (NumAlignedDPRCS2Regs) {
1816  MBB.addLiveIn(NextReg);
1817  // vstr.64 uses addrmode5 which has an offset scale of 4.
1818  BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
1819  .addReg(NextReg)
1820  .addReg(ARM::R4)
1821  .addImm((NextReg - R4BaseReg) * 2)
1822  .add(predOps(ARMCC::AL));
1823  }
1824 
1825  // The last spill instruction inserted should kill the scratch register r4.
1826  std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1827 }
1828 
1829 /// Skip past the code inserted by emitAlignedDPRCS2Spills, and return an
1830 /// iterator to the following instruction.
1833  unsigned NumAlignedDPRCS2Regs) {
1834  // sub r4, sp, #numregs * 8
1835  // bic r4, r4, #align - 1
1836  // mov sp, r4
1837  ++MI; ++MI; ++MI;
1838  assert(MI->mayStore() && "Expecting spill instruction");
1839 
1840  // These switches all fall through.
1841  switch(NumAlignedDPRCS2Regs) {
1842  case 7:
1843  ++MI;
1844  assert(MI->mayStore() && "Expecting spill instruction");
1846  default:
1847  ++MI;
1848  assert(MI->mayStore() && "Expecting spill instruction");
1850  case 1:
1851  case 2:
1852  case 4:
1853  assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
1854  ++MI;
1855  }
1856  return MI;
1857 }
1858 
1859 /// Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers
1860 /// starting from d8. These instructions are assumed to execute while the
1861 /// stack is still aligned, unlike the code inserted by emitPopInst.
1864  unsigned NumAlignedDPRCS2Regs,
1866  const TargetRegisterInfo *TRI) {
1867  MachineFunction &MF = *MBB.getParent();
1869  DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1870  const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1871 
1872  // Find the frame index assigned to d8.
1873  int D8SpillFI = 0;
1874  for (const CalleeSavedInfo &I : CSI)
1875  if (I.getReg() == ARM::D8) {
1876  D8SpillFI = I.getFrameIdx();
1877  break;
1878  }
1879 
1880  // Materialize the address of the d8 spill slot into the scratch register r4.
1881  // This can be fairly complicated if the stack frame is large, so just use
1882  // the normal frame index elimination mechanism to do it. This code runs as
1883  // the initial part of the epilog where the stack and base pointers haven't
1884  // been changed yet.
1885  bool isThumb = AFI->isThumbFunction();
1886  assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
1887 
1888  unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
1889  BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1890  .addFrameIndex(D8SpillFI)
1891  .addImm(0)
1892  .add(predOps(ARMCC::AL))
1893  .add(condCodeOp());
1894 
1895  // Now restore NumAlignedDPRCS2Regs registers starting from d8.
1896  unsigned NextReg = ARM::D8;
1897 
1898  // 16-byte aligned vld1.64 with 4 d-regs and writeback.
1899  if (NumAlignedDPRCS2Regs >= 6) {
1900  unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1901  &ARM::QQPRRegClass);
1902  BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1905  .addImm(16)
1907  .add(predOps(ARMCC::AL));
1908  NextReg += 4;
1909  NumAlignedDPRCS2Regs -= 4;
1910  }
1911 
1912  // We won't modify r4 beyond this point. It currently points to the next
1913  // register to be spilled.
1914  unsigned R4BaseReg = NextReg;
1915 
1916  // 16-byte aligned vld1.64 with 4 d-regs, no writeback.
1917  if (NumAlignedDPRCS2Regs >= 4) {
1918  unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1919  &ARM::QQPRRegClass);
1920  BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1921  .addReg(ARM::R4)
1922  .addImm(16)
1924  .add(predOps(ARMCC::AL));
1925  NextReg += 4;
1926  NumAlignedDPRCS2Regs -= 4;
1927  }
1928 
1929  // 16-byte aligned vld1.64 with 2 d-regs.
1930  if (NumAlignedDPRCS2Regs >= 2) {
1931  unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1932  &ARM::QPRRegClass);
1933  BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1934  .addReg(ARM::R4)
1935  .addImm(16)
1936  .add(predOps(ARMCC::AL));
1937  NextReg += 2;
1938  NumAlignedDPRCS2Regs -= 2;
1939  }
1940 
1941  // Finally, use a vanilla vldr.64 for the remaining odd register.
1942  if (NumAlignedDPRCS2Regs)
1943  BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1944  .addReg(ARM::R4)
1945  .addImm(2 * (NextReg - R4BaseReg))
1946  .add(predOps(ARMCC::AL));
1947 
1948  // Last store kills r4.
1949  std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1950 }
1951 
1954  ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
1955  if (CSI.empty())
1956  return false;
1957 
1958  MachineFunction &MF = *MBB.getParent();
1960 
1961  unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
1962  unsigned PushOneOpc = AFI->isThumbFunction() ?
1963  ARM::t2STR_PRE : ARM::STR_PRE_IMM;
1964  unsigned FltOpc = ARM::VSTMDDB_UPD;
1965  unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
1966  // Compute PAC in R12.
1967  if (AFI->shouldSignReturnAddress()) {
1968  BuildMI(MBB, MI, DebugLoc(), STI.getInstrInfo()->get(ARM::t2PAC))
1970  }
1971  // Save the non-secure floating point context.
1972  if (llvm::any_of(CSI, [](const CalleeSavedInfo &C) {
1973  return C.getReg() == ARM::FPCXTNS;
1974  })) {
1975  BuildMI(MBB, MI, DebugLoc(), STI.getInstrInfo()->get(ARM::VSTR_FPCXTNS_pre),
1976  ARM::SP)
1977  .addReg(ARM::SP)
1978  .addImm(-4)
1979  .add(predOps(ARMCC::AL));
1980  }
1981  if (STI.splitFramePointerPush(MF)) {
1982  emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false,
1984  emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1985  NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1986  emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false,
1988  } else {
1989  emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register,
1991  emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register,
1993  emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1994  NumAlignedDPRCS2Regs, MachineInstr::FrameSetup);
1995  }
1996 
1997  // The code above does not insert spill code for the aligned DPRCS2 registers.
1998  // The stack realignment code will be inserted between the push instructions
1999  // and these spills.
2000  if (NumAlignedDPRCS2Regs)
2001  emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
2002 
2003  return true;
2004 }
2005 
2009  if (CSI.empty())
2010  return false;
2011 
2012  MachineFunction &MF = *MBB.getParent();
2014  bool isVarArg = AFI->getArgRegsSaveSize() > 0;
2015  unsigned NumAlignedDPRCS2Regs = AFI->getNumAlignedDPRCS2Regs();
2016 
2017  // The emitPopInst calls below do not insert reloads for the aligned DPRCS2
2018  // registers. Do that here instead.
2019  if (NumAlignedDPRCS2Regs)
2020  emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
2021 
2022  unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
2023  unsigned LdrOpc =
2024  AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST_IMM;
2025  unsigned FltOpc = ARM::VLDMDIA_UPD;
2026  if (STI.splitFramePointerPush(MF)) {
2027  emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
2029  emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
2030  NumAlignedDPRCS2Regs);
2031  emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
2033  } else {
2034  emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
2035  NumAlignedDPRCS2Regs);
2036  emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
2037  &isARMArea2Register, 0);
2038  emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
2039  &isARMArea1Register, 0);
2040  }
2041 
2042  return true;
2043 }
2044 
2045 // FIXME: Make generic?
2047  const ARMBaseInstrInfo &TII) {
2048  unsigned FnSize = 0;
2049  for (auto &MBB : MF) {
2050  for (auto &MI : MBB)
2051  FnSize += TII.getInstSizeInBytes(MI);
2052  }
2053  if (MF.getJumpTableInfo())
2054  for (auto &Table: MF.getJumpTableInfo()->getJumpTables())
2055  FnSize += Table.MBBs.size() * 4;
2056  FnSize += MF.getConstantPool()->getConstants().size() * 4;
2057  return FnSize;
2058 }
2059 
2060 /// estimateRSStackSizeLimit - Look at each instruction that references stack
2061 /// frames and return the stack size limit beyond which some of these
2062 /// instructions will require a scratch register during their expansion later.
2063 // FIXME: Move to TII?
2065  const TargetFrameLowering *TFI,
2066  bool &HasNonSPFrameIndex) {
2067  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2068  const ARMBaseInstrInfo &TII =
2069  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
2071  unsigned Limit = (1 << 12) - 1;
2072  for (auto &MBB : MF) {
2073  for (auto &MI : MBB) {
2074  if (MI.isDebugInstr())
2075  continue;
2076  for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2077  if (!MI.getOperand(i).isFI())
2078  continue;
2079 
2080  // When using ADDri to get the address of a stack object, 255 is the
2081  // largest offset guaranteed to fit in the immediate offset.
2082  if (MI.getOpcode() == ARM::ADDri) {
2083  Limit = std::min(Limit, (1U << 8) - 1);
2084  break;
2085  }
2086  // t2ADDri will not require an extra register, it can reuse the
2087  // destination.
2088  if (MI.getOpcode() == ARM::t2ADDri || MI.getOpcode() == ARM::t2ADDri12)
2089  break;
2090 
2091  const MCInstrDesc &MCID = MI.getDesc();
2092  const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF);
2093  if (RegClass && !RegClass->contains(ARM::SP))
2094  HasNonSPFrameIndex = true;
2095 
2096  // Otherwise check the addressing mode.
2097  switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {
2098  case ARMII::AddrMode_i12:
2099  case ARMII::AddrMode2:
2100  // Default 12 bit limit.
2101  break;
2102  case ARMII::AddrMode3:
2104  Limit = std::min(Limit, (1U << 8) - 1);
2105  break;
2106  case ARMII::AddrMode5FP16:
2107  Limit = std::min(Limit, ((1U << 8) - 1) * 2);
2108  break;
2109  case ARMII::AddrMode5:
2112  Limit = std::min(Limit, ((1U << 8) - 1) * 4);
2113  break;
2114  case ARMII::AddrModeT2_i12:
2115  // i12 supports only positive offset so these will be converted to
2116  // i8 opcodes. See llvm::rewriteT2FrameIndex.
2117  if (TFI->hasFP(MF) && AFI->hasStackFrame())
2118  Limit = std::min(Limit, (1U << 8) - 1);
2119  break;
2120  case ARMII::AddrMode4:
2121  case ARMII::AddrMode6:
2122  // Addressing modes 4 & 6 (load/store) instructions can't encode an
2123  // immediate offset for stack references.
2124  return 0;
2125  case ARMII::AddrModeT2_i7:
2126  Limit = std::min(Limit, ((1U << 7) - 1) * 1);
2127  break;
2129  Limit = std::min(Limit, ((1U << 7) - 1) * 2);
2130  break;
2132  Limit = std::min(Limit, ((1U << 7) - 1) * 4);
2133  break;
2134  default:
2135  llvm_unreachable("Unhandled addressing mode in stack size limit calculation");
2136  }
2137  break; // At most one FI per instruction
2138  }
2139  }
2140  }
2141 
2142  return Limit;
2143 }
2144 
2145 // In functions that realign the stack, it can be an advantage to spill the
2146 // callee-saved vector registers after realigning the stack. The vst1 and vld1
2147 // instructions take alignment hints that can improve performance.
2148 static void
2150  MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(0);
2151  if (!SpillAlignedNEONRegs)
2152  return;
2153 
2154  // Naked functions don't spill callee-saved registers.
2155  if (MF.getFunction().hasFnAttribute(Attribute::Naked))
2156  return;
2157 
2158  // We are planning to use NEON instructions vst1 / vld1.
2159  if (!MF.getSubtarget<ARMSubtarget>().hasNEON())
2160  return;
2161 
2162  // Don't bother if the default stack alignment is sufficiently high.
2163  if (MF.getSubtarget().getFrameLowering()->getStackAlign() >= Align(8))
2164  return;
2165 
2166  // Aligned spills require stack realignment.
2167  if (!static_cast<const ARMBaseRegisterInfo *>(
2169  return;
2170 
2171  // We always spill contiguous d-registers starting from d8. Count how many
2172  // needs spilling. The register allocator will almost always use the
2173  // callee-saved registers in order, but it can happen that there are holes in
2174  // the range. Registers above the hole will be spilled to the standard DPRCS
2175  // area.
2176  unsigned NumSpills = 0;
2177  for (; NumSpills < 8; ++NumSpills)
2178  if (!SavedRegs.test(ARM::D8 + NumSpills))
2179  break;
2180 
2181  // Don't do this for just one d-register. It's not worth it.
2182  if (NumSpills < 2)
2183  return;
2184 
2185  // Spill the first NumSpills D-registers after realigning the stack.
2186  MF.getInfo<ARMFunctionInfo>()->setNumAlignedDPRCS2Regs(NumSpills);
2187 
2188  // A scratch register is required for the vst1 / vld1 instructions.
2189  SavedRegs.set(ARM::R4);
2190 }
2191 
2193  // For CMSE entry functions, we want to save the FPCXT_NS immediately
2194  // upon function entry (resp. restore it immmediately before return)
2195  if (STI.hasV8_1MMainlineOps() &&
2197  return false;
2198 
2199  // We are disabling shrinkwrapping for now when PAC is enabled, as
2200  // shrinkwrapping can cause clobbering of r12 when the PAC code is
2201  // generated. A follow-up patch will fix this in a more performant manner.
2203  true /* SpillsLR */))
2204  return false;
2205 
2206  return true;
2207 }
2208 
2210  const auto &Subtarget = MF.getSubtarget<ARMSubtarget>();
2211  return Subtarget.createAAPCSFrameChainLeaf() ||
2212  (Subtarget.createAAPCSFrameChain() && MF.getFrameInfo().hasCalls());
2213 }
2214 
2215 // Thumb1 may require a spill when storing to a frame index through FP, for
2216 // cases where FP is a high register (R11). This scans the function for cases
2217 // where this may happen.
2219  const TargetFrameLowering &TFI) {
2220  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2221  if (!AFI->isThumb1OnlyFunction())
2222  return false;
2223 
2224  for (const auto &MBB : MF)
2225  for (const auto &MI : MBB)
2226  if (MI.getOpcode() == ARM::tSTRspi || MI.getOpcode() == ARM::tSTRi)
2227  for (const auto &Op : MI.operands())
2228  if (Op.isFI()) {
2229  Register Reg;
2230  TFI.getFrameIndexReference(MF, Op.getIndex(), Reg);
2231  if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::SP)
2232  return true;
2233  }
2234  return false;
2235 }
2236 
2238  BitVector &SavedRegs,
2239  RegScavenger *RS) const {
2240  TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
2241  // This tells PEI to spill the FP as if it is any other callee-save register
2242  // to take advantage the eliminateFrameIndex machinery. This also ensures it
2243  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
2244  // to combine multiple loads / stores.
2245  bool CanEliminateFrame = !(requiresAAPCSFrameRecord(MF) && hasFP(MF));
2246  bool CS1Spilled = false;
2247  bool LRSpilled = false;
2248  unsigned NumGPRSpills = 0;
2249  unsigned NumFPRSpills = 0;
2250  SmallVector<unsigned, 4> UnspilledCS1GPRs;
2251  SmallVector<unsigned, 4> UnspilledCS2GPRs;
2252  const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
2253  MF.getSubtarget().getRegisterInfo());
2254  const ARMBaseInstrInfo &TII =
2255  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
2257  MachineFrameInfo &MFI = MF.getFrameInfo();
2260  (void)TRI; // Silence unused warning in non-assert builds.
2261  Register FramePtr = RegInfo->getFrameRegister(MF);
2262 
2263  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
2264  // scratch register. Also spill R4 if Thumb2 function has varsized objects,
2265  // since it's not always possible to restore sp from fp in a single
2266  // instruction.
2267  // FIXME: It will be better just to find spare register here.
2268  if (AFI->isThumb2Function() &&
2269  (MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(MF)))
2270  SavedRegs.set(ARM::R4);
2271 
2272  // If a stack probe will be emitted, spill R4 and LR, since they are
2273  // clobbered by the stack probe call.
2274  // This estimate should be a safe, conservative estimate. The actual
2275  // stack probe is enabled based on the size of the local objects;
2276  // this estimate also includes the varargs store size.
2277  if (STI.isTargetWindows() &&
2278  WindowsRequiresStackProbe(MF, MFI.estimateStackSize(MF))) {
2279  SavedRegs.set(ARM::R4);
2280  SavedRegs.set(ARM::LR);
2281  }
2282 
2283  if (AFI->isThumb1OnlyFunction()) {
2284  // Spill LR if Thumb1 function uses variable length argument lists.
2285  if (AFI->getArgRegsSaveSize() > 0)
2286  SavedRegs.set(ARM::LR);
2287 
2288  // Spill R4 if Thumb1 epilogue has to restore SP from FP or the function
2289  // requires stack alignment. We don't know for sure what the stack size
2290  // will be, but for this, an estimate is good enough. If there anything
2291  // changes it, it'll be a spill, which implies we've used all the registers
2292  // and so R4 is already used, so not marking it here will be OK.
2293  // FIXME: It will be better just to find spare register here.
2294  if (MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(MF) ||
2295  MFI.estimateStackSize(MF) > 508)
2296  SavedRegs.set(ARM::R4);
2297  }
2298 
2299  // See if we can spill vector registers to aligned stack.
2300  checkNumAlignedDPRCS2Regs(MF, SavedRegs);
2301 
2302  // Spill the BasePtr if it's used.
2303  if (RegInfo->hasBasePointer(MF))
2304  SavedRegs.set(RegInfo->getBaseRegister());
2305 
2306  // On v8.1-M.Main CMSE entry functions save/restore FPCXT.
2307  if (STI.hasV8_1MMainlineOps() && AFI->isCmseNSEntryFunction())
2308  CanEliminateFrame = false;
2309 
2310  // Don't spill FP if the frame can be eliminated. This is determined
2311  // by scanning the callee-save registers to see if any is modified.
2312  const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
2313  for (unsigned i = 0; CSRegs[i]; ++i) {
2314  unsigned Reg = CSRegs[i];
2315  bool Spilled = false;
2316  if (SavedRegs.test(Reg)) {
2317  Spilled = true;
2318  CanEliminateFrame = false;
2319  }
2320 
2321  if (!ARM::GPRRegClass.contains(Reg)) {
2322  if (Spilled) {
2323  if (ARM::SPRRegClass.contains(Reg))
2324  NumFPRSpills++;
2325  else if (ARM::DPRRegClass.contains(Reg))
2326  NumFPRSpills += 2;
2327  else if (ARM::QPRRegClass.contains(Reg))
2328  NumFPRSpills += 4;
2329  }
2330  continue;
2331  }
2332 
2333  if (Spilled) {
2334  NumGPRSpills++;
2335 
2336  if (!STI.splitFramePushPop(MF)) {
2337  if (Reg == ARM::LR)
2338  LRSpilled = true;
2339  CS1Spilled = true;
2340  continue;
2341  }
2342 
2343  // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
2344  switch (Reg) {
2345  case ARM::LR:
2346  LRSpilled = true;
2348  case ARM::R0: case ARM::R1:
2349  case ARM::R2: case ARM::R3:
2350  case ARM::R4: case ARM::R5:
2351  case ARM::R6: case ARM::R7:
2352  CS1Spilled = true;
2353  break;
2354  default:
2355  break;
2356  }
2357  } else {
2358  if (!STI.splitFramePushPop(MF)) {
2359  UnspilledCS1GPRs.push_back(Reg);
2360  continue;
2361  }
2362 
2363  switch (Reg) {
2364  case ARM::R0: case ARM::R1:
2365  case ARM::R2: case ARM::R3:
2366  case ARM::R4: case ARM::R5:
2367  case ARM::R6: case ARM::R7:
2368  case ARM::LR:
2369  UnspilledCS1GPRs.push_back(Reg);
2370  break;
2371  default:
2372  UnspilledCS2GPRs.push_back(Reg);
2373  break;
2374  }
2375  }
2376  }
2377 
2378  bool ForceLRSpill = false;
2379  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
2380  unsigned FnSize = EstimateFunctionSizeInBytes(MF, TII);
2381  // Force LR to be spilled if the Thumb function size is > 2048. This enables
2382  // use of BL to implement far jump.
2383  if (FnSize >= (1 << 11)) {
2384  CanEliminateFrame = false;
2385  ForceLRSpill = true;
2386  }
2387  }
2388 
2389  // If any of the stack slot references may be out of range of an immediate
2390  // offset, make sure a register (or a spill slot) is available for the
2391  // register scavenger. Note that if we're indexing off the frame pointer, the
2392  // effective stack size is 4 bytes larger since the FP points to the stack
2393  // slot of the previous FP. Also, if we have variable sized objects in the
2394  // function, stack slot references will often be negative, and some of
2395  // our instructions are positive-offset only, so conservatively consider
2396  // that case to want a spill slot (or register) as well. Similarly, if
2397  // the function adjusts the stack pointer during execution and the
2398  // adjustments aren't already part of our stack size estimate, our offset
2399  // calculations may be off, so be conservative.
2400  // FIXME: We could add logic to be more precise about negative offsets
2401  // and which instructions will need a scratch register for them. Is it
2402  // worth the effort and added fragility?
2403  unsigned EstimatedStackSize =
2404  MFI.estimateStackSize(MF) + 4 * (NumGPRSpills + NumFPRSpills);
2405 
2406  // Determine biggest (positive) SP offset in MachineFrameInfo.
2407  int MaxFixedOffset = 0;
2408  for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
2409  int MaxObjectOffset = MFI.getObjectOffset(I) + MFI.getObjectSize(I);
2410  MaxFixedOffset = std::max(MaxFixedOffset, MaxObjectOffset);
2411  }
2412 
2413  bool HasFP = hasFP(MF);
2414  if (HasFP) {
2415  if (AFI->hasStackFrame())
2416  EstimatedStackSize += 4;
2417  } else {
2418  // If FP is not used, SP will be used to access arguments, so count the
2419  // size of arguments into the estimation.
2420  EstimatedStackSize += MaxFixedOffset;
2421  }
2422  EstimatedStackSize += 16; // For possible paddings.
2423 
2424  unsigned EstimatedRSStackSizeLimit, EstimatedRSFixedSizeLimit;
2425  bool HasNonSPFrameIndex = false;
2426  if (AFI->isThumb1OnlyFunction()) {
2427  // For Thumb1, don't bother to iterate over the function. The only
2428  // instruction that requires an emergency spill slot is a store to a
2429  // frame index.
2430  //
2431  // tSTRspi, which is used for sp-relative accesses, has an 8-bit unsigned
2432  // immediate. tSTRi, which is used for bp- and fp-relative accesses, has
2433  // a 5-bit unsigned immediate.
2434  //
2435  // We could try to check if the function actually contains a tSTRspi
2436  // that might need the spill slot, but it's not really important.
2437  // Functions with VLAs or extremely large call frames are rare, and
2438  // if a function is allocating more than 1KB of stack, an extra 4-byte
2439  // slot probably isn't relevant.
2440  //
2441  // A special case is the scenario where r11 is used as FP, where accesses
2442  // to a frame index will require its value to be moved into a low reg.
2443  // This is handled later on, once we are able to determine if we have any
2444  // fp-relative accesses.
2445  if (RegInfo->hasBasePointer(MF))
2446  EstimatedRSStackSizeLimit = (1U << 5) * 4;
2447  else
2448  EstimatedRSStackSizeLimit = (1U << 8) * 4;
2449  EstimatedRSFixedSizeLimit = (1U << 5) * 4;
2450  } else {
2451  EstimatedRSStackSizeLimit =
2452  estimateRSStackSizeLimit(MF, this, HasNonSPFrameIndex);
2453  EstimatedRSFixedSizeLimit = EstimatedRSStackSizeLimit;
2454  }
2455  // Final estimate of whether sp or bp-relative accesses might require
2456  // scavenging.
2457  bool HasLargeStack = EstimatedStackSize > EstimatedRSStackSizeLimit;
2458 
2459  // If the stack pointer moves and we don't have a base pointer, the
2460  // estimate logic doesn't work. The actual offsets might be larger when
2461  // we're constructing a call frame, or we might need to use negative
2462  // offsets from fp.
2463  bool HasMovingSP = MFI.hasVarSizedObjects() ||
2464  (MFI.adjustsStack() && !canSimplifyCallFramePseudos(MF));
2465  bool HasBPOrFixedSP = RegInfo->hasBasePointer(MF) || !HasMovingSP;
2466 
2467  // If we have a frame pointer, we assume arguments will be accessed
2468  // relative to the frame pointer. Check whether fp-relative accesses to
2469  // arguments require scavenging.
2470  //
2471  // We could do slightly better on Thumb1; in some cases, an sp-relative
2472  // offset would be legal even though an fp-relative offset is not.
2473  int MaxFPOffset = getMaxFPOffset(STI, *AFI, MF);
2474  bool HasLargeArgumentList =
2475  HasFP && (MaxFixedOffset - MaxFPOffset) > (int)EstimatedRSFixedSizeLimit;
2476 
2477  bool BigFrameOffsets = HasLargeStack || !HasBPOrFixedSP ||
2478  HasLargeArgumentList || HasNonSPFrameIndex;
2479  LLVM_DEBUG(dbgs() << "EstimatedLimit: " << EstimatedRSStackSizeLimit
2480  << "; EstimatedStack: " << EstimatedStackSize
2481  << "; EstimatedFPStack: " << MaxFixedOffset - MaxFPOffset
2482  << "; BigFrameOffsets: " << BigFrameOffsets << "\n");
2483  if (BigFrameOffsets ||
2484  !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) {
2485  AFI->setHasStackFrame(true);
2486 
2487  if (HasFP) {
2488  SavedRegs.set(FramePtr);
2489  // If the frame pointer is required by the ABI, also spill LR so that we
2490  // emit a complete frame record.
2491  if ((requiresAAPCSFrameRecord(MF) ||
2493  !LRSpilled) {
2494  SavedRegs.set(ARM::LR);
2495  LRSpilled = true;
2496  NumGPRSpills++;
2497  auto LRPos = llvm::find(UnspilledCS1GPRs, ARM::LR);
2498  if (LRPos != UnspilledCS1GPRs.end())
2499  UnspilledCS1GPRs.erase(LRPos);
2500  }
2501  auto FPPos = llvm::find(UnspilledCS1GPRs, FramePtr);
2502  if (FPPos != UnspilledCS1GPRs.end())
2503  UnspilledCS1GPRs.erase(FPPos);
2504  NumGPRSpills++;
2505  if (FramePtr == ARM::R7)
2506  CS1Spilled = true;
2507  }
2508 
2509  // This is true when we inserted a spill for a callee-save GPR which is
2510  // not otherwise used by the function. This guaranteees it is possible
2511  // to scavenge a register to hold the address of a stack slot. On Thumb1,
2512  // the register must be a valid operand to tSTRi, i.e. r4-r7. For other
2513  // subtargets, this is any GPR, i.e. r4-r11 or lr.
2514  //
2515  // If we don't insert a spill, we instead allocate an emergency spill
2516  // slot, which can be used by scavenging to spill an arbitrary register.
2517  //
2518  // We currently don't try to figure out whether any specific instruction
2519  // requires scavening an additional register.
2520  bool ExtraCSSpill = false;
2521 
2522  if (AFI->isThumb1OnlyFunction()) {
2523  // For Thumb1-only targets, we need some low registers when we save and
2524  // restore the high registers (which aren't allocatable, but could be
2525  // used by inline assembly) because the push/pop instructions can not
2526  // access high registers. If necessary, we might need to push more low
2527  // registers to ensure that there is at least one free that can be used
2528  // for the saving & restoring, and preferably we should ensure that as
2529  // many as are needed are available so that fewer push/pop instructions
2530  // are required.
2531 
2532  // Low registers which are not currently pushed, but could be (r4-r7).
2533  SmallVector<unsigned, 4> AvailableRegs;
2534 
2535  // Unused argument registers (r0-r3) can be clobbered in the prologue for
2536  // free.
2537  int EntryRegDeficit = 0;
2538  for (unsigned Reg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3}) {
2539  if (!MF.getRegInfo().isLiveIn(Reg)) {
2540  --EntryRegDeficit;
2541  LLVM_DEBUG(dbgs()
2542  << printReg(Reg, TRI)
2543  << " is unused argument register, EntryRegDeficit = "
2544  << EntryRegDeficit << "\n");
2545  }
2546  }
2547 
2548  // Unused return registers can be clobbered in the epilogue for free.
2549  int ExitRegDeficit = AFI->getReturnRegsCount() - 4;
2550  LLVM_DEBUG(dbgs() << AFI->getReturnRegsCount()
2551  << " return regs used, ExitRegDeficit = "
2552  << ExitRegDeficit << "\n");
2553 
2554  int RegDeficit = std::max(EntryRegDeficit, ExitRegDeficit);
2555  LLVM_DEBUG(dbgs() << "RegDeficit = " << RegDeficit << "\n");
2556 
2557  // r4-r6 can be used in the prologue if they are pushed by the first push
2558  // instruction.
2559  for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6}) {
2560  if (SavedRegs.test(Reg)) {
2561  --RegDeficit;
2562  LLVM_DEBUG(dbgs() << printReg(Reg, TRI)
2563  << " is saved low register, RegDeficit = "
2564  << RegDeficit << "\n");
2565  } else {
2566  AvailableRegs.push_back(Reg);
2567  LLVM_DEBUG(
2568  dbgs()
2569  << printReg(Reg, TRI)
2570  << " is non-saved low register, adding to AvailableRegs\n");
2571  }
2572  }
2573 
2574  // r7 can be used if it is not being used as the frame pointer.
2575  if (!HasFP || FramePtr != ARM::R7) {
2576  if (SavedRegs.test(ARM::R7)) {
2577  --RegDeficit;
2578  LLVM_DEBUG(dbgs() << "%r7 is saved low register, RegDeficit = "
2579  << RegDeficit << "\n");
2580  } else {
2581  AvailableRegs.push_back(ARM::R7);
2582  LLVM_DEBUG(
2583  dbgs()
2584  << "%r7 is non-saved low register, adding to AvailableRegs\n");
2585  }
2586  }
2587 
2588  // Each of r8-r11 needs to be copied to a low register, then pushed.
2589  for (unsigned Reg : {ARM::R8, ARM::R9, ARM::R10, ARM::R11}) {
2590  if (SavedRegs.test(Reg)) {
2591  ++RegDeficit;
2592  LLVM_DEBUG(dbgs() << printReg(Reg, TRI)
2593  << " is saved high register, RegDeficit = "
2594  << RegDeficit << "\n");
2595  }
2596  }
2597 
2598  // LR can only be used by PUSH, not POP, and can't be used at all if the
2599  // llvm.returnaddress intrinsic is used. This is only worth doing if we
2600  // are more limited at function entry than exit.
2601  if ((EntryRegDeficit > ExitRegDeficit) &&
2602  !(MF.getRegInfo().isLiveIn(ARM::LR) &&
2604  if (SavedRegs.test(ARM::LR)) {
2605  --RegDeficit;
2606  LLVM_DEBUG(dbgs() << "%lr is saved register, RegDeficit = "
2607  << RegDeficit << "\n");
2608  } else {
2609  AvailableRegs.push_back(ARM::LR);
2610  LLVM_DEBUG(dbgs() << "%lr is not saved, adding to AvailableRegs\n");
2611  }
2612  }
2613 
2614  // If there are more high registers that need pushing than low registers
2615  // available, push some more low registers so that we can use fewer push
2616  // instructions. This might not reduce RegDeficit all the way to zero,
2617  // because we can only guarantee that r4-r6 are available, but r8-r11 may
2618  // need saving.
2619  LLVM_DEBUG(dbgs() << "Final RegDeficit = " << RegDeficit << "\n");
2620  for (; RegDeficit > 0 && !AvailableRegs.empty(); --RegDeficit) {
2621  unsigned Reg = AvailableRegs.pop_back_val();
2622  LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
2623  << " to make up reg deficit\n");
2624  SavedRegs.set(Reg);
2625  NumGPRSpills++;
2626  CS1Spilled = true;
2627  assert(!MRI.isReserved(Reg) && "Should not be reserved");
2628  if (Reg != ARM::LR && !MRI.isPhysRegUsed(Reg))
2629  ExtraCSSpill = true;
2630  UnspilledCS1GPRs.erase(llvm::find(UnspilledCS1GPRs, Reg));
2631  if (Reg == ARM::LR)
2632  LRSpilled = true;
2633  }
2634  LLVM_DEBUG(dbgs() << "After adding spills, RegDeficit = " << RegDeficit
2635  << "\n");
2636  }
2637 
2638  // Avoid spilling LR in Thumb1 if there's a tail call: it's expensive to
2639  // restore LR in that case.
2640  bool ExpensiveLRRestore = AFI->isThumb1OnlyFunction() && MFI.hasTailCall();
2641 
2642  // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
2643  // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
2644  if (!LRSpilled && CS1Spilled && !ExpensiveLRRestore) {
2645  SavedRegs.set(ARM::LR);
2646  NumGPRSpills++;
2648  LRPos = llvm::find(UnspilledCS1GPRs, (unsigned)ARM::LR);
2649  if (LRPos != UnspilledCS1GPRs.end())
2650  UnspilledCS1GPRs.erase(LRPos);
2651 
2652  ForceLRSpill = false;
2653  if (!MRI.isReserved(ARM::LR) && !MRI.isPhysRegUsed(ARM::LR) &&
2654  !AFI->isThumb1OnlyFunction())
2655  ExtraCSSpill = true;
2656  }
2657 
2658  // If stack and double are 8-byte aligned and we are spilling an odd number
2659  // of GPRs, spill one extra callee save GPR so we won't have to pad between
2660  // the integer and double callee save areas.
2661  LLVM_DEBUG(dbgs() << "NumGPRSpills = " << NumGPRSpills << "\n");
2662  const Align TargetAlign = getStackAlign();
2663  if (TargetAlign >= Align(8) && (NumGPRSpills & 1)) {
2664  if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
2665  for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
2666  unsigned Reg = UnspilledCS1GPRs[i];
2667  // Don't spill high register if the function is thumb. In the case of
2668  // Windows on ARM, accept R11 (frame pointer)
2669  if (!AFI->isThumbFunction() ||
2670  (STI.isTargetWindows() && Reg == ARM::R11) ||
2671  isARMLowRegister(Reg) ||
2672  (Reg == ARM::LR && !ExpensiveLRRestore)) {
2673  SavedRegs.set(Reg);
2674  LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
2675  << " to make up alignment\n");
2676  if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg) &&
2677  !(Reg == ARM::LR && AFI->isThumb1OnlyFunction()))
2678  ExtraCSSpill = true;
2679  break;
2680  }
2681  }
2682  } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
2683  unsigned Reg = UnspilledCS2GPRs.front();
2684  SavedRegs.set(Reg);
2685  LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, TRI)
2686  << " to make up alignment\n");
2687  if (!MRI.isReserved(Reg) && !MRI.isPhysRegUsed(Reg))
2688  ExtraCSSpill = true;
2689  }
2690  }
2691 
2692  // Estimate if we might need to scavenge a register at some point in order
2693  // to materialize a stack offset. If so, either spill one additional
2694  // callee-saved register or reserve a special spill slot to facilitate
2695  // register scavenging. Thumb1 needs a spill slot for stack pointer
2696  // adjustments and for frame index accesses when FP is high register,
2697  // even when the frame itself is small.
2698  if (!ExtraCSSpill &&
2699  (BigFrameOffsets || canSpillOnFrameIndexAccess(MF, *this))) {
2700  // If any non-reserved CS register isn't spilled, just spill one or two
2701  // extra. That should take care of it!
2702  unsigned NumExtras = TargetAlign.value() / 4;
2703  SmallVector<unsigned, 2> Extras;
2704  while (NumExtras && !UnspilledCS1GPRs.empty()) {
2705  unsigned Reg = UnspilledCS1GPRs.pop_back_val();
2706  if (!MRI.isReserved(Reg) &&
2707  (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg))) {
2708  Extras.push_back(Reg);
2709  NumExtras--;
2710  }
2711  }
2712  // For non-Thumb1 functions, also check for hi-reg CS registers
2713  if (!AFI->isThumb1OnlyFunction()) {
2714  while (NumExtras && !UnspilledCS2GPRs.empty()) {
2715  unsigned Reg = UnspilledCS2GPRs.pop_back_val();
2716  if (!MRI.isReserved(Reg)) {
2717  Extras.push_back(Reg);
2718  NumExtras--;
2719  }
2720  }
2721  }
2722  if (NumExtras == 0) {
2723  for (unsigned Reg : Extras) {
2724  SavedRegs.set(Reg);
2725  if (!MRI.isPhysRegUsed(Reg))
2726  ExtraCSSpill = true;
2727  }
2728  }
2729  if (!ExtraCSSpill && RS) {
2730  // Reserve a slot closest to SP or frame pointer.
2731  LLVM_DEBUG(dbgs() << "Reserving emergency spill slot\n");
2732  const TargetRegisterClass &RC = ARM::GPRRegClass;
2733  unsigned Size = TRI->getSpillSize(RC);
2734  Align Alignment = TRI->getSpillAlign(RC);
2736  MFI.CreateStackObject(Size, Alignment, false));
2737  }
2738  }
2739  }
2740 
2741  if (ForceLRSpill)
2742  SavedRegs.set(ARM::LR);
2743  AFI->setLRIsSpilled(SavedRegs.test(ARM::LR));
2744 }
2745 
2747  BitVector &SavedRegs) const {
2748  TargetFrameLowering::getCalleeSaves(MF, SavedRegs);
2749 
2750  // If we have the "returned" parameter attribute which guarantees that we
2751  // return the value which was passed in r0 unmodified (e.g. C++ 'structors),
2752  // record that fact for IPRA.
2753  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2754  if (AFI->getPreservesR0())
2755  SavedRegs.set(ARM::R0);
2756 }
2757 
2760  std::vector<CalleeSavedInfo> &CSI) const {
2761  // For CMSE entry functions, handle floating-point context as if it was a
2762  // callee-saved register.
2763  if (STI.hasV8_1MMainlineOps() &&
2765  CSI.emplace_back(ARM::FPCXTNS);
2766  CSI.back().setRestored(false);
2767  }
2768 
2769  // For functions, which sign their return address, upon function entry, the
2770  // return address PAC is computed in R12. Treat R12 as a callee-saved register
2771  // in this case.
2772  const auto &AFI = *MF.getInfo<ARMFunctionInfo>();
2773  if (AFI.shouldSignReturnAddress()) {
2774  // The order of register must match the order we push them, because the
2775  // PEI assigns frame indices in that order. When compiling for return
2776  // address sign and authenication, we use split push, therefore the orders
2777  // we want are:
2778  // LR, R7, R6, R5, R4, <R12>, R11, R10, R9, R8, D15-D8
2779  CSI.insert(find_if(CSI,
2780  [=](const auto &CS) {
2781  Register Reg = CS.getReg();
2782  return Reg == ARM::R10 || Reg == ARM::R11 ||
2783  Reg == ARM::R8 || Reg == ARM::R9 ||
2784  ARM::DPRRegClass.contains(Reg);
2785  }),
2786  CalleeSavedInfo(ARM::R12));
2787  }
2788 
2789  return false;
2790 }
2791 
2793 ARMFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
2794  static const SpillSlot FixedSpillOffsets[] = {{ARM::FPCXTNS, -4}};
2795  NumEntries = array_lengthof(FixedSpillOffsets);
2796  return FixedSpillOffsets;
2797 }
2798 
2799 MachineBasicBlock::iterator ARMFrameLowering::eliminateCallFramePseudoInstr(
2802  const ARMBaseInstrInfo &TII =
2803  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
2805  bool isARM = !AFI->isThumbFunction();
2806  DebugLoc dl = I->getDebugLoc();
2807  unsigned Opc = I->getOpcode();
2808  bool IsDestroy = Opc == TII.getCallFrameDestroyOpcode();
2809  unsigned CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0;
2810 
2811  assert(!AFI->isThumb1OnlyFunction() &&
2812  "This eliminateCallFramePseudoInstr does not support Thumb1!");
2813 
2814  int PIdx = I->findFirstPredOperandIdx();
2815  ARMCC::CondCodes Pred = (PIdx == -1)
2816  ? ARMCC::AL
2817  : (ARMCC::CondCodes)I->getOperand(PIdx).getImm();
2818  unsigned PredReg = TII.getFramePred(*I);
2819 
2820  if (!hasReservedCallFrame(MF)) {
2821  // Bail early if the callee is expected to do the adjustment.
2822  if (IsDestroy && CalleePopAmount != -1U)
2823  return MBB.erase(I);
2824 
2825  // If we have alloca, convert as follows:
2826  // ADJCALLSTACKDOWN -> sub, sp, sp, amount
2827  // ADJCALLSTACKUP -> add, sp, sp, amount
2828  unsigned Amount = TII.getFrameSize(*I);
2829  if (Amount != 0) {
2830  // We need to keep the stack aligned properly. To do this, we round the
2831  // amount of space needed for the outgoing arguments up to the next
2832  // alignment boundary.
2833  Amount = alignSPAdjust(Amount);
2834 
2835  if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
2836  emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, MachineInstr::NoFlags,
2837  Pred, PredReg);
2838  } else {
2839  assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
2840  emitSPUpdate(isARM, MBB, I, dl, TII, Amount, MachineInstr::NoFlags,
2841  Pred, PredReg);
2842  }
2843  }
2844  } else if (CalleePopAmount != -1U) {
2845  // If the calling convention demands that the callee pops arguments from the
2846  // stack, we want to add it back if we have a reserved call frame.
2847  emitSPUpdate(isARM, MBB, I, dl, TII, -CalleePopAmount,
2848  MachineInstr::NoFlags, Pred, PredReg);
2849  }
2850  return MBB.erase(I);
2851 }
2852 
2853 /// Get the minimum constant for ARM that is greater than or equal to the
2854 /// argument. In ARM, constants can have any value that can be produced by
2855 /// rotating an 8-bit value to the right by an even number of bits within a
2856 /// 32-bit word.
2858  unsigned Shifted = 0;
2859 
2860  if (Value == 0)
2861  return 0;
2862 
2863  while (!(Value & 0xC0000000)) {
2864  Value = Value << 2;
2865  Shifted += 2;
2866  }
2867 
2868  bool Carry = (Value & 0x00FFFFFF);
2869  Value = ((Value & 0xFF000000) >> 24) + Carry;
2870 
2871  if (Value & 0x0000100)
2872  Value = Value & 0x000001FC;
2873 
2874  if (Shifted > 24)
2875  Value = Value >> (Shifted - 24);
2876  else
2877  Value = Value << (24 - Shifted);
2878 
2879  return Value;
2880 }
2881 
2882 // The stack limit in the TCB is set to this many bytes above the actual
2883 // stack limit.
2884 static const uint64_t kSplitStackAvailable = 256;
2885 
2886 // Adjust the function prologue to enable split stacks. This currently only
2887 // supports android and linux.
2888 //
2889 // The ABI of the segmented stack prologue is a little arbitrarily chosen, but
2890 // must be well defined in order to allow for consistent implementations of the
2891 // __morestack helper function. The ABI is also not a normal ABI in that it
2892 // doesn't follow the normal calling conventions because this allows the
2893 // prologue of each function to be optimized further.
2894 //
2895 // Currently, the ABI looks like (when calling __morestack)
2896 //
2897 // * r4 holds the minimum stack size requested for this function call
2898 // * r5 holds the stack size of the arguments to the function
2899 // * the beginning of the function is 3 instructions after the call to
2900 // __morestack
2901 //
2902 // Implementations of __morestack should use r4 to allocate a new stack, r5 to
2903 // place the arguments on to the new stack, and the 3-instruction knowledge to
2904 // jump directly to the body of the function when working on the new stack.
2905 //
2906 // An old (and possibly no longer compatible) implementation of __morestack for
2907 // ARM can be found at [1].
2908 //
2909 // [1] - https://github.com/mozilla/rust/blob/86efd9/src/rt/arch/arm/morestack.S
2911  MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2912  unsigned Opcode;
2913  unsigned CFIIndex;
2914  const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>();
2915  bool Thumb = ST->isThumb();
2916  bool Thumb2 = ST->isThumb2();
2917 
2918  // Sadly, this currently doesn't support varargs, platforms other than
2919  // android/linux. Note that thumb1/thumb2 are support for android/linux.
2920  if (MF.getFunction().isVarArg())
2921  report_fatal_error("Segmented stacks do not support vararg functions.");
2922  if (!ST->isTargetAndroid() && !ST->isTargetLinux())
2923  report_fatal_error("Segmented stacks not supported on this platform.");
2924 
2925  MachineFrameInfo &MFI = MF.getFrameInfo();
2926  MachineModuleInfo &MMI = MF.getMMI();
2927  MCContext &Context = MMI.getContext();
2928  const MCRegisterInfo *MRI = Context.getRegisterInfo();
2929  const ARMBaseInstrInfo &TII =
2930  *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
2931  ARMFunctionInfo *ARMFI = MF.getInfo<ARMFunctionInfo>();
2932  DebugLoc DL;
2933 
2934  if (!MFI.needsSplitStackProlog())
2935  return;
2936 
2937  uint64_t StackSize = MFI.getStackSize();
2938 
2939  // Use R4 and R5 as scratch registers.
2940  // We save R4 and R5 before use and restore them before leaving the function.
2941  unsigned ScratchReg0 = ARM::R4;
2942  unsigned ScratchReg1 = ARM::R5;
2943  uint64_t AlignedStackSize;
2944 
2945  MachineBasicBlock *PrevStackMBB = MF.CreateMachineBasicBlock();
2946  MachineBasicBlock *PostStackMBB = MF.CreateMachineBasicBlock();
2947  MachineBasicBlock *AllocMBB = MF.CreateMachineBasicBlock();
2950 
2951  // Grab everything that reaches PrologueMBB to update there liveness as well.
2952  SmallPtrSet<MachineBasicBlock *, 8> BeforePrologueRegion;
2954  WalkList.push_back(&PrologueMBB);
2955 
2956  do {
2957  MachineBasicBlock *CurMBB = WalkList.pop_back_val();
2958  for (MachineBasicBlock *PredBB : CurMBB->predecessors()) {
2959  if (BeforePrologueRegion.insert(PredBB).second)
2960  WalkList.push_back(PredBB);
2961  }
2962  } while (!WalkList.empty());
2963 
2964  // The order in that list is important.
2965  // The blocks will all be inserted before PrologueMBB using that order.
2966  // Therefore the block that should appear first in the CFG should appear
2967  // first in the list.
2968  MachineBasicBlock *AddedBlocks[] = {PrevStackMBB, McrMBB, GetMBB, AllocMBB,
2969  PostStackMBB};
2970 
2971  for (MachineBasicBlock *B : AddedBlocks)
2972  BeforePrologueRegion.insert(B);
2973 
2974  for (const auto &LI : PrologueMBB.liveins()) {
2975  for (MachineBasicBlock *PredBB : BeforePrologueRegion)
2976  PredBB->addLiveIn(LI);
2977  }
2978 
2979  // Remove the newly added blocks from the list, since we know
2980  // we do not have to do the following updates for them.
2981  for (MachineBasicBlock *B : AddedBlocks) {
2982  BeforePrologueRegion.erase(B);
2983  MF.insert(PrologueMBB.getIterator(), B);
2984  }
2985 
2986  for (MachineBasicBlock *MBB : BeforePrologueRegion) {
2987  // Make sure the LiveIns are still sorted and unique.
2989  // Replace the edges to PrologueMBB by edges to the sequences
2990  // we are about to add, but only update for immediate predecessors.
2991  if (MBB->isSuccessor(&PrologueMBB))
2992  MBB->ReplaceUsesOfBlockWith(&PrologueMBB, AddedBlocks[0]);
2993  }
2994 
2995  // The required stack size that is aligned to ARM constant criterion.
2996  AlignedStackSize = alignToARMConstant(StackSize);
2997 
2998  // When the frame size is less than 256 we just compare the stack
2999  // boundary directly to the value of the stack pointer, per gcc.
3000  bool CompareStackPointer = AlignedStackSize < kSplitStackAvailable;
3001 
3002  // We will use two of the callee save registers as scratch registers so we
3003  // need to save those registers onto the stack.
3004  // We will use SR0 to hold stack limit and SR1 to hold the stack size
3005  // requested and arguments for __morestack().
3006  // SR0: Scratch Register #0
3007  // SR1: Scratch Register #1
3008  // push {SR0, SR1}
3009  if (Thumb) {
3010  BuildMI(PrevStackMBB, DL, TII.get(ARM::tPUSH))
3011  .add(predOps(ARMCC::AL))
3012  .addReg(ScratchReg0)
3013  .addReg(ScratchReg1);
3014  } else {
3015  BuildMI(PrevStackMBB, DL, TII.get(ARM::STMDB_UPD))
3016  .addReg(ARM::SP, RegState::Define)
3017  .addReg(ARM::SP)
3018  .add(predOps(ARMCC::AL))
3019  .addReg(ScratchReg0)
3020  .addReg(ScratchReg1);
3021  }
3022 
3023  // Emit the relevant DWARF information about the change in stack pointer as
3024  // well as where to find both r4 and r5 (the callee-save registers)
3025  if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
3026  CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 8));
3027  BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
3028  .addCFIIndex(CFIIndex);
3030  nullptr, MRI->getDwarfRegNum(ScratchReg1, true), -4));
3031  BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
3032  .addCFIIndex(CFIIndex);
3034  nullptr, MRI->getDwarfRegNum(ScratchReg0, true), -8));
3035  BuildMI(PrevStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
3036  .addCFIIndex(CFIIndex);
3037  }
3038 
3039  // mov SR1, sp
3040  if (Thumb) {
3041  BuildMI(McrMBB, DL, TII.get(ARM::tMOVr), ScratchReg1)
3042  .addReg(ARM::SP)
3043  .add(predOps(ARMCC::AL));
3044  } else if (CompareStackPointer) {
3045  BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
3046  .addReg(ARM::SP)
3047  .add(predOps(ARMCC::AL))
3048  .add(condCodeOp());
3049  }
3050 
3051  // sub SR1, sp, #StackSize
3052  if (!CompareStackPointer && Thumb) {
3053  if (AlignedStackSize < 256) {
3054  BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)
3055  .add(condCodeOp())
3056  .addReg(ScratchReg1)
3057  .addImm(AlignedStackSize)
3058  .add(predOps(ARMCC::AL));
3059  } else {
3060  if (Thumb2) {
3061  BuildMI(McrMBB, DL, TII.get(ARM::t2MOVi32imm), ScratchReg0)
3062  .addImm(AlignedStackSize);
3063  } else {
3064  auto MBBI = McrMBB->end();
3065  auto RegInfo = STI.getRegisterInfo();
3066  RegInfo->emitLoadConstPool(*McrMBB, MBBI, DL, ScratchReg0, 0,
3067  AlignedStackSize);
3068  }
3069  BuildMI(McrMBB, DL, TII.get(ARM::tSUBrr), ScratchReg1)
3070  .add(condCodeOp())
3071  .addReg(ScratchReg1)
3072  .addReg(ScratchReg0)
3073  .add(predOps(ARMCC::AL));
3074  }
3075  } else if (!CompareStackPointer) {
3076  if (AlignedStackSize < 256) {
3077  BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
3078  .addReg(ARM::SP)
3079  .addImm(AlignedStackSize)
3080  .add(predOps(ARMCC::AL))
3081  .add(condCodeOp());
3082  } else {
3083  auto MBBI = McrMBB->end();
3084  auto RegInfo = STI.getRegisterInfo();
3085  RegInfo->emitLoadConstPool(*McrMBB, MBBI, DL, ScratchReg0, 0,
3086  AlignedStackSize);
3087  BuildMI(McrMBB, DL, TII.get(ARM::SUBrr), ScratchReg1)
3088  .addReg(ARM::SP)
3089  .addReg(ScratchReg0)
3090  .add(predOps(ARMCC::AL))
3091  .add(condCodeOp());
3092  }
3093  }
3094 
3095  if (Thumb && ST->isThumb1Only()) {
3096  unsigned PCLabelId = ARMFI->createPICLabelUId();
3098  MF.getFunction().getContext(), "__STACK_LIMIT", PCLabelId, 0);
3100  unsigned CPI = MCP->getConstantPoolIndex(NewCPV, Align(4));
3101 
3102  // ldr SR0, [pc, offset(STACK_LIMIT)]
3103  BuildMI(GetMBB, DL, TII.get(ARM::tLDRpci), ScratchReg0)
3104  .addConstantPoolIndex(CPI)
3105  .add(predOps(ARMCC::AL));
3106 
3107  // ldr SR0, [SR0]
3108  BuildMI(GetMBB, DL, TII.get(ARM::tLDRi), ScratchReg0)
3109  .addReg(ScratchReg0)
3110  .addImm(0)
3111  .add(predOps(ARMCC::AL));
3112  } else {
3113  // Get TLS base address from the coprocessor
3114  // mrc p15, #0, SR0, c13, c0, #3
3115  BuildMI(McrMBB, DL, TII.get(Thumb ? ARM::t2MRC : ARM::MRC),
3116  ScratchReg0)
3117  .addImm(15)
3118  .addImm(0)
3119  .addImm(13)
3120  .addImm(0)
3121  .addImm(3)
3122  .add(predOps(ARMCC::AL));
3123 
3124  // Use the last tls slot on android and a private field of the TCP on linux.
3125  assert(ST->isTargetAndroid() || ST->isTargetLinux());
3126  unsigned TlsOffset = ST->isTargetAndroid() ? 63 : 1;
3127 
3128  // Get the stack limit from the right offset
3129  // ldr SR0, [sr0, #4 * TlsOffset]
3130  BuildMI(GetMBB, DL, TII.get(Thumb ? ARM::t2LDRi12 : ARM::LDRi12),
3131  ScratchReg0)
3132  .addReg(ScratchReg0)
3133  .addImm(4 * TlsOffset)
3134  .add(predOps(ARMCC::AL));
3135  }
3136 
3137  // Compare stack limit with stack size requested.
3138  // cmp SR0, SR1
3139  Opcode = Thumb ? ARM::tCMPr : ARM::CMPrr;
3140  BuildMI(GetMBB, DL, TII.get(Opcode))
3141  .addReg(ScratchReg0)
3142  .addReg(ScratchReg1)
3143  .add(predOps(ARMCC::AL));
3144 
3145  // This jump is taken if StackLimit < SP - stack required.
3146  Opcode = Thumb ? ARM::tBcc : ARM::Bcc;
3147  BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
3148  .addImm(ARMCC::LO)
3149  .addReg(ARM::CPSR);
3150 
3151 
3152  // Calling __morestack(StackSize, Size of stack arguments).
3153  // __morestack knows that the stack size requested is in SR0(r4)
3154  // and amount size of stack arguments is in SR1(r5).
3155 
3156  // Pass first argument for the __morestack by Scratch Register #0.
3157  // The amount size of stack required
3158  if (Thumb) {
3159  if (AlignedStackSize < 256) {
3160  BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0)
3161  .add(condCodeOp())
3162  .addImm(AlignedStackSize)
3163  .add(predOps(ARMCC::AL));
3164  } else {
3165  if (Thumb2) {
3166  BuildMI(AllocMBB, DL, TII.get(ARM::t2MOVi32imm), ScratchReg0)
3167  .addImm(AlignedStackSize);
3168  } else {
3169  auto MBBI = AllocMBB->end();
3170  auto RegInfo = STI.getRegisterInfo();
3171  RegInfo->emitLoadConstPool(*AllocMBB, MBBI, DL, ScratchReg0, 0,
3172  AlignedStackSize);
3173  }
3174  }
3175  } else {
3176  if (AlignedStackSize < 256) {
3177  BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
3178  .addImm(AlignedStackSize)
3179  .add(predOps(ARMCC::AL))
3180  .add(condCodeOp());
3181  } else {
3182  auto MBBI = AllocMBB->end();
3183  auto RegInfo = STI.getRegisterInfo();
3184  RegInfo->emitLoadConstPool(*AllocMBB, MBBI, DL, ScratchReg0, 0,
3185  AlignedStackSize);
3186  }
3187  }
3188 
3189  // Pass second argument for the __morestack by Scratch Register #1.
3190  // The amount size of stack consumed to save function arguments.
3191  if (Thumb) {
3192  if (ARMFI->getArgumentStackSize() < 256) {
3193  BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)
3194  .add(condCodeOp())
3196  .add(predOps(ARMCC::AL));
3197  } else {
3198  if (Thumb2) {
3199  BuildMI(AllocMBB, DL, TII.get(ARM::t2MOVi32imm), ScratchReg1)
3201  } else {
3202  auto MBBI = AllocMBB->end();
3203  auto RegInfo = STI.getRegisterInfo();
3204  RegInfo->emitLoadConstPool(
3205  *AllocMBB, MBBI, DL, ScratchReg1, 0,
3207  }
3208  }
3209  } else {
3210  if (alignToARMConstant(ARMFI->getArgumentStackSize()) < 256) {
3211  BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
3213  .add(predOps(ARMCC::AL))
3214  .add(condCodeOp());
3215  } else {
3216  auto MBBI = AllocMBB->end();
3217  auto RegInfo = STI.getRegisterInfo();
3218  RegInfo->emitLoadConstPool(
3219  *AllocMBB, MBBI, DL, ScratchReg1, 0,
3221  }
3222  }
3223 
3224  // push {lr} - Save return address of this function.
3225  if (Thumb) {
3226  BuildMI(AllocMBB, DL, TII.get(ARM::tPUSH))
3227  .add(predOps(ARMCC::AL))
3228  .addReg(ARM::LR);
3229  } else {
3230  BuildMI(AllocMBB, DL, TII.get(ARM::STMDB_UPD))
3231  .addReg(ARM::SP, RegState::Define)
3232  .addReg(ARM::SP)
3233  .add(predOps(ARMCC::AL))
3234  .addReg(ARM::LR);
3235  }
3236 
3237  // Emit the DWARF info about the change in stack as well as where to find the
3238  // previous link register
3239  if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
3240  CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 12));
3241  BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
3242  .addCFIIndex(CFIIndex);
3244  nullptr, MRI->getDwarfRegNum(ARM::LR, true), -12));
3245  BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
3246  .addCFIIndex(CFIIndex);
3247  }
3248 
3249  // Call __morestack().
3250  if (Thumb) {
3251  BuildMI(AllocMBB, DL, TII.get(ARM::tBL))
3252  .add(predOps(ARMCC::AL))
3253  .addExternalSymbol("__morestack");
3254  } else {
3255  BuildMI(AllocMBB, DL, TII.get(ARM::BL))
3256  .addExternalSymbol("__morestack");
3257  }
3258 
3259  // pop {lr} - Restore return address of this original function.
3260  if (Thumb) {
3261  if (ST->isThumb1Only()) {
3262  BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
3263  .add(predOps(ARMCC::AL))
3264  .addReg(ScratchReg0);
3265  BuildMI(AllocMBB, DL, TII.get(ARM::tMOVr), ARM::LR)
3266  .addReg(ScratchReg0)
3267  .add(predOps(ARMCC::AL));
3268  } else {
3269  BuildMI(AllocMBB, DL, TII.get(ARM::t2LDR_POST))
3270  .addReg(ARM::LR, RegState::Define)
3271  .addReg(ARM::SP, RegState::Define)
3272  .addReg(ARM::SP)
3273  .addImm(4)
3274  .add(predOps(ARMCC::AL));
3275  }
3276  } else {
3277  BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
3278  .addReg(ARM::SP, RegState::Define)
3279  .addReg(ARM::SP)
3280  .add(predOps(ARMCC::AL))
3281  .addReg(ARM::LR);
3282  }
3283 
3284  // Restore SR0 and SR1 in case of __morestack() was called.
3285  // __morestack() will skip PostStackMBB block so we need to restore
3286  // scratch registers from here.
3287  // pop {SR0, SR1}
3288  if (Thumb) {
3289  BuildMI(AllocMBB, DL, TII.get(ARM::tPOP))
3290  .add(predOps(ARMCC::AL))
3291  .addReg(ScratchReg0)
3292  .addReg(ScratchReg1);
3293  } else {
3294  BuildMI(AllocMBB, DL, TII.get(ARM::LDMIA_UPD))
3295  .addReg(ARM::SP, RegState::Define)
3296  .addReg(ARM::SP)
3297  .add(predOps(ARMCC::AL))
3298  .addReg(ScratchReg0)
3299  .addReg(ScratchReg1);
3300  }
3301 
3302  // Update the CFA offset now that we've popped
3303  if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
3304  CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
3305  BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
3306  .addCFIIndex(CFIIndex);
3307  }
3308 
3309  // Return from this function.
3310  BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL));
3311 
3312  // Restore SR0 and SR1 in case of __morestack() was not called.
3313  // pop {SR0, SR1}
3314  if (Thumb) {
3315  BuildMI(PostStackMBB, DL, TII.get(ARM::tPOP))
3316  .add(predOps(ARMCC::AL))
3317  .addReg(ScratchReg0)
3318  .addReg(ScratchReg1);
3319  } else {
3320  BuildMI(PostStackMBB, DL, TII.get(ARM::LDMIA_UPD))
3321  .addReg(ARM::SP, RegState::Define)
3322  .addReg(ARM::SP)
3323  .add(predOps(ARMCC::AL))
3324  .addReg(ScratchReg0)
3325  .addReg(ScratchReg1);
3326  }
3327 
3328  // Update the CFA offset now that we've popped
3329  if (!MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
3330  CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
3331  BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
3332  .addCFIIndex(CFIIndex);
3333 
3334  // Tell debuggers that r4 and r5 are now the same as they were in the
3335  // previous function, that they're the "Same Value".
3337  nullptr, MRI->getDwarfRegNum(ScratchReg0, true)));
3338  BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
3339  .addCFIIndex(CFIIndex);
3341  nullptr, MRI->getDwarfRegNum(ScratchReg1, true)));
3342  BuildMI(PostStackMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
3343  .addCFIIndex(CFIIndex);
3344  }
3345 
3346  // Organizing MBB lists
3347  PostStackMBB->addSuccessor(&PrologueMBB);
3348 
3349  AllocMBB->addSuccessor(PostStackMBB);
3350 
3351  GetMBB->addSuccessor(PostStackMBB);
3352  GetMBB->addSuccessor(AllocMBB);
3353 
3354  McrMBB->addSuccessor(GetMBB);
3355 
3356  PrevStackMBB->addSuccessor(McrMBB);
3357 
3358 #ifdef EXPENSIVE_CHECKS
3359  MF.verify();
3360 #endif
3361 }
llvm::MachineFunction::hasWinCFI
bool hasWinCFI() const
Definition: MachineFunction.h:738
i
i
Definition: README.txt:29
ARMSubtarget.h
llvm::TargetFrameLowering::getCalleeSaves
virtual void getCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const
Returns the callee-saved registers as computed by determineCalleeSaves in the BitVector SavedRegs.
Definition: TargetFrameLoweringImpl.cpp:70
llvm::ARMFunctionInfo::getReturnRegsCount
unsigned getReturnRegsCount() const
Definition: ARMMachineFunctionInfo.h:180
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:354
llvm::ARMFunctionInfo
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
Definition: ARMMachineFunctionInfo.h:27
llvm::ARMFrameLowering::canSimplifyCallFramePseudos
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override
canSimplifyCallFramePseudos - If there is a reserved call frame, the call frame pseudos can be simpli...
Definition: ARMFrameLowering.cpp:244
llvm::ARMBaseRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
Definition: ARMBaseRegisterInfo.cpp:63
llvm::ARMII::AddrMode4
@ AddrMode4
Definition: ARMBaseInfo.h:190
MCDwarf.h
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
MathExtras.h
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm::MachineConstantPool::getConstantPoolIndex
unsigned getConstantPoolIndex(const Constant *C, Align Alignment)
getConstantPoolIndex - Create a new entry in the constant pool or return an existing one.
Definition: MachineFunction.cpp:1477
canSpillOnFrameIndexAccess
static bool canSpillOnFrameIndexAccess(const MachineFunction &MF, const TargetFrameLowering &TFI)
Definition: ARMFrameLowering.cpp:2218
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::SmallVectorImpl::erase
iterator erase(const_iterator CI)
Definition: SmallVector.h:724
llvm::MachineInstrBuilder::copyImplicitOps
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
Definition: MachineInstrBuilder.h:315
llvm::MachineRegisterInfo::isPhysRegUsed
bool isPhysRegUsed(MCRegister PhysReg, bool SkipRegMaskTest=false) const
Return true if the specified register is modified or read in this function.
Definition: MachineRegisterInfo.cpp:581
llvm::ARMFunctionInfo::setGPRCalleeSavedArea2Size
void setGPRCalleeSavedArea2Size(unsigned s)
Definition: ARMMachineFunctionInfo.h:216
llvm::ARMConstantPoolValue
ARMConstantPoolValue - ARM specific constantpool value.
Definition: ARMConstantPoolValue.h:61
llvm::ARMII::AddrModeT2_ldrex
@ AddrModeT2_ldrex
Definition: ARMBaseInfo.h:206
estimateRSStackSizeLimit
static unsigned estimateRSStackSizeLimit(MachineFunction &MF, const TargetFrameLowering *TFI, bool &HasNonSPFrameIndex)
estimateRSStackSizeLimit - Look at each instruction that references stack frames and return the stack...
Definition: ARMFrameLowering.cpp:2064
llvm::ARM_AM::lsr
@ lsr
Definition: ARMAddressingModes.h:31
llvm::SmallPtrSetImpl::erase
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
Definition: SmallPtrSet.h:379
llvm::ARMFunctionInfo::setDPRCalleeSavedGapSize
void setDPRCalleeSavedGapSize(unsigned s)
Definition: ARMMachineFunctionInfo.h:217
llvm::TargetFrameLowering
Information about stack frame layout on the target.
Definition: TargetFrameLowering.h:43
llvm::MachineModuleInfo::getContext
const MCContext & getContext() const
Definition: MachineModuleInfo.h:144
llvm::ARMFrameLowering::getFrameIndexReference
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - Provide a base+offset reference to an FI slot for debug info.
Definition: ARMFrameLowering.cpp:1407
llvm::ARMII::AddrModeT2_i8neg
@ AddrModeT2_i8neg
Definition: ARMBaseInfo.h:200
MCInstrDesc.h
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineBasicBlock::ReplaceUsesOfBlockWith
void ReplaceUsesOfBlockWith(MachineBasicBlock *Old, MachineBasicBlock *New)
Given a machine basic block that branched to 'Old', change the code and CFG so that it branches to 'N...
Definition: MachineBasicBlock.cpp:1339
RegSize
unsigned RegSize
Definition: AArch64MIPeepholeOpt.cpp:121
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
llvm::Function
Definition: Function.h:60
llvm::ARMFunctionInfo::shouldRestoreSPFromFP
bool shouldRestoreSPFromFP() const
Definition: ARMMachineFunctionInfo.h:186
llvm::BitVector::set
BitVector & set()
Definition: BitVector.h:344
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::emitT2RegPlusImmediate
void emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
Definition: Thumb2InstrInfo.cpp:287
llvm::ARMFunctionInfo::setGPRCalleeSavedArea1Size
void setGPRCalleeSavedArea1Size(unsigned s)
Definition: ARMMachineFunctionInfo.h:215
llvm::ARMII::AddrModeT2_i8s4
@ AddrModeT2_i8s4
Definition: ARMBaseInfo.h:203
llvm::MachineInstrBuilder::addCFIIndex
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
Definition: MachineInstrBuilder.h:247
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::CodeModel::Medium
@ Medium
Definition: CodeGen.h:28
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::ARMFrameLowering::assignCalleeSavedSpillSlots
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI) const override
Definition: ARMFrameLowering.cpp:2758
llvm::ARMFunctionInfo::isThumb1OnlyFunction
bool isThumb1OnlyFunction() const
Definition: ARMMachineFunctionInfo.h:168
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::ARMFunctionInfo::createPICLabelUId
unsigned createPICLabelUId()
Definition: ARMMachineFunctionInfo.h:234
llvm::ARMFunctionInfo::getGPRCalleeSavedArea1Size
unsigned getGPRCalleeSavedArea1Size() const
Definition: ARMMachineFunctionInfo.h:208
ARMMachineFunctionInfo.h
llvm::ARMFrameLowering::hasReservedCallFrame
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: ARMFrameLowering.cpp:226
llvm::MachineFrameInfo::getOffsetAdjustment
int getOffsetAdjustment() const
Return the correction for frame offsets.
Definition: MachineFrameInfo.h:586
llvm::ARMFunctionInfo::getGPRCalleeSavedArea2Size
unsigned getGPRCalleeSavedArea2Size() const
Definition: ARMMachineFunctionInfo.h:209
MachineBasicBlock.h
llvm::ARMII::AddrMode3
@ AddrMode3
Definition: ARMBaseInfo.h:189
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::ARMII::AddrMode2
@ AddrMode2
Definition: ARMBaseInfo.h:188
R4
#define R4(n)
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::MCRegisterInfo::getEncodingValue
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Definition: MCRegisterInfo.h:553
llvm::ARMFunctionInfo::getArgumentStackToRestore
unsigned getArgumentStackToRestore() const
Definition: ARMMachineFunctionInfo.h:223
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:319
llvm::StackOffset::getFixed
ScalarTy getFixed() const
Definition: TypeSize.h:149
MachineJumpTableInfo.h
llvm::MachineBasicBlock::liveins
iterator_range< livein_iterator > liveins() const
Definition: MachineBasicBlock.h:422
TargetInstrInfo.h
llvm::ARMII::AddrMode5FP16
@ AddrMode5FP16
Definition: ARMBaseInfo.h:205
llvm::MachineFunction::insert
void insert(iterator MBBI, MachineBasicBlock *MBB)
Definition: MachineFunction.h:872
llvm::ARMSubtarget::getInstrInfo
const ARMBaseInstrInfo * getInstrInfo() const override
Definition: ARMSubtarget.h:264
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
STLExtras.h
llvm::ARMFrameLowering::enableShrinkWrapping
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
Definition: ARMFrameLowering.cpp:2192
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:654
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:28
llvm::ARMFrameLowering::enableCalleeSaveSkip
bool enableCalleeSaveSkip(const MachineFunction &MF) const override
Returns true if the target can safely skip saving callee-saved registers for noreturn nounwind functi...
Definition: ARMFrameLowering.cpp:189
llvm::MCCFIInstruction::createSameValue
static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register)
.cfi_same_value Current value of Register is the same as in the previous frame.
Definition: MCDwarf.h:609
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::ARMFrameLowering::getCalleeSaves
void getCalleeSaves(const MachineFunction &MF, BitVector &SavedRegs) const override
Returns the callee-saved registers as computed by determineCalleeSaves in the BitVector SavedRegs.
Definition: ARMFrameLowering.cpp:2746
llvm::MachineFrameInfo::getMaxCallFrameSize
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
Definition: MachineFrameInfo.h:646
llvm::ARCISD::BL
@ BL
Definition: ARCISelLowering.h:34
llvm::MachineFrameInfo::setObjectAlignment
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
Definition: MachineFrameInfo.h:490
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:159
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::MCCFIInstruction::cfiDefCfaOffset
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:540
MachineRegisterInfo.h
llvm::MachineInstr::FrameDestroy
@ FrameDestroy
Definition: MachineInstr.h:86
llvm::ARMBaseRegisterInfo::getBaseRegister
Register getBaseRegister() const
Definition: ARMBaseRegisterInfo.h:209
llvm::MachineBasicBlock::erase
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1299
llvm::ARMFrameLowering::keepFramePointer
bool keepFramePointer(const MachineFunction &MF) const override
Return true if the target wants to keep the frame pointer regardless of the function attribute "frame...
Definition: ARMFrameLowering.cpp:180
llvm::ARMFunctionInfo::getDPRCalleeSavedAreaSize
unsigned getDPRCalleeSavedAreaSize() const
Definition: ARMMachineFunctionInfo.h:211
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::ARMFunctionInfo::isCmseNSEntryFunction
bool isCmseNSEntryFunction() const
Definition: ARMMachineFunctionInfo.h:171
llvm::MachineBasicBlock::addSuccessor
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:747
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
CommandLine.h
llvm::ARMSubtarget::splitFramePushPop
bool splitFramePushPop(const MachineFunction &MF) const
Returns true if the frame setup is split into two separate pushes (first r0-r7,lr then r8-r11),...
Definition: ARMSubtarget.h:443
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::ARMII::AddrMode_i12
@ AddrMode_i12
Definition: ARMBaseInfo.h:204
ARMConstantPoolValue.h
llvm::getDefRegState
unsigned getDefRegState(bool B)
Definition: MachineInstrBuilder.h:502
R2
#define R2(n)
llvm::TargetRegisterClass::contains
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
Definition: TargetRegisterInfo.h:94
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::isSEHInstruction
static bool isSEHInstruction(const MachineInstr &MI)
Definition: ARMBaseInstrInfo.h:760
llvm::isSplitFPArea2Register
static bool isSplitFPArea2Register(unsigned Reg, bool SplitFramePushPop)
Definition: ARMBaseRegisterInfo.h:89
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::MachineBasicBlock::insertAfter
iterator insertAfter(iterator I, MachineInstr *MI)
Insert MI into the instruction list after I.
Definition: MachineBasicBlock.h:903
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::ARMFunctionInfo::setShouldRestoreSPFromFP
void setShouldRestoreSPFromFP(bool s)
Definition: ARMMachineFunctionInfo.h:187
TargetMachine.h
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
ARMBaseInfo.h
llvm::MutableArrayRef
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:306
llvm::RegState::ImplicitKill
@ ImplicitKill
Definition: MachineInstrBuilder.h:64
llvm::MachineFrameInfo::isReturnAddressTaken
bool isReturnAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Definition: MachineFrameInfo.h:376
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::ARMFunctionInfo::getDPRCalleeSavedGapSize
unsigned getDPRCalleeSavedGapSize() const
Definition: ARMMachineFunctionInfo.h:210
WindowsRequiresStackProbe
static bool WindowsRequiresStackProbe(const MachineFunction &MF, size_t StackSizeInBytes)
Definition: ARMFrameLowering.cpp:555
llvm::TargetFrameLowering::getStackAlign
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Definition: TargetFrameLowering.h:100
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::ARMBaseRegisterInfo::getFrameRegister
Register getFrameRegister(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:485
llvm::MachineRegisterInfo::isReserved
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Definition: MachineRegisterInfo.h:925
llvm::ARMFunctionInfo::setDPRCalleeSavedAreaSize
void setDPRCalleeSavedAreaSize(unsigned s)
Definition: ARMMachineFunctionInfo.h:218
llvm::ARMFrameLowering::emitPrologue
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
Definition: ARMFrameLowering.cpp:705
llvm::Log2
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:209
int
Clang compiles this i1 i64 store i64 i64 store i64 i64 store i64 i64 store i64 align Which gets codegen d xmm0 movaps rbp movaps rbp movaps rbp movaps rbp rbp rbp rbp rbp It would be better to have movq s of instead of the movaps s LLVM produces ret int
Definition: README.txt:536
MCContext.h
llvm::MachineBasicBlock::isSuccessor
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
Definition: MachineBasicBlock.cpp:909
llvm::ARM_AM::no_shift
@ no_shift
Definition: ARMAddressingModes.h:28
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::ARMII::AddrModeT2_i7s4
@ AddrModeT2_i7s4
Definition: ARMBaseInfo.h:207
llvm::ARMFrameLowering::restoreCalleeSavedRegisters
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
Definition: ARMFrameLowering.cpp:2006
getArgumentStackToRestore
static int getArgumentStackToRestore(MachineFunction &MF, MachineBasicBlock &MBB)
Definition: ARMFrameLowering.cpp:253
llvm::MachineInstr::addRegisterKilled
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
Definition: MachineInstr.cpp:1828
TargetOpcodes.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
First
into llvm powi allowing the code generator to produce balanced multiplication trees First
Definition: README.txt:54
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::ARMFunctionInfo::getFramePtrSpillOffset
unsigned getFramePtrSpillOffset() const
Definition: ARMMachineFunctionInfo.h:192
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
ARMBaseInfo.h
llvm::ARMConstantPoolSymbol::Create
static ARMConstantPoolSymbol * Create(LLVMContext &C, StringRef s, unsigned ID, unsigned char PCAdj)
Definition: ARMConstantPoolValue.cpp:233
llvm::MachineModuleInfo
This class contains meta information specific to a module.
Definition: MachineModuleInfo.h:75
llvm::TargetFrameLowering::hasFP
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
insertSEH
static MachineBasicBlock::iterator insertSEH(MachineBasicBlock::iterator MBBI, const TargetInstrInfo &TII, unsigned Flags)
Definition: ARMFrameLowering.cpp:291
checkNumAlignedDPRCS2Regs
static void checkNumAlignedDPRCS2Regs(MachineFunction &MF, BitVector &SavedRegs)
Definition: ARMFrameLowering.cpp:2149
BitVector.h
llvm::ARMBaseRegisterInfo::cannotEliminateFrame
bool cannotEliminateFrame(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:476
llvm::MachineFunction::setHasWinCFI
void setHasWinCFI(bool v)
Definition: MachineFunction.h:741
llvm::MachineFrameInfo::getStackSize
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
Definition: MachineFrameInfo.h:577
DebugLoc.h
SmallPtrSet.h
llvm::MachineFrameInfo::getObjectOffset
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
Definition: MachineFrameInfo.h:518
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
isThumb
static bool isThumb(const MCSubtargetInfo &STI)
Definition: ARMAsmPrinter.cpp:470
llvm::BitVector
Definition: BitVector.h:75
llvm::ARMFunctionInfo::setHasStackFrame
void setHasStackFrame(bool s)
Definition: ARMMachineFunctionInfo.h:184
initMBBRange
static MachineBasicBlock::iterator initMBBRange(MachineBasicBlock &MBB, const MachineBasicBlock::iterator &MBBI)
Definition: ARMFrameLowering.cpp:477
llvm::ARMFunctionInfo::isThumbFunction
bool isThumbFunction() const
Definition: ARMMachineFunctionInfo.h:167
llvm::MachineFunction::verify
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
Definition: MachineVerifier.cpp:339
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::MachineFrameInfo::isFixedObjectIndex
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
Definition: MachineFrameInfo.h:680
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::array_lengthof
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLArrayExtras.h:29
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
emitSPUpdate
static void emitSPUpdate(bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, const ARMBaseInstrInfo &TII, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0)
Definition: ARMFrameLowering.cpp:520
llvm::ARMII::AddrModeT2_i7
@ AddrModeT2_i7
Definition: ARMBaseInfo.h:209
llvm::MCCFIInstruction::createDefCfaRegister
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
Definition: MCDwarf.h:533
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::ARMFrameLowering::hasFP
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
Definition: ARMFrameLowering.cpp:202
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::TargetOptions::DisableFramePointerElim
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
Definition: TargetOptionsImpl.cpp:23
llvm::MachineFunction::getMMI
MachineModuleInfo & getMMI() const
Definition: MachineFunction.h:607
llvm::TargetRegisterInfo::getSpillAlign
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
Definition: TargetRegisterInfo.h:289
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::MachineInstrBuilder::addFrameIndex
const MachineInstrBuilder & addFrameIndex(int Idx) const
Definition: MachineInstrBuilder.h:152
llvm::MachineInstrBuilder::setMIFlag
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
Definition: MachineInstrBuilder.h:278
llvm::Function::hasFnAttribute
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:625
llvm::cl::opt< bool >
llvm::TargetFrameLowering::alignSPAdjust
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
Definition: TargetFrameLowering.h:105
llvm::TargetRegisterInfo::getSpillSize
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Definition: TargetRegisterInfo.h:283
ARMBaseRegisterInfo.h
llvm::count
auto count(R &&Range, const E &Element)
Wrapper function around std::count to count the number of times an element Element occurs in the give...
Definition: STLExtras.h:1709
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:238
llvm::find
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1637
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::ARMFunctionInfo::getFPCXTSaveAreaSize
unsigned getFPCXTSaveAreaSize() const
Definition: ARMMachineFunctionInfo.h:206
llvm::ARM_AM::add
@ add
Definition: ARMAddressingModes.h:39
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1133
llvm::ARMCC::LO
@ LO
Definition: ARMBaseInfo.h:34
llvm::numbers::e
constexpr double e
Definition: MathExtras.h:57
llvm::TargetRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const TargetRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: TargetRegisterInfo.h:588
SpillAlignedNEONRegs
static cl::opt< bool > SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true), cl::desc("Align ARM NEON spills in prolog and epilog"))
llvm::MachineConstantPool
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
Definition: MachineConstantPool.h:117
llvm::ARMFrameLowering::adjustForSegmentedStacks
void adjustForSegmentedStacks(MachineFunction &MF, MachineBasicBlock &MBB) const override
Adjust the prologue to have the function use segmented stacks.
Definition: ARMFrameLowering.cpp:2910
llvm::condCodeOp
static MachineOperand condCodeOp(unsigned CCReg=0)
Get the operand corresponding to the conditional code result.
Definition: ARMBaseInstrInfo.h:550
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::ARMBaseInstrInfo
Definition: ARMBaseInstrInfo.h:37
llvm::ARMII::AddrModeMask
@ AddrModeMask
Definition: ARMBaseInfo.h:303
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
MCRegisterInfo.h
MachineConstantPool.h
llvm::ARMFunctionInfo::setFPCXTSaveAreaSize
void setFPCXTSaveAreaSize(unsigned s)
Definition: ARMMachineFunctionInfo.h:213
llvm::ARMSubtarget::isTargetELF
bool isTargetELF() const
Definition: ARMSubtarget.h:374
llvm::MachineFunction::CreateMachineBasicBlock
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
Definition: MachineFunction.cpp:439
llvm::ARMFrameLowering::ARMFrameLowering
ARMFrameLowering(const ARMSubtarget &sti)
Definition: ARMFrameLowering.cpp:176
llvm::MachineBasicBlock::getLastNonDebugInstr
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
Definition: MachineBasicBlock.cpp:263
emitAlignedDPRCS2Restores
static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI)
Emit aligned reload instructions for NumAlignedDPRCS2Regs D-registers starting from d8.
Definition: ARMFrameLowering.cpp:1862
llvm::ARMSubtarget::getFrameLowering
const ARMFrameLowering * getFrameLowering() const override
Definition: ARMSubtarget.h:272
llvm::ARMFrameLowering::ResolveFrameIndexReference
int ResolveFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg, int SPAdj) const
Definition: ARMFrameLowering.cpp:1413
llvm::MachineInstr::NoFlags
@ NoFlags
Definition: MachineInstr.h:83
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
llvm::ARMSubtarget::splitFramePointerPush
bool splitFramePointerPush(const MachineFunction &MF) const
Definition: ARMSubtarget.cpp:495
llvm::ARMFrameLowering::getCalleeSavedSpillSlots
const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const override
getCalleeSavedSpillSlots - This method returns a pointer to an array of pairs, that contains an entry...
Definition: ARMFrameLowering.cpp:2793
llvm::MachineFunction::getConstantPool
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
Definition: MachineFunction.h:688
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:672
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:234
llvm::RegScavenger::addScavengingFrameIndex
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Definition: RegisterScavenging.h:143
ARMBaseInstrInfo.h
llvm::tryFoldSPUpdateIntoPushPop
bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget, MachineFunction &MF, MachineInstr *MI, unsigned NumBytes)
Tries to add registers to the reglist of a given base-updating push/pop instruction to adjust the sta...
Definition: ARMBaseInstrInfo.cpp:2518
llvm::MCCFIInstruction::cfiDefCfa
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:526
MachineModuleInfo.h
needsWinCFI
static bool needsWinCFI(const MachineFunction &MF)
Definition: ARMFrameLowering.cpp:283
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::ARMII::AddrModeT2_i7s2
@ AddrModeT2_i7s2
Definition: ARMBaseInfo.h:208
llvm::MachineBasicBlock::predecessors
iterator_range< pred_iterator > predecessors()
Definition: MachineBasicBlock.h:359
llvm::MachineFrameInfo::needsSplitStackProlog
bool needsSplitStackProlog() const
Return true if this function requires a split stack prolog, even if it uses no stack space.
Definition: MachineFrameInfo.h:401
R6
#define R6(n)
llvm::MachineFunction
Definition: MachineFunction.h:257
alignToARMConstant
static uint32_t alignToARMConstant(uint32_t Value)
Get the minimum constant for ARM that is greater than or equal to the argument.
Definition: ARMFrameLowering.cpp:2857
llvm::ARMFunctionInfo::setFramePtrSpillOffset
void setFramePtrSpillOffset(unsigned o)
Definition: ARMMachineFunctionInfo.h:193
llvm::MachineBasicBlock::succ_empty
bool succ_empty() const
Definition: MachineBasicBlock.h:357
TargetOptions.h
llvm::MachineFrameInfo::getCalleeSavedInfo
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
Definition: MachineFrameInfo.h:779
llvm::MachineBasicBlock::getFirstTerminator
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
Definition: MachineBasicBlock.cpp:238
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:205
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition: MachineBasicBlock.h:242
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
ARMAddressingModes.h
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
llvm::ARMSubtarget::getRegisterInfo
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:276
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1624
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
Compiler.h
llvm::ARMFunctionInfo::shouldSignReturnAddress
bool shouldSignReturnAddress() const
Definition: ARMMachineFunctionInfo.h:291
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:82
llvm::MachineInstr::NoMerge
@ NoMerge
Definition: MachineInstr.h:112
TargetSubtargetInfo.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ARMFunctionInfo::setGPRCalleeSavedArea2Offset
void setGPRCalleeSavedArea2Offset(unsigned o)
Definition: ARMMachineFunctionInfo.h:203
kSplitStackAvailable
static const uint64_t kSplitStackAvailable
Definition: ARMFrameLowering.cpp:2884
llvm::MachineFrameInfo::getPristineRegs
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
Definition: MachineFrameInfo.cpp:115
llvm::isARMArea2Register
static bool isARMArea2Register(unsigned Reg, bool SplitFramePushPop)
Definition: ARMBaseRegisterInfo.h:62
llvm::ARMFrameLowering::determineCalleeSaves
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: ARMFrameLowering.cpp:2237
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::ARMSubtarget::isTargetWindows
bool isTargetWindows() const
Definition: ARMSubtarget.h:371
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::ARMFunctionInfo::setGPRCalleeSavedArea1Offset
void setGPRCalleeSavedArea1Offset(unsigned o)
Definition: ARMMachineFunctionInfo.h:202
llvm::MachineFrameInfo::getMaxAlign
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Definition: MachineFrameInfo.h:593
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:377
llvm::MachineFrameInfo::isFrameAddressTaken
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Definition: MachineFrameInfo.h:370
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1644
llvm::ARMII::AddrMode6
@ AddrMode6
Definition: ARMBaseInfo.h:192
llvm::MachineFrameInfo::hasCalls
bool hasCalls() const
Return true if the current function has any function calls.
Definition: MachineFrameInfo.h:605
llvm::ARM_AM::getAM2Opc
unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, unsigned IdxMode=0)
Definition: ARMAddressingModes.h:413
llvm::ARMBaseRegisterInfo
Definition: ARMBaseRegisterInfo.h:127
CallingConv.h
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
Attributes.h
llvm::ARMFrameLowering::emitEpilogue
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
Definition: ARMFrameLowering.cpp:1246
llvm::BitVector::test
bool test(unsigned Idx) const
Definition: BitVector.h:454
sizeOfSPAdjustment
static int sizeOfSPAdjustment(const MachineInstr &MI)
Definition: ARMFrameLowering.cpp:530
llvm::MachineRegisterInfo::isLiveIn
bool isLiveIn(Register Reg) const
Definition: MachineRegisterInfo.cpp:432
ARMFrameLowering.h
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::TargetSubtargetInfo::getFrameLowering
virtual const TargetFrameLowering * getFrameLowering() const
Definition: TargetSubtargetInfo.h:94
llvm::CalleeSavedInfo
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Definition: MachineFrameInfo.h:33
llvm::MachineBasicBlock::sortUniqueLiveIns
void sortUniqueLiveIns()
Sorts and uniques the LiveIns vector.
Definition: MachineBasicBlock.cpp:582
uint16_t
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:652
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:345
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::ARMII::AddrMode5
@ AddrMode5
Definition: ARMBaseInfo.h:191
llvm::ARMBaseRegisterInfo::canRealignStack
bool canRealignStack(const MachineFunction &MF) const override
Definition: ARMBaseRegisterInfo.cpp:453
llvm::ARMII::AddrModeT2_i12
@ AddrModeT2_i12
Definition: ARMBaseInfo.h:197
llvm::TargetFrameLowering::getFrameIndexReference
virtual StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const
getFrameIndexReference - This method should return the base register and offset used to reference a f...
Definition: TargetFrameLoweringImpl.cpp:50
llvm::ARMFunctionInfo::setDPRCalleeSavedAreaOffset
void setDPRCalleeSavedAreaOffset(unsigned o)
Definition: ARMMachineFunctionInfo.h:204
llvm::MachineInstrBuilder::addConstantPoolIndex
const MachineInstrBuilder & addConstantPoolIndex(unsigned Idx, int Offset=0, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:158
insertSEHRange
static void insertSEHRange(MachineBasicBlock &MBB, MachineBasicBlock::iterator Start, const MachineBasicBlock::iterator &End, const ARMBaseInstrInfo &TII, unsigned MIFlags)
Definition: ARMFrameLowering.cpp:483
emitRegPlusImmediate
static void emitRegPlusImmediate(bool isARM, MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, const ARMBaseInstrInfo &TII, unsigned DestReg, unsigned SrcReg, int NumBytes, unsigned MIFlags=MachineInstr::NoFlags, ARMCC::CondCodes Pred=ARMCC::AL, unsigned PredReg=0)
Definition: ARMFrameLowering.cpp:507
Function.h
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::sort
void sort(IteratorTy Start, IteratorTy End)
Definition: STLExtras.h:1562
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
emitAlignedDPRCS2Spills
static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI)
Emit aligned spill instructions for NumAlignedDPRCS2Regs D-registers starting from d8.
Definition: ARMFrameLowering.cpp:1689
llvm::ARMFunctionInfo::setLRIsSpilled
void setLRIsSpilled(bool s)
Definition: ARMMachineFunctionInfo.h:190
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:591
emitAligningInstructions
static void emitAligningInstructions(MachineFunction &MF, ARMFunctionInfo *AFI, const TargetInstrInfo &TII, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const unsigned Reg, const Align Alignment, const bool MustBeSingleInstruction)
Emit an instruction sequence that will align the address in register Reg by zero-ing out the lower bi...
Definition: ARMFrameLowering.cpp:620
llvm::ARMCC::CondCodes
CondCodes
Definition: ARMBaseInfo.h:30
llvm::ARM_AM::getSORegOpc
unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm)
Definition: ARMAddressingModes.h:112
llvm::ARMFunctionInfo::getArgumentStackSize
unsigned getArgumentStackSize() const
Definition: ARMMachineFunctionInfo.h:220
CodeGen.h
llvm::TargetRegisterInfo::hasStackRealignment
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
Definition: TargetRegisterInfo.h:947
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
llvm::Function::isVarArg
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
Definition: Function.h:188
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineFunction::addFrameInst
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
Definition: MachineFunction.cpp:310
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::isARMArea3Register
static bool isARMArea3Register(unsigned Reg, bool SplitFramePushPop)
Definition: ARMBaseRegisterInfo.h:101
llvm::ARMFunctionInfo::getNumAlignedDPRCS2Regs
unsigned getNumAlignedDPRCS2Regs() const
Definition: ARMMachineFunctionInfo.h:195
llvm::isSplitFPArea1Register
static bool isSplitFPArea1Register(unsigned Reg, bool SplitFramePushPop)
Definition: ARMBaseRegisterInfo.h:74
SmallVector.h
llvm::ARMFrameLowering::STI
const ARMSubtarget & STI
Definition: ARMFrameLowering.h:23
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:278
MachineInstrBuilder.h
llvm::ARMFunctionInfo::hasStackFrame
bool hasStackFrame() const
Definition: ARMMachineFunctionInfo.h:183
llvm::MachineInstrBuilder::setMIFlags
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
Definition: MachineInstrBuilder.h:273
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::emitARMRegPlusImmediate
void emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags=0)
emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of instructions to materializea des...
Definition: ARMBaseInstrInfo.cpp:2477
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
llvm::ARMFunctionInfo::getArgRegsSaveSize
unsigned getArgRegsSaveSize() const
Definition: ARMMachineFunctionInfo.h:177
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
MachineOperand.h
llvm::ARMBaseRegisterInfo::hasBasePointer
bool hasBasePointer(const MachineFunction &MF) const
Definition: ARMBaseRegisterInfo.cpp:416
llvm::isARMLowRegister
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:160
llvm::MachineFrameInfo::setOffsetAdjustment
void setOffsetAdjustment(int Adj)
Set the correction for frame offsets.
Definition: MachineFrameInfo.h:589
llvm::MCCFIInstruction::createOffset
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:564
requiresAAPCSFrameRecord
static bool requiresAAPCSFrameRecord(const MachineFunction &MF)
Definition: ARMFrameLowering.cpp:2209
llvm::ARMFrameLowering::spillCalleeSavedRegisters
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Definition: ARMFrameLowering.cpp:1952
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
getMaxFPOffset
static int getMaxFPOffset(const ARMSubtarget &STI, const ARMFunctionInfo &AFI, const MachineFunction &MF)
We need the offset of the frame pointer relative to other MachineFrameInfo offsets which are encoded ...
Definition: ARMFrameLowering.cpp:686
llvm::predOps
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Definition: ARMBaseInstrInfo.h:542
llvm::MachineFrameInfo::getStackProtectorIndex
int getStackProtectorIndex() const
Return the index for the stack protector object.
Definition: MachineFrameInfo.h:357
llvm::ARMFunctionInfo::getPreservesR0
bool getPreservesR0() const
Definition: ARMMachineFunctionInfo.h:289
llvm::TargetFrameLowering::determineCalleeSaves
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
Definition: TargetFrameLoweringImpl.cpp:83
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
EstimateFunctionSizeInBytes
static unsigned EstimateFunctionSizeInBytes(const MachineFunction &MF, const ARMBaseInstrInfo &TII)
Definition: ARMFrameLowering.cpp:2046
llvm::HexagonII::FPPos
@ FPPos
Definition: HexagonBaseInfo.h:139
llvm::cl::desc
Definition: CommandLine.h:405
RegisterScavenging.h
raw_ostream.h
MachineFunction.h
llvm::printReg
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:111
llvm::ARMFunctionInfo::isThumb2Function
bool isThumb2Function() const
Definition: ARMMachineFunctionInfo.h:169
llvm::CallingConv::GHC
@ GHC
Definition: CallingConv.h:51
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCAsmInfo::usesWindowsCFI
bool usesWindowsCFI() const
Definition: MCAsmInfo.h:793
llvm::TargetFrameLowering::SpillSlot
Definition: TargetFrameLowering.h:51
llvm::ARMFrameLowering::isFPReserved
bool isFPReserved(const MachineFunction &MF) const
isFPReserved - Return true if the frame pointer register should be considered a reserved register on ...
Definition: ARMFrameLowering.cpp:217
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
TargetRegisterInfo.h
Debug.h
llvm::ARM_AM::lsl
@ lsl
Definition: ARMAddressingModes.h:30
llvm::isARMArea1Register
static bool isARMArea1Register(unsigned Reg, bool SplitFramePushPop)
isARMArea1Register - Returns true if the register is a low register (r0-r7) or a stack/pc register th...
Definition: ARMBaseRegisterInfo.h:46
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:280
llvm::ARMBaseRegisterInfo::emitLoadConstPool
virtual void emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred=ARMCC::AL, Register PredReg=Register(), unsigned MIFlags=MachineInstr::NoFlags) const
emitLoadConstPool - Emits a load from constpool to materialize the specified immediate.
Definition: ARMBaseRegisterInfo.cpp:496
llvm::t1CondCodeOp
static MachineOperand t1CondCodeOp(bool isDead=false)
Get the operand corresponding to the conditional code result for Thumb1.
Definition: ARMBaseInstrInfo.h:557
llvm::SmallPtrSetImpl::insert
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:365
skipAlignedDPRCS2Spills
static MachineBasicBlock::iterator skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs)
Skip past the code inserted by emitAlignedDPRCS2Spills, and return an iterator to the following instr...
Definition: ARMFrameLowering.cpp:1832