LLVM  14.0.0git
ARMAsmPrinter.cpp
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1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format ARM assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMAsmPrinter.h"
15 #include "ARM.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMTargetObjectFile.h"
22 #include "MCTargetDesc/ARMMCExpr.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/BinaryFormat/COFF.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/MC/TargetRegistry.h"
46 #include "llvm/Support/Debug.h"
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "asm-printer"
54 
56  std::unique_ptr<MCStreamer> Streamer)
57  : AsmPrinter(TM, std::move(Streamer)), Subtarget(nullptr), AFI(nullptr),
58  MCP(nullptr), InConstantPool(false), OptimizationGoals(-1) {}
59 
61  // Make sure to terminate any constant pools that were at the end
62  // of the function.
63  if (!InConstantPool)
64  return;
65  InConstantPool = false;
66  OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
67 }
68 
70  if (AFI->isThumbFunction()) {
71  OutStreamer->emitAssemblerFlag(MCAF_Code16);
72  OutStreamer->emitThumbFunc(CurrentFnSym);
73  } else {
74  OutStreamer->emitAssemblerFlag(MCAF_Code32);
75  }
76 
77  // Emit symbol for CMSE non-secure entry point
78  if (AFI->isCmseNSEntryFunction()) {
79  MCSymbol *S =
82  OutStreamer->emitSymbolAttribute(S, MCSA_ELF_TypeFunction);
83  OutStreamer->emitLabel(S);
84  }
85 
86  OutStreamer->emitLabel(CurrentFnSym);
87 }
88 
91  assert(Size && "C++ constructor pointer had zero size!");
92 
93  const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
94  assert(GV && "C++ constructor pointer was not a GlobalValue!");
95 
96  const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
98  (Subtarget->isTargetELF()
101  OutContext);
102 
103  OutStreamer->emitValue(E, Size);
104 }
105 
107  if (PromotedGlobals.count(GV))
108  // The global was promoted into a constant pool. It should not be emitted.
109  return;
111 }
112 
113 /// runOnMachineFunction - This uses the emitInstruction()
114 /// method to print assembly for each instruction.
115 ///
117  AFI = MF.getInfo<ARMFunctionInfo>();
118  MCP = MF.getConstantPool();
119  Subtarget = &MF.getSubtarget<ARMSubtarget>();
120 
122  const Function &F = MF.getFunction();
123  const TargetMachine& TM = MF.getTarget();
124 
125  // Collect all globals that had their storage promoted to a constant pool.
126  // Functions are emitted before variables, so this accumulates promoted
127  // globals from all functions in PromotedGlobals.
128  for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
129  PromotedGlobals.insert(GV);
130 
131  // Calculate this function's optimization goal.
132  unsigned OptimizationGoal;
133  if (F.hasOptNone())
134  // For best debugging illusion, speed and small size sacrificed
135  OptimizationGoal = 6;
136  else if (F.hasMinSize())
137  // Aggressively for small size, speed and debug illusion sacrificed
138  OptimizationGoal = 4;
139  else if (F.hasOptSize())
140  // For small size, but speed and debugging illusion preserved
141  OptimizationGoal = 3;
142  else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
143  // Aggressively for speed, small size and debug illusion sacrificed
144  OptimizationGoal = 2;
145  else if (TM.getOptLevel() > CodeGenOpt::None)
146  // For speed, but small size and good debug illusion preserved
147  OptimizationGoal = 1;
148  else // TM.getOptLevel() == CodeGenOpt::None
149  // For good debugging, but speed and small size preserved
150  OptimizationGoal = 5;
151 
152  // Combine a new optimization goal with existing ones.
153  if (OptimizationGoals == -1) // uninitialized goals
154  OptimizationGoals = OptimizationGoal;
155  else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
156  OptimizationGoals = 0;
157 
158  if (Subtarget->isTargetCOFF()) {
159  bool Internal = F.hasInternalLinkage();
163 
164  OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
165  OutStreamer->EmitCOFFSymbolStorageClass(Scl);
166  OutStreamer->EmitCOFFSymbolType(Type);
167  OutStreamer->EndCOFFSymbolDef();
168  }
169 
170  // Emit the rest of the function body.
172 
173  // Emit the XRay table for this function.
174  emitXRayTable();
175 
176  // If we need V4T thumb mode Register Indirect Jump pads, emit them.
177  // These are created per function, rather than per TU, since it's
178  // relatively easy to exceed the thumb branch range within a TU.
179  if (! ThumbIndirectPads.empty()) {
180  OutStreamer->emitAssemblerFlag(MCAF_Code16);
181  emitAlignment(Align(2));
182  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
183  OutStreamer->emitLabel(TIP.second);
185  .addReg(TIP.first)
186  // Add predicate operands.
187  .addImm(ARMCC::AL)
188  .addReg(0));
189  }
190  ThumbIndirectPads.clear();
191  }
192 
193  // We didn't modify anything.
194  return false;
195 }
196 
198  raw_ostream &O) {
199  assert(MO.isGlobal() && "caller should check MO.isGlobal");
200  unsigned TF = MO.getTargetFlags();
201  if (TF & ARMII::MO_LO16)
202  O << ":lower16:";
203  else if (TF & ARMII::MO_HI16)
204  O << ":upper16:";
205  GetARMGVSymbol(MO.getGlobal(), TF)->print(O, MAI);
206  printOffset(MO.getOffset(), O);
207 }
208 
210  raw_ostream &O) {
211  const MachineOperand &MO = MI->getOperand(OpNum);
212 
213  switch (MO.getType()) {
214  default: llvm_unreachable("<unknown operand type>");
216  Register Reg = MO.getReg();
218  assert(!MO.getSubReg() && "Subregs should be eliminated!");
219  if(ARM::GPRPairRegClass.contains(Reg)) {
220  const MachineFunction &MF = *MI->getParent()->getParent();
222  Reg = TRI->getSubReg(Reg, ARM::gsub_0);
223  }
225  break;
226  }
228  O << '#';
229  unsigned TF = MO.getTargetFlags();
230  if (TF == ARMII::MO_LO16)
231  O << ":lower16:";
232  else if (TF == ARMII::MO_HI16)
233  O << ":upper16:";
234  O << MO.getImm();
235  break;
236  }
238  MO.getMBB()->getSymbol()->print(O, MAI);
239  return;
241  PrintSymbolOperand(MO, O);
242  break;
243  }
245  if (Subtarget->genExecuteOnly())
246  llvm_unreachable("execute-only should not generate constant pools");
247  GetCPISymbol(MO.getIndex())->print(O, MAI);
248  break;
249  }
250 }
251 
252 MCSymbol *ARMAsmPrinter::GetCPISymbol(unsigned CPID) const {
253  // The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
254  // indexes in MachineConstantPool, which isn't in sync with indexes used here.
255  const DataLayout &DL = getDataLayout();
256  return OutContext.getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
257  "CPI" + Twine(getFunctionNumber()) + "_" +
258  Twine(CPID));
259 }
260 
261 //===--------------------------------------------------------------------===//
262 
263 MCSymbol *ARMAsmPrinter::
264 GetARMJTIPICJumpTableLabel(unsigned uid) const {
265  const DataLayout &DL = getDataLayout();
267  raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
268  << getFunctionNumber() << '_' << uid;
270 }
271 
272 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
273  const char *ExtraCode, raw_ostream &O) {
274  // Does this asm operand have a single letter operand modifier?
275  if (ExtraCode && ExtraCode[0]) {
276  if (ExtraCode[1] != 0) return true; // Unknown modifier.
277 
278  switch (ExtraCode[0]) {
279  default:
280  // See if this is a generic print operand
281  return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
282  case 'P': // Print a VFP double precision register.
283  case 'q': // Print a NEON quad precision register.
284  printOperand(MI, OpNum, O);
285  return false;
286  case 'y': // Print a VFP single precision register as indexed double.
287  if (MI->getOperand(OpNum).isReg()) {
288  MCRegister Reg = MI->getOperand(OpNum).getReg().asMCReg();
290  // Find the 'd' register that has this 's' register as a sub-register,
291  // and determine the lane number.
292  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
293  if (!ARM::DPRRegClass.contains(*SR))
294  continue;
295  bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
296  O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
297  return false;
298  }
299  }
300  return true;
301  case 'B': // Bitwise inverse of integer or symbol without a preceding #.
302  if (!MI->getOperand(OpNum).isImm())
303  return true;
304  O << ~(MI->getOperand(OpNum).getImm());
305  return false;
306  case 'L': // The low 16 bits of an immediate constant.
307  if (!MI->getOperand(OpNum).isImm())
308  return true;
309  O << (MI->getOperand(OpNum).getImm() & 0xffff);
310  return false;
311  case 'M': { // A register range suitable for LDM/STM.
312  if (!MI->getOperand(OpNum).isReg())
313  return true;
314  const MachineOperand &MO = MI->getOperand(OpNum);
315  Register RegBegin = MO.getReg();
316  // This takes advantage of the 2 operand-ness of ldm/stm and that we've
317  // already got the operands in registers that are operands to the
318  // inline asm statement.
319  O << "{";
320  if (ARM::GPRPairRegClass.contains(RegBegin)) {
322  Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
323  O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
324  RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
325  }
326  O << ARMInstPrinter::getRegisterName(RegBegin);
327 
328  // FIXME: The register allocator not only may not have given us the
329  // registers in sequence, but may not be in ascending registers. This
330  // will require changes in the register allocator that'll need to be
331  // propagated down here if the operands change.
332  unsigned RegOps = OpNum + 1;
333  while (MI->getOperand(RegOps).isReg()) {
334  O << ", "
335  << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
336  RegOps++;
337  }
338 
339  O << "}";
340 
341  return false;
342  }
343  case 'R': // The most significant register of a pair.
344  case 'Q': { // The least significant register of a pair.
345  if (OpNum == 0)
346  return true;
347  const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
348  if (!FlagsOP.isImm())
349  return true;
350  unsigned Flags = FlagsOP.getImm();
351 
352  // This operand may not be the one that actually provides the register. If
353  // it's tied to a previous one then we should refer instead to that one
354  // for registers and their classes.
355  unsigned TiedIdx;
356  if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
357  for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
358  unsigned OpFlags = MI->getOperand(OpNum).getImm();
359  OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
360  }
361  Flags = MI->getOperand(OpNum).getImm();
362 
363  // Later code expects OpNum to be pointing at the register rather than
364  // the flags.
365  OpNum += 1;
366  }
367 
368  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
369  unsigned RC;
370  bool FirstHalf;
371  const ARMBaseTargetMachine &ATM =
372  static_cast<const ARMBaseTargetMachine &>(TM);
373 
374  // 'Q' should correspond to the low order register and 'R' to the high
375  // order register. Whether this corresponds to the upper or lower half
376  // depends on the endianess mode.
377  if (ExtraCode[0] == 'Q')
378  FirstHalf = ATM.isLittleEndian();
379  else
380  // ExtraCode[0] == 'R'.
381  FirstHalf = !ATM.isLittleEndian();
383  if (InlineAsm::hasRegClassConstraint(Flags, RC) &&
384  ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
385  if (NumVals != 1)
386  return true;
387  const MachineOperand &MO = MI->getOperand(OpNum);
388  if (!MO.isReg())
389  return true;
391  Register Reg =
392  TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1);
394  return false;
395  }
396  if (NumVals != 2)
397  return true;
398  unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
399  if (RegOp >= MI->getNumOperands())
400  return true;
401  const MachineOperand &MO = MI->getOperand(RegOp);
402  if (!MO.isReg())
403  return true;
404  Register Reg = MO.getReg();
406  return false;
407  }
408 
409  case 'e': // The low doubleword register of a NEON quad register.
410  case 'f': { // The high doubleword register of a NEON quad register.
411  if (!MI->getOperand(OpNum).isReg())
412  return true;
413  Register Reg = MI->getOperand(OpNum).getReg();
414  if (!ARM::QPRRegClass.contains(Reg))
415  return true;
417  Register SubReg =
418  TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1);
420  return false;
421  }
422 
423  // This modifier is not yet supported.
424  case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
425  return true;
426  case 'H': { // The highest-numbered register of a pair.
427  const MachineOperand &MO = MI->getOperand(OpNum);
428  if (!MO.isReg())
429  return true;
430  const MachineFunction &MF = *MI->getParent()->getParent();
432  Register Reg = MO.getReg();
433  if(!ARM::GPRPairRegClass.contains(Reg))
434  return false;
435  Reg = TRI->getSubReg(Reg, ARM::gsub_1);
437  return false;
438  }
439  }
440  }
441 
442  printOperand(MI, OpNum, O);
443  return false;
444 }
445 
447  unsigned OpNum, const char *ExtraCode,
448  raw_ostream &O) {
449  // Does this asm operand have a single letter operand modifier?
450  if (ExtraCode && ExtraCode[0]) {
451  if (ExtraCode[1] != 0) return true; // Unknown modifier.
452 
453  switch (ExtraCode[0]) {
454  case 'A': // A memory operand for a VLD1/VST1 instruction.
455  default: return true; // Unknown modifier.
456  case 'm': // The base register of a memory operand.
457  if (!MI->getOperand(OpNum).isReg())
458  return true;
459  O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
460  return false;
461  }
462  }
463 
464  const MachineOperand &MO = MI->getOperand(OpNum);
465  assert(MO.isReg() && "unexpected inline asm memory operand");
466  O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
467  return false;
468 }
469 
470 static bool isThumb(const MCSubtargetInfo& STI) {
471  return STI.getFeatureBits()[ARM::ModeThumb];
472 }
473 
475  const MCSubtargetInfo *EndInfo) const {
476  // If either end mode is unknown (EndInfo == NULL) or different than
477  // the start mode, then restore the start mode.
478  const bool WasThumb = isThumb(StartInfo);
479  if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
480  OutStreamer->emitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
481  }
482 }
483 
485  const Triple &TT = TM.getTargetTriple();
486  // Use unified assembler syntax.
487  OutStreamer->emitAssemblerFlag(MCAF_SyntaxUnified);
488 
489  // Emit ARM Build Attributes
490  if (TT.isOSBinFormatELF())
491  emitAttributes();
492 
493  // Use the triple's architecture and subarchitecture to determine
494  // if we're thumb for the purposes of the top level code16 assembler
495  // flag.
496  if (!M.getModuleInlineAsm().empty() && TT.isThumb())
497  OutStreamer->emitAssemblerFlag(MCAF_Code16);
498 }
499 
500 static void
503  // L_foo$stub:
504  OutStreamer.emitLabel(StubLabel);
505  // .indirect_symbol _foo
506  OutStreamer.emitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
507 
508  if (MCSym.getInt())
509  // External to current translation unit.
510  OutStreamer.emitIntValue(0, 4/*size*/);
511  else
512  // Internal to current translation unit.
513  //
514  // When we place the LSDA into the TEXT section, the type info
515  // pointers need to be indirect and pc-rel. We accomplish this by
516  // using NLPs; however, sometimes the types are local to the file.
517  // We need to fill in the value for the NLP in those cases.
518  OutStreamer.emitValue(
519  MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
520  4 /*size*/);
521 }
522 
523 
525  const Triple &TT = TM.getTargetTriple();
526  if (TT.isOSBinFormatMachO()) {
527  // All darwin targets use mach-o.
528  const TargetLoweringObjectFileMachO &TLOFMacho =
529  static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
530  MachineModuleInfoMachO &MMIMacho =
532 
533  // Output non-lazy-pointers for external and common global variables.
535 
536  if (!Stubs.empty()) {
537  // Switch with ".non_lazy_symbol_pointer" directive.
538  OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
539  emitAlignment(Align(4));
540 
541  for (auto &Stub : Stubs)
542  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
543 
544  Stubs.clear();
545  OutStreamer->AddBlankLine();
546  }
547 
548  Stubs = MMIMacho.GetThreadLocalGVStubList();
549  if (!Stubs.empty()) {
550  // Switch with ".non_lazy_symbol_pointer" directive.
551  OutStreamer->SwitchSection(TLOFMacho.getThreadLocalPointerSection());
552  emitAlignment(Align(4));
553 
554  for (auto &Stub : Stubs)
555  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
556 
557  Stubs.clear();
558  OutStreamer->AddBlankLine();
559  }
560 
561  // Funny Darwin hack: This flag tells the linker that no global symbols
562  // contain code that falls through to other global symbols (e.g. the obvious
563  // implementation of multiple entry points). If this doesn't occur, the
564  // linker can safely perform dead code stripping. Since LLVM never
565  // generates code that does this, it is always safe to set.
566  OutStreamer->emitAssemblerFlag(MCAF_SubsectionsViaSymbols);
567  }
568 
569  // The last attribute to be emitted is ABI_optimization_goals
570  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
571  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
572 
573  if (OptimizationGoals > 0 &&
574  (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
575  Subtarget->isTargetMuslAEABI()))
577  OptimizationGoals = -1;
578 
580 }
581 
582 //===----------------------------------------------------------------------===//
583 // Helper routines for emitStartOfAsmFile() and emitEndOfAsmFile()
584 // FIXME:
585 // The following seem like one-off assembler flags, but they actually need
586 // to appear in the .ARM.attributes section in ELF.
587 // Instead of subclassing the MCELFStreamer, we do the work here.
588 
589  // Returns true if all functions have the same function attribute value.
590  // It also returns true when the module has no functions.
592  StringRef Value) {
593  return !any_of(M, [&](const Function &F) {
594  return F.getFnAttribute(Attr).getValueAsString() != Value;
595  });
596 }
597 // Returns true if all functions have the same denormal mode.
598 // It also returns true when the module has no functions.
600  StringRef Attr,
602  return !any_of(M, [&](const Function &F) {
603  StringRef AttrVal = F.getFnAttribute(Attr).getValueAsString();
604  return parseDenormalFPAttribute(AttrVal) != Value;
605  });
606 }
607 
608 void ARMAsmPrinter::emitAttributes() {
609  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
610  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
611 
613 
614  ATS.switchVendor("aeabi");
615 
616  // Compute ARM ELF Attributes based on the default subtarget that
617  // we'd have constructed. The existing ARM behavior isn't LTO clean
618  // anyhow.
619  // FIXME: For ifunc related functions we could iterate over and look
620  // for a feature string that doesn't match the default one.
621  const Triple &TT = TM.getTargetTriple();
622  StringRef CPU = TM.getTargetCPU();
624  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
625  if (!FS.empty()) {
626  if (!ArchFS.empty())
627  ArchFS = (Twine(ArchFS) + "," + FS).str();
628  else
629  ArchFS = std::string(FS);
630  }
631  const ARMBaseTargetMachine &ATM =
632  static_cast<const ARMBaseTargetMachine &>(TM);
633  const ARMSubtarget STI(TT, std::string(CPU), ArchFS, ATM,
634  ATM.isLittleEndian());
635 
636  // Emit build attributes for the available hardware.
637  ATS.emitTargetAttributes(STI);
638 
639  // RW data addressing.
640  if (isPositionIndependent()) {
643  } else if (STI.isRWPI()) {
644  // RWPI specific attributes.
647  }
648 
649  // RO data addressing.
650  if (isPositionIndependent() || STI.isROPI()) {
653  }
654 
655  // GOT use.
656  if (isPositionIndependent()) {
659  } else {
662  }
663 
664  // Set FP Denormals.
665  if (checkDenormalAttributeConsistency(*MMI->getModule(), "denormal-fp-math",
670  "denormal-fp-math",
674  else if (!TM.Options.UnsafeFPMath)
677  else {
678  if (!STI.hasVFP2Base()) {
679  // When the target doesn't have an FPU (by design or
680  // intention), the assumptions made on the software support
681  // mirror that of the equivalent hardware support *if it
682  // existed*. For v7 and better we indicate that denormals are
683  // flushed preserving sign, and for V6 we indicate that
684  // denormals are flushed to positive zero.
685  if (STI.hasV7Ops())
688  } else if (STI.hasVFP3Base()) {
689  // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
690  // the sign bit of the zero matches the sign bit of the input or
691  // result that is being flushed to zero.
694  }
695  // For VFPv2 implementations it is implementation defined as
696  // to whether denormals are flushed to positive zero or to
697  // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
698  // LLVM has chosen to flush this to positive zero (most likely for
699  // GCC compatibility), so that's the chosen value here (the
700  // absence of its emission implies zero).
701  }
702 
703  // Set FP exceptions and rounding
705  "no-trapping-math", "true") ||
709  else if (!TM.Options.UnsafeFPMath) {
711 
712  // If the user has permitted this code to choose the IEEE 754
713  // rounding at run-time, emit the rounding attribute.
716  }
717 
718  // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
719  // equivalent of GCC's -ffinite-math-only flag.
723  else
726 
727  // FIXME: add more flags to ARMBuildAttributes.h
728  // 8-bytes alignment stuff.
731 
732  // Hard float. Use both S and D registers and conform to AAPCS-VFP.
733  if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
735 
736  // FIXME: To support emitting this build attribute as GCC does, the
737  // -mfp16-format option and associated plumbing must be
738  // supported. For now the __fp16 type is exposed by default, so this
739  // attribute should be emitted with value 1.
742 
743  if (MMI) {
744  if (const Module *SourceModule = MMI->getModule()) {
745  // ABI_PCS_wchar_t to indicate wchar_t width
746  // FIXME: There is no way to emit value 0 (wchar_t prohibited).
747  if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
748  SourceModule->getModuleFlag("wchar_size"))) {
749  int WCharWidth = WCharWidthValue->getZExtValue();
750  assert((WCharWidth == 2 || WCharWidth == 4) &&
751  "wchar_t width must be 2 or 4 bytes");
753  }
754 
755  // ABI_enum_size to indicate enum width
756  // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
757  // (all enums contain a value needing 32 bits to encode).
758  if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
759  SourceModule->getModuleFlag("min_enum_size"))) {
760  int EnumWidth = EnumWidthValue->getZExtValue();
761  assert((EnumWidth == 1 || EnumWidth == 4) &&
762  "Minimum enum width must be 1 or 4 bytes");
763  int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
764  ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
765  }
766 
767  auto *PACValue = mdconst::extract_or_null<ConstantInt>(
768  SourceModule->getModuleFlag("sign-return-address"));
769  if (PACValue && PACValue->getZExtValue() == 1) {
770  // If "+pacbti" is used as an architecture extension,
771  // Tag_PAC_extension is emitted in
772  // ARMTargetStreamer::emitTargetAttributes().
773  if (!STI.hasPACBTI()) {
776  }
778  }
779 
780  auto *BTIValue = mdconst::extract_or_null<ConstantInt>(
781  SourceModule->getModuleFlag("branch-target-enforcement"));
782  if (BTIValue && BTIValue->getZExtValue() == 1) {
783  // If "+pacbti" is used as an architecture extension,
784  // Tag_BTI_extension is emitted in
785  // ARMTargetStreamer::emitTargetAttributes().
786  if (!STI.hasPACBTI()) {
789  }
791  }
792  }
793  }
794 
795  // We currently do not support using R9 as the TLS pointer.
796  if (STI.isRWPI())
799  else if (STI.isR9Reserved())
802  else
805 }
806 
807 //===----------------------------------------------------------------------===//
808 
809 static MCSymbol *getBFLabel(StringRef Prefix, unsigned FunctionNumber,
810  unsigned LabelId, MCContext &Ctx) {
811 
812  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
813  + "BF" + Twine(FunctionNumber) + "_" + Twine(LabelId));
814  return Label;
815 }
816 
817 static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
818  unsigned LabelId, MCContext &Ctx) {
819 
820  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
821  + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
822  return Label;
823 }
824 
827  switch (Modifier) {
828  case ARMCP::no_modifier:
830  case ARMCP::TLSGD:
832  case ARMCP::TPOFF:
834  case ARMCP::GOTTPOFF:
836  case ARMCP::SBREL:
838  case ARMCP::GOT_PREL:
840  case ARMCP::SECREL:
842  }
843  llvm_unreachable("Invalid ARMCPModifier!");
844 }
845 
846 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
847  unsigned char TargetFlags) {
848  if (Subtarget->isTargetMachO()) {
849  bool IsIndirect =
850  (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
851 
852  if (!IsIndirect)
853  return getSymbol(GV);
854 
855  // FIXME: Remove this when Darwin transition to @GOT like syntax.
856  MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
857  MachineModuleInfoMachO &MMIMachO =
860  GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
861  : MMIMachO.getGVStubEntry(MCSym);
862 
863  if (!StubSym.getPointer())
865  !GV->hasInternalLinkage());
866  return MCSym;
867  } else if (Subtarget->isTargetCOFF()) {
868  assert(Subtarget->isTargetWindows() &&
869  "Windows is the only supported COFF target");
870 
871  bool IsIndirect =
872  (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB));
873  if (!IsIndirect)
874  return getSymbol(GV);
875 
877  if (TargetFlags & ARMII::MO_DLLIMPORT)
878  Name = "__imp_";
879  else if (TargetFlags & ARMII::MO_COFFSTUB)
880  Name = ".refptr.";
881  getNameWithPrefix(Name, GV);
882 
884 
885  if (TargetFlags & ARMII::MO_COFFSTUB) {
886  MachineModuleInfoCOFF &MMICOFF =
889  MMICOFF.getGVStubEntry(MCSym);
890 
891  if (!StubSym.getPointer())
892  StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV), true);
893  }
894 
895  return MCSym;
896  } else if (Subtarget->isTargetELF()) {
897  return getSymbol(GV);
898  }
899  llvm_unreachable("unexpected target");
900 }
901 
903  MachineConstantPoolValue *MCPV) {
904  const DataLayout &DL = getDataLayout();
905  int Size = DL.getTypeAllocSize(MCPV->getType());
906 
907  ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
908 
909  if (ACPV->isPromotedGlobal()) {
910  // This constant pool entry is actually a global whose storage has been
911  // promoted into the constant pool. This global may be referenced still
912  // by debug information, and due to the way AsmPrinter is set up, the debug
913  // info is immutable by the time we decide to promote globals to constant
914  // pools. Because of this, we need to ensure we emit a symbol for the global
915  // with private linkage (the default) so debug info can refer to it.
916  //
917  // However, if this global is promoted into several functions we must ensure
918  // we don't try and emit duplicate symbols!
919  auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
920  for (const auto *GV : ACPC->promotedGlobals()) {
921  if (!EmittedPromotedGlobalLabels.count(GV)) {
922  MCSymbol *GVSym = getSymbol(GV);
923  OutStreamer->emitLabel(GVSym);
924  EmittedPromotedGlobalLabels.insert(GV);
925  }
926  }
927  return emitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
928  }
929 
930  MCSymbol *MCSym;
931  if (ACPV->isLSDA()) {
932  MCSym = getMBBExceptionSym(MF->front());
933  } else if (ACPV->isBlockAddress()) {
934  const BlockAddress *BA =
935  cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
936  MCSym = GetBlockAddressSymbol(BA);
937  } else if (ACPV->isGlobalValue()) {
938  const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
939 
940  // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
941  // flag the global as MO_NONLAZY.
942  unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
943  MCSym = GetARMGVSymbol(GV, TF);
944  } else if (ACPV->isMachineBasicBlock()) {
945  const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
946  MCSym = MBB->getSymbol();
947  } else {
948  assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
949  auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
950  MCSym = GetExternalSymbolSymbol(Sym);
951  }
952 
953  // Create an MCSymbol for the reference.
954  const MCExpr *Expr =
956  OutContext);
957 
958  if (ACPV->getPCAdjustment()) {
959  MCSymbol *PCLabel =
960  getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
961  ACPV->getLabelId(), OutContext);
962  const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
963  PCRelExpr =
964  MCBinaryExpr::createAdd(PCRelExpr,
966  OutContext),
967  OutContext);
968  if (ACPV->mustAddCurrentAddress()) {
969  // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
970  // label, so just emit a local label end reference that instead.
972  OutStreamer->emitLabel(DotSym);
973  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
974  PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
975  }
976  Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
977  }
978  OutStreamer->emitValue(Expr, Size);
979 }
980 
982  const MachineOperand &MO1 = MI->getOperand(1);
983  unsigned JTI = MO1.getIndex();
984 
985  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
986  // ARM mode tables.
987  emitAlignment(Align(4));
988 
989  // Emit a label for the jump table.
990  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
991  OutStreamer->emitLabel(JTISymbol);
992 
993  // Mark the jump table as data-in-code.
994  OutStreamer->emitDataRegion(MCDR_DataRegionJT32);
995 
996  // Emit each entry of the table.
997  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
998  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
999  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1000 
1001  for (MachineBasicBlock *MBB : JTBBs) {
1002  // Construct an MCExpr for the entry. We want a value of the form:
1003  // (BasicBlockAddr - TableBeginAddr)
1004  //
1005  // For example, a table with entries jumping to basic blocks BB0 and BB1
1006  // would look like:
1007  // LJTI_0_0:
1008  // .word (LBB0 - LJTI_0_0)
1009  // .word (LBB1 - LJTI_0_0)
1011 
1012  if (isPositionIndependent() || Subtarget->isROPI())
1013  Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
1014  OutContext),
1015  OutContext);
1016  // If we're generating a table of Thumb addresses in static relocation
1017  // model, we need to add one to keep interworking correctly.
1018  else if (AFI->isThumbFunction())
1020  OutContext);
1021  OutStreamer->emitValue(Expr, 4);
1022  }
1023  // Mark the end of jump table data-in-code region.
1024  OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1025 }
1026 
1028  const MachineOperand &MO1 = MI->getOperand(1);
1029  unsigned JTI = MO1.getIndex();
1030 
1031  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1032  // ARM mode tables.
1033  emitAlignment(Align(4));
1034 
1035  // Emit a label for the jump table.
1036  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1037  OutStreamer->emitLabel(JTISymbol);
1038 
1039  // Emit each entry of the table.
1040  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1041  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1042  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1043 
1044  for (MachineBasicBlock *MBB : JTBBs) {
1045  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1046  OutContext);
1047  // If this isn't a TBB or TBH, the entries are direct branch instructions.
1049  .addExpr(MBBSymbolExpr)
1050  .addImm(ARMCC::AL)
1051  .addReg(0));
1052  }
1053 }
1054 
1056  unsigned OffsetWidth) {
1057  assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1058  const MachineOperand &MO1 = MI->getOperand(1);
1059  unsigned JTI = MO1.getIndex();
1060 
1061  if (Subtarget->isThumb1Only())
1062  emitAlignment(Align(4));
1063 
1064  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1065  OutStreamer->emitLabel(JTISymbol);
1066 
1067  // Emit each entry of the table.
1068  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1069  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1070  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1071 
1072  // Mark the jump table as data-in-code.
1073  OutStreamer->emitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1075 
1076  for (auto MBB : JTBBs) {
1077  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1078  OutContext);
1079  // Otherwise it's an offset from the dispatch instruction. Construct an
1080  // MCExpr for the entry. We want a value of the form:
1081  // (BasicBlockAddr - TBBInstAddr + 4) / 2
1082  //
1083  // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1084  // would look like:
1085  // LJTI_0_0:
1086  // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1087  // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1088  // where LCPI0_0 is a label defined just before the TBB instruction using
1089  // this table.
1090  MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1091  const MCExpr *Expr = MCBinaryExpr::createAdd(
1094  Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1096  OutContext);
1097  OutStreamer->emitValue(Expr, OffsetWidth);
1098  }
1099  // Mark the end of jump table data-in-code region. 32-bit offsets use
1100  // actual branch instructions here, so we don't mark those as a data-region
1101  // at all.
1102  OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1103 
1104  // Make sure the next instruction is 2-byte aligned.
1105  emitAlignment(Align(2));
1106 }
1107 
1108 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1109  assert(MI->getFlag(MachineInstr::FrameSetup) &&
1110  "Only instruction which are involved into frame setup code are allowed");
1111 
1112  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1113  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1114  const MachineFunction &MF = *MI->getParent()->getParent();
1115  const TargetRegisterInfo *TargetRegInfo =
1117  const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
1118 
1119  Register FramePtr = TargetRegInfo->getFrameRegister(MF);
1120  unsigned Opc = MI->getOpcode();
1121  unsigned SrcReg, DstReg;
1122 
1123  switch (Opc) {
1124  case ARM::tPUSH:
1125  // special case: tPUSH does not have src/dst regs.
1126  SrcReg = DstReg = ARM::SP;
1127  break;
1128  case ARM::tLDRpci:
1129  case ARM::t2MOVi16:
1130  case ARM::t2MOVTi16:
1131  // special cases:
1132  // 1) for Thumb1 code we sometimes materialize the constant via constpool
1133  // load.
1134  // 2) for Thumb2 execute only code we materialize the constant via
1135  // immediate constants in 2 separate instructions (MOVW/MOVT).
1136  SrcReg = ~0U;
1137  DstReg = MI->getOperand(0).getReg();
1138  break;
1139  default:
1140  SrcReg = MI->getOperand(1).getReg();
1141  DstReg = MI->getOperand(0).getReg();
1142  break;
1143  }
1144 
1145  // Try to figure out the unwinding opcode out of src / dst regs.
1146  if (MI->mayStore()) {
1147  // Register saves.
1148  assert(DstReg == ARM::SP &&
1149  "Only stack pointer as a destination reg is supported");
1150 
1151  SmallVector<unsigned, 4> RegList;
1152  // Skip src & dst reg, and pred ops.
1153  unsigned StartOp = 2 + 2;
1154  // Use all the operands.
1155  unsigned NumOffset = 0;
1156  // Amount of SP adjustment folded into a push, before the
1157  // registers are stored (pad at higher addresses).
1158  unsigned PadBefore = 0;
1159  // Amount of SP adjustment folded into a push, after the
1160  // registers are stored (pad at lower addresses).
1161  unsigned PadAfter = 0;
1162 
1163  switch (Opc) {
1164  default:
1165  MI->print(errs());
1166  llvm_unreachable("Unsupported opcode for unwinding information");
1167  case ARM::tPUSH:
1168  // Special case here: no src & dst reg, but two extra imp ops.
1169  StartOp = 2; NumOffset = 2;
1171  case ARM::STMDB_UPD:
1172  case ARM::t2STMDB_UPD:
1173  case ARM::VSTMDDB_UPD:
1174  assert(SrcReg == ARM::SP &&
1175  "Only stack pointer as a source reg is supported");
1176  for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1177  i != NumOps; ++i) {
1178  const MachineOperand &MO = MI->getOperand(i);
1179  // Actually, there should never be any impdef stuff here. Skip it
1180  // temporary to workaround PR11902.
1181  if (MO.isImplicit())
1182  continue;
1183  // Registers, pushed as a part of folding an SP update into the
1184  // push instruction are marked as undef and should not be
1185  // restored when unwinding, because the function can modify the
1186  // corresponding stack slots.
1187  if (MO.isUndef()) {
1188  assert(RegList.empty() &&
1189  "Pad registers must come before restored ones");
1190  unsigned Width =
1191  TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
1192  PadAfter += Width;
1193  continue;
1194  }
1195  // Check for registers that are remapped (for a Thumb1 prologue that
1196  // saves high registers).
1197  Register Reg = MO.getReg();
1198  if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Reg))
1199  Reg = RemappedReg;
1200  RegList.push_back(Reg);
1201  }
1202  break;
1203  case ARM::STR_PRE_IMM:
1204  case ARM::STR_PRE_REG:
1205  case ARM::t2STR_PRE:
1206  assert(MI->getOperand(2).getReg() == ARM::SP &&
1207  "Only stack pointer as a source reg is supported");
1208  if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1209  SrcReg = RemappedReg;
1210 
1211  RegList.push_back(SrcReg);
1212  break;
1213  case ARM::t2STRD_PRE:
1214  assert(MI->getOperand(3).getReg() == ARM::SP &&
1215  "Only stack pointer as a source reg is supported");
1216  SrcReg = MI->getOperand(1).getReg();
1217  if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1218  SrcReg = RemappedReg;
1219  RegList.push_back(SrcReg);
1220  SrcReg = MI->getOperand(2).getReg();
1221  if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1222  SrcReg = RemappedReg;
1223  RegList.push_back(SrcReg);
1224  PadBefore = -MI->getOperand(4).getImm() - 8;
1225  break;
1226  }
1228  if (PadBefore)
1229  ATS.emitPad(PadBefore);
1230  ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1231  // Account for the SP adjustment, folded into the push.
1232  if (PadAfter)
1233  ATS.emitPad(PadAfter);
1234  }
1235  } else {
1236  // Changes of stack / frame pointer.
1237  if (SrcReg == ARM::SP) {
1238  int64_t Offset = 0;
1239  switch (Opc) {
1240  default:
1241  MI->print(errs());
1242  llvm_unreachable("Unsupported opcode for unwinding information");
1243  case ARM::MOVr:
1244  case ARM::tMOVr:
1245  Offset = 0;
1246  break;
1247  case ARM::ADDri:
1248  case ARM::t2ADDri:
1249  case ARM::t2ADDri12:
1250  case ARM::t2ADDspImm:
1251  case ARM::t2ADDspImm12:
1252  Offset = -MI->getOperand(2).getImm();
1253  break;
1254  case ARM::SUBri:
1255  case ARM::t2SUBri:
1256  case ARM::t2SUBri12:
1257  case ARM::t2SUBspImm:
1258  case ARM::t2SUBspImm12:
1259  Offset = MI->getOperand(2).getImm();
1260  break;
1261  case ARM::tSUBspi:
1262  Offset = MI->getOperand(2).getImm()*4;
1263  break;
1264  case ARM::tADDspi:
1265  case ARM::tADDrSPi:
1266  Offset = -MI->getOperand(2).getImm()*4;
1267  break;
1268  case ARM::tADDhirr:
1269  Offset =
1270  -AFI->EHPrologueOffsetInRegs.lookup(MI->getOperand(2).getReg());
1271  break;
1272  }
1273 
1275  if (DstReg == FramePtr && FramePtr != ARM::SP)
1276  // Set-up of the frame pointer. Positive values correspond to "add"
1277  // instruction.
1278  ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1279  else if (DstReg == ARM::SP) {
1280  // Change of SP by an offset. Positive values correspond to "sub"
1281  // instruction.
1282  ATS.emitPad(Offset);
1283  } else {
1284  // Move of SP to a register. Positive values correspond to an "add"
1285  // instruction.
1286  ATS.emitMovSP(DstReg, -Offset);
1287  }
1288  }
1289  } else if (DstReg == ARM::SP) {
1290  MI->print(errs());
1291  llvm_unreachable("Unsupported opcode for unwinding information");
1292  } else {
1293  int64_t Offset = 0;
1294  switch (Opc) {
1295  case ARM::tMOVr:
1296  // If a Thumb1 function spills r8-r11, we copy the values to low
1297  // registers before pushing them. Record the copy so we can emit the
1298  // correct ".save" later.
1299  AFI->EHPrologueRemappedRegs[DstReg] = SrcReg;
1300  break;
1301  case ARM::tLDRpci: {
1302  // Grab the constpool index and check, whether it corresponds to
1303  // original or cloned constpool entry.
1304  unsigned CPI = MI->getOperand(1).getIndex();
1305  const MachineConstantPool *MCP = MF.getConstantPool();
1306  if (CPI >= MCP->getConstants().size())
1307  CPI = AFI->getOriginalCPIdx(CPI);
1308  assert(CPI != -1U && "Invalid constpool index");
1309 
1310  // Derive the actual offset.
1311  const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1312  assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1313  Offset = cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1314  AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1315  break;
1316  }
1317  case ARM::t2MOVi16:
1318  Offset = MI->getOperand(1).getImm();
1319  AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1320  break;
1321  case ARM::t2MOVTi16:
1322  Offset = MI->getOperand(2).getImm();
1323  AFI->EHPrologueOffsetInRegs[DstReg] |= (Offset << 16);
1324  break;
1325  case ARM::t2PAC:
1326  case ARM::t2PACBTI:
1327  AFI->EHPrologueRemappedRegs[ARM::R12] = ARM::RA_AUTH_CODE;
1328  break;
1329  default:
1330  MI->print(errs());
1331  llvm_unreachable("Unsupported opcode for unwinding information");
1332  }
1333  }
1334  }
1335 }
1336 
1337 // Simple pseudo-instructions have their lowering (with expansion to real
1338 // instructions) auto-generated.
1339 #include "ARMGenMCPseudoLowering.inc"
1340 
1342  const DataLayout &DL = getDataLayout();
1343  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1344  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1345 
1346  // If we just ended a constant pool, mark it as such.
1347  if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1348  OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1349  InConstantPool = false;
1350  }
1351 
1352  // Emit unwinding stuff for frame-related instructions
1353  if (Subtarget->isTargetEHABICompatible() &&
1354  MI->getFlag(MachineInstr::FrameSetup))
1355  EmitUnwindingInstruction(MI);
1356 
1357  // Do any auto-generated pseudo lowerings.
1358  if (emitPseudoExpansionLowering(*OutStreamer, MI))
1359  return;
1360 
1361  assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1362  "Pseudo flag setting opcode should be expanded early");
1363 
1364  // Check for manual lowerings.
1365  unsigned Opc = MI->getOpcode();
1366  switch (Opc) {
1367  case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1368  case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1369  case ARM::LEApcrel:
1370  case ARM::tLEApcrel:
1371  case ARM::t2LEApcrel: {
1372  // FIXME: Need to also handle globals and externals
1373  MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1374  EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1375  ARM::t2LEApcrel ? ARM::t2ADR
1376  : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1377  : ARM::ADR))
1378  .addReg(MI->getOperand(0).getReg())
1380  // Add predicate operands.
1381  .addImm(MI->getOperand(2).getImm())
1382  .addReg(MI->getOperand(3).getReg()));
1383  return;
1384  }
1385  case ARM::LEApcrelJT:
1386  case ARM::tLEApcrelJT:
1387  case ARM::t2LEApcrelJT: {
1388  MCSymbol *JTIPICSymbol =
1389  GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1390  EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1391  ARM::t2LEApcrelJT ? ARM::t2ADR
1392  : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1393  : ARM::ADR))
1394  .addReg(MI->getOperand(0).getReg())
1395  .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1396  // Add predicate operands.
1397  .addImm(MI->getOperand(2).getImm())
1398  .addReg(MI->getOperand(3).getReg()));
1399  return;
1400  }
1401  // Darwin call instructions are just normal call instructions with different
1402  // clobber semantics (they clobber R9).
1403  case ARM::BX_CALL: {
1405  .addReg(ARM::LR)
1406  .addReg(ARM::PC)
1407  // Add predicate operands.
1408  .addImm(ARMCC::AL)
1409  .addReg(0)
1410  // Add 's' bit operand (always reg0 for this)
1411  .addReg(0));
1412 
1413  assert(Subtarget->hasV4TOps());
1415  .addReg(MI->getOperand(0).getReg()));
1416  return;
1417  }
1418  case ARM::tBX_CALL: {
1419  if (Subtarget->hasV5TOps())
1420  llvm_unreachable("Expected BLX to be selected for v5t+");
1421 
1422  // On ARM v4t, when doing a call from thumb mode, we need to ensure
1423  // that the saved lr has its LSB set correctly (the arch doesn't
1424  // have blx).
1425  // So here we generate a bl to a small jump pad that does bx rN.
1426  // The jump pads are emitted after the function body.
1427 
1428  Register TReg = MI->getOperand(0).getReg();
1429  MCSymbol *TRegSym = nullptr;
1430  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
1431  if (TIP.first == TReg) {
1432  TRegSym = TIP.second;
1433  break;
1434  }
1435  }
1436 
1437  if (!TRegSym) {
1438  TRegSym = OutContext.createTempSymbol();
1439  ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1440  }
1441 
1442  // Create a link-saving branch to the Reg Indirect Jump Pad.
1444  // Predicate comes first here.
1445  .addImm(ARMCC::AL).addReg(0)
1446  .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1447  return;
1448  }
1449  case ARM::BMOVPCRX_CALL: {
1451  .addReg(ARM::LR)
1452  .addReg(ARM::PC)
1453  // Add predicate operands.
1454  .addImm(ARMCC::AL)
1455  .addReg(0)
1456  // Add 's' bit operand (always reg0 for this)
1457  .addReg(0));
1458 
1460  .addReg(ARM::PC)
1461  .addReg(MI->getOperand(0).getReg())
1462  // Add predicate operands.
1463  .addImm(ARMCC::AL)
1464  .addReg(0)
1465  // Add 's' bit operand (always reg0 for this)
1466  .addReg(0));
1467  return;
1468  }
1469  case ARM::BMOVPCB_CALL: {
1471  .addReg(ARM::LR)
1472  .addReg(ARM::PC)
1473  // Add predicate operands.
1474  .addImm(ARMCC::AL)
1475  .addReg(0)
1476  // Add 's' bit operand (always reg0 for this)
1477  .addReg(0));
1478 
1479  const MachineOperand &Op = MI->getOperand(0);
1480  const GlobalValue *GV = Op.getGlobal();
1481  const unsigned TF = Op.getTargetFlags();
1482  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1483  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1485  .addExpr(GVSymExpr)
1486  // Add predicate operands.
1487  .addImm(ARMCC::AL)
1488  .addReg(0));
1489  return;
1490  }
1491  case ARM::MOVi16_ga_pcrel:
1492  case ARM::t2MOVi16_ga_pcrel: {
1493  MCInst TmpInst;
1494  TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1495  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1496 
1497  unsigned TF = MI->getOperand(1).getTargetFlags();
1498  const GlobalValue *GV = MI->getOperand(1).getGlobal();
1499  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1500  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1501 
1502  MCSymbol *LabelSym =
1503  getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1504  MI->getOperand(2).getImm(), OutContext);
1505  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1506  unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1507  const MCExpr *PCRelExpr =
1509  MCBinaryExpr::createAdd(LabelSymExpr,
1512  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1513 
1514  // Add predicate operands.
1516  TmpInst.addOperand(MCOperand::createReg(0));
1517  // Add 's' bit operand (always reg0 for this)
1518  TmpInst.addOperand(MCOperand::createReg(0));
1519  EmitToStreamer(*OutStreamer, TmpInst);
1520  return;
1521  }
1522  case ARM::MOVTi16_ga_pcrel:
1523  case ARM::t2MOVTi16_ga_pcrel: {
1524  MCInst TmpInst;
1525  TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1526  ? ARM::MOVTi16 : ARM::t2MOVTi16);
1527  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1528  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1529 
1530  unsigned TF = MI->getOperand(2).getTargetFlags();
1531  const GlobalValue *GV = MI->getOperand(2).getGlobal();
1532  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1533  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1534 
1535  MCSymbol *LabelSym =
1536  getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1537  MI->getOperand(3).getImm(), OutContext);
1538  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1539  unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1540  const MCExpr *PCRelExpr =
1542  MCBinaryExpr::createAdd(LabelSymExpr,
1545  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1546  // Add predicate operands.
1548  TmpInst.addOperand(MCOperand::createReg(0));
1549  // Add 's' bit operand (always reg0 for this)
1550  TmpInst.addOperand(MCOperand::createReg(0));
1551  EmitToStreamer(*OutStreamer, TmpInst);
1552  return;
1553  }
1554  case ARM::t2BFi:
1555  case ARM::t2BFic:
1556  case ARM::t2BFLi:
1557  case ARM::t2BFr:
1558  case ARM::t2BFLr: {
1559  // This is a Branch Future instruction.
1560 
1561  const MCExpr *BranchLabel = MCSymbolRefExpr::create(
1562  getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1563  MI->getOperand(0).getIndex(), OutContext),
1564  OutContext);
1565 
1566  auto MCInst = MCInstBuilder(Opc).addExpr(BranchLabel);
1567  if (MI->getOperand(1).isReg()) {
1568  // For BFr/BFLr
1569  MCInst.addReg(MI->getOperand(1).getReg());
1570  } else {
1571  // For BFi/BFLi/BFic
1572  const MCExpr *BranchTarget;
1573  if (MI->getOperand(1).isMBB())
1575  MI->getOperand(1).getMBB()->getSymbol(), OutContext);
1576  else if (MI->getOperand(1).isGlobal()) {
1577  const GlobalValue *GV = MI->getOperand(1).getGlobal();
1579  GetARMGVSymbol(GV, MI->getOperand(1).getTargetFlags()), OutContext);
1580  } else if (MI->getOperand(1).isSymbol()) {
1582  GetExternalSymbolSymbol(MI->getOperand(1).getSymbolName()),
1583  OutContext);
1584  } else
1585  llvm_unreachable("Unhandled operand kind in Branch Future instruction");
1586 
1587  MCInst.addExpr(BranchTarget);
1588  }
1589 
1590  if (Opc == ARM::t2BFic) {
1591  const MCExpr *ElseLabel = MCSymbolRefExpr::create(
1592  getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1593  MI->getOperand(2).getIndex(), OutContext),
1594  OutContext);
1595  MCInst.addExpr(ElseLabel);
1596  MCInst.addImm(MI->getOperand(3).getImm());
1597  } else {
1598  MCInst.addImm(MI->getOperand(2).getImm())
1599  .addReg(MI->getOperand(3).getReg());
1600  }
1601 
1603  return;
1604  }
1605  case ARM::t2BF_LabelPseudo: {
1606  // This is a pseudo op for a label used by a branch future instruction
1607 
1608  // Emit the label.
1609  OutStreamer->emitLabel(getBFLabel(DL.getPrivateGlobalPrefix(),
1611  MI->getOperand(0).getIndex(), OutContext));
1612  return;
1613  }
1614  case ARM::tPICADD: {
1615  // This is a pseudo op for a label + instruction sequence, which looks like:
1616  // LPC0:
1617  // add r0, pc
1618  // This adds the address of LPC0 to r0.
1619 
1620  // Emit the label.
1621  OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1623  MI->getOperand(2).getImm(), OutContext));
1624 
1625  // Form and emit the add.
1626  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1627  .addReg(MI->getOperand(0).getReg())
1628  .addReg(MI->getOperand(0).getReg())
1629  .addReg(ARM::PC)
1630  // Add predicate operands.
1631  .addImm(ARMCC::AL)
1632  .addReg(0));
1633  return;
1634  }
1635  case ARM::PICADD: {
1636  // This is a pseudo op for a label + instruction sequence, which looks like:
1637  // LPC0:
1638  // add r0, pc, r0
1639  // This adds the address of LPC0 to r0.
1640 
1641  // Emit the label.
1642  OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1644  MI->getOperand(2).getImm(), OutContext));
1645 
1646  // Form and emit the add.
1648  .addReg(MI->getOperand(0).getReg())
1649  .addReg(ARM::PC)
1650  .addReg(MI->getOperand(1).getReg())
1651  // Add predicate operands.
1652  .addImm(MI->getOperand(3).getImm())
1653  .addReg(MI->getOperand(4).getReg())
1654  // Add 's' bit operand (always reg0 for this)
1655  .addReg(0));
1656  return;
1657  }
1658  case ARM::PICSTR:
1659  case ARM::PICSTRB:
1660  case ARM::PICSTRH:
1661  case ARM::PICLDR:
1662  case ARM::PICLDRB:
1663  case ARM::PICLDRH:
1664  case ARM::PICLDRSB:
1665  case ARM::PICLDRSH: {
1666  // This is a pseudo op for a label + instruction sequence, which looks like:
1667  // LPC0:
1668  // OP r0, [pc, r0]
1669  // The LCP0 label is referenced by a constant pool entry in order to get
1670  // a PC-relative address at the ldr instruction.
1671 
1672  // Emit the label.
1673  OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1675  MI->getOperand(2).getImm(), OutContext));
1676 
1677  // Form and emit the load
1678  unsigned Opcode;
1679  switch (MI->getOpcode()) {
1680  default:
1681  llvm_unreachable("Unexpected opcode!");
1682  case ARM::PICSTR: Opcode = ARM::STRrs; break;
1683  case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1684  case ARM::PICSTRH: Opcode = ARM::STRH; break;
1685  case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1686  case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1687  case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1688  case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1689  case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1690  }
1692  .addReg(MI->getOperand(0).getReg())
1693  .addReg(ARM::PC)
1694  .addReg(MI->getOperand(1).getReg())
1695  .addImm(0)
1696  // Add predicate operands.
1697  .addImm(MI->getOperand(3).getImm())
1698  .addReg(MI->getOperand(4).getReg()));
1699 
1700  return;
1701  }
1702  case ARM::CONSTPOOL_ENTRY: {
1703  if (Subtarget->genExecuteOnly())
1704  llvm_unreachable("execute-only should not generate constant pools");
1705 
1706  /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1707  /// in the function. The first operand is the ID# for this instruction, the
1708  /// second is the index into the MachineConstantPool that this is, the third
1709  /// is the size in bytes of this constant pool entry.
1710  /// The required alignment is specified on the basic block holding this MI.
1711  unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1712  unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1713 
1714  // If this is the first entry of the pool, mark it.
1715  if (!InConstantPool) {
1716  OutStreamer->emitDataRegion(MCDR_DataRegion);
1717  InConstantPool = true;
1718  }
1719 
1720  OutStreamer->emitLabel(GetCPISymbol(LabelId));
1721 
1722  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1723  if (MCPE.isMachineConstantPoolEntry())
1725  else
1727  return;
1728  }
1729  case ARM::JUMPTABLE_ADDRS:
1731  return;
1732  case ARM::JUMPTABLE_INSTS:
1734  return;
1735  case ARM::JUMPTABLE_TBB:
1736  case ARM::JUMPTABLE_TBH:
1737  emitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1738  return;
1739  case ARM::t2BR_JT: {
1741  .addReg(ARM::PC)
1742  .addReg(MI->getOperand(0).getReg())
1743  // Add predicate operands.
1744  .addImm(ARMCC::AL)
1745  .addReg(0));
1746  return;
1747  }
1748  case ARM::t2TBB_JT:
1749  case ARM::t2TBH_JT: {
1750  unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1751  // Lower and emit the PC label, then the instruction itself.
1752  OutStreamer->emitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1754  .addReg(MI->getOperand(0).getReg())
1755  .addReg(MI->getOperand(1).getReg())
1756  // Add predicate operands.
1757  .addImm(ARMCC::AL)
1758  .addReg(0));
1759  return;
1760  }
1761  case ARM::tTBB_JT:
1762  case ARM::tTBH_JT: {
1763 
1764  bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1765  Register Base = MI->getOperand(0).getReg();
1766  Register Idx = MI->getOperand(1).getReg();
1767  assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1768 
1769  // Multiply up idx if necessary.
1770  if (!Is8Bit)
1772  .addReg(Idx)
1773  .addReg(ARM::CPSR)
1774  .addReg(Idx)
1775  .addImm(1)
1776  // Add predicate operands.
1777  .addImm(ARMCC::AL)
1778  .addReg(0));
1779 
1780  if (Base == ARM::PC) {
1781  // TBB [base, idx] =
1782  // ADDS idx, idx, base
1783  // LDRB idx, [idx, #4] ; or LDRH if TBH
1784  // LSLS idx, #1
1785  // ADDS pc, pc, idx
1786 
1787  // When using PC as the base, it's important that there is no padding
1788  // between the last ADDS and the start of the jump table. The jump table
1789  // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1790  //
1791  // FIXME: Ideally we could vary the LDRB index based on the padding
1792  // between the sequence and jump table, however that relies on MCExprs
1793  // for load indexes which are currently not supported.
1794  OutStreamer->emitCodeAlignment(4, &getSubtargetInfo());
1795  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1796  .addReg(Idx)
1797  .addReg(Idx)
1798  .addReg(Base)
1799  // Add predicate operands.
1800  .addImm(ARMCC::AL)
1801  .addReg(0));
1802 
1803  unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1805  .addReg(Idx)
1806  .addReg(Idx)
1807  .addImm(Is8Bit ? 4 : 2)
1808  // Add predicate operands.
1809  .addImm(ARMCC::AL)
1810  .addReg(0));
1811  } else {
1812  // TBB [base, idx] =
1813  // LDRB idx, [base, idx] ; or LDRH if TBH
1814  // LSLS idx, #1
1815  // ADDS pc, pc, idx
1816 
1817  unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1819  .addReg(Idx)
1820  .addReg(Base)
1821  .addReg(Idx)
1822  // Add predicate operands.
1823  .addImm(ARMCC::AL)
1824  .addReg(0));
1825  }
1826 
1828  .addReg(Idx)
1829  .addReg(ARM::CPSR)
1830  .addReg(Idx)
1831  .addImm(1)
1832  // Add predicate operands.
1833  .addImm(ARMCC::AL)
1834  .addReg(0));
1835 
1836  OutStreamer->emitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1837  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1838  .addReg(ARM::PC)
1839  .addReg(ARM::PC)
1840  .addReg(Idx)
1841  // Add predicate operands.
1842  .addImm(ARMCC::AL)
1843  .addReg(0));
1844  return;
1845  }
1846  case ARM::tBR_JTr:
1847  case ARM::BR_JTr: {
1848  // mov pc, target
1849  MCInst TmpInst;
1850  unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1851  ARM::MOVr : ARM::tMOVr;
1852  TmpInst.setOpcode(Opc);
1853  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1854  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1855  // Add predicate operands.
1857  TmpInst.addOperand(MCOperand::createReg(0));
1858  // Add 's' bit operand (always reg0 for this)
1859  if (Opc == ARM::MOVr)
1860  TmpInst.addOperand(MCOperand::createReg(0));
1861  EmitToStreamer(*OutStreamer, TmpInst);
1862  return;
1863  }
1864  case ARM::BR_JTm_i12: {
1865  // ldr pc, target
1866  MCInst TmpInst;
1867  TmpInst.setOpcode(ARM::LDRi12);
1868  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1869  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1870  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1871  // Add predicate operands.
1873  TmpInst.addOperand(MCOperand::createReg(0));
1874  EmitToStreamer(*OutStreamer, TmpInst);
1875  return;
1876  }
1877  case ARM::BR_JTm_rs: {
1878  // ldr pc, target
1879  MCInst TmpInst;
1880  TmpInst.setOpcode(ARM::LDRrs);
1881  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1882  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1883  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1884  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1885  // Add predicate operands.
1887  TmpInst.addOperand(MCOperand::createReg(0));
1888  EmitToStreamer(*OutStreamer, TmpInst);
1889  return;
1890  }
1891  case ARM::BR_JTadd: {
1892  // add pc, target, idx
1894  .addReg(ARM::PC)
1895  .addReg(MI->getOperand(0).getReg())
1896  .addReg(MI->getOperand(1).getReg())
1897  // Add predicate operands.
1898  .addImm(ARMCC::AL)
1899  .addReg(0)
1900  // Add 's' bit operand (always reg0 for this)
1901  .addReg(0));
1902  return;
1903  }
1904  case ARM::SPACE:
1905  OutStreamer->emitZeros(MI->getOperand(1).getImm());
1906  return;
1907  case ARM::TRAP: {
1908  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1909  // FIXME: Remove this special case when they do.
1910  if (!Subtarget->isTargetMachO()) {
1911  uint32_t Val = 0xe7ffdefeUL;
1912  OutStreamer->AddComment("trap");
1913  ATS.emitInst(Val);
1914  return;
1915  }
1916  break;
1917  }
1918  case ARM::TRAPNaCl: {
1919  uint32_t Val = 0xe7fedef0UL;
1920  OutStreamer->AddComment("trap");
1921  ATS.emitInst(Val);
1922  return;
1923  }
1924  case ARM::tTRAP: {
1925  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1926  // FIXME: Remove this special case when they do.
1927  if (!Subtarget->isTargetMachO()) {
1928  uint16_t Val = 0xdefe;
1929  OutStreamer->AddComment("trap");
1930  ATS.emitInst(Val, 'n');
1931  return;
1932  }
1933  break;
1934  }
1935  case ARM::t2Int_eh_sjlj_setjmp:
1936  case ARM::t2Int_eh_sjlj_setjmp_nofp:
1937  case ARM::tInt_eh_sjlj_setjmp: {
1938  // Two incoming args: GPR:$src, GPR:$val
1939  // mov $val, pc
1940  // adds $val, #7
1941  // str $val, [$src, #4]
1942  // movs r0, #0
1943  // b LSJLJEH
1944  // movs r0, #1
1945  // LSJLJEH:
1946  Register SrcReg = MI->getOperand(0).getReg();
1947  Register ValReg = MI->getOperand(1).getReg();
1948  MCSymbol *Label = OutContext.createTempSymbol("SJLJEH");
1949  OutStreamer->AddComment("eh_setjmp begin");
1951  .addReg(ValReg)
1952  .addReg(ARM::PC)
1953  // Predicate.
1954  .addImm(ARMCC::AL)
1955  .addReg(0));
1956 
1958  .addReg(ValReg)
1959  // 's' bit operand
1960  .addReg(ARM::CPSR)
1961  .addReg(ValReg)
1962  .addImm(7)
1963  // Predicate.
1964  .addImm(ARMCC::AL)
1965  .addReg(0));
1966 
1968  .addReg(ValReg)
1969  .addReg(SrcReg)
1970  // The offset immediate is #4. The operand value is scaled by 4 for the
1971  // tSTR instruction.
1972  .addImm(1)
1973  // Predicate.
1974  .addImm(ARMCC::AL)
1975  .addReg(0));
1976 
1978  .addReg(ARM::R0)
1979  .addReg(ARM::CPSR)
1980  .addImm(0)
1981  // Predicate.
1982  .addImm(ARMCC::AL)
1983  .addReg(0));
1984 
1985  const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1987  .addExpr(SymbolExpr)
1988  .addImm(ARMCC::AL)
1989  .addReg(0));
1990 
1991  OutStreamer->AddComment("eh_setjmp end");
1993  .addReg(ARM::R0)
1994  .addReg(ARM::CPSR)
1995  .addImm(1)
1996  // Predicate.
1997  .addImm(ARMCC::AL)
1998  .addReg(0));
1999 
2000  OutStreamer->emitLabel(Label);
2001  return;
2002  }
2003 
2004  case ARM::Int_eh_sjlj_setjmp_nofp:
2005  case ARM::Int_eh_sjlj_setjmp: {
2006  // Two incoming args: GPR:$src, GPR:$val
2007  // add $val, pc, #8
2008  // str $val, [$src, #+4]
2009  // mov r0, #0
2010  // add pc, pc, #0
2011  // mov r0, #1
2012  Register SrcReg = MI->getOperand(0).getReg();
2013  Register ValReg = MI->getOperand(1).getReg();
2014 
2015  OutStreamer->AddComment("eh_setjmp begin");
2017  .addReg(ValReg)
2018  .addReg(ARM::PC)
2019  .addImm(8)
2020  // Predicate.
2021  .addImm(ARMCC::AL)
2022  .addReg(0)
2023  // 's' bit operand (always reg0 for this).
2024  .addReg(0));
2025 
2027  .addReg(ValReg)
2028  .addReg(SrcReg)
2029  .addImm(4)
2030  // Predicate.
2031  .addImm(ARMCC::AL)
2032  .addReg(0));
2033 
2035  .addReg(ARM::R0)
2036  .addImm(0)
2037  // Predicate.
2038  .addImm(ARMCC::AL)
2039  .addReg(0)
2040  // 's' bit operand (always reg0 for this).
2041  .addReg(0));
2042 
2044  .addReg(ARM::PC)
2045  .addReg(ARM::PC)
2046  .addImm(0)
2047  // Predicate.
2048  .addImm(ARMCC::AL)
2049  .addReg(0)
2050  // 's' bit operand (always reg0 for this).
2051  .addReg(0));
2052 
2053  OutStreamer->AddComment("eh_setjmp end");
2055  .addReg(ARM::R0)
2056  .addImm(1)
2057  // Predicate.
2058  .addImm(ARMCC::AL)
2059  .addReg(0)
2060  // 's' bit operand (always reg0 for this).
2061  .addReg(0));
2062  return;
2063  }
2064  case ARM::Int_eh_sjlj_longjmp: {
2065  // ldr sp, [$src, #8]
2066  // ldr $scratch, [$src, #4]
2067  // ldr r7, [$src]
2068  // bx $scratch
2069  Register SrcReg = MI->getOperand(0).getReg();
2070  Register ScratchReg = MI->getOperand(1).getReg();
2072  .addReg(ARM::SP)
2073  .addReg(SrcReg)
2074  .addImm(8)
2075  // Predicate.
2076  .addImm(ARMCC::AL)
2077  .addReg(0));
2078 
2080  .addReg(ScratchReg)
2081  .addReg(SrcReg)
2082  .addImm(4)
2083  // Predicate.
2084  .addImm(ARMCC::AL)
2085  .addReg(0));
2086 
2087  const MachineFunction &MF = *MI->getParent()->getParent();
2088  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
2089 
2090  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2091  // These platforms always use the same frame register
2093  .addReg(STI.getFramePointerReg())
2094  .addReg(SrcReg)
2095  .addImm(0)
2096  // Predicate.
2097  .addImm(ARMCC::AL)
2098  .addReg(0));
2099  } else {
2100  // If the calling code might use either R7 or R11 as
2101  // frame pointer register, restore it into both.
2103  .addReg(ARM::R7)
2104  .addReg(SrcReg)
2105  .addImm(0)
2106  // Predicate.
2107  .addImm(ARMCC::AL)
2108  .addReg(0));
2110  .addReg(ARM::R11)
2111  .addReg(SrcReg)
2112  .addImm(0)
2113  // Predicate.
2114  .addImm(ARMCC::AL)
2115  .addReg(0));
2116  }
2117 
2118  assert(Subtarget->hasV4TOps());
2120  .addReg(ScratchReg)
2121  // Predicate.
2122  .addImm(ARMCC::AL)
2123  .addReg(0));
2124  return;
2125  }
2126  case ARM::tInt_eh_sjlj_longjmp: {
2127  // ldr $scratch, [$src, #8]
2128  // mov sp, $scratch
2129  // ldr $scratch, [$src, #4]
2130  // ldr r7, [$src]
2131  // bx $scratch
2132  Register SrcReg = MI->getOperand(0).getReg();
2133  Register ScratchReg = MI->getOperand(1).getReg();
2134 
2135  const MachineFunction &MF = *MI->getParent()->getParent();
2136  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
2137 
2139  .addReg(ScratchReg)
2140  .addReg(SrcReg)
2141  // The offset immediate is #8. The operand value is scaled by 4 for the
2142  // tLDR instruction.
2143  .addImm(2)
2144  // Predicate.
2145  .addImm(ARMCC::AL)
2146  .addReg(0));
2147 
2149  .addReg(ARM::SP)
2150  .addReg(ScratchReg)
2151  // Predicate.
2152  .addImm(ARMCC::AL)
2153  .addReg(0));
2154 
2156  .addReg(ScratchReg)
2157  .addReg(SrcReg)
2158  .addImm(1)
2159  // Predicate.
2160  .addImm(ARMCC::AL)
2161  .addReg(0));
2162 
2163  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2164  // These platforms always use the same frame register
2166  .addReg(STI.getFramePointerReg())
2167  .addReg(SrcReg)
2168  .addImm(0)
2169  // Predicate.
2170  .addImm(ARMCC::AL)
2171  .addReg(0));
2172  } else {
2173  // If the calling code might use either R7 or R11 as
2174  // frame pointer register, restore it into both.
2176  .addReg(ARM::R7)
2177  .addReg(SrcReg)
2178  .addImm(0)
2179  // Predicate.
2180  .addImm(ARMCC::AL)
2181  .addReg(0));
2183  .addReg(ARM::R11)
2184  .addReg(SrcReg)
2185  .addImm(0)
2186  // Predicate.
2187  .addImm(ARMCC::AL)
2188  .addReg(0));
2189  }
2190 
2192  .addReg(ScratchReg)
2193  // Predicate.
2194  .addImm(ARMCC::AL)
2195  .addReg(0));
2196  return;
2197  }
2198  case ARM::tInt_WIN_eh_sjlj_longjmp: {
2199  // ldr.w r11, [$src, #0]
2200  // ldr.w sp, [$src, #8]
2201  // ldr.w pc, [$src, #4]
2202 
2203  Register SrcReg = MI->getOperand(0).getReg();
2204 
2205  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2206  .addReg(ARM::R11)
2207  .addReg(SrcReg)
2208  .addImm(0)
2209  // Predicate
2210  .addImm(ARMCC::AL)
2211  .addReg(0));
2212  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2213  .addReg(ARM::SP)
2214  .addReg(SrcReg)
2215  .addImm(8)
2216  // Predicate
2217  .addImm(ARMCC::AL)
2218  .addReg(0));
2219  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2220  .addReg(ARM::PC)
2221  .addReg(SrcReg)
2222  .addImm(4)
2223  // Predicate
2224  .addImm(ARMCC::AL)
2225  .addReg(0));
2226  return;
2227  }
2228  case ARM::PATCHABLE_FUNCTION_ENTER:
2230  return;
2231  case ARM::PATCHABLE_FUNCTION_EXIT:
2233  return;
2234  case ARM::PATCHABLE_TAIL_CALL:
2236  return;
2237  case ARM::SpeculationBarrierISBDSBEndBB: {
2238  // Print DSB SYS + ISB
2239  MCInst TmpInstDSB;
2240  TmpInstDSB.setOpcode(ARM::DSB);
2241  TmpInstDSB.addOperand(MCOperand::createImm(0xf));
2242  EmitToStreamer(*OutStreamer, TmpInstDSB);
2243  MCInst TmpInstISB;
2244  TmpInstISB.setOpcode(ARM::ISB);
2245  TmpInstISB.addOperand(MCOperand::createImm(0xf));
2246  EmitToStreamer(*OutStreamer, TmpInstISB);
2247  return;
2248  }
2249  case ARM::t2SpeculationBarrierISBDSBEndBB: {
2250  // Print DSB SYS + ISB
2251  MCInst TmpInstDSB;
2252  TmpInstDSB.setOpcode(ARM::t2DSB);
2253  TmpInstDSB.addOperand(MCOperand::createImm(0xf));
2255  TmpInstDSB.addOperand(MCOperand::createReg(0));
2256  EmitToStreamer(*OutStreamer, TmpInstDSB);
2257  MCInst TmpInstISB;
2258  TmpInstISB.setOpcode(ARM::t2ISB);
2259  TmpInstISB.addOperand(MCOperand::createImm(0xf));
2261  TmpInstISB.addOperand(MCOperand::createReg(0));
2262  EmitToStreamer(*OutStreamer, TmpInstISB);
2263  return;
2264  }
2265  case ARM::SpeculationBarrierSBEndBB: {
2266  // Print SB
2267  MCInst TmpInstSB;
2268  TmpInstSB.setOpcode(ARM::SB);
2269  EmitToStreamer(*OutStreamer, TmpInstSB);
2270  return;
2271  }
2272  case ARM::t2SpeculationBarrierSBEndBB: {
2273  // Print SB
2274  MCInst TmpInstSB;
2275  TmpInstSB.setOpcode(ARM::t2SB);
2276  EmitToStreamer(*OutStreamer, TmpInstSB);
2277  return;
2278  }
2279  }
2280 
2281  MCInst TmpInst;
2282  LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2283 
2284  EmitToStreamer(*OutStreamer, TmpInst);
2285 }
2286 
2287 //===----------------------------------------------------------------------===//
2288 // Target Registry Stuff
2289 //===----------------------------------------------------------------------===//
2290 
2291 // Force static initialization.
2297 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::ARMCP::ARMCPModifier
ARMCPModifier
Definition: ARMConstantPoolValue.h:46
checkDenormalAttributeConsistency
static bool checkDenormalAttributeConsistency(const Module &M, StringRef Attr, DenormalMode Value)
Definition: ARMAsmPrinter.cpp:599
llvm::ARMConstantPoolValue::getPCAdjustment
unsigned char getPCAdjustment() const
Definition: ARMConstantPoolValue.h:105
llvm::TargetOptions::HonorSignDependentRoundingFPMathOption
unsigned HonorSignDependentRoundingFPMathOption
HonorSignDependentRoundingFPMath - This returns true when the -enable-sign-dependent-rounding-fp-math...
Definition: TargetOptions.h:205
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:188
llvm::ARMBuildAttrs::AddressRWPCRel
@ AddressRWPCRel
Definition: ARMBuildAttributes.h:164
llvm::AsmPrinter::isPositionIndependent
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:214
llvm::ARMBuildAttrs::BTI_extension
@ BTI_extension
Definition: ARMBuildAttributes.h:74
MachineModuleInfoImpls.h
llvm::ARMFunctionInfo
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
Definition: ARMMachineFunctionInfo.h:27
llvm::MCBinaryExpr::createDiv
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:535
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
llvm::ARMSubtarget::hasV5TOps
bool hasV5TOps() const
Definition: ARMSubtarget.h:627
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::ARMBuildAttrs::PACRET_use
@ PACRET_use
Definition: ARMBuildAttributes.h:79
llvm::ARMBuildAttrs::ABI_PCS_R9_use
@ ABI_PCS_R9_use
Definition: ARMBuildAttributes.h:47
LLVMInitializeARMAsmPrinter
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMAsmPrinter()
Definition: ARMAsmPrinter.cpp:2292
llvm::ARMII::MO_HI16
@ MO_HI16
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address.
Definition: ARMBaseInfo.h:254
llvm::AsmPrinter::printOffset
void printOffset(int64_t Offset, raw_ostream &OS) const
This is just convenient handler for printing offsets.
Definition: AsmPrinter.cpp:3134
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::ARMConstantPoolValue
ARMConstantPoolValue - ARM specific constantpool value.
Definition: ARMConstantPoolValue.h:61
ARMTargetInfo.h
llvm::ARM_MC::ParseARMTriple
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Definition: ARMMCTargetDesc.cpp:153
llvm::ARMAsmPrinter::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This uses the emitInstruction() method to print assembly for each instruction.
Definition: ARMAsmPrinter.cpp:116
llvm::ARM::PredBlockMask::TT
@ TT
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::ARMCP::TPOFF
@ TPOFF
Global Offset Table, Thread Pointer Offset.
Definition: ARMConstantPoolValue.h:51
llvm::MCSymbolRefExpr::VK_ARM_GOT_PREL
@ VK_ARM_GOT_PREL
Definition: MCExpr.h:231
llvm::getTheARMBETarget
Target & getTheARMBETarget()
Definition: ARMTargetInfo.cpp:17
llvm::COFF::IMAGE_SYM_CLASS_STATIC
@ IMAGE_SYM_CLASS_STATIC
Static.
Definition: COFF.h:210
llvm::cl::Prefix
@ Prefix
Definition: CommandLine.h:164
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::ARMBuildAttrs::ABI_align_preserved
@ ABI_align_preserved
Definition: ARMBuildAttributes.h:58
llvm::ARMBuildAttrs::ABI_enum_size
@ ABI_enum_size
Definition: ARMBuildAttributes.h:59
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:563
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::Function
Definition: Function.h:62
ARMInstPrinter.h
llvm::DenseMapBase::lookup
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:197
llvm::ARMTargetStreamer
Definition: MCStreamer.h:133
llvm::MachineConstantPoolEntry::MachineCPVal
MachineConstantPoolValue * MachineCPVal
Definition: MachineConstantPool.h:72
llvm::AsmPrinter::MAI
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:88
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::convertAddSubFlagsOpcode
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
Definition: ARMBaseInstrInfo.cpp:2468
llvm::MCSymbolRefExpr::VK_ARM_TARGET1
@ VK_ARM_TARGET1
Definition: MCExpr.h:232
llvm::AsmPrinter::emitGlobalConstant
void emitGlobalConstant(const DataLayout &DL, const Constant *CV)
Print a general LLVM constant to the .s file.
Definition: AsmPrinter.cpp:3118
llvm::SmallVector< unsigned, 4 >
llvm::ARMFunctionInfo::EHPrologueOffsetInRegs
DenseMap< unsigned, unsigned > EHPrologueOffsetInRegs
Definition: ARMMachineFunctionInfo.h:278
llvm::ARMII::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: ARMBaseInfo.h:263
llvm::MCObjectFileInfo::getThreadLocalPointerSection
MCSection * getThreadLocalPointerSection() const
Definition: MCObjectFileInfo.h:405
llvm::MCSymbolRefExpr::VK_ARM_SBREL
@ VK_ARM_SBREL
Definition: MCExpr.h:235
llvm::COFF::IMAGE_SYM_CLASS_EXTERNAL
@ IMAGE_SYM_CLASS_EXTERNAL
External symbol.
Definition: COFF.h:209
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::GlobalVariable
Definition: GlobalVariable.h:39
ARMMachineFunctionInfo.h
llvm::ARMFunctionInfo::getOriginalCPIdx
unsigned getOriginalCPIdx(unsigned CloneIdx) const
Definition: ARMMachineFunctionInfo.h:244
llvm::AsmPrinter::getNameWithPrefix
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:489
MCInstBuilder.h
llvm::COFF::SCT_COMPLEX_TYPE_SHIFT
@ SCT_COMPLEX_TYPE_SHIFT
Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT))
Definition: COFF.h:265
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCAssembler.h
llvm::ARMAsmPrinter::printOperand
void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O)
Definition: ARMAsmPrinter.cpp:209
COFF.h
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::MachineModuleInfoImpl::SymbolListTy
std::vector< std::pair< MCSymbol *, StubValueTy > > SymbolListTy
Definition: MachineModuleInfo.h:62
llvm::MCStreamer::emitValue
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:177
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::ARMInstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=ARM::NoRegAltName)
llvm::MachineConstantPoolValue
Abstract base class for all machine specific constantpool value subclasses.
Definition: MachineConstantPool.h:35
llvm::ARMConstantPoolValue::isLSDA
bool isLSDA() const
Definition: ARMConstantPoolValue.h:110
llvm::ARMII::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:275
MachineJumpTableInfo.h
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:350
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::AsmPrinter::emitAlignment
void emitAlignment(Align Alignment, const GlobalObject *GV=nullptr, unsigned MaxBytesToEmit=0) const
Emit an alignment directive to the specified power of two boundary.
Definition: AsmPrinter.cpp:2485
Module.h
llvm::ARMBuildAttrs::FP16FormatIEEE
@ FP16FormatIEEE
Definition: ARMBuildAttributes.h:225
llvm::ARMBuildAttrs::AllowBTIInNOPSpace
@ AllowBTIInNOPSpace
Definition: ARMBuildAttributes.h:253
llvm::ARMBuildAttrs::AddressDirect
@ AddressDirect
Definition: ARMBuildAttributes.h:173
llvm::ARMAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
Definition: ARMMCInstLower.cpp:216
llvm::ExceptionHandling::ARM
@ ARM
ARM EHABI.
llvm::ARMCP::no_modifier
@ no_modifier
Definition: ARMConstantPoolValue.h:47
llvm::FloatABI::Hard
@ Hard
Definition: TargetOptions.h:31
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
ARMMCExpr.h
llvm::ARMBuildAttrs::AddressGOT
@ AddressGOT
Definition: ARMBuildAttributes.h:174
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
llvm::MachineModuleInfoMachO::getGVStubEntry
StubValueTy & getGVStubEntry(MCSymbol *Sym)
Definition: MachineModuleInfoImpls.h:44
llvm::ARMBuildAttrs::BTI_use
@ BTI_use
Definition: ARMBuildAttributes.h:78
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
TargetParser.h
llvm::ARMConstantPoolValue::isGlobalValue
bool isGlobalValue() const
Definition: ARMConstantPoolValue.h:107
llvm::InlineAsm::MIOp_FirstOperand
@ MIOp_FirstOperand
Definition: InlineAsm.h:225
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:600
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1564
llvm::ARMCP::SECREL
@ SECREL
Thread Pointer Offset.
Definition: ARMConstantPoolValue.h:52
llvm::TargetLoweringObjectFileMachO
Definition: TargetLoweringObjectFileImpl.h:114
llvm::ARMTargetStreamer::emitPad
virtual void emitPad(int64_t Offset)
Definition: ARMTargetStreamer.cpp:99
llvm::ARMMCExpr::createUpper16
static const ARMMCExpr * createUpper16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:38
llvm::ARMBuildAttrs::PACRETUsed
@ PACRETUsed
Definition: ARMBuildAttributes.h:262
MCELFStreamer.h
llvm::AsmPrinter::emitGlobalVariable
virtual void emitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
Definition: AsmPrinter.cpp:516
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:52
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AsmPrinter::EmitToStreamer
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:242
llvm::MCDR_DataRegionJT16
@ MCDR_DataRegionJT16
.data_region jt16
Definition: MCDirectives.h:61
llvm::COFF::SymbolStorageClass
SymbolStorageClass
Storage class tells where and what the symbol represents.
Definition: COFF.h:203
getBFLabel
static MCSymbol * getBFLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
Definition: ARMAsmPrinter.cpp:809
llvm::ARMBuildAttrs::conformance
@ conformance
Definition: ARMBuildAttributes.h:76
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::MachineConstantPoolValue::getType
Type * getType() const
Definition: MachineConstantPool.h:44
llvm::parseDenormalFPAttribute
DenormalMode parseDenormalFPAttribute(StringRef Str)
Returns the denormal mode to use for inputs and outputs.
Definition: FloatingPointMode.h:174
llvm::ARMFunctionInfo::EHPrologueRemappedRegs
DenseMap< unsigned, unsigned > EHPrologueRemappedRegs
Definition: ARMMachineFunctionInfo.h:277
llvm::ARMConstantPoolValue::isExtSymbol
bool isExtSymbol() const
Definition: ARMConstantPoolValue.h:108
llvm::ARMFunctionInfo::isCmseNSEntryFunction
bool isCmseNSEntryFunction() const
Definition: ARMMachineFunctionInfo.h:165
llvm::getTheARMLETarget
Target & getTheARMLETarget()
Definition: ARMTargetInfo.cpp:13
MCObjectStreamer.h
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:60
llvm::ARMBuildAttrs::ABI_FP_exceptions
@ ABI_FP_exceptions
Definition: ARMBuildAttributes.h:54
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:199
llvm::ARMSubtarget::isTargetMuslAEABI
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:801
ARMConstantPoolValue.h
llvm::ARMII::MO_NO_FLAG
@ MO_NO_FLAG
Definition: ARMBaseInfo.h:246
llvm::MachineModuleInfoMachO::GetThreadLocalGVStubList
SymbolListTy GetThreadLocalGVStubList()
Definition: MachineModuleInfoImpls.h:56
llvm::ARMAsmPrinter::emitMachineConstantPoolValue
void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file.
Definition: ARMAsmPrinter.cpp:902
llvm::MCDR_DataRegion
@ MCDR_DataRegion
.data_region
Definition: MCDirectives.h:59
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:835
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
llvm::ARMAsmPrinter::emitInstruction
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
Definition: ARMAsmPrinter.cpp:1341
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:191
llvm::LowerARMMachineInstrToMCInst
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP)
Definition: ARMMCInstLower.cpp:123
llvm::ARMTargetStreamer::emitRegSave
virtual void emitRegSave(const SmallVectorImpl< unsigned > &RegList, bool isVector)
Definition: ARMTargetStreamer.cpp:100
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:380
llvm::TargetOptions::NoInfsFPMath
unsigned NoInfsFPMath
NoInfsFPMath - This flag is enabled when the -enable-no-infs-fp-math flag is specified on the command...
Definition: TargetOptions.h:167
TargetMachine.h
llvm::AsmPrinter::emitLinkage
virtual void emitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const
This emits linkage information about GVSym based on GV, if this is supported by the target.
Definition: AsmPrinter.cpp:449
Constants.h
llvm::ARMTargetStreamer::emitInst
virtual void emitInst(uint32_t Inst, char Suffix='\0')
Definition: ARMTargetStreamer.cpp:53
SmallString.h
llvm::getTheThumbLETarget
Target & getTheThumbLETarget()
Definition: ARMTargetInfo.cpp:21
llvm::ARMBuildAttrs::PAC_extension
@ PAC_extension
Definition: ARMBuildAttributes.h:73
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:62
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:739
llvm::AsmPrinter::OutStreamer
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:97
MCContext.h
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MCStreamer::emitLabel
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:415
llvm::ARMBuildAttrs::BTIUsed
@ BTIUsed
Definition: ARMBuildAttributes.h:258
llvm::AsmPrinter::SetupMachineFunction
virtual void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
Definition: AsmPrinter.cpp:1998
MCSymbol.h
llvm::MCAF_Code16
@ MCAF_Code16
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:53
MCInst.h
false
Definition: StackSlotColoring.cpp:142
ARMAsmPrinter.h
FramePtr
static const unsigned FramePtr
Definition: XCoreFrameLowering.cpp:34
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::ARMBaseTargetMachine::isLittleEndian
bool isLittleEndian() const
Definition: ARMTargetMachine.h:53
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:82
llvm::AsmPrinter::CurrentFnSym
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:119
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::ARMSubtarget::isTargetAEABI
bool isTargetAEABI() const
Definition: ARMSubtarget.h:791
llvm::MCOI::BranchTarget
@ BranchTarget
Definition: MCInstrDesc.h:52
llvm::ARMAsmPrinter::emitFunctionBodyEnd
void emitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
Definition: ARMAsmPrinter.cpp:60
llvm::ARMBuildAttrs::ABI_FP_rounding
@ ABI_FP_rounding
Definition: ARMBuildAttributes.h:52
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:91
llvm::ARMConstantPoolValue::getModifier
ARMCP::ARMCPModifier getModifier() const
Definition: ARMConstantPoolValue.h:98
llvm::GlobalValue::hasInternalLinkage
bool hasInternalLinkage() const
Definition: GlobalValue.h:449
llvm::MCSymbol::getName
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:198
isThumb
static bool isThumb(const MCSubtargetInfo &STI)
Definition: ARMAsmPrinter.cpp:470
llvm::ARMFunctionInfo::isThumbFunction
bool isThumbFunction() const
Definition: ARMMachineFunctionInfo.h:161
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::ARMBuildAttrs::AddressRWSBRel
@ AddressRWSBRel
Definition: ARMBuildAttributes.h:165
llvm::ARMBuildAttrs::R9IsSB
@ R9IsSB
Definition: ARMBuildAttributes.h:159
llvm::MCSymbol::print
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:59
llvm::ARMBuildAttrs::IEEEDenormals
@ IEEEDenormals
Definition: ARMBuildAttributes.h:193
llvm::TargetOptions::FloatABIType
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line.
Definition: TargetOptions.h:362
Type.h
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
llvm::ARMAsmPrinter::emitXXStructor
void emitXXStructor(const DataLayout &DL, const Constant *CV) override
Targets can override this to change how global constants that are part of a C++ static/global constru...
Definition: ARMAsmPrinter.cpp:89
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:125
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::MCDR_DataRegionJT32
@ MCDR_DataRegionJT32
.data_region jt32
Definition: MCDirectives.h:62
llvm::MachineModuleInfoCOFF
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
Definition: MachineModuleInfoImpls.h:85
llvm::ARMTargetStreamer::emitSetFP
virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset=0)
Definition: ARMTargetStreamer.cpp:96
llvm::TargetOptions::NoTrappingFPMath
unsigned NoTrappingFPMath
NoTrappingFPMath - This flag is enabled when the -enable-no-trapping-fp-math is specified on the comm...
Definition: TargetOptions.h:178
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::PointerIntPair::getPointer
PointerTy getPointer() const
Definition: PointerIntPair.h:59
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::DenormalMode::getPositiveZero
static constexpr DenormalMode getPositiveZero()
Definition: FloatingPointMode.h:110
llvm::ARMBuildAttrs::ABI_FP_denormal
@ ABI_FP_denormal
Definition: ARMBuildAttributes.h:53
llvm::ARMBuildAttrs::AllowIEEE754
@ AllowIEEE754
Definition: ARMBuildAttributes.h:199
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:206
llvm::ARMBuildAttrs::ABI_VFP_args
@ ABI_VFP_args
Definition: ARMBuildAttributes.h:61
llvm::ARMAsmPrinter::PrintAsmMemoryOperand
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
Definition: ARMAsmPrinter.cpp:446
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineJumpTableInfo::getJumpTables
const std::vector< MachineJumpTableEntry > & getJumpTables() const
Definition: MachineJumpTableInfo.h:99
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:739
llvm::ARMSubtarget::isThumb1Only
bool isThumb1Only() const
Definition: ARMSubtarget.h:831
llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:221
llvm::MCAF_SubsectionsViaSymbols
@ MCAF_SubsectionsViaSymbols
.subsections_via_symbols (MachO)
Definition: MCDirectives.h:52
llvm::ARMCP::TLSGD
@ TLSGD
None.
Definition: ARMConstantPoolValue.h:48
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
uint64_t
llvm::ARMCP::GOT_PREL
@ GOT_PREL
Thread Local Storage (General Dynamic Mode)
Definition: ARMConstantPoolValue.h:49
llvm::ARMBuildAttrs::Not_Allowed
@ Not_Allowed
Definition: ARMBuildAttributes.h:124
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:136
ARMTargetObjectFile.h
llvm::ARMBuildAttrs::R9IsGPR
@ R9IsGPR
Definition: ARMBuildAttributes.h:158
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1092
llvm::AsmPrinter::GetBlockAddressSymbol
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
Definition: AsmPrinter.cpp:3155
llvm::TargetRegisterInfo::getFrameRegister
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
llvm::ARMAsmPrinter::emitGlobalVariable
void emitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
Definition: ARMAsmPrinter.cpp:106
llvm::MachineConstantPool
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
Definition: MachineConstantPool.h:117
llvm::MCObjectFileInfo::getNonLazySymbolPointerSection
MCSection * getNonLazySymbolPointerSection() const
Definition: MCObjectFileInfo.h:402
llvm::ARMII::MO_NONLAZY
@ MO_NONLAZY
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which,...
Definition: ARMBaseInfo.h:288
llvm::ARMBuildAttrs::R9Reserved
@ R9Reserved
Definition: ARMBuildAttributes.h:161
llvm::PointerIntPair::getInt
IntType getInt() const
Definition: PointerIntPair.h:61
llvm::ARMSubtarget::getFramePointerReg
MCPhysReg getFramePointerReg() const
Definition: ARMSubtarget.h:843
llvm::DenormalMode
Represent subnormal handling kind for floating point instruction inputs and outputs.
Definition: FloatingPointMode.h:67
llvm::MCInstBuilder
Definition: MCInstBuilder.h:21
llvm::ARMSubtarget::isTargetELF
bool isTargetELF() const
Definition: ARMSubtarget.h:781
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:219
MachineFunctionPass.h
llvm::ARMSubtarget::isTargetCOFF
bool isTargetCOFF() const
Definition: ARMSubtarget.h:780
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:121
llvm::ARMSubtarget::isROPI
bool isROPI() const
Definition: ARMSubtarget.cpp:349
llvm::MachineFunction::getConstantPool
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
Definition: MachineFunction.h:673
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineConstantPoolEntry::isMachineConstantPoolEntry
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
Definition: MachineConstantPool.h:93
llvm::AsmPrinter::getSymbol
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:494
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:80
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1707
llvm::MCStreamer::emitIntValue
virtual void emitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers.
Definition: MCStreamer.cpp:133
llvm::ARMBuildAttrs::AddressROPCRel
@ AddressROPCRel
Definition: ARMBuildAttributes.h:169
llvm::ARMBuildAttrs::PreserveFPSign
@ PreserveFPSign
Definition: ARMBuildAttributes.h:194
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:610
llvm::GlobalValue::isThreadLocal
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
Definition: GlobalValue.h:244
llvm::ARMBuildAttrs::ABI_FP_number_model
@ ABI_FP_number_model
Definition: ARMBuildAttributes.h:56
llvm::AsmPrinter::getMBBExceptionSym
MCSymbol * getMBBExceptionSym(const MachineBasicBlock &MBB)
Definition: AsmPrinter.cpp:1991
llvm::AsmPrinter::MF
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:100
llvm::ARMTargetStreamer::switchVendor
virtual void switchVendor(StringRef Vendor)
Definition: ARMTargetStreamer.cpp:105
llvm::AsmPrinter::OutContext
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:92
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
llvm::ARMAsmPrinter::GetCPISymbol
MCSymbol * GetCPISymbol(unsigned CPID) const override
Return the symbol for the specified constant pool entry.
Definition: ARMAsmPrinter.cpp:252
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
ARM.h
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::MCSymbolRefExpr::VK_TPOFF
@ VK_TPOFF
Definition: MCExpr.h:212
llvm::ARMFunctionInfo::getGlobalsPromotedToConstantPool
SmallPtrSet< const GlobalVariable *, 2 > & getGlobalsPromotedToConstantPool()
Definition: ARMMachineFunctionInfo.h:267
llvm::ARMBuildAttrs::ABI_align_needed
@ ABI_align_needed
Definition: ARMBuildAttributes.h:57
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::ARMAsmPrinter::ARMAsmPrinter
ARMAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
Definition: ARMAsmPrinter.cpp:55
Mangler.h
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:525
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:848
llvm::AsmPrinter::GetExternalSymbolSymbol
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
Definition: AsmPrinter.cpp:3211
llvm::ARMBuildAttrs::PositiveZero
@ PositiveZero
Definition: ARMBuildAttributes.h:192
ARMAddressingModes.h
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:552
MCAsmInfo.h
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1656
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MCInstBuilder::addImm
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::ARMBuildAttrs::ABI_optimization_goals
@ ABI_optimization_goals
Definition: ARMBuildAttributes.h:63
A
* A
Definition: README_ALTIVEC.txt:89
uint32_t
llvm::AArch64ISD::ADR
@ ADR
Definition: AArch64ISelLowering.h:62
llvm::MachineModuleInfoCOFF::getGVStubEntry
StubValueTy & getGVStubEntry(MCSymbol *Sym)
Definition: MachineModuleInfoImpls.h:95
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:56
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetMachine::getTargetFeatureString
StringRef getTargetFeatureString() const
Definition: TargetMachine.h:131
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MCInstBuilder::addExpr
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Definition: MCInstBuilder.h:55
llvm::ARMBuildAttrs::Allowed
@ Allowed
Definition: ARMBuildAttributes.h:125
getModifierVariantKind
static MCSymbolRefExpr::VariantKind getModifierVariantKind(ARMCP::ARMCPModifier Modifier)
Definition: ARMAsmPrinter.cpp:826
llvm::ARMBuildAttrs::AllowPACInNOPSpace
@ AllowPACInNOPSpace
Definition: ARMBuildAttributes.h:248
llvm::MCSA_IndirectSymbol
@ MCSA_IndirectSymbol
.indirect_symbol (MachO)
Definition: MCDirectives.h:34
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:290
llvm::MCContext::createTempSymbol
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:303
llvm::ARMAsmPrinter::emitFunctionEntryLabel
void emitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Definition: ARMAsmPrinter.cpp:69
llvm::ARMSubtarget::hasV4TOps
bool hasV4TOps() const
Definition: ARMSubtarget.h:626
llvm::Constant::stripPointerCasts
const Constant * stripPointerCasts() const
Definition: Constant.h:213
llvm::ARMBuildAttrs::ABI_PCS_RO_data
@ ABI_PCS_RO_data
Definition: ARMBuildAttributes.h:49
llvm::ARMConstantPoolValue::getLabelId
unsigned getLabelId() const
Definition: ARMConstantPoolValue.h:104
llvm::ARMSubtarget::isTargetWindows
bool isTargetWindows() const
Definition: ARMSubtarget.h:778
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:365
llvm::AsmPrinter::MMI
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
Definition: AsmPrinter.h:103
llvm::MachineConstantPoolEntry::Val
union llvm::MachineConstantPoolEntry::@183 Val
The constant itself.
llvm::ARMAsmPrinter::emitInlineAsmEnd
void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const override
Let the target do anything it needs to do after emitting inlineasm.
Definition: ARMAsmPrinter.cpp:474
llvm::MCAF_Code32
@ MCAF_Code32
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:54
llvm::ARMAsmPrinter::PrintAsmOperand
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Definition: ARMAsmPrinter.cpp:272
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::DenormalMode::getPreserveSign
static constexpr DenormalMode getPreserveSign()
Definition: FloatingPointMode.h:105
llvm::ARMTargetStreamer::emitTargetAttributes
void emitTargetAttributes(const MCSubtargetInfo &STI)
Emit the build attributes that only depend on the hardware that we expect.
Definition: ARMTargetStreamer.cpp:164
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::MCAF_SyntaxUnified
@ MCAF_SyntaxUnified
.syntax (ARM/ELF)
Definition: MCDirectives.h:51
llvm::ARMTargetStreamer::emitTextAttribute
virtual void emitTextAttribute(unsigned Attribute, StringRef String)
Definition: ARMTargetStreamer.cpp:107
llvm::MachineConstantPoolEntry
This class is a data container for one entry in a MachineConstantPool.
Definition: MachineConstantPool.h:67
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
std
Definition: BitVector.h:850
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::ARMSubtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: ARMSubtarget.h:771
llvm::ARMII::MO_LO16
@ MO_LO16
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address.
Definition: ARMBaseInfo.h:250
llvm::ARMConstantPoolValue::isBlockAddress
bool isBlockAddress() const
Definition: ARMConstantPoolValue.h:109
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:276
llvm::InlineAsm::hasRegClassConstraint
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:359
uint16_t
llvm::ARMAsmPrinter::LowerPATCHABLE_TAIL_CALL
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
Definition: ARMMCInstLower.cpp:226
llvm::ARMConstantPoolValue::mustAddCurrentAddress
bool mustAddCurrentAddress() const
Definition: ARMConstantPoolValue.h:102
llvm::ARMBuildAttrs::ABI_PCS_RW_data
@ ABI_PCS_RW_data
Definition: ARMBuildAttributes.h:48
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:637
llvm::MachineConstantPool::getConstants
const std::vector< MachineConstantPoolEntry > & getConstants() const
Definition: MachineConstantPool.h:145
llvm::ARMTargetStreamer::emitMovSP
virtual void emitMovSP(unsigned Reg, int64_t Offset=0)
Definition: ARMTargetStreamer.cpp:98
llvm::ARMAsmPrinter::emitEndOfAsmFile
void emitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
Definition: ARMAsmPrinter.cpp:524
llvm::MCStreamer::emitSymbolAttribute
virtual bool emitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
llvm::ARMAsmPrinter::PrintSymbolOperand
void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override
Print the MachineOperand as a symbol.
Definition: ARMAsmPrinter.cpp:197
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::AsmPrinter::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:237
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:557
llvm::MachineModuleInfoMachO::GetGVStubList
SymbolListTy GetGVStubList()
Accessor methods to return the set of stubs in sorted order.
Definition: MachineModuleInfoImpls.h:55
llvm::ARMSubtarget::isTargetMachO
bool isTargetMachO() const
Definition: ARMSubtarget.h:782
checkFunctionsAttributeConsistency
static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr, StringRef Value)
Definition: ARMAsmPrinter.cpp:591
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::ARMBuildAttrs::ABI_PCS_wchar_t
@ ABI_PCS_wchar_t
Definition: ARMBuildAttributes.h:51
llvm::ARMConstantPoolValue::isPromotedGlobal
bool isPromotedGlobal() const
Definition: ARMConstantPoolValue.h:112
llvm::ARMBuildAttrs::ABI_PCS_GOT_use
@ ABI_PCS_GOT_use
Definition: ARMBuildAttributes.h:50
llvm::AsmPrinter
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:82
llvm::MCSymbolRefExpr::VK_TLSGD
@ VK_TLSGD
Definition: MCExpr.h:209
llvm::ARMTargetStreamer::emitAttribute
virtual void emitAttribute(unsigned Attribute, unsigned Value)
Definition: ARMTargetStreamer.cpp:106
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
getPICLabel
static MCSymbol * getPICLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
Definition: ARMAsmPrinter.cpp:817
llvm::ARMAsmPrinter::emitJumpTableInsts
void emitJumpTableInsts(const MachineInstr *MI)
Definition: ARMAsmPrinter.cpp:1027
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:416
ARMBuildAttributes.h
llvm::MCSA_ELF_TypeFunction
@ MCSA_ELF_TypeFunction
.type _foo, STT_FUNC # aka @function
Definition: MCDirectives.h:23
llvm::ARMCP::GOTTPOFF
@ GOTTPOFF
Global Offset Table, PC Relative.
Definition: ARMConstantPoolValue.h:50
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:762
llvm::TargetOptions::NoNaNsFPMath
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
Definition: TargetOptions.h:173
llvm::PointerIntPair
PointerIntPair - This class implements a pair of a pointer and small integer.
Definition: PointerIntPair.h:45
llvm::TargetMachine::getTargetCPU
StringRef getTargetCPU() const
Definition: TargetMachine.h:130
llvm::MCStreamer::getContext
MCContext & getContext() const
Definition: MCStreamer.h:280
llvm::AsmPrinter::TM
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:85
llvm::MCDR_DataRegionJT8
@ MCDR_DataRegionJT8
.data_region jt8
Definition: MCDirectives.h:60
llvm::ARMBuildAttrs::HardFPAAPCS
@ HardFPAAPCS
Definition: ARMBuildAttributes.h:217
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:344
llvm::AsmPrinter::getSymbolWithGlobalValueBase
MCSymbol * getSymbolWithGlobalValueBase(const GlobalValue *GV, StringRef Suffix) const
Return the MCSymbol for a private symbol with global value name as its base, with the specified suffi...
Definition: AsmPrinter.cpp:3205
llvm::AsmPrinter::getObjFileLowering
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:223
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
MCStreamer.h
llvm::ARMSubtarget::isTargetEHABICompatible
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:809
llvm::AsmPrinter::emitFunctionBody
void emitFunctionBody()
This method emits the body and trailer for a function.
Definition: AsmPrinter.cpp:1249
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:129
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:661
llvm::AsmPrinter::getDataLayout
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:227
llvm::ARMSubtarget::isGVIndirectSymbol
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
Definition: ARMSubtarget.cpp:358
llvm::MCInstBuilder::addReg
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
llvm::TargetOptions::UnsafeFPMath
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
Definition: TargetOptions.h:161
llvm::ARMMCExpr::createLower16
static const ARMMCExpr * createLower16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:42
llvm::ARMAsmPrinter::emitStartOfAsmFile
void emitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
Definition: ARMAsmPrinter.cpp:484
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1094
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MachineModuleInfoMachO::getThreadLocalGVStubEntry
StubValueTy & getThreadLocalGVStubEntry(MCSymbol *Sym)
Definition: MachineModuleInfoImpls.h:49
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
llvm::ARMTargetStreamer::finishAttributeSection
virtual void finishAttributeSection()
Definition: ARMTargetStreamer.cpp:116
llvm::AsmPrinter::emitXRayTable
void emitXRayTable()
Emit a table with all XRay instrumentation points.
Definition: AsmPrinter.cpp:3513
llvm::MachineFunction::getJumpTableInfo
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
Definition: MachineFunction.h:664
llvm::getTheThumbBETarget
Target & getTheThumbBETarget()
Definition: ARMTargetInfo.cpp:25
llvm::ARMAsmPrinter::emitJumpTableTBInst
void emitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth)
Definition: ARMAsmPrinter.cpp:1055
llvm::RegisterAsmPrinter
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...
Definition: TargetRegistry.h:1338
llvm::ARMConstantPoolValue::isMachineBasicBlock
bool isMachineBasicBlock() const
Definition: ARMConstantPoolValue.h:111
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
raw_ostream.h
llvm::ARMAsmPrinter::emitJumpTableAddrs
void emitJumpTableAddrs(const MachineInstr *MI)
Definition: ARMAsmPrinter.cpp:981
ARMTargetMachine.h
llvm::COFF::IMAGE_SYM_DTYPE_FUNCTION
@ IMAGE_SYM_DTYPE_FUNCTION
A function that returns a base type.
Definition: COFF.h:261
llvm::MCDR_DataRegionEnd
@ MCDR_DataRegionEnd
.end_data_region
Definition: MCDirectives.h:63
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::AsmPrinter::getFunctionNumber
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:219
llvm::MachineConstantPoolEntry::ConstVal
const Constant * ConstVal
Definition: MachineConstantPool.h:71
llvm::MachineModuleInfo::getModule
const Module * getModule() const
Definition: MachineModuleInfo.h:173
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Debug.h
llvm::ARMBuildAttrs::ABI_FP_16bit_format
@ ABI_FP_16bit_format
Definition: ARMBuildAttributes.h:68
llvm::MCSymbolRefExpr::VK_SECREL
@ VK_SECREL
Definition: MCExpr.h:223
emitNonLazySymbolPointer
static void emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, MachineModuleInfoImpl::StubValueTy &MCSym)
Definition: ARMAsmPrinter.cpp:501
llvm::ARMSubtarget::isTargetGNUAEABI
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:796
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::AsmPrinter::PrintAsmOperand
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Definition: AsmPrinterInlineAsm.cpp:466
llvm::MachineModuleInfo::getObjFileInfo
Ty & getObjFileInfo()
Keep track of various per-module pieces of information for backends that would like to do so.
Definition: MachineModuleInfo.h:190
llvm::ARMCP::SBREL
@ SBREL
Section Relative (Windows TLS)
Definition: ARMConstantPoolValue.h:53
llvm::MCSymbolRefExpr::VK_GOTTPOFF
@ VK_GOTTPOFF
Definition: MCExpr.h:204
llvm::ARMSubtarget::genExecuteOnly
bool genExecuteOnly() const
Definition: ARMSubtarget.h:748
llvm::MachineModuleInfoMachO
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets.
Definition: MachineModuleInfoImpls.h:28
SetVector.h
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:339
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:58
llvm::DataLayout::getTypeAllocSize
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:506
llvm::ARMAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
Definition: ARMMCInstLower.cpp:221