LLVM  15.0.0git
ARMAsmPrinter.cpp
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1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format ARM assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMAsmPrinter.h"
15 #include "ARM.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMTargetObjectFile.h"
22 #include "MCTargetDesc/ARMMCExpr.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/BinaryFormat/COFF.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
44 #include "llvm/MC/TargetRegistry.h"
46 #include "llvm/Support/Debug.h"
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "asm-printer"
54 
56  std::unique_ptr<MCStreamer> Streamer)
57  : AsmPrinter(TM, std::move(Streamer)), Subtarget(nullptr), AFI(nullptr),
58  MCP(nullptr), InConstantPool(false), OptimizationGoals(-1) {}
59 
61  // Make sure to terminate any constant pools that were at the end
62  // of the function.
63  if (!InConstantPool)
64  return;
65  InConstantPool = false;
66  OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
67 }
68 
70  if (AFI->isThumbFunction()) {
71  OutStreamer->emitAssemblerFlag(MCAF_Code16);
72  OutStreamer->emitThumbFunc(CurrentFnSym);
73  } else {
74  OutStreamer->emitAssemblerFlag(MCAF_Code32);
75  }
76 
77  // Emit symbol for CMSE non-secure entry point
78  if (AFI->isCmseNSEntryFunction()) {
79  MCSymbol *S =
82  OutStreamer->emitSymbolAttribute(S, MCSA_ELF_TypeFunction);
83  OutStreamer->emitLabel(S);
84  }
85 
86  OutStreamer->emitLabel(CurrentFnSym);
87 }
88 
91  assert(Size && "C++ constructor pointer had zero size!");
92 
93  const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
94  assert(GV && "C++ constructor pointer was not a GlobalValue!");
95 
96  const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
98  (Subtarget->isTargetELF()
101  OutContext);
102 
103  OutStreamer->emitValue(E, Size);
104 }
105 
107  if (PromotedGlobals.count(GV))
108  // The global was promoted into a constant pool. It should not be emitted.
109  return;
111 }
112 
113 /// runOnMachineFunction - This uses the emitInstruction()
114 /// method to print assembly for each instruction.
115 ///
117  AFI = MF.getInfo<ARMFunctionInfo>();
118  MCP = MF.getConstantPool();
119  Subtarget = &MF.getSubtarget<ARMSubtarget>();
120 
122  const Function &F = MF.getFunction();
123  const TargetMachine& TM = MF.getTarget();
124 
125  // Collect all globals that had their storage promoted to a constant pool.
126  // Functions are emitted before variables, so this accumulates promoted
127  // globals from all functions in PromotedGlobals.
128  for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
129  PromotedGlobals.insert(GV);
130 
131  // Calculate this function's optimization goal.
132  unsigned OptimizationGoal;
133  if (F.hasOptNone())
134  // For best debugging illusion, speed and small size sacrificed
135  OptimizationGoal = 6;
136  else if (F.hasMinSize())
137  // Aggressively for small size, speed and debug illusion sacrificed
138  OptimizationGoal = 4;
139  else if (F.hasOptSize())
140  // For small size, but speed and debugging illusion preserved
141  OptimizationGoal = 3;
142  else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
143  // Aggressively for speed, small size and debug illusion sacrificed
144  OptimizationGoal = 2;
145  else if (TM.getOptLevel() > CodeGenOpt::None)
146  // For speed, but small size and good debug illusion preserved
147  OptimizationGoal = 1;
148  else // TM.getOptLevel() == CodeGenOpt::None
149  // For good debugging, but speed and small size preserved
150  OptimizationGoal = 5;
151 
152  // Combine a new optimization goal with existing ones.
153  if (OptimizationGoals == -1) // uninitialized goals
154  OptimizationGoals = OptimizationGoal;
155  else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
156  OptimizationGoals = 0;
157 
158  if (Subtarget->isTargetCOFF()) {
159  bool Internal = F.hasInternalLinkage();
163 
164  OutStreamer->beginCOFFSymbolDef(CurrentFnSym);
165  OutStreamer->emitCOFFSymbolStorageClass(Scl);
166  OutStreamer->emitCOFFSymbolType(Type);
167  OutStreamer->endCOFFSymbolDef();
168  }
169 
170  // Emit the rest of the function body.
172 
173  // Emit the XRay table for this function.
174  emitXRayTable();
175 
176  // If we need V4T thumb mode Register Indirect Jump pads, emit them.
177  // These are created per function, rather than per TU, since it's
178  // relatively easy to exceed the thumb branch range within a TU.
179  if (! ThumbIndirectPads.empty()) {
180  OutStreamer->emitAssemblerFlag(MCAF_Code16);
181  emitAlignment(Align(2));
182  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
183  OutStreamer->emitLabel(TIP.second);
185  .addReg(TIP.first)
186  // Add predicate operands.
187  .addImm(ARMCC::AL)
188  .addReg(0));
189  }
190  ThumbIndirectPads.clear();
191  }
192 
193  // We didn't modify anything.
194  return false;
195 }
196 
198  raw_ostream &O) {
199  assert(MO.isGlobal() && "caller should check MO.isGlobal");
200  unsigned TF = MO.getTargetFlags();
201  if (TF & ARMII::MO_LO16)
202  O << ":lower16:";
203  else if (TF & ARMII::MO_HI16)
204  O << ":upper16:";
205  GetARMGVSymbol(MO.getGlobal(), TF)->print(O, MAI);
206  printOffset(MO.getOffset(), O);
207 }
208 
210  raw_ostream &O) {
211  const MachineOperand &MO = MI->getOperand(OpNum);
212 
213  switch (MO.getType()) {
214  default: llvm_unreachable("<unknown operand type>");
216  Register Reg = MO.getReg();
218  assert(!MO.getSubReg() && "Subregs should be eliminated!");
219  if(ARM::GPRPairRegClass.contains(Reg)) {
220  const MachineFunction &MF = *MI->getParent()->getParent();
222  Reg = TRI->getSubReg(Reg, ARM::gsub_0);
223  }
225  break;
226  }
228  O << '#';
229  unsigned TF = MO.getTargetFlags();
230  if (TF == ARMII::MO_LO16)
231  O << ":lower16:";
232  else if (TF == ARMII::MO_HI16)
233  O << ":upper16:";
234  O << MO.getImm();
235  break;
236  }
238  MO.getMBB()->getSymbol()->print(O, MAI);
239  return;
241  PrintSymbolOperand(MO, O);
242  break;
243  }
245  if (Subtarget->genExecuteOnly())
246  llvm_unreachable("execute-only should not generate constant pools");
247  GetCPISymbol(MO.getIndex())->print(O, MAI);
248  break;
249  }
250 }
251 
252 MCSymbol *ARMAsmPrinter::GetCPISymbol(unsigned CPID) const {
253  // The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
254  // indexes in MachineConstantPool, which isn't in sync with indexes used here.
255  const DataLayout &DL = getDataLayout();
256  return OutContext.getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
257  "CPI" + Twine(getFunctionNumber()) + "_" +
258  Twine(CPID));
259 }
260 
261 //===--------------------------------------------------------------------===//
262 
263 MCSymbol *ARMAsmPrinter::
264 GetARMJTIPICJumpTableLabel(unsigned uid) const {
265  const DataLayout &DL = getDataLayout();
267  raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
268  << getFunctionNumber() << '_' << uid;
270 }
271 
272 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
273  const char *ExtraCode, raw_ostream &O) {
274  // Does this asm operand have a single letter operand modifier?
275  if (ExtraCode && ExtraCode[0]) {
276  if (ExtraCode[1] != 0) return true; // Unknown modifier.
277 
278  switch (ExtraCode[0]) {
279  default:
280  // See if this is a generic print operand
281  return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
282  case 'P': // Print a VFP double precision register.
283  case 'q': // Print a NEON quad precision register.
284  printOperand(MI, OpNum, O);
285  return false;
286  case 'y': // Print a VFP single precision register as indexed double.
287  if (MI->getOperand(OpNum).isReg()) {
288  MCRegister Reg = MI->getOperand(OpNum).getReg().asMCReg();
290  // Find the 'd' register that has this 's' register as a sub-register,
291  // and determine the lane number.
292  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
293  if (!ARM::DPRRegClass.contains(*SR))
294  continue;
295  bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
296  O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
297  return false;
298  }
299  }
300  return true;
301  case 'B': // Bitwise inverse of integer or symbol without a preceding #.
302  if (!MI->getOperand(OpNum).isImm())
303  return true;
304  O << ~(MI->getOperand(OpNum).getImm());
305  return false;
306  case 'L': // The low 16 bits of an immediate constant.
307  if (!MI->getOperand(OpNum).isImm())
308  return true;
309  O << (MI->getOperand(OpNum).getImm() & 0xffff);
310  return false;
311  case 'M': { // A register range suitable for LDM/STM.
312  if (!MI->getOperand(OpNum).isReg())
313  return true;
314  const MachineOperand &MO = MI->getOperand(OpNum);
315  Register RegBegin = MO.getReg();
316  // This takes advantage of the 2 operand-ness of ldm/stm and that we've
317  // already got the operands in registers that are operands to the
318  // inline asm statement.
319  O << "{";
320  if (ARM::GPRPairRegClass.contains(RegBegin)) {
322  Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
323  O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
324  RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
325  }
326  O << ARMInstPrinter::getRegisterName(RegBegin);
327 
328  // FIXME: The register allocator not only may not have given us the
329  // registers in sequence, but may not be in ascending registers. This
330  // will require changes in the register allocator that'll need to be
331  // propagated down here if the operands change.
332  unsigned RegOps = OpNum + 1;
333  while (MI->getOperand(RegOps).isReg()) {
334  O << ", "
335  << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
336  RegOps++;
337  }
338 
339  O << "}";
340 
341  return false;
342  }
343  case 'R': // The most significant register of a pair.
344  case 'Q': { // The least significant register of a pair.
345  if (OpNum == 0)
346  return true;
347  const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
348  if (!FlagsOP.isImm())
349  return true;
350  unsigned Flags = FlagsOP.getImm();
351 
352  // This operand may not be the one that actually provides the register. If
353  // it's tied to a previous one then we should refer instead to that one
354  // for registers and their classes.
355  unsigned TiedIdx;
356  if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
357  for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
358  unsigned OpFlags = MI->getOperand(OpNum).getImm();
359  OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
360  }
361  Flags = MI->getOperand(OpNum).getImm();
362 
363  // Later code expects OpNum to be pointing at the register rather than
364  // the flags.
365  OpNum += 1;
366  }
367 
368  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
369  unsigned RC;
370  bool FirstHalf;
371  const ARMBaseTargetMachine &ATM =
372  static_cast<const ARMBaseTargetMachine &>(TM);
373 
374  // 'Q' should correspond to the low order register and 'R' to the high
375  // order register. Whether this corresponds to the upper or lower half
376  // depends on the endianess mode.
377  if (ExtraCode[0] == 'Q')
378  FirstHalf = ATM.isLittleEndian();
379  else
380  // ExtraCode[0] == 'R'.
381  FirstHalf = !ATM.isLittleEndian();
383  if (InlineAsm::hasRegClassConstraint(Flags, RC) &&
384  ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
385  if (NumVals != 1)
386  return true;
387  const MachineOperand &MO = MI->getOperand(OpNum);
388  if (!MO.isReg())
389  return true;
391  Register Reg =
392  TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1);
394  return false;
395  }
396  if (NumVals != 2)
397  return true;
398  unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
399  if (RegOp >= MI->getNumOperands())
400  return true;
401  const MachineOperand &MO = MI->getOperand(RegOp);
402  if (!MO.isReg())
403  return true;
404  Register Reg = MO.getReg();
406  return false;
407  }
408 
409  case 'e': // The low doubleword register of a NEON quad register.
410  case 'f': { // The high doubleword register of a NEON quad register.
411  if (!MI->getOperand(OpNum).isReg())
412  return true;
413  Register Reg = MI->getOperand(OpNum).getReg();
414  if (!ARM::QPRRegClass.contains(Reg))
415  return true;
417  Register SubReg =
418  TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1);
420  return false;
421  }
422 
423  // This modifier is not yet supported.
424  case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
425  return true;
426  case 'H': { // The highest-numbered register of a pair.
427  const MachineOperand &MO = MI->getOperand(OpNum);
428  if (!MO.isReg())
429  return true;
430  const MachineFunction &MF = *MI->getParent()->getParent();
432  Register Reg = MO.getReg();
433  if(!ARM::GPRPairRegClass.contains(Reg))
434  return false;
435  Reg = TRI->getSubReg(Reg, ARM::gsub_1);
437  return false;
438  }
439  }
440  }
441 
442  printOperand(MI, OpNum, O);
443  return false;
444 }
445 
447  unsigned OpNum, const char *ExtraCode,
448  raw_ostream &O) {
449  // Does this asm operand have a single letter operand modifier?
450  if (ExtraCode && ExtraCode[0]) {
451  if (ExtraCode[1] != 0) return true; // Unknown modifier.
452 
453  switch (ExtraCode[0]) {
454  case 'A': // A memory operand for a VLD1/VST1 instruction.
455  default: return true; // Unknown modifier.
456  case 'm': // The base register of a memory operand.
457  if (!MI->getOperand(OpNum).isReg())
458  return true;
459  O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
460  return false;
461  }
462  }
463 
464  const MachineOperand &MO = MI->getOperand(OpNum);
465  assert(MO.isReg() && "unexpected inline asm memory operand");
466  O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
467  return false;
468 }
469 
470 static bool isThumb(const MCSubtargetInfo& STI) {
471  return STI.getFeatureBits()[ARM::ModeThumb];
472 }
473 
475  const MCSubtargetInfo *EndInfo) const {
476  // If either end mode is unknown (EndInfo == NULL) or different than
477  // the start mode, then restore the start mode.
478  const bool WasThumb = isThumb(StartInfo);
479  if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
480  OutStreamer->emitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
481  }
482 }
483 
485  const Triple &TT = TM.getTargetTriple();
486  // Use unified assembler syntax.
487  OutStreamer->emitAssemblerFlag(MCAF_SyntaxUnified);
488 
489  // Emit ARM Build Attributes
490  if (TT.isOSBinFormatELF())
491  emitAttributes();
492 
493  // Use the triple's architecture and subarchitecture to determine
494  // if we're thumb for the purposes of the top level code16 assembler
495  // flag.
496  if (!M.getModuleInlineAsm().empty() && TT.isThumb())
497  OutStreamer->emitAssemblerFlag(MCAF_Code16);
498 }
499 
500 static void
503  // L_foo$stub:
504  OutStreamer.emitLabel(StubLabel);
505  // .indirect_symbol _foo
506  OutStreamer.emitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
507 
508  if (MCSym.getInt())
509  // External to current translation unit.
510  OutStreamer.emitIntValue(0, 4/*size*/);
511  else
512  // Internal to current translation unit.
513  //
514  // When we place the LSDA into the TEXT section, the type info
515  // pointers need to be indirect and pc-rel. We accomplish this by
516  // using NLPs; however, sometimes the types are local to the file.
517  // We need to fill in the value for the NLP in those cases.
518  OutStreamer.emitValue(
519  MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
520  4 /*size*/);
521 }
522 
523 
525  const Triple &TT = TM.getTargetTriple();
526  if (TT.isOSBinFormatMachO()) {
527  // All darwin targets use mach-o.
528  const TargetLoweringObjectFileMachO &TLOFMacho =
529  static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
530  MachineModuleInfoMachO &MMIMacho =
532 
533  // Output non-lazy-pointers for external and common global variables.
535 
536  if (!Stubs.empty()) {
537  // Switch with ".non_lazy_symbol_pointer" directive.
538  OutStreamer->switchSection(TLOFMacho.getNonLazySymbolPointerSection());
539  emitAlignment(Align(4));
540 
541  for (auto &Stub : Stubs)
542  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
543 
544  Stubs.clear();
545  OutStreamer->addBlankLine();
546  }
547 
548  Stubs = MMIMacho.GetThreadLocalGVStubList();
549  if (!Stubs.empty()) {
550  // Switch with ".non_lazy_symbol_pointer" directive.
551  OutStreamer->switchSection(TLOFMacho.getThreadLocalPointerSection());
552  emitAlignment(Align(4));
553 
554  for (auto &Stub : Stubs)
555  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
556 
557  Stubs.clear();
558  OutStreamer->addBlankLine();
559  }
560 
561  // Funny Darwin hack: This flag tells the linker that no global symbols
562  // contain code that falls through to other global symbols (e.g. the obvious
563  // implementation of multiple entry points). If this doesn't occur, the
564  // linker can safely perform dead code stripping. Since LLVM never
565  // generates code that does this, it is always safe to set.
566  OutStreamer->emitAssemblerFlag(MCAF_SubsectionsViaSymbols);
567  }
568 
569  // The last attribute to be emitted is ABI_optimization_goals
570  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
571  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
572 
573  if (OptimizationGoals > 0 &&
574  (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
575  Subtarget->isTargetMuslAEABI()))
577  OptimizationGoals = -1;
578 
580 }
581 
582 //===----------------------------------------------------------------------===//
583 // Helper routines for emitStartOfAsmFile() and emitEndOfAsmFile()
584 // FIXME:
585 // The following seem like one-off assembler flags, but they actually need
586 // to appear in the .ARM.attributes section in ELF.
587 // Instead of subclassing the MCELFStreamer, we do the work here.
588 
589  // Returns true if all functions have the same function attribute value.
590  // It also returns true when the module has no functions.
592  StringRef Value) {
593  return !any_of(M, [&](const Function &F) {
594  return F.getFnAttribute(Attr).getValueAsString() != Value;
595  });
596 }
597 // Returns true if all functions have the same denormal mode.
598 // It also returns true when the module has no functions.
600  StringRef Attr,
602  return !any_of(M, [&](const Function &F) {
603  StringRef AttrVal = F.getFnAttribute(Attr).getValueAsString();
604  return parseDenormalFPAttribute(AttrVal) != Value;
605  });
606 }
607 
608 void ARMAsmPrinter::emitAttributes() {
609  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
610  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
611 
613 
614  ATS.switchVendor("aeabi");
615 
616  // Compute ARM ELF Attributes based on the default subtarget that
617  // we'd have constructed. The existing ARM behavior isn't LTO clean
618  // anyhow.
619  // FIXME: For ifunc related functions we could iterate over and look
620  // for a feature string that doesn't match the default one.
621  const Triple &TT = TM.getTargetTriple();
622  StringRef CPU = TM.getTargetCPU();
624  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
625  if (!FS.empty()) {
626  if (!ArchFS.empty())
627  ArchFS = (Twine(ArchFS) + "," + FS).str();
628  else
629  ArchFS = std::string(FS);
630  }
631  const ARMBaseTargetMachine &ATM =
632  static_cast<const ARMBaseTargetMachine &>(TM);
633  const ARMSubtarget STI(TT, std::string(CPU), ArchFS, ATM,
634  ATM.isLittleEndian());
635 
636  // Emit build attributes for the available hardware.
637  ATS.emitTargetAttributes(STI);
638 
639  // RW data addressing.
640  if (isPositionIndependent()) {
643  } else if (STI.isRWPI()) {
644  // RWPI specific attributes.
647  }
648 
649  // RO data addressing.
650  if (isPositionIndependent() || STI.isROPI()) {
653  }
654 
655  // GOT use.
656  if (isPositionIndependent()) {
659  } else {
662  }
663 
664  // Set FP Denormals.
665  if (checkDenormalAttributeConsistency(*MMI->getModule(), "denormal-fp-math",
670  "denormal-fp-math",
674  else if (!TM.Options.UnsafeFPMath)
677  else {
678  if (!STI.hasVFP2Base()) {
679  // When the target doesn't have an FPU (by design or
680  // intention), the assumptions made on the software support
681  // mirror that of the equivalent hardware support *if it
682  // existed*. For v7 and better we indicate that denormals are
683  // flushed preserving sign, and for V6 we indicate that
684  // denormals are flushed to positive zero.
685  if (STI.hasV7Ops())
688  } else if (STI.hasVFP3Base()) {
689  // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
690  // the sign bit of the zero matches the sign bit of the input or
691  // result that is being flushed to zero.
694  }
695  // For VFPv2 implementations it is implementation defined as
696  // to whether denormals are flushed to positive zero or to
697  // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
698  // LLVM has chosen to flush this to positive zero (most likely for
699  // GCC compatibility), so that's the chosen value here (the
700  // absence of its emission implies zero).
701  }
702 
703  // Set FP exceptions and rounding
705  "no-trapping-math", "true") ||
709  else if (!TM.Options.UnsafeFPMath) {
711 
712  // If the user has permitted this code to choose the IEEE 754
713  // rounding at run-time, emit the rounding attribute.
716  }
717 
718  // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
719  // equivalent of GCC's -ffinite-math-only flag.
723  else
726 
727  // FIXME: add more flags to ARMBuildAttributes.h
728  // 8-bytes alignment stuff.
731 
732  // Hard float. Use both S and D registers and conform to AAPCS-VFP.
733  if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
735 
736  // FIXME: To support emitting this build attribute as GCC does, the
737  // -mfp16-format option and associated plumbing must be
738  // supported. For now the __fp16 type is exposed by default, so this
739  // attribute should be emitted with value 1.
742 
743  if (const Module *SourceModule = MMI->getModule()) {
744  // ABI_PCS_wchar_t to indicate wchar_t width
745  // FIXME: There is no way to emit value 0 (wchar_t prohibited).
746  if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
747  SourceModule->getModuleFlag("wchar_size"))) {
748  int WCharWidth = WCharWidthValue->getZExtValue();
749  assert((WCharWidth == 2 || WCharWidth == 4) &&
750  "wchar_t width must be 2 or 4 bytes");
752  }
753 
754  // ABI_enum_size to indicate enum width
755  // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
756  // (all enums contain a value needing 32 bits to encode).
757  if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
758  SourceModule->getModuleFlag("min_enum_size"))) {
759  int EnumWidth = EnumWidthValue->getZExtValue();
760  assert((EnumWidth == 1 || EnumWidth == 4) &&
761  "Minimum enum width must be 1 or 4 bytes");
762  int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
763  ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
764  }
765 
766  auto *PACValue = mdconst::extract_or_null<ConstantInt>(
767  SourceModule->getModuleFlag("sign-return-address"));
768  if (PACValue && PACValue->getZExtValue() == 1) {
769  // If "+pacbti" is used as an architecture extension,
770  // Tag_PAC_extension is emitted in
771  // ARMTargetStreamer::emitTargetAttributes().
772  if (!STI.hasPACBTI()) {
775  }
777  }
778 
779  auto *BTIValue = mdconst::extract_or_null<ConstantInt>(
780  SourceModule->getModuleFlag("branch-target-enforcement"));
781  if (BTIValue && BTIValue->getZExtValue() == 1) {
782  // If "+pacbti" is used as an architecture extension,
783  // Tag_BTI_extension is emitted in
784  // ARMTargetStreamer::emitTargetAttributes().
785  if (!STI.hasPACBTI()) {
788  }
790  }
791  }
792 
793  // We currently do not support using R9 as the TLS pointer.
794  if (STI.isRWPI())
797  else if (STI.isR9Reserved())
800  else
803 }
804 
805 //===----------------------------------------------------------------------===//
806 
807 static MCSymbol *getBFLabel(StringRef Prefix, unsigned FunctionNumber,
808  unsigned LabelId, MCContext &Ctx) {
809 
810  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
811  + "BF" + Twine(FunctionNumber) + "_" + Twine(LabelId));
812  return Label;
813 }
814 
815 static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
816  unsigned LabelId, MCContext &Ctx) {
817 
818  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
819  + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
820  return Label;
821 }
822 
825  switch (Modifier) {
826  case ARMCP::no_modifier:
828  case ARMCP::TLSGD:
830  case ARMCP::TPOFF:
832  case ARMCP::GOTTPOFF:
834  case ARMCP::SBREL:
836  case ARMCP::GOT_PREL:
838  case ARMCP::SECREL:
840  }
841  llvm_unreachable("Invalid ARMCPModifier!");
842 }
843 
844 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
845  unsigned char TargetFlags) {
846  if (Subtarget->isTargetMachO()) {
847  bool IsIndirect =
848  (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
849 
850  if (!IsIndirect)
851  return getSymbol(GV);
852 
853  // FIXME: Remove this when Darwin transition to @GOT like syntax.
854  MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
855  MachineModuleInfoMachO &MMIMachO =
858  GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
859  : MMIMachO.getGVStubEntry(MCSym);
860 
861  if (!StubSym.getPointer())
863  !GV->hasInternalLinkage());
864  return MCSym;
865  } else if (Subtarget->isTargetCOFF()) {
866  assert(Subtarget->isTargetWindows() &&
867  "Windows is the only supported COFF target");
868 
869  bool IsIndirect =
870  (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB));
871  if (!IsIndirect)
872  return getSymbol(GV);
873 
875  if (TargetFlags & ARMII::MO_DLLIMPORT)
876  Name = "__imp_";
877  else if (TargetFlags & ARMII::MO_COFFSTUB)
878  Name = ".refptr.";
879  getNameWithPrefix(Name, GV);
880 
882 
883  if (TargetFlags & ARMII::MO_COFFSTUB) {
884  MachineModuleInfoCOFF &MMICOFF =
887  MMICOFF.getGVStubEntry(MCSym);
888 
889  if (!StubSym.getPointer())
890  StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV), true);
891  }
892 
893  return MCSym;
894  } else if (Subtarget->isTargetELF()) {
895  return getSymbol(GV);
896  }
897  llvm_unreachable("unexpected target");
898 }
899 
901  MachineConstantPoolValue *MCPV) {
902  const DataLayout &DL = getDataLayout();
903  int Size = DL.getTypeAllocSize(MCPV->getType());
904 
905  ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
906 
907  if (ACPV->isPromotedGlobal()) {
908  // This constant pool entry is actually a global whose storage has been
909  // promoted into the constant pool. This global may be referenced still
910  // by debug information, and due to the way AsmPrinter is set up, the debug
911  // info is immutable by the time we decide to promote globals to constant
912  // pools. Because of this, we need to ensure we emit a symbol for the global
913  // with private linkage (the default) so debug info can refer to it.
914  //
915  // However, if this global is promoted into several functions we must ensure
916  // we don't try and emit duplicate symbols!
917  auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
918  for (const auto *GV : ACPC->promotedGlobals()) {
919  if (!EmittedPromotedGlobalLabels.count(GV)) {
920  MCSymbol *GVSym = getSymbol(GV);
921  OutStreamer->emitLabel(GVSym);
922  EmittedPromotedGlobalLabels.insert(GV);
923  }
924  }
925  return emitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
926  }
927 
928  MCSymbol *MCSym;
929  if (ACPV->isLSDA()) {
930  MCSym = getMBBExceptionSym(MF->front());
931  } else if (ACPV->isBlockAddress()) {
932  const BlockAddress *BA =
933  cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
934  MCSym = GetBlockAddressSymbol(BA);
935  } else if (ACPV->isGlobalValue()) {
936  const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
937 
938  // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
939  // flag the global as MO_NONLAZY.
940  unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
941  MCSym = GetARMGVSymbol(GV, TF);
942  } else if (ACPV->isMachineBasicBlock()) {
943  const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
944  MCSym = MBB->getSymbol();
945  } else {
946  assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
947  auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
948  MCSym = GetExternalSymbolSymbol(Sym);
949  }
950 
951  // Create an MCSymbol for the reference.
952  const MCExpr *Expr =
954  OutContext);
955 
956  if (ACPV->getPCAdjustment()) {
957  MCSymbol *PCLabel =
958  getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
959  ACPV->getLabelId(), OutContext);
960  const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
961  PCRelExpr =
962  MCBinaryExpr::createAdd(PCRelExpr,
964  OutContext),
965  OutContext);
966  if (ACPV->mustAddCurrentAddress()) {
967  // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
968  // label, so just emit a local label end reference that instead.
970  OutStreamer->emitLabel(DotSym);
971  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
972  PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
973  }
974  Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
975  }
976  OutStreamer->emitValue(Expr, Size);
977 }
978 
980  const MachineOperand &MO1 = MI->getOperand(1);
981  unsigned JTI = MO1.getIndex();
982 
983  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
984  // ARM mode tables.
985  emitAlignment(Align(4));
986 
987  // Emit a label for the jump table.
988  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
989  OutStreamer->emitLabel(JTISymbol);
990 
991  // Mark the jump table as data-in-code.
992  OutStreamer->emitDataRegion(MCDR_DataRegionJT32);
993 
994  // Emit each entry of the table.
995  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
996  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
997  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
998 
999  for (MachineBasicBlock *MBB : JTBBs) {
1000  // Construct an MCExpr for the entry. We want a value of the form:
1001  // (BasicBlockAddr - TableBeginAddr)
1002  //
1003  // For example, a table with entries jumping to basic blocks BB0 and BB1
1004  // would look like:
1005  // LJTI_0_0:
1006  // .word (LBB0 - LJTI_0_0)
1007  // .word (LBB1 - LJTI_0_0)
1009 
1010  if (isPositionIndependent() || Subtarget->isROPI())
1011  Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
1012  OutContext),
1013  OutContext);
1014  // If we're generating a table of Thumb addresses in static relocation
1015  // model, we need to add one to keep interworking correctly.
1016  else if (AFI->isThumbFunction())
1018  OutContext);
1019  OutStreamer->emitValue(Expr, 4);
1020  }
1021  // Mark the end of jump table data-in-code region.
1022  OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1023 }
1024 
1026  const MachineOperand &MO1 = MI->getOperand(1);
1027  unsigned JTI = MO1.getIndex();
1028 
1029  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1030  // ARM mode tables.
1031  emitAlignment(Align(4));
1032 
1033  // Emit a label for the jump table.
1034  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1035  OutStreamer->emitLabel(JTISymbol);
1036 
1037  // Emit each entry of the table.
1038  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1039  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1040  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1041 
1042  for (MachineBasicBlock *MBB : JTBBs) {
1043  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1044  OutContext);
1045  // If this isn't a TBB or TBH, the entries are direct branch instructions.
1047  .addExpr(MBBSymbolExpr)
1048  .addImm(ARMCC::AL)
1049  .addReg(0));
1050  }
1051 }
1052 
1054  unsigned OffsetWidth) {
1055  assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1056  const MachineOperand &MO1 = MI->getOperand(1);
1057  unsigned JTI = MO1.getIndex();
1058 
1059  if (Subtarget->isThumb1Only())
1060  emitAlignment(Align(4));
1061 
1062  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1063  OutStreamer->emitLabel(JTISymbol);
1064 
1065  // Emit each entry of the table.
1066  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1067  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1068  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1069 
1070  // Mark the jump table as data-in-code.
1071  OutStreamer->emitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1073 
1074  for (auto MBB : JTBBs) {
1075  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1076  OutContext);
1077  // Otherwise it's an offset from the dispatch instruction. Construct an
1078  // MCExpr for the entry. We want a value of the form:
1079  // (BasicBlockAddr - TBBInstAddr + 4) / 2
1080  //
1081  // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1082  // would look like:
1083  // LJTI_0_0:
1084  // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1085  // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1086  // where LCPI0_0 is a label defined just before the TBB instruction using
1087  // this table.
1088  MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1089  const MCExpr *Expr = MCBinaryExpr::createAdd(
1092  Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1094  OutContext);
1095  OutStreamer->emitValue(Expr, OffsetWidth);
1096  }
1097  // Mark the end of jump table data-in-code region. 32-bit offsets use
1098  // actual branch instructions here, so we don't mark those as a data-region
1099  // at all.
1100  OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1101 
1102  // Make sure the next instruction is 2-byte aligned.
1103  emitAlignment(Align(2));
1104 }
1105 
1106 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1107  assert(MI->getFlag(MachineInstr::FrameSetup) &&
1108  "Only instruction which are involved into frame setup code are allowed");
1109 
1110  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1111  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1112  const MachineFunction &MF = *MI->getParent()->getParent();
1113  const TargetRegisterInfo *TargetRegInfo =
1115  const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
1116 
1117  Register FramePtr = TargetRegInfo->getFrameRegister(MF);
1118  unsigned Opc = MI->getOpcode();
1119  unsigned SrcReg, DstReg;
1120 
1121  switch (Opc) {
1122  case ARM::tPUSH:
1123  // special case: tPUSH does not have src/dst regs.
1124  SrcReg = DstReg = ARM::SP;
1125  break;
1126  case ARM::tLDRpci:
1127  case ARM::t2MOVi16:
1128  case ARM::t2MOVTi16:
1129  // special cases:
1130  // 1) for Thumb1 code we sometimes materialize the constant via constpool
1131  // load.
1132  // 2) for Thumb2 execute only code we materialize the constant via
1133  // immediate constants in 2 separate instructions (MOVW/MOVT).
1134  SrcReg = ~0U;
1135  DstReg = MI->getOperand(0).getReg();
1136  break;
1137  default:
1138  SrcReg = MI->getOperand(1).getReg();
1139  DstReg = MI->getOperand(0).getReg();
1140  break;
1141  }
1142 
1143  // Try to figure out the unwinding opcode out of src / dst regs.
1144  if (MI->mayStore()) {
1145  // Register saves.
1146  assert(DstReg == ARM::SP &&
1147  "Only stack pointer as a destination reg is supported");
1148 
1149  SmallVector<unsigned, 4> RegList;
1150  // Skip src & dst reg, and pred ops.
1151  unsigned StartOp = 2 + 2;
1152  // Use all the operands.
1153  unsigned NumOffset = 0;
1154  // Amount of SP adjustment folded into a push, before the
1155  // registers are stored (pad at higher addresses).
1156  unsigned PadBefore = 0;
1157  // Amount of SP adjustment folded into a push, after the
1158  // registers are stored (pad at lower addresses).
1159  unsigned PadAfter = 0;
1160 
1161  switch (Opc) {
1162  default:
1163  MI->print(errs());
1164  llvm_unreachable("Unsupported opcode for unwinding information");
1165  case ARM::tPUSH:
1166  // Special case here: no src & dst reg, but two extra imp ops.
1167  StartOp = 2; NumOffset = 2;
1169  case ARM::STMDB_UPD:
1170  case ARM::t2STMDB_UPD:
1171  case ARM::VSTMDDB_UPD:
1172  assert(SrcReg == ARM::SP &&
1173  "Only stack pointer as a source reg is supported");
1174  for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1175  i != NumOps; ++i) {
1176  const MachineOperand &MO = MI->getOperand(i);
1177  // Actually, there should never be any impdef stuff here. Skip it
1178  // temporary to workaround PR11902.
1179  if (MO.isImplicit())
1180  continue;
1181  // Registers, pushed as a part of folding an SP update into the
1182  // push instruction are marked as undef and should not be
1183  // restored when unwinding, because the function can modify the
1184  // corresponding stack slots.
1185  if (MO.isUndef()) {
1186  assert(RegList.empty() &&
1187  "Pad registers must come before restored ones");
1188  unsigned Width =
1189  TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
1190  PadAfter += Width;
1191  continue;
1192  }
1193  // Check for registers that are remapped (for a Thumb1 prologue that
1194  // saves high registers).
1195  Register Reg = MO.getReg();
1196  if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Reg))
1197  Reg = RemappedReg;
1198  RegList.push_back(Reg);
1199  }
1200  break;
1201  case ARM::STR_PRE_IMM:
1202  case ARM::STR_PRE_REG:
1203  case ARM::t2STR_PRE:
1204  assert(MI->getOperand(2).getReg() == ARM::SP &&
1205  "Only stack pointer as a source reg is supported");
1206  if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1207  SrcReg = RemappedReg;
1208 
1209  RegList.push_back(SrcReg);
1210  break;
1211  case ARM::t2STRD_PRE:
1212  assert(MI->getOperand(3).getReg() == ARM::SP &&
1213  "Only stack pointer as a source reg is supported");
1214  SrcReg = MI->getOperand(1).getReg();
1215  if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1216  SrcReg = RemappedReg;
1217  RegList.push_back(SrcReg);
1218  SrcReg = MI->getOperand(2).getReg();
1219  if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(SrcReg))
1220  SrcReg = RemappedReg;
1221  RegList.push_back(SrcReg);
1222  PadBefore = -MI->getOperand(4).getImm() - 8;
1223  break;
1224  }
1226  if (PadBefore)
1227  ATS.emitPad(PadBefore);
1228  ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1229  // Account for the SP adjustment, folded into the push.
1230  if (PadAfter)
1231  ATS.emitPad(PadAfter);
1232  }
1233  } else {
1234  // Changes of stack / frame pointer.
1235  if (SrcReg == ARM::SP) {
1236  int64_t Offset = 0;
1237  switch (Opc) {
1238  default:
1239  MI->print(errs());
1240  llvm_unreachable("Unsupported opcode for unwinding information");
1241  case ARM::MOVr:
1242  case ARM::tMOVr:
1243  Offset = 0;
1244  break;
1245  case ARM::ADDri:
1246  case ARM::t2ADDri:
1247  case ARM::t2ADDri12:
1248  case ARM::t2ADDspImm:
1249  case ARM::t2ADDspImm12:
1250  Offset = -MI->getOperand(2).getImm();
1251  break;
1252  case ARM::SUBri:
1253  case ARM::t2SUBri:
1254  case ARM::t2SUBri12:
1255  case ARM::t2SUBspImm:
1256  case ARM::t2SUBspImm12:
1257  Offset = MI->getOperand(2).getImm();
1258  break;
1259  case ARM::tSUBspi:
1260  Offset = MI->getOperand(2).getImm()*4;
1261  break;
1262  case ARM::tADDspi:
1263  case ARM::tADDrSPi:
1264  Offset = -MI->getOperand(2).getImm()*4;
1265  break;
1266  case ARM::tADDhirr:
1267  Offset =
1268  -AFI->EHPrologueOffsetInRegs.lookup(MI->getOperand(2).getReg());
1269  break;
1270  }
1271 
1273  if (DstReg == FramePtr && FramePtr != ARM::SP)
1274  // Set-up of the frame pointer. Positive values correspond to "add"
1275  // instruction.
1276  ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1277  else if (DstReg == ARM::SP) {
1278  // Change of SP by an offset. Positive values correspond to "sub"
1279  // instruction.
1280  ATS.emitPad(Offset);
1281  } else {
1282  // Move of SP to a register. Positive values correspond to an "add"
1283  // instruction.
1284  ATS.emitMovSP(DstReg, -Offset);
1285  }
1286  }
1287  } else if (DstReg == ARM::SP) {
1288  MI->print(errs());
1289  llvm_unreachable("Unsupported opcode for unwinding information");
1290  } else {
1291  int64_t Offset = 0;
1292  switch (Opc) {
1293  case ARM::tMOVr:
1294  // If a Thumb1 function spills r8-r11, we copy the values to low
1295  // registers before pushing them. Record the copy so we can emit the
1296  // correct ".save" later.
1297  AFI->EHPrologueRemappedRegs[DstReg] = SrcReg;
1298  break;
1299  case ARM::tLDRpci: {
1300  // Grab the constpool index and check, whether it corresponds to
1301  // original or cloned constpool entry.
1302  unsigned CPI = MI->getOperand(1).getIndex();
1303  const MachineConstantPool *MCP = MF.getConstantPool();
1304  if (CPI >= MCP->getConstants().size())
1305  CPI = AFI->getOriginalCPIdx(CPI);
1306  assert(CPI != -1U && "Invalid constpool index");
1307 
1308  // Derive the actual offset.
1309  const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1310  assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1311  Offset = cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1312  AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1313  break;
1314  }
1315  case ARM::t2MOVi16:
1316  Offset = MI->getOperand(1).getImm();
1317  AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1318  break;
1319  case ARM::t2MOVTi16:
1320  Offset = MI->getOperand(2).getImm();
1321  AFI->EHPrologueOffsetInRegs[DstReg] |= (Offset << 16);
1322  break;
1323  case ARM::t2PAC:
1324  case ARM::t2PACBTI:
1325  AFI->EHPrologueRemappedRegs[ARM::R12] = ARM::RA_AUTH_CODE;
1326  break;
1327  default:
1328  MI->print(errs());
1329  llvm_unreachable("Unsupported opcode for unwinding information");
1330  }
1331  }
1332  }
1333 }
1334 
1335 // Simple pseudo-instructions have their lowering (with expansion to real
1336 // instructions) auto-generated.
1337 #include "ARMGenMCPseudoLowering.inc"
1338 
1340  const DataLayout &DL = getDataLayout();
1341  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1342  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1343 
1344  // If we just ended a constant pool, mark it as such.
1345  if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1346  OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1347  InConstantPool = false;
1348  }
1349 
1350  // Emit unwinding stuff for frame-related instructions
1351  if (Subtarget->isTargetEHABICompatible() &&
1352  MI->getFlag(MachineInstr::FrameSetup))
1353  EmitUnwindingInstruction(MI);
1354 
1355  // Do any auto-generated pseudo lowerings.
1356  if (emitPseudoExpansionLowering(*OutStreamer, MI))
1357  return;
1358 
1359  assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1360  "Pseudo flag setting opcode should be expanded early");
1361 
1362  // Check for manual lowerings.
1363  unsigned Opc = MI->getOpcode();
1364  switch (Opc) {
1365  case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1366  case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1367  case ARM::LEApcrel:
1368  case ARM::tLEApcrel:
1369  case ARM::t2LEApcrel: {
1370  // FIXME: Need to also handle globals and externals
1371  MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1372  EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1373  ARM::t2LEApcrel ? ARM::t2ADR
1374  : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1375  : ARM::ADR))
1376  .addReg(MI->getOperand(0).getReg())
1378  // Add predicate operands.
1379  .addImm(MI->getOperand(2).getImm())
1380  .addReg(MI->getOperand(3).getReg()));
1381  return;
1382  }
1383  case ARM::LEApcrelJT:
1384  case ARM::tLEApcrelJT:
1385  case ARM::t2LEApcrelJT: {
1386  MCSymbol *JTIPICSymbol =
1387  GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1388  EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1389  ARM::t2LEApcrelJT ? ARM::t2ADR
1390  : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1391  : ARM::ADR))
1392  .addReg(MI->getOperand(0).getReg())
1393  .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1394  // Add predicate operands.
1395  .addImm(MI->getOperand(2).getImm())
1396  .addReg(MI->getOperand(3).getReg()));
1397  return;
1398  }
1399  // Darwin call instructions are just normal call instructions with different
1400  // clobber semantics (they clobber R9).
1401  case ARM::BX_CALL: {
1403  .addReg(ARM::LR)
1404  .addReg(ARM::PC)
1405  // Add predicate operands.
1406  .addImm(ARMCC::AL)
1407  .addReg(0)
1408  // Add 's' bit operand (always reg0 for this)
1409  .addReg(0));
1410 
1411  assert(Subtarget->hasV4TOps());
1413  .addReg(MI->getOperand(0).getReg()));
1414  return;
1415  }
1416  case ARM::tBX_CALL: {
1417  if (Subtarget->hasV5TOps())
1418  llvm_unreachable("Expected BLX to be selected for v5t+");
1419 
1420  // On ARM v4t, when doing a call from thumb mode, we need to ensure
1421  // that the saved lr has its LSB set correctly (the arch doesn't
1422  // have blx).
1423  // So here we generate a bl to a small jump pad that does bx rN.
1424  // The jump pads are emitted after the function body.
1425 
1426  Register TReg = MI->getOperand(0).getReg();
1427  MCSymbol *TRegSym = nullptr;
1428  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
1429  if (TIP.first == TReg) {
1430  TRegSym = TIP.second;
1431  break;
1432  }
1433  }
1434 
1435  if (!TRegSym) {
1436  TRegSym = OutContext.createTempSymbol();
1437  ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1438  }
1439 
1440  // Create a link-saving branch to the Reg Indirect Jump Pad.
1442  // Predicate comes first here.
1443  .addImm(ARMCC::AL).addReg(0)
1444  .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1445  return;
1446  }
1447  case ARM::BMOVPCRX_CALL: {
1449  .addReg(ARM::LR)
1450  .addReg(ARM::PC)
1451  // Add predicate operands.
1452  .addImm(ARMCC::AL)
1453  .addReg(0)
1454  // Add 's' bit operand (always reg0 for this)
1455  .addReg(0));
1456 
1458  .addReg(ARM::PC)
1459  .addReg(MI->getOperand(0).getReg())
1460  // Add predicate operands.
1461  .addImm(ARMCC::AL)
1462  .addReg(0)
1463  // Add 's' bit operand (always reg0 for this)
1464  .addReg(0));
1465  return;
1466  }
1467  case ARM::BMOVPCB_CALL: {
1469  .addReg(ARM::LR)
1470  .addReg(ARM::PC)
1471  // Add predicate operands.
1472  .addImm(ARMCC::AL)
1473  .addReg(0)
1474  // Add 's' bit operand (always reg0 for this)
1475  .addReg(0));
1476 
1477  const MachineOperand &Op = MI->getOperand(0);
1478  const GlobalValue *GV = Op.getGlobal();
1479  const unsigned TF = Op.getTargetFlags();
1480  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1481  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1483  .addExpr(GVSymExpr)
1484  // Add predicate operands.
1485  .addImm(ARMCC::AL)
1486  .addReg(0));
1487  return;
1488  }
1489  case ARM::MOVi16_ga_pcrel:
1490  case ARM::t2MOVi16_ga_pcrel: {
1491  MCInst TmpInst;
1492  TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1493  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1494 
1495  unsigned TF = MI->getOperand(1).getTargetFlags();
1496  const GlobalValue *GV = MI->getOperand(1).getGlobal();
1497  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1498  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1499 
1500  MCSymbol *LabelSym =
1501  getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1502  MI->getOperand(2).getImm(), OutContext);
1503  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1504  unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1505  const MCExpr *PCRelExpr =
1507  MCBinaryExpr::createAdd(LabelSymExpr,
1510  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1511 
1512  // Add predicate operands.
1514  TmpInst.addOperand(MCOperand::createReg(0));
1515  // Add 's' bit operand (always reg0 for this)
1516  TmpInst.addOperand(MCOperand::createReg(0));
1517  EmitToStreamer(*OutStreamer, TmpInst);
1518  return;
1519  }
1520  case ARM::MOVTi16_ga_pcrel:
1521  case ARM::t2MOVTi16_ga_pcrel: {
1522  MCInst TmpInst;
1523  TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1524  ? ARM::MOVTi16 : ARM::t2MOVTi16);
1525  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1526  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1527 
1528  unsigned TF = MI->getOperand(2).getTargetFlags();
1529  const GlobalValue *GV = MI->getOperand(2).getGlobal();
1530  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1531  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1532 
1533  MCSymbol *LabelSym =
1534  getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1535  MI->getOperand(3).getImm(), OutContext);
1536  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1537  unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1538  const MCExpr *PCRelExpr =
1540  MCBinaryExpr::createAdd(LabelSymExpr,
1543  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1544  // Add predicate operands.
1546  TmpInst.addOperand(MCOperand::createReg(0));
1547  // Add 's' bit operand (always reg0 for this)
1548  TmpInst.addOperand(MCOperand::createReg(0));
1549  EmitToStreamer(*OutStreamer, TmpInst);
1550  return;
1551  }
1552  case ARM::t2BFi:
1553  case ARM::t2BFic:
1554  case ARM::t2BFLi:
1555  case ARM::t2BFr:
1556  case ARM::t2BFLr: {
1557  // This is a Branch Future instruction.
1558 
1559  const MCExpr *BranchLabel = MCSymbolRefExpr::create(
1560  getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1561  MI->getOperand(0).getIndex(), OutContext),
1562  OutContext);
1563 
1564  auto MCInst = MCInstBuilder(Opc).addExpr(BranchLabel);
1565  if (MI->getOperand(1).isReg()) {
1566  // For BFr/BFLr
1567  MCInst.addReg(MI->getOperand(1).getReg());
1568  } else {
1569  // For BFi/BFLi/BFic
1570  const MCExpr *BranchTarget;
1571  if (MI->getOperand(1).isMBB())
1573  MI->getOperand(1).getMBB()->getSymbol(), OutContext);
1574  else if (MI->getOperand(1).isGlobal()) {
1575  const GlobalValue *GV = MI->getOperand(1).getGlobal();
1577  GetARMGVSymbol(GV, MI->getOperand(1).getTargetFlags()), OutContext);
1578  } else if (MI->getOperand(1).isSymbol()) {
1580  GetExternalSymbolSymbol(MI->getOperand(1).getSymbolName()),
1581  OutContext);
1582  } else
1583  llvm_unreachable("Unhandled operand kind in Branch Future instruction");
1584 
1585  MCInst.addExpr(BranchTarget);
1586  }
1587 
1588  if (Opc == ARM::t2BFic) {
1589  const MCExpr *ElseLabel = MCSymbolRefExpr::create(
1590  getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1591  MI->getOperand(2).getIndex(), OutContext),
1592  OutContext);
1593  MCInst.addExpr(ElseLabel);
1594  MCInst.addImm(MI->getOperand(3).getImm());
1595  } else {
1596  MCInst.addImm(MI->getOperand(2).getImm())
1597  .addReg(MI->getOperand(3).getReg());
1598  }
1599 
1601  return;
1602  }
1603  case ARM::t2BF_LabelPseudo: {
1604  // This is a pseudo op for a label used by a branch future instruction
1605 
1606  // Emit the label.
1607  OutStreamer->emitLabel(getBFLabel(DL.getPrivateGlobalPrefix(),
1609  MI->getOperand(0).getIndex(), OutContext));
1610  return;
1611  }
1612  case ARM::tPICADD: {
1613  // This is a pseudo op for a label + instruction sequence, which looks like:
1614  // LPC0:
1615  // add r0, pc
1616  // This adds the address of LPC0 to r0.
1617 
1618  // Emit the label.
1619  OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1621  MI->getOperand(2).getImm(), OutContext));
1622 
1623  // Form and emit the add.
1624  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1625  .addReg(MI->getOperand(0).getReg())
1626  .addReg(MI->getOperand(0).getReg())
1627  .addReg(ARM::PC)
1628  // Add predicate operands.
1629  .addImm(ARMCC::AL)
1630  .addReg(0));
1631  return;
1632  }
1633  case ARM::PICADD: {
1634  // This is a pseudo op for a label + instruction sequence, which looks like:
1635  // LPC0:
1636  // add r0, pc, r0
1637  // This adds the address of LPC0 to r0.
1638 
1639  // Emit the label.
1640  OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1642  MI->getOperand(2).getImm(), OutContext));
1643 
1644  // Form and emit the add.
1646  .addReg(MI->getOperand(0).getReg())
1647  .addReg(ARM::PC)
1648  .addReg(MI->getOperand(1).getReg())
1649  // Add predicate operands.
1650  .addImm(MI->getOperand(3).getImm())
1651  .addReg(MI->getOperand(4).getReg())
1652  // Add 's' bit operand (always reg0 for this)
1653  .addReg(0));
1654  return;
1655  }
1656  case ARM::PICSTR:
1657  case ARM::PICSTRB:
1658  case ARM::PICSTRH:
1659  case ARM::PICLDR:
1660  case ARM::PICLDRB:
1661  case ARM::PICLDRH:
1662  case ARM::PICLDRSB:
1663  case ARM::PICLDRSH: {
1664  // This is a pseudo op for a label + instruction sequence, which looks like:
1665  // LPC0:
1666  // OP r0, [pc, r0]
1667  // The LCP0 label is referenced by a constant pool entry in order to get
1668  // a PC-relative address at the ldr instruction.
1669 
1670  // Emit the label.
1671  OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1673  MI->getOperand(2).getImm(), OutContext));
1674 
1675  // Form and emit the load
1676  unsigned Opcode;
1677  switch (MI->getOpcode()) {
1678  default:
1679  llvm_unreachable("Unexpected opcode!");
1680  case ARM::PICSTR: Opcode = ARM::STRrs; break;
1681  case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1682  case ARM::PICSTRH: Opcode = ARM::STRH; break;
1683  case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1684  case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1685  case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1686  case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1687  case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1688  }
1690  .addReg(MI->getOperand(0).getReg())
1691  .addReg(ARM::PC)
1692  .addReg(MI->getOperand(1).getReg())
1693  .addImm(0)
1694  // Add predicate operands.
1695  .addImm(MI->getOperand(3).getImm())
1696  .addReg(MI->getOperand(4).getReg()));
1697 
1698  return;
1699  }
1700  case ARM::CONSTPOOL_ENTRY: {
1701  if (Subtarget->genExecuteOnly())
1702  llvm_unreachable("execute-only should not generate constant pools");
1703 
1704  /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1705  /// in the function. The first operand is the ID# for this instruction, the
1706  /// second is the index into the MachineConstantPool that this is, the third
1707  /// is the size in bytes of this constant pool entry.
1708  /// The required alignment is specified on the basic block holding this MI.
1709  unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1710  unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1711 
1712  // If this is the first entry of the pool, mark it.
1713  if (!InConstantPool) {
1714  OutStreamer->emitDataRegion(MCDR_DataRegion);
1715  InConstantPool = true;
1716  }
1717 
1718  OutStreamer->emitLabel(GetCPISymbol(LabelId));
1719 
1720  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1721  if (MCPE.isMachineConstantPoolEntry())
1723  else
1725  return;
1726  }
1727  case ARM::JUMPTABLE_ADDRS:
1729  return;
1730  case ARM::JUMPTABLE_INSTS:
1732  return;
1733  case ARM::JUMPTABLE_TBB:
1734  case ARM::JUMPTABLE_TBH:
1735  emitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1736  return;
1737  case ARM::t2BR_JT: {
1739  .addReg(ARM::PC)
1740  .addReg(MI->getOperand(0).getReg())
1741  // Add predicate operands.
1742  .addImm(ARMCC::AL)
1743  .addReg(0));
1744  return;
1745  }
1746  case ARM::t2TBB_JT:
1747  case ARM::t2TBH_JT: {
1748  unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1749  // Lower and emit the PC label, then the instruction itself.
1750  OutStreamer->emitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1752  .addReg(MI->getOperand(0).getReg())
1753  .addReg(MI->getOperand(1).getReg())
1754  // Add predicate operands.
1755  .addImm(ARMCC::AL)
1756  .addReg(0));
1757  return;
1758  }
1759  case ARM::tTBB_JT:
1760  case ARM::tTBH_JT: {
1761 
1762  bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1763  Register Base = MI->getOperand(0).getReg();
1764  Register Idx = MI->getOperand(1).getReg();
1765  assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1766 
1767  // Multiply up idx if necessary.
1768  if (!Is8Bit)
1770  .addReg(Idx)
1771  .addReg(ARM::CPSR)
1772  .addReg(Idx)
1773  .addImm(1)
1774  // Add predicate operands.
1775  .addImm(ARMCC::AL)
1776  .addReg(0));
1777 
1778  if (Base == ARM::PC) {
1779  // TBB [base, idx] =
1780  // ADDS idx, idx, base
1781  // LDRB idx, [idx, #4] ; or LDRH if TBH
1782  // LSLS idx, #1
1783  // ADDS pc, pc, idx
1784 
1785  // When using PC as the base, it's important that there is no padding
1786  // between the last ADDS and the start of the jump table. The jump table
1787  // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1788  //
1789  // FIXME: Ideally we could vary the LDRB index based on the padding
1790  // between the sequence and jump table, however that relies on MCExprs
1791  // for load indexes which are currently not supported.
1792  OutStreamer->emitCodeAlignment(4, &getSubtargetInfo());
1793  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1794  .addReg(Idx)
1795  .addReg(Idx)
1796  .addReg(Base)
1797  // Add predicate operands.
1798  .addImm(ARMCC::AL)
1799  .addReg(0));
1800 
1801  unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1803  .addReg(Idx)
1804  .addReg(Idx)
1805  .addImm(Is8Bit ? 4 : 2)
1806  // Add predicate operands.
1807  .addImm(ARMCC::AL)
1808  .addReg(0));
1809  } else {
1810  // TBB [base, idx] =
1811  // LDRB idx, [base, idx] ; or LDRH if TBH
1812  // LSLS idx, #1
1813  // ADDS pc, pc, idx
1814 
1815  unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1817  .addReg(Idx)
1818  .addReg(Base)
1819  .addReg(Idx)
1820  // Add predicate operands.
1821  .addImm(ARMCC::AL)
1822  .addReg(0));
1823  }
1824 
1826  .addReg(Idx)
1827  .addReg(ARM::CPSR)
1828  .addReg(Idx)
1829  .addImm(1)
1830  // Add predicate operands.
1831  .addImm(ARMCC::AL)
1832  .addReg(0));
1833 
1834  OutStreamer->emitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1835  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1836  .addReg(ARM::PC)
1837  .addReg(ARM::PC)
1838  .addReg(Idx)
1839  // Add predicate operands.
1840  .addImm(ARMCC::AL)
1841  .addReg(0));
1842  return;
1843  }
1844  case ARM::tBR_JTr:
1845  case ARM::BR_JTr: {
1846  // mov pc, target
1847  MCInst TmpInst;
1848  unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1849  ARM::MOVr : ARM::tMOVr;
1850  TmpInst.setOpcode(Opc);
1851  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1852  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1853  // Add predicate operands.
1855  TmpInst.addOperand(MCOperand::createReg(0));
1856  // Add 's' bit operand (always reg0 for this)
1857  if (Opc == ARM::MOVr)
1858  TmpInst.addOperand(MCOperand::createReg(0));
1859  EmitToStreamer(*OutStreamer, TmpInst);
1860  return;
1861  }
1862  case ARM::BR_JTm_i12: {
1863  // ldr pc, target
1864  MCInst TmpInst;
1865  TmpInst.setOpcode(ARM::LDRi12);
1866  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1867  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1868  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1869  // Add predicate operands.
1871  TmpInst.addOperand(MCOperand::createReg(0));
1872  EmitToStreamer(*OutStreamer, TmpInst);
1873  return;
1874  }
1875  case ARM::BR_JTm_rs: {
1876  // ldr pc, target
1877  MCInst TmpInst;
1878  TmpInst.setOpcode(ARM::LDRrs);
1879  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1880  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1881  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1882  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1883  // Add predicate operands.
1885  TmpInst.addOperand(MCOperand::createReg(0));
1886  EmitToStreamer(*OutStreamer, TmpInst);
1887  return;
1888  }
1889  case ARM::BR_JTadd: {
1890  // add pc, target, idx
1892  .addReg(ARM::PC)
1893  .addReg(MI->getOperand(0).getReg())
1894  .addReg(MI->getOperand(1).getReg())
1895  // Add predicate operands.
1896  .addImm(ARMCC::AL)
1897  .addReg(0)
1898  // Add 's' bit operand (always reg0 for this)
1899  .addReg(0));
1900  return;
1901  }
1902  case ARM::SPACE:
1903  OutStreamer->emitZeros(MI->getOperand(1).getImm());
1904  return;
1905  case ARM::TRAP: {
1906  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1907  // FIXME: Remove this special case when they do.
1908  if (!Subtarget->isTargetMachO()) {
1909  uint32_t Val = 0xe7ffdefeUL;
1910  OutStreamer->AddComment("trap");
1911  ATS.emitInst(Val);
1912  return;
1913  }
1914  break;
1915  }
1916  case ARM::TRAPNaCl: {
1917  uint32_t Val = 0xe7fedef0UL;
1918  OutStreamer->AddComment("trap");
1919  ATS.emitInst(Val);
1920  return;
1921  }
1922  case ARM::tTRAP: {
1923  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1924  // FIXME: Remove this special case when they do.
1925  if (!Subtarget->isTargetMachO()) {
1926  uint16_t Val = 0xdefe;
1927  OutStreamer->AddComment("trap");
1928  ATS.emitInst(Val, 'n');
1929  return;
1930  }
1931  break;
1932  }
1933  case ARM::t2Int_eh_sjlj_setjmp:
1934  case ARM::t2Int_eh_sjlj_setjmp_nofp:
1935  case ARM::tInt_eh_sjlj_setjmp: {
1936  // Two incoming args: GPR:$src, GPR:$val
1937  // mov $val, pc
1938  // adds $val, #7
1939  // str $val, [$src, #4]
1940  // movs r0, #0
1941  // b LSJLJEH
1942  // movs r0, #1
1943  // LSJLJEH:
1944  Register SrcReg = MI->getOperand(0).getReg();
1945  Register ValReg = MI->getOperand(1).getReg();
1946  MCSymbol *Label = OutContext.createTempSymbol("SJLJEH");
1947  OutStreamer->AddComment("eh_setjmp begin");
1949  .addReg(ValReg)
1950  .addReg(ARM::PC)
1951  // Predicate.
1952  .addImm(ARMCC::AL)
1953  .addReg(0));
1954 
1956  .addReg(ValReg)
1957  // 's' bit operand
1958  .addReg(ARM::CPSR)
1959  .addReg(ValReg)
1960  .addImm(7)
1961  // Predicate.
1962  .addImm(ARMCC::AL)
1963  .addReg(0));
1964 
1966  .addReg(ValReg)
1967  .addReg(SrcReg)
1968  // The offset immediate is #4. The operand value is scaled by 4 for the
1969  // tSTR instruction.
1970  .addImm(1)
1971  // Predicate.
1972  .addImm(ARMCC::AL)
1973  .addReg(0));
1974 
1976  .addReg(ARM::R0)
1977  .addReg(ARM::CPSR)
1978  .addImm(0)
1979  // Predicate.
1980  .addImm(ARMCC::AL)
1981  .addReg(0));
1982 
1983  const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1985  .addExpr(SymbolExpr)
1986  .addImm(ARMCC::AL)
1987  .addReg(0));
1988 
1989  OutStreamer->AddComment("eh_setjmp end");
1991  .addReg(ARM::R0)
1992  .addReg(ARM::CPSR)
1993  .addImm(1)
1994  // Predicate.
1995  .addImm(ARMCC::AL)
1996  .addReg(0));
1997 
1998  OutStreamer->emitLabel(Label);
1999  return;
2000  }
2001 
2002  case ARM::Int_eh_sjlj_setjmp_nofp:
2003  case ARM::Int_eh_sjlj_setjmp: {
2004  // Two incoming args: GPR:$src, GPR:$val
2005  // add $val, pc, #8
2006  // str $val, [$src, #+4]
2007  // mov r0, #0
2008  // add pc, pc, #0
2009  // mov r0, #1
2010  Register SrcReg = MI->getOperand(0).getReg();
2011  Register ValReg = MI->getOperand(1).getReg();
2012 
2013  OutStreamer->AddComment("eh_setjmp begin");
2015  .addReg(ValReg)
2016  .addReg(ARM::PC)
2017  .addImm(8)
2018  // Predicate.
2019  .addImm(ARMCC::AL)
2020  .addReg(0)
2021  // 's' bit operand (always reg0 for this).
2022  .addReg(0));
2023 
2025  .addReg(ValReg)
2026  .addReg(SrcReg)
2027  .addImm(4)
2028  // Predicate.
2029  .addImm(ARMCC::AL)
2030  .addReg(0));
2031 
2033  .addReg(ARM::R0)
2034  .addImm(0)
2035  // Predicate.
2036  .addImm(ARMCC::AL)
2037  .addReg(0)
2038  // 's' bit operand (always reg0 for this).
2039  .addReg(0));
2040 
2042  .addReg(ARM::PC)
2043  .addReg(ARM::PC)
2044  .addImm(0)
2045  // Predicate.
2046  .addImm(ARMCC::AL)
2047  .addReg(0)
2048  // 's' bit operand (always reg0 for this).
2049  .addReg(0));
2050 
2051  OutStreamer->AddComment("eh_setjmp end");
2053  .addReg(ARM::R0)
2054  .addImm(1)
2055  // Predicate.
2056  .addImm(ARMCC::AL)
2057  .addReg(0)
2058  // 's' bit operand (always reg0 for this).
2059  .addReg(0));
2060  return;
2061  }
2062  case ARM::Int_eh_sjlj_longjmp: {
2063  // ldr sp, [$src, #8]
2064  // ldr $scratch, [$src, #4]
2065  // ldr r7, [$src]
2066  // bx $scratch
2067  Register SrcReg = MI->getOperand(0).getReg();
2068  Register ScratchReg = MI->getOperand(1).getReg();
2070  .addReg(ARM::SP)
2071  .addReg(SrcReg)
2072  .addImm(8)
2073  // Predicate.
2074  .addImm(ARMCC::AL)
2075  .addReg(0));
2076 
2078  .addReg(ScratchReg)
2079  .addReg(SrcReg)
2080  .addImm(4)
2081  // Predicate.
2082  .addImm(ARMCC::AL)
2083  .addReg(0));
2084 
2085  const MachineFunction &MF = *MI->getParent()->getParent();
2086  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
2087 
2088  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2089  // These platforms always use the same frame register
2091  .addReg(STI.getFramePointerReg())
2092  .addReg(SrcReg)
2093  .addImm(0)
2094  // Predicate.
2095  .addImm(ARMCC::AL)
2096  .addReg(0));
2097  } else {
2098  // If the calling code might use either R7 or R11 as
2099  // frame pointer register, restore it into both.
2101  .addReg(ARM::R7)
2102  .addReg(SrcReg)
2103  .addImm(0)
2104  // Predicate.
2105  .addImm(ARMCC::AL)
2106  .addReg(0));
2108  .addReg(ARM::R11)
2109  .addReg(SrcReg)
2110  .addImm(0)
2111  // Predicate.
2112  .addImm(ARMCC::AL)
2113  .addReg(0));
2114  }
2115 
2116  assert(Subtarget->hasV4TOps());
2118  .addReg(ScratchReg)
2119  // Predicate.
2120  .addImm(ARMCC::AL)
2121  .addReg(0));
2122  return;
2123  }
2124  case ARM::tInt_eh_sjlj_longjmp: {
2125  // ldr $scratch, [$src, #8]
2126  // mov sp, $scratch
2127  // ldr $scratch, [$src, #4]
2128  // ldr r7, [$src]
2129  // bx $scratch
2130  Register SrcReg = MI->getOperand(0).getReg();
2131  Register ScratchReg = MI->getOperand(1).getReg();
2132 
2133  const MachineFunction &MF = *MI->getParent()->getParent();
2134  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
2135 
2137  .addReg(ScratchReg)
2138  .addReg(SrcReg)
2139  // The offset immediate is #8. The operand value is scaled by 4 for the
2140  // tLDR instruction.
2141  .addImm(2)
2142  // Predicate.
2143  .addImm(ARMCC::AL)
2144  .addReg(0));
2145 
2147  .addReg(ARM::SP)
2148  .addReg(ScratchReg)
2149  // Predicate.
2150  .addImm(ARMCC::AL)
2151  .addReg(0));
2152 
2154  .addReg(ScratchReg)
2155  .addReg(SrcReg)
2156  .addImm(1)
2157  // Predicate.
2158  .addImm(ARMCC::AL)
2159  .addReg(0));
2160 
2161  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2162  // These platforms always use the same frame register
2164  .addReg(STI.getFramePointerReg())
2165  .addReg(SrcReg)
2166  .addImm(0)
2167  // Predicate.
2168  .addImm(ARMCC::AL)
2169  .addReg(0));
2170  } else {
2171  // If the calling code might use either R7 or R11 as
2172  // frame pointer register, restore it into both.
2174  .addReg(ARM::R7)
2175  .addReg(SrcReg)
2176  .addImm(0)
2177  // Predicate.
2178  .addImm(ARMCC::AL)
2179  .addReg(0));
2181  .addReg(ARM::R11)
2182  .addReg(SrcReg)
2183  .addImm(0)
2184  // Predicate.
2185  .addImm(ARMCC::AL)
2186  .addReg(0));
2187  }
2188 
2190  .addReg(ScratchReg)
2191  // Predicate.
2192  .addImm(ARMCC::AL)
2193  .addReg(0));
2194  return;
2195  }
2196  case ARM::tInt_WIN_eh_sjlj_longjmp: {
2197  // ldr.w r11, [$src, #0]
2198  // ldr.w sp, [$src, #8]
2199  // ldr.w pc, [$src, #4]
2200 
2201  Register SrcReg = MI->getOperand(0).getReg();
2202 
2203  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2204  .addReg(ARM::R11)
2205  .addReg(SrcReg)
2206  .addImm(0)
2207  // Predicate
2208  .addImm(ARMCC::AL)
2209  .addReg(0));
2210  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2211  .addReg(ARM::SP)
2212  .addReg(SrcReg)
2213  .addImm(8)
2214  // Predicate
2215  .addImm(ARMCC::AL)
2216  .addReg(0));
2217  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2218  .addReg(ARM::PC)
2219  .addReg(SrcReg)
2220  .addImm(4)
2221  // Predicate
2222  .addImm(ARMCC::AL)
2223  .addReg(0));
2224  return;
2225  }
2226  case ARM::PATCHABLE_FUNCTION_ENTER:
2228  return;
2229  case ARM::PATCHABLE_FUNCTION_EXIT:
2231  return;
2232  case ARM::PATCHABLE_TAIL_CALL:
2234  return;
2235  case ARM::SpeculationBarrierISBDSBEndBB: {
2236  // Print DSB SYS + ISB
2237  MCInst TmpInstDSB;
2238  TmpInstDSB.setOpcode(ARM::DSB);
2239  TmpInstDSB.addOperand(MCOperand::createImm(0xf));
2240  EmitToStreamer(*OutStreamer, TmpInstDSB);
2241  MCInst TmpInstISB;
2242  TmpInstISB.setOpcode(ARM::ISB);
2243  TmpInstISB.addOperand(MCOperand::createImm(0xf));
2244  EmitToStreamer(*OutStreamer, TmpInstISB);
2245  return;
2246  }
2247  case ARM::t2SpeculationBarrierISBDSBEndBB: {
2248  // Print DSB SYS + ISB
2249  MCInst TmpInstDSB;
2250  TmpInstDSB.setOpcode(ARM::t2DSB);
2251  TmpInstDSB.addOperand(MCOperand::createImm(0xf));
2253  TmpInstDSB.addOperand(MCOperand::createReg(0));
2254  EmitToStreamer(*OutStreamer, TmpInstDSB);
2255  MCInst TmpInstISB;
2256  TmpInstISB.setOpcode(ARM::t2ISB);
2257  TmpInstISB.addOperand(MCOperand::createImm(0xf));
2259  TmpInstISB.addOperand(MCOperand::createReg(0));
2260  EmitToStreamer(*OutStreamer, TmpInstISB);
2261  return;
2262  }
2263  case ARM::SpeculationBarrierSBEndBB: {
2264  // Print SB
2265  MCInst TmpInstSB;
2266  TmpInstSB.setOpcode(ARM::SB);
2267  EmitToStreamer(*OutStreamer, TmpInstSB);
2268  return;
2269  }
2270  case ARM::t2SpeculationBarrierSBEndBB: {
2271  // Print SB
2272  MCInst TmpInstSB;
2273  TmpInstSB.setOpcode(ARM::t2SB);
2274  EmitToStreamer(*OutStreamer, TmpInstSB);
2275  return;
2276  }
2277 
2278  case ARM::SEH_StackAlloc:
2279  ATS.emitARMWinCFIAllocStack(MI->getOperand(0).getImm(),
2280  MI->getOperand(1).getImm());
2281  return;
2282 
2283  case ARM::SEH_SaveRegs:
2284  case ARM::SEH_SaveRegs_Ret:
2285  ATS.emitARMWinCFISaveRegMask(MI->getOperand(0).getImm(),
2286  MI->getOperand(1).getImm());
2287  return;
2288 
2289  case ARM::SEH_SaveSP:
2290  ATS.emitARMWinCFISaveSP(MI->getOperand(0).getImm());
2291  return;
2292 
2293  case ARM::SEH_SaveFRegs:
2294  ATS.emitARMWinCFISaveFRegs(MI->getOperand(0).getImm(),
2295  MI->getOperand(1).getImm());
2296  return;
2297 
2298  case ARM::SEH_SaveLR:
2299  ATS.emitARMWinCFISaveLR(MI->getOperand(0).getImm());
2300  return;
2301 
2302  case ARM::SEH_Nop:
2303  case ARM::SEH_Nop_Ret:
2304  ATS.emitARMWinCFINop(MI->getOperand(0).getImm());
2305  return;
2306 
2307  case ARM::SEH_PrologEnd:
2308  ATS.emitARMWinCFIPrologEnd(/*Fragment=*/false);
2309  return;
2310 
2311  case ARM::SEH_EpilogStart:
2313  return;
2314 
2315  case ARM::SEH_EpilogEnd:
2316  ATS.emitARMWinCFIEpilogEnd();
2317  return;
2318  }
2319 
2320  MCInst TmpInst;
2321  LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2322 
2323  EmitToStreamer(*OutStreamer, TmpInst);
2324 }
2325 
2326 //===----------------------------------------------------------------------===//
2327 // Target Registry Stuff
2328 //===----------------------------------------------------------------------===//
2329 
2330 // Force static initialization.
2336 }
llvm::ARMBuildAttrs::FP16FormatIEEE
@ FP16FormatIEEE
Definition: ARMBuildAttributes.h:226
llvm::Check::Size
@ Size
Definition: FileCheck.h:77
i
i
Definition: README.txt:29
llvm::ARMCP::ARMCPModifier
ARMCPModifier
Definition: ARMConstantPoolValue.h:46
checkDenormalAttributeConsistency
static bool checkDenormalAttributeConsistency(const Module &M, StringRef Attr, DenormalMode Value)
Definition: ARMAsmPrinter.cpp:599
llvm::ARMConstantPoolValue::getPCAdjustment
unsigned char getPCAdjustment() const
Definition: ARMConstantPoolValue.h:105
llvm::TargetOptions::HonorSignDependentRoundingFPMathOption
unsigned HonorSignDependentRoundingFPMathOption
HonorSignDependentRoundingFPMath - This returns true when the -enable-sign-dependent-rounding-fp-math...
Definition: TargetOptions.h:207
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:186
llvm::AsmPrinter::isPositionIndependent
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:373
llvm::ARMBuildAttrs::BTI_extension
@ BTI_extension
Definition: ARMBuildAttributes.h:74
MachineModuleInfoImpls.h
llvm::ARMFunctionInfo
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
Definition: ARMMachineFunctionInfo.h:27
llvm::MCBinaryExpr::createDiv
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:535
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:52
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::ARMBuildAttrs::PACRET_use
@ PACRET_use
Definition: ARMBuildAttributes.h:79
llvm::ARMBuildAttrs::ABI_PCS_R9_use
@ ABI_PCS_R9_use
Definition: ARMBuildAttributes.h:47
LLVMInitializeARMAsmPrinter
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMAsmPrinter()
Definition: ARMAsmPrinter.cpp:2331
llvm::ARMII::MO_HI16
@ MO_HI16
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address.
Definition: ARMBaseInfo.h:254
llvm::AsmPrinter::printOffset
void printOffset(int64_t Offset, raw_ostream &OS) const
This is just convenient handler for printing offsets.
Definition: AsmPrinter.cpp:3299
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::ARMConstantPoolValue
ARMConstantPoolValue - ARM specific constantpool value.
Definition: ARMConstantPoolValue.h:61
ARMTargetInfo.h
llvm::ARM_MC::ParseARMTriple
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Definition: ARMMCTargetDesc.cpp:141
llvm::ARMAsmPrinter::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This uses the emitInstruction() method to print assembly for each instruction.
Definition: ARMAsmPrinter.cpp:116
llvm::ARM::PredBlockMask::TT
@ TT
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::ARMBuildAttrs::Not_Allowed
@ Not_Allowed
Definition: ARMBuildAttributes.h:125
llvm::ARMCP::TPOFF
@ TPOFF
Global Offset Table, Thread Pointer Offset.
Definition: ARMConstantPoolValue.h:51
llvm::MCSymbolRefExpr::VK_ARM_GOT_PREL
@ VK_ARM_GOT_PREL
Definition: MCExpr.h:231
llvm::getTheARMBETarget
Target & getTheARMBETarget()
Definition: ARMTargetInfo.cpp:17
llvm::COFF::IMAGE_SYM_CLASS_STATIC
@ IMAGE_SYM_CLASS_STATIC
Static.
Definition: COFF.h:209
llvm::cl::Prefix
@ Prefix
Definition: CommandLine.h:160
llvm::ARMSubtarget
Definition: ARMSubtarget.h:47
llvm::ARMBuildAttrs::ABI_align_preserved
@ ABI_align_preserved
Definition: ARMBuildAttributes.h:58
llvm::ARMBuildAttrs::ABI_enum_size
@ ABI_enum_size
Definition: ARMBuildAttributes.h:59
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:572
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::Function
Definition: Function.h:60
ARMInstPrinter.h
llvm::DenseMapBase::lookup
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:199
llvm::ARMTargetStreamer
Definition: MCStreamer.h:135
llvm::MachineConstantPoolEntry::MachineCPVal
MachineConstantPoolValue * MachineCPVal
Definition: MachineConstantPool.h:72
llvm::AsmPrinter::MAI
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:87
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::convertAddSubFlagsOpcode
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
Definition: ARMBaseInstrInfo.cpp:2470
llvm::MCSymbolRefExpr::VK_ARM_TARGET1
@ VK_ARM_TARGET1
Definition: MCExpr.h:232
llvm::AsmPrinter::emitGlobalConstant
void emitGlobalConstant(const DataLayout &DL, const Constant *CV)
Print a general LLVM constant to the .s file.
Definition: AsmPrinter.cpp:3283
llvm::SmallVector< unsigned, 4 >
llvm::ARMFunctionInfo::EHPrologueOffsetInRegs
DenseMap< unsigned, unsigned > EHPrologueOffsetInRegs
Definition: ARMMachineFunctionInfo.h:283
llvm::ARMII::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: ARMBaseInfo.h:263
llvm::MCObjectFileInfo::getThreadLocalPointerSection
MCSection * getThreadLocalPointerSection() const
Definition: MCObjectFileInfo.h:414
llvm::ARMBuildAttrs::AllowBTIInNOPSpace
@ AllowBTIInNOPSpace
Definition: ARMBuildAttributes.h:254
llvm::MCSymbolRefExpr::VK_ARM_SBREL
@ VK_ARM_SBREL
Definition: MCExpr.h:235
llvm::COFF::IMAGE_SYM_CLASS_EXTERNAL
@ IMAGE_SYM_CLASS_EXTERNAL
External symbol.
Definition: COFF.h:208
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::GlobalVariable
Definition: GlobalVariable.h:39
ARMMachineFunctionInfo.h
llvm::ARMFunctionInfo::getOriginalCPIdx
unsigned getOriginalCPIdx(unsigned CloneIdx) const
Definition: ARMMachineFunctionInfo.h:249
llvm::AsmPrinter::getNameWithPrefix
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:649
MCInstBuilder.h
llvm::COFF::SCT_COMPLEX_TYPE_SHIFT
@ SCT_COMPLEX_TYPE_SHIFT
Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT))
Definition: COFF.h:264
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCAssembler.h
llvm::ARMTargetStreamer::emitARMWinCFINop
virtual void emitARMWinCFINop(bool Wide)
Definition: ARMTargetStreamer.cpp:126
llvm::ARMAsmPrinter::printOperand
void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O)
Definition: ARMAsmPrinter.cpp:209
COFF.h
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::MachineModuleInfoImpl::SymbolListTy
std::vector< std::pair< MCSymbol *, StubValueTy > > SymbolListTy
Definition: MachineModuleInfo.h:60
llvm::MCStreamer::emitValue
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:178
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::ARMInstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=ARM::NoRegAltName)
llvm::MachineConstantPoolValue
Abstract base class for all machine specific constantpool value subclasses.
Definition: MachineConstantPool.h:35
llvm::ARMConstantPoolValue::isLSDA
bool isLSDA() const
Definition: ARMConstantPoolValue.h:110
llvm::ARMII::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:275
MachineJumpTableInfo.h
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:361
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::MachineConstantPoolEntry::Val
union llvm::MachineConstantPoolEntry::@189 Val
The constant itself.
llvm::AsmPrinter::emitAlignment
void emitAlignment(Align Alignment, const GlobalObject *GV=nullptr, unsigned MaxBytesToEmit=0) const
Emit an alignment directive to the specified power of two boundary.
Definition: AsmPrinter.cpp:2650
Module.h
llvm::ARMTargetStreamer::emitARMWinCFIAllocStack
virtual void emitARMWinCFIAllocStack(unsigned Size, bool Wide)
Definition: ARMTargetStreamer.cpp:121
llvm::ARMAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
Definition: ARMMCInstLower.cpp:216
llvm::ExceptionHandling::ARM
@ ARM
ARM EHABI.
llvm::ARMCP::no_modifier
@ no_modifier
Definition: ARMConstantPoolValue.h:47
llvm::FloatABI::Hard
@ Hard
Definition: TargetOptions.h:31
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:79
ARMMCExpr.h
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
llvm::MachineModuleInfoMachO::getGVStubEntry
StubValueTy & getGVStubEntry(MCSymbol *Sym)
Definition: MachineModuleInfoImpls.h:44
llvm::ARMBuildAttrs::R9Reserved
@ R9Reserved
Definition: ARMBuildAttributes.h:162
llvm::ARMBuildAttrs::BTI_use
@ BTI_use
Definition: ARMBuildAttributes.h:78
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
TargetParser.h
llvm::ARMConstantPoolValue::isGlobalValue
bool isGlobalValue() const
Definition: ARMConstantPoolValue.h:107
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:609
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::ARMCP::SECREL
@ SECREL
Thread Pointer Offset.
Definition: ARMConstantPoolValue.h:52
llvm::TargetLoweringObjectFileMachO
Definition: TargetLoweringObjectFileImpl.h:115
llvm::ARMTargetStreamer::emitPad
virtual void emitPad(int64_t Offset)
Definition: ARMTargetStreamer.cpp:99
llvm::ARMMCExpr::createUpper16
static const ARMMCExpr * createUpper16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:38
llvm::InlineAsm::MIOp_FirstOperand
@ MIOp_FirstOperand
Definition: InlineAsm.h:225
MCELFStreamer.h
llvm::AsmPrinter::emitGlobalVariable
virtual void emitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
Definition: AsmPrinter.cpp:676
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:51
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AsmPrinter::EmitToStreamer
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:401
llvm::MCDR_DataRegionJT16
@ MCDR_DataRegionJT16
.data_region jt16
Definition: MCDirectives.h:62
llvm::COFF::SymbolStorageClass
SymbolStorageClass
Storage class tells where and what the symbol represents.
Definition: COFF.h:202
getBFLabel
static MCSymbol * getBFLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
Definition: ARMAsmPrinter.cpp:807
llvm::ARMBuildAttrs::conformance
@ conformance
Definition: ARMBuildAttributes.h:76
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
llvm::MachineConstantPoolValue::getType
Type * getType() const
Definition: MachineConstantPool.h:44
llvm::parseDenormalFPAttribute
DenormalMode parseDenormalFPAttribute(StringRef Str)
Returns the denormal mode to use for inputs and outputs.
Definition: FloatingPointMode.h:176
llvm::ARMFunctionInfo::EHPrologueRemappedRegs
DenseMap< unsigned, unsigned > EHPrologueRemappedRegs
Definition: ARMMachineFunctionInfo.h:282
llvm::ARMConstantPoolValue::isExtSymbol
bool isExtSymbol() const
Definition: ARMConstantPoolValue.h:108
llvm::ARMFunctionInfo::isCmseNSEntryFunction
bool isCmseNSEntryFunction() const
Definition: ARMMachineFunctionInfo.h:170
llvm::getTheARMLETarget
Target & getTheARMLETarget()
Definition: ARMTargetInfo.cpp:13
MCObjectStreamer.h
llvm::ARMBuildAttrs::R9IsSB
@ R9IsSB
Definition: ARMBuildAttributes.h:160
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:57
llvm::ARMBuildAttrs::ABI_FP_exceptions
@ ABI_FP_exceptions
Definition: ARMBuildAttributes.h:54
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:212
llvm::ARMSubtarget::isTargetMuslAEABI
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:394
ARMConstantPoolValue.h
llvm::ARMII::MO_NO_FLAG
@ MO_NO_FLAG
Definition: ARMBaseInfo.h:246
llvm::MachineModuleInfoMachO::GetThreadLocalGVStubList
SymbolListTy GetThreadLocalGVStubList()
Definition: MachineModuleInfoImpls.h:56
llvm::ARMAsmPrinter::emitMachineConstantPoolValue
void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file.
Definition: ARMAsmPrinter.cpp:900
llvm::MCDR_DataRegion
@ MCDR_DataRegion
.data_region
Definition: MCDirectives.h:60
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:865
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:666
llvm::ARMAsmPrinter::emitInstruction
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
Definition: ARMAsmPrinter.cpp:1339
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:207
llvm::LowerARMMachineInstrToMCInst
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP)
Definition: ARMMCInstLower.cpp:123
llvm::ARMTargetStreamer::emitRegSave
virtual void emitRegSave(const SmallVectorImpl< unsigned > &RegList, bool isVector)
Definition: ARMTargetStreamer.cpp:100
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
llvm::TargetOptions::NoInfsFPMath
unsigned NoInfsFPMath
NoInfsFPMath - This flag is enabled when the -enable-no-infs-fp-math flag is specified on the command...
Definition: TargetOptions.h:169
TargetMachine.h
llvm::AsmPrinter::emitLinkage
virtual void emitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const
This emits linkage information about GVSym based on GV, if this is supported by the target.
Definition: AsmPrinter.cpp:609
Constants.h
llvm::ARMTargetStreamer::emitInst
virtual void emitInst(uint32_t Inst, char Suffix='\0')
Definition: ARMTargetStreamer.cpp:53
SmallString.h
llvm::getTheThumbLETarget
Target & getTheThumbLETarget()
Definition: ARMTargetInfo.cpp:21
llvm::ARMBuildAttrs::PAC_extension
@ PAC_extension
Definition: ARMBuildAttributes.h:73
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:61
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:754
llvm::AsmPrinter::OutStreamer
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:96
MCContext.h
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MCStreamer::emitLabel
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:423
llvm::AsmPrinter::SetupMachineFunction
virtual void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
Definition: AsmPrinter.cpp:2153
MCSymbol.h
llvm::MCAF_Code16
@ MCAF_Code16
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:54
MCInst.h
false
Definition: StackSlotColoring.cpp:141
ARMAsmPrinter.h
FramePtr
static const unsigned FramePtr
Definition: XCoreFrameLowering.cpp:34
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::ARMBaseTargetMachine::isLittleEndian
bool isLittleEndian() const
Definition: ARMTargetMachine.h:53
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::ARMBuildAttrs::AddressROPCRel
@ AddressROPCRel
Definition: ARMBuildAttributes.h:170
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:84
llvm::ARMBuildAttrs::AddressRWSBRel
@ AddressRWSBRel
Definition: ARMBuildAttributes.h:166
llvm::AsmPrinter::CurrentFnSym
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:118
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::ARMSubtarget::isTargetAEABI
bool isTargetAEABI() const
Definition: ARMSubtarget.h:384
llvm::MCOI::BranchTarget
@ BranchTarget
Definition: MCInstrDesc.h:53
llvm::ARMAsmPrinter::emitFunctionBodyEnd
void emitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
Definition: ARMAsmPrinter.cpp:60
llvm::ARMBuildAttrs::ABI_FP_rounding
@ ABI_FP_rounding
Definition: ARMBuildAttributes.h:52
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:93
llvm::ARMConstantPoolValue::getModifier
ARMCP::ARMCPModifier getModifier() const
Definition: ARMConstantPoolValue.h:98
llvm::GlobalValue::hasInternalLinkage
bool hasInternalLinkage() const
Definition: GlobalValue.h:491
llvm::MCSymbol::getName
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:198
isThumb
static bool isThumb(const MCSubtargetInfo &STI)
Definition: ARMAsmPrinter.cpp:470
llvm::ARMFunctionInfo::isThumbFunction
bool isThumbFunction() const
Definition: ARMMachineFunctionInfo.h:166
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::MCSymbol::print
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:58
llvm::TargetOptions::FloatABIType
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line.
Definition: TargetOptions.h:381
Type.h
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::ARMTargetStreamer::emitARMWinCFIPrologEnd
virtual void emitARMWinCFIPrologEnd(bool Fragment)
Definition: ARMTargetStreamer.cpp:127
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
llvm::ARMAsmPrinter::emitXXStructor
void emitXXStructor(const DataLayout &DL, const Constant *CV) override
Targets can override this to change how global constants that are part of a C++ static/global constru...
Definition: ARMAsmPrinter.cpp:89
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:129
llvm::MCDR_DataRegionJT32
@ MCDR_DataRegionJT32
.data_region jt32
Definition: MCDirectives.h:63
llvm::MachineModuleInfoCOFF
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
Definition: MachineModuleInfoImpls.h:85
llvm::ARMTargetStreamer::emitSetFP
virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset=0)
Definition: ARMTargetStreamer.cpp:96
llvm::TargetOptions::NoTrappingFPMath
unsigned NoTrappingFPMath
NoTrappingFPMath - This flag is enabled when the -enable-no-trapping-fp-math is specified on the comm...
Definition: TargetOptions.h:180
llvm::ARMTargetStreamer::emitARMWinCFISaveRegMask
virtual void emitARMWinCFISaveRegMask(unsigned Mask, bool Wide)
Definition: ARMTargetStreamer.cpp:122
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::PointerIntPair::getPointer
PointerTy getPointer() const
Definition: PointerIntPair.h:60
llvm::ARMTargetStreamer::emitARMWinCFIEpilogStart
virtual void emitARMWinCFIEpilogStart(unsigned Condition)
Definition: ARMTargetStreamer.cpp:128
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
llvm::DenormalMode::getPositiveZero
static constexpr DenormalMode getPositiveZero()
Definition: FloatingPointMode.h:112
llvm::ARMBuildAttrs::ABI_FP_denormal
@ ABI_FP_denormal
Definition: ARMBuildAttributes.h:53
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:239
llvm::ARMBuildAttrs::BTIUsed
@ BTIUsed
Definition: ARMBuildAttributes.h:259
llvm::ARMBuildAttrs::ABI_VFP_args
@ ABI_VFP_args
Definition: ARMBuildAttributes.h:61
llvm::ARMAsmPrinter::PrintAsmMemoryOperand
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
Definition: ARMAsmPrinter.cpp:446
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineJumpTableInfo::getJumpTables
const std::vector< MachineJumpTableEntry > & getJumpTables() const
Definition: MachineJumpTableInfo.h:99
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:394
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:750
llvm::ARMSubtarget::isThumb1Only
bool isThumb1Only() const
Definition: ARMSubtarget.h:422
llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:220
llvm::MCAF_SubsectionsViaSymbols
@ MCAF_SubsectionsViaSymbols
.subsections_via_symbols (MachO)
Definition: MCDirectives.h:53
llvm::ARMCP::TLSGD
@ TLSGD
None.
Definition: ARMConstantPoolValue.h:48
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
llvm::ARMCP::GOT_PREL
@ GOT_PREL
Thread Local Storage (General Dynamic Mode)
Definition: ARMConstantPoolValue.h:49
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
ARMTargetObjectFile.h
llvm::ARMBuildAttrs::PreserveFPSign
@ PreserveFPSign
Definition: ARMBuildAttributes.h:195
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1133
llvm::AsmPrinter::GetBlockAddressSymbol
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
Definition: AsmPrinter.cpp:3320
llvm::ARMTargetStreamer::emitARMWinCFIEpilogEnd
virtual void emitARMWinCFIEpilogEnd()
Definition: ARMTargetStreamer.cpp:129
llvm::TargetRegisterInfo::getFrameRegister
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
llvm::ARMAsmPrinter::emitGlobalVariable
void emitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
Definition: ARMAsmPrinter.cpp:106
llvm::MachineConstantPool
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
Definition: MachineConstantPool.h:117
llvm::MCObjectFileInfo::getNonLazySymbolPointerSection
MCSection * getNonLazySymbolPointerSection() const
Definition: MCObjectFileInfo.h:411
llvm::ARMII::MO_NONLAZY
@ MO_NONLAZY
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which,...
Definition: ARMBaseInfo.h:288
llvm::PointerIntPair::getInt
IntType getInt() const
Definition: PointerIntPair.h:62
llvm::ARMSubtarget::getFramePointerReg
MCPhysReg getFramePointerReg() const
Definition: ARMSubtarget.h:432
llvm::DenormalMode
Represent subnormal handling kind for floating point instruction inputs and outputs.
Definition: FloatingPointMode.h:69
llvm::MCInstBuilder
Definition: MCInstBuilder.h:21
llvm::ARMSubtarget::isTargetELF
bool isTargetELF() const
Definition: ARMSubtarget.h:374
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:218
MachineFunctionPass.h
llvm::ARMSubtarget::isTargetCOFF
bool isTargetCOFF() const
Definition: ARMSubtarget.h:373
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:118
llvm::ARMBuildAttrs::AddressDirect
@ AddressDirect
Definition: ARMBuildAttributes.h:174
llvm::ARMSubtarget::isROPI
bool isROPI() const
Definition: ARMSubtarget.cpp:343
llvm::MachineFunction::getConstantPool
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
Definition: MachineFunction.h:688
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineConstantPoolEntry::isMachineConstantPoolEntry
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
Definition: MachineConstantPool.h:93
llvm::AsmPrinter::getSymbol
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:654
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1675
llvm::X86AS::FS
@ FS
Definition: X86.h:192
llvm::MCStreamer::emitIntValue
virtual void emitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers.
Definition: MCStreamer.cpp:134
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:610
llvm::GlobalValue::isThreadLocal
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
Definition: GlobalValue.h:249
llvm::ARMBuildAttrs::ABI_FP_number_model
@ ABI_FP_number_model
Definition: ARMBuildAttributes.h:56
llvm::AsmPrinter::getMBBExceptionSym
MCSymbol * getMBBExceptionSym(const MachineBasicBlock &MBB)
Definition: AsmPrinter.cpp:2146
llvm::AsmPrinter::MF
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:99
llvm::ARMTargetStreamer::switchVendor
virtual void switchVendor(StringRef Vendor)
Definition: ARMTargetStreamer.cpp:105
llvm::AsmPrinter::OutContext
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:91
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:644
llvm::ARMBuildAttrs::AllowIEEE754
@ AllowIEEE754
Definition: ARMBuildAttributes.h:200
llvm::ARMAsmPrinter::GetCPISymbol
MCSymbol * GetCPISymbol(unsigned CPID) const override
Return the symbol for the specified constant pool entry.
Definition: ARMAsmPrinter.cpp:252
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
ARM.h
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::MCSymbolRefExpr::VK_TPOFF
@ VK_TPOFF
Definition: MCExpr.h:212
llvm::ARMFunctionInfo::getGlobalsPromotedToConstantPool
SmallPtrSet< const GlobalVariable *, 2 > & getGlobalsPromotedToConstantPool()
Definition: ARMMachineFunctionInfo.h:272
llvm::ARMBuildAttrs::ABI_align_needed
@ ABI_align_needed
Definition: ARMBuildAttributes.h:57
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::ARMAsmPrinter::ARMAsmPrinter
ARMAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
Definition: ARMAsmPrinter.cpp:55
Mangler.h
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:525
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:849
llvm::AsmPrinter::GetExternalSymbolSymbol
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
Definition: AsmPrinter.cpp:3377
ARMAddressingModes.h
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:561
MCAsmInfo.h
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1624
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::MCInstBuilder::addImm
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::ARMBuildAttrs::ABI_optimization_goals
@ ABI_optimization_goals
Definition: ARMBuildAttributes.h:63
A
* A
Definition: README_ALTIVEC.txt:89
uint32_t
llvm::AArch64ISD::ADR
@ ADR
Definition: AArch64ISelLowering.h:64
llvm::MachineModuleInfoCOFF::getGVStubEntry
StubValueTy & getGVStubEntry(MCSymbol *Sym)
Definition: MachineModuleInfoImpls.h:95
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:55
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetMachine::getTargetFeatureString
StringRef getTargetFeatureString() const
Definition: TargetMachine.h:128
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MCInstBuilder::addExpr
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Definition: MCInstBuilder.h:55
getModifierVariantKind
static MCSymbolRefExpr::VariantKind getModifierVariantKind(ARMCP::ARMCPModifier Modifier)
Definition: ARMAsmPrinter.cpp:824
llvm::MCSA_IndirectSymbol
@ MCSA_IndirectSymbol
.indirect_symbol (MachO)
Definition: MCDirectives.h:35
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:280
llvm::MCContext::createTempSymbol
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:324
llvm::ARMBuildAttrs::PositiveZero
@ PositiveZero
Definition: ARMBuildAttributes.h:193
llvm::ARMAsmPrinter::emitFunctionEntryLabel
void emitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Definition: ARMAsmPrinter.cpp:69
llvm::Constant::stripPointerCasts
const Constant * stripPointerCasts() const
Definition: Constant.h:213
llvm::ARMBuildAttrs::ABI_PCS_RO_data
@ ABI_PCS_RO_data
Definition: ARMBuildAttributes.h:49
llvm::ARMConstantPoolValue::getLabelId
unsigned getLabelId() const
Definition: ARMConstantPoolValue.h:104
llvm::ARMSubtarget::isTargetWindows
bool isTargetWindows() const
Definition: ARMSubtarget.h:371
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:364
llvm::AsmPrinter::MMI
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
Definition: AsmPrinter.h:102
llvm::ARMBuildAttrs::AddressGOT
@ AddressGOT
Definition: ARMBuildAttributes.h:175
llvm::ARMAsmPrinter::emitInlineAsmEnd
void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const override
Let the target do anything it needs to do after emitting inlineasm.
Definition: ARMAsmPrinter.cpp:474
llvm::MCAF_Code32
@ MCAF_Code32
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:55
llvm::ARMAsmPrinter::PrintAsmOperand
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Definition: ARMAsmPrinter.cpp:272
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::DenormalMode::getPreserveSign
static constexpr DenormalMode getPreserveSign()
Definition: FloatingPointMode.h:107
llvm::ARMTargetStreamer::emitTargetAttributes
void emitTargetAttributes(const MCSubtargetInfo &STI)
Emit the build attributes that only depend on the hardware that we expect.
Definition: ARMTargetStreamer.cpp:177
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::ARMBuildAttrs::AddressRWPCRel
@ AddressRWPCRel
Definition: ARMBuildAttributes.h:165
llvm::MCAF_SyntaxUnified
@ MCAF_SyntaxUnified
.syntax (ARM/ELF)
Definition: MCDirectives.h:52
llvm::ARMTargetStreamer::emitTextAttribute
virtual void emitTextAttribute(unsigned Attribute, StringRef String)
Definition: ARMTargetStreamer.cpp:107
llvm::MachineConstantPoolEntry
This class is a data container for one entry in a MachineConstantPool.
Definition: MachineConstantPool.h:67
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
std
Definition: BitVector.h:851
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::ARMSubtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: ARMSubtarget.h:363
llvm::ARMII::MO_LO16
@ MO_LO16
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address.
Definition: ARMBaseInfo.h:250
llvm::ARMConstantPoolValue::isBlockAddress
bool isBlockAddress() const
Definition: ARMConstantPoolValue.h:109
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:277
llvm::InlineAsm::hasRegClassConstraint
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:370
uint16_t
llvm::ARMAsmPrinter::LowerPATCHABLE_TAIL_CALL
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
Definition: ARMMCInstLower.cpp:226
llvm::ARMConstantPoolValue::mustAddCurrentAddress
bool mustAddCurrentAddress() const
Definition: ARMConstantPoolValue.h:102
llvm::ARMBuildAttrs::ABI_PCS_RW_data
@ ABI_PCS_RW_data
Definition: ARMBuildAttributes.h:48
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:652
llvm::MachineConstantPool::getConstants
const std::vector< MachineConstantPoolEntry > & getConstants() const
Definition: MachineConstantPool.h:145
llvm::ARMBuildAttrs::AllowPACInNOPSpace
@ AllowPACInNOPSpace
Definition: ARMBuildAttributes.h:249
llvm::ARMTargetStreamer::emitMovSP
virtual void emitMovSP(unsigned Reg, int64_t Offset=0)
Definition: ARMTargetStreamer.cpp:98
llvm::ARMAsmPrinter::emitEndOfAsmFile
void emitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
Definition: ARMAsmPrinter.cpp:524
llvm::MCStreamer::emitSymbolAttribute
virtual bool emitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
llvm::ARMAsmPrinter::PrintSymbolOperand
void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override
Print the MachineOperand as a symbol.
Definition: ARMAsmPrinter.cpp:197
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:345
llvm::AsmPrinter::getSubtargetInfo
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
Definition: AsmPrinter.cpp:396
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:566
llvm::MachineModuleInfoMachO::GetGVStubList
SymbolListTy GetGVStubList()
Accessor methods to return the set of stubs in sorted order.
Definition: MachineModuleInfoImpls.h:55
llvm::ARMSubtarget::isTargetMachO
bool isTargetMachO() const
Definition: ARMSubtarget.h:375
checkFunctionsAttributeConsistency
static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr, StringRef Value)
Definition: ARMAsmPrinter.cpp:591
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::ARMBuildAttrs::ABI_PCS_wchar_t
@ ABI_PCS_wchar_t
Definition: ARMBuildAttributes.h:51
llvm::ARMConstantPoolValue::isPromotedGlobal
bool isPromotedGlobal() const
Definition: ARMConstantPoolValue.h:112
llvm::ARMBuildAttrs::ABI_PCS_GOT_use
@ ABI_PCS_GOT_use
Definition: ARMBuildAttributes.h:50
llvm::AsmPrinter
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:81
llvm::MCSymbolRefExpr::VK_TLSGD
@ VK_TLSGD
Definition: MCExpr.h:209
llvm::ARMTargetStreamer::emitAttribute
virtual void emitAttribute(unsigned Attribute, unsigned Value)
Definition: ARMTargetStreamer.cpp:106
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
getPICLabel
static MCSymbol * getPICLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
Definition: ARMAsmPrinter.cpp:815
llvm::ARMAsmPrinter::emitJumpTableInsts
void emitJumpTableInsts(const MachineInstr *MI)
Definition: ARMAsmPrinter.cpp:1025
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:436
llvm::ARMBuildAttrs::R9IsGPR
@ R9IsGPR
Definition: ARMBuildAttributes.h:159
ARMBuildAttributes.h
llvm::MCSA_ELF_TypeFunction
@ MCSA_ELF_TypeFunction
.type _foo, STT_FUNC # aka @function
Definition: MCDirectives.h:23
llvm::ARMCP::GOTTPOFF
@ GOTTPOFF
Global Offset Table, PC Relative.
Definition: ARMConstantPoolValue.h:50
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:777
llvm::ARMTargetStreamer::emitARMWinCFISaveFRegs
virtual void emitARMWinCFISaveFRegs(unsigned First, unsigned Last)
Definition: ARMTargetStreamer.cpp:124
llvm::TargetOptions::NoNaNsFPMath
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
Definition: TargetOptions.h:175
llvm::PointerIntPair
PointerIntPair - This class implements a pair of a pointer and small integer.
Definition: PointerIntPair.h:46
llvm::TargetMachine::getTargetCPU
StringRef getTargetCPU() const
Definition: TargetMachine.h:127
llvm::MCStreamer::getContext
MCContext & getContext() const
Definition: MCStreamer.h:293
llvm::AsmPrinter::TM
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:84
llvm::MCDR_DataRegionJT8
@ MCDR_DataRegionJT8
.data_region jt8
Definition: MCDirectives.h:61
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:355
llvm::ARMBuildAttrs::PACRETUsed
@ PACRETUsed
Definition: ARMBuildAttributes.h:263
llvm::AsmPrinter::getSymbolWithGlobalValueBase
MCSymbol * getSymbolWithGlobalValueBase(const GlobalValue *GV, StringRef Suffix) const
Return the MCSymbol for a private symbol with global value name as its base, with the specified suffi...
Definition: AsmPrinter.cpp:3371
llvm::AsmPrinter::getObjFileLowering
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:382
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
MCStreamer.h
llvm::ARMSubtarget::isTargetEHABICompatible
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:402
llvm::ARMTargetStreamer::emitARMWinCFISaveSP
virtual void emitARMWinCFISaveSP(unsigned Reg)
Definition: ARMTargetStreamer.cpp:123
llvm::AsmPrinter::emitFunctionBody
void emitFunctionBody()
This method emits the body and trailer for a function.
Definition: AsmPrinter.cpp:1413
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:126
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:662
llvm::ARMTargetStreamer::emitARMWinCFISaveLR
virtual void emitARMWinCFISaveLR(unsigned Offset)
Definition: ARMTargetStreamer.cpp:125
llvm::ARMBuildAttrs::Allowed
@ Allowed
Definition: ARMBuildAttributes.h:126
llvm::AsmPrinter::getDataLayout
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:386
llvm::ARMSubtarget::isGVIndirectSymbol
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
Definition: ARMSubtarget.cpp:352
llvm::MCInstBuilder::addReg
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
llvm::TargetOptions::UnsafeFPMath
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
Definition: TargetOptions.h:163
llvm::ARMMCExpr::createLower16
static const ARMMCExpr * createLower16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:42
llvm::ARMAsmPrinter::emitStartOfAsmFile
void emitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
Definition: ARMAsmPrinter.cpp:484
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1113
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::MachineModuleInfoMachO::getThreadLocalGVStubEntry
StubValueTy & getThreadLocalGVStubEntry(MCSymbol *Sym)
Definition: MachineModuleInfoImpls.h:49
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
llvm::ARMTargetStreamer::finishAttributeSection
virtual void finishAttributeSection()
Definition: ARMTargetStreamer.cpp:116
llvm::AsmPrinter::emitXRayTable
void emitXRayTable()
Emit a table with all XRay instrumentation points.
Definition: AsmPrinter.cpp:3679
llvm::MachineFunction::getJumpTableInfo
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
Definition: MachineFunction.h:679
llvm::getTheThumbBETarget
Target & getTheThumbBETarget()
Definition: ARMTargetInfo.cpp:25
llvm::ARMAsmPrinter::emitJumpTableTBInst
void emitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth)
Definition: ARMAsmPrinter.cpp:1053
llvm::RegisterAsmPrinter
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...
Definition: TargetRegistry.h:1381
llvm::ARMConstantPoolValue::isMachineBasicBlock
bool isMachineBasicBlock() const
Definition: ARMConstantPoolValue.h:111
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
raw_ostream.h
llvm::ARMAsmPrinter::emitJumpTableAddrs
void emitJumpTableAddrs(const MachineInstr *MI)
Definition: ARMAsmPrinter.cpp:979
ARMTargetMachine.h
llvm::COFF::IMAGE_SYM_DTYPE_FUNCTION
@ IMAGE_SYM_DTYPE_FUNCTION
A function that returns a base type.
Definition: COFF.h:260
llvm::ARMBuildAttrs::IEEEDenormals
@ IEEEDenormals
Definition: ARMBuildAttributes.h:194
llvm::MCDR_DataRegionEnd
@ MCDR_DataRegionEnd
.end_data_region
Definition: MCDirectives.h:64
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::AsmPrinter::getFunctionNumber
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:378
llvm::MachineConstantPoolEntry::ConstVal
const Constant * ConstVal
Definition: MachineConstantPool.h:71
llvm::MachineModuleInfo::getModule
const Module * getModule() const
Definition: MachineModuleInfo.h:151
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Debug.h
llvm::ARMBuildAttrs::ABI_FP_16bit_format
@ ABI_FP_16bit_format
Definition: ARMBuildAttributes.h:68
llvm::MCSymbolRefExpr::VK_SECREL
@ VK_SECREL
Definition: MCExpr.h:223
emitNonLazySymbolPointer
static void emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, MachineModuleInfoImpl::StubValueTy &MCSym)
Definition: ARMAsmPrinter.cpp:501
llvm::ARMSubtarget::isTargetGNUAEABI
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:389
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::AsmPrinter::PrintAsmOperand
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Definition: AsmPrinterInlineAsm.cpp:467
llvm::MachineModuleInfo::getObjFileInfo
Ty & getObjFileInfo()
Keep track of various per-module pieces of information for backends that would like to do so.
Definition: MachineModuleInfo.h:171
llvm::ARMCP::SBREL
@ SBREL
Section Relative (Windows TLS)
Definition: ARMConstantPoolValue.h:53
llvm::ARMBuildAttrs::HardFPAAPCS
@ HardFPAAPCS
Definition: ARMBuildAttributes.h:218
llvm::MCSymbolRefExpr::VK_GOTTPOFF
@ VK_GOTTPOFF
Definition: MCExpr.h:204
llvm::MachineModuleInfoMachO
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets.
Definition: MachineModuleInfoImpls.h:28
SetVector.h
llvm::sampleprof::Base
@ Base
Definition: Discriminator.h:58
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:338
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:57
llvm::DataLayout::getTypeAllocSize
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:506
llvm::ARMAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
Definition: ARMMCInstLower.cpp:221