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53 #define DEBUG_TYPE "asm-printer"
56 std::unique_ptr<MCStreamer> Streamer)
58 MCP(nullptr), InConstantPool(
false), OptimizationGoals(-1) {}
65 InConstantPool =
false;
91 assert(
Size &&
"C++ constructor pointer had zero size!");
94 assert(GV &&
"C++ constructor pointer was not a GlobalValue!");
107 if (PromotedGlobals.count(GV))
129 PromotedGlobals.insert(GV);
132 unsigned OptimizationGoal;
135 OptimizationGoal = 6;
136 else if (
F.hasMinSize())
138 OptimizationGoal = 4;
139 else if (
F.hasOptSize())
141 OptimizationGoal = 3;
144 OptimizationGoal = 2;
147 OptimizationGoal = 1;
150 OptimizationGoal = 5;
153 if (OptimizationGoals == -1)
154 OptimizationGoals = OptimizationGoal;
155 else if (OptimizationGoals != (
int)OptimizationGoal)
156 OptimizationGoals = 0;
159 bool Internal =
F.hasInternalLinkage();
179 if (! ThumbIndirectPads.empty()) {
182 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
190 ThumbIndirectPads.clear();
245 if (Subtarget->genExecuteOnly())
264 GetARMJTIPICJumpTableLabel(
unsigned uid)
const {
275 if (ExtraCode && ExtraCode[0]) {
276 if (ExtraCode[1] != 0)
return true;
278 switch (ExtraCode[0]) {
287 if (
MI->getOperand(OpNum).isReg()) {
293 if (!ARM::DPRRegClass.
contains(*SR))
302 if (!
MI->getOperand(OpNum).isImm())
304 O << ~(
MI->getOperand(OpNum).getImm());
307 if (!
MI->getOperand(OpNum).isImm())
309 O << (
MI->getOperand(OpNum).getImm() & 0xffff);
312 if (!
MI->getOperand(OpNum).isReg())
320 if (ARM::GPRPairRegClass.
contains(RegBegin)) {
332 unsigned RegOps = OpNum + 1;
333 while (
MI->getOperand(RegOps).isReg()) {
348 if (!FlagsOP.
isImm())
350 unsigned Flags = FlagsOP.
getImm();
358 unsigned OpFlags =
MI->getOperand(OpNum).getImm();
361 Flags =
MI->getOperand(OpNum).getImm();
377 if (ExtraCode[0] ==
'Q')
398 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
399 if (RegOp >=
MI->getNumOperands())
411 if (!
MI->getOperand(OpNum).isReg())
447 unsigned OpNum,
const char *ExtraCode,
450 if (ExtraCode && ExtraCode[0]) {
451 if (ExtraCode[1] != 0)
return true;
453 switch (ExtraCode[0]) {
455 default:
return true;
457 if (!
MI->getOperand(OpNum).isReg())
465 assert(MO.
isReg() &&
"unexpected inline asm memory operand");
478 const bool WasThumb =
isThumb(StartInfo);
479 if (!EndInfo || WasThumb !=
isThumb(*EndInfo)) {
490 if (TT.isOSBinFormatELF())
496 if (!
M.getModuleInlineAsm().empty() && TT.isThumb())
526 if (TT.isOSBinFormatMachO()) {
536 if (!Stubs.empty()) {
541 for (
auto &Stub : Stubs)
549 if (!Stubs.empty()) {
554 for (
auto &Stub : Stubs)
573 if (OptimizationGoals > 0 &&
577 OptimizationGoals = -1;
594 return F.getFnAttribute(Attr).getValueAsString() !=
Value;
603 StringRef AttrVal =
F.getFnAttribute(Attr).getValueAsString();
608 void ARMAsmPrinter::emitAttributes() {
627 ArchFS = (
Twine(ArchFS) +
"," +
FS).str();
629 ArchFS = std::string(
FS);
633 const ARMSubtarget STI(TT, std::string(CPU), ArchFS, ATM,
643 }
else if (STI.isRWPI()) {
678 if (!STI.hasVFP2Base()) {
688 }
else if (STI.hasVFP3Base()) {
705 "no-trapping-math",
"true") ||
746 if (
auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
747 SourceModule->getModuleFlag(
"wchar_size"))) {
748 int WCharWidth = WCharWidthValue->getZExtValue();
749 assert((WCharWidth == 2 || WCharWidth == 4) &&
750 "wchar_t width must be 2 or 4 bytes");
757 if (
auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
758 SourceModule->getModuleFlag(
"min_enum_size"))) {
759 int EnumWidth = EnumWidthValue->getZExtValue();
760 assert((EnumWidth == 1 || EnumWidth == 4) &&
761 "Minimum enum width must be 1 or 4 bytes");
762 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
766 auto *PACValue = mdconst::extract_or_null<ConstantInt>(
767 SourceModule->getModuleFlag(
"sign-return-address"));
768 if (PACValue && PACValue->getZExtValue() == 1) {
772 if (!STI.hasPACBTI()) {
779 auto *BTIValue = mdconst::extract_or_null<ConstantInt>(
780 SourceModule->getModuleFlag(
"branch-target-enforcement"));
781 if (BTIValue && BTIValue->getZExtValue() == 1) {
785 if (!STI.hasPACBTI()) {
797 else if (STI.isR9Reserved())
811 +
"BF" +
Twine(FunctionNumber) +
"_" +
Twine(LabelId));
819 +
"PC" +
Twine(FunctionNumber) +
"_" +
Twine(LabelId));
845 unsigned char TargetFlags) {
861 if (!StubSym.getPointer())
867 "Windows is the only supported COFF target");
889 if (!StubSym.getPointer())
917 auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
918 for (
const auto *GV : ACPC->promotedGlobals()) {
919 if (!EmittedPromotedGlobalLabels.count(GV)) {
922 EmittedPromotedGlobalLabels.insert(GV);
933 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
936 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
941 MCSym = GetARMGVSymbol(GV, TF);
947 auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
988 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
997 const std::vector<MachineBasicBlock*> &JTBBs =
JT[JTI].MBBs;
1034 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1040 const std::vector<MachineBasicBlock*> &JTBBs =
JT[JTI].MBBs;
1047 .addExpr(MBBSymbolExpr)
1054 unsigned OffsetWidth) {
1055 assert((OffsetWidth == 1 || OffsetWidth == 2) &&
"invalid tbb/tbh width");
1062 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1068 const std::vector<MachineBasicBlock*> &JTBBs =
JT[JTI].MBBs;
1074 for (
auto MBB : JTBBs) {
1106 void ARMAsmPrinter::EmitUnwindingInstruction(
const MachineInstr *
MI) {
1108 "Only instruction which are involved into frame setup code are allowed");
1118 unsigned Opc =
MI->getOpcode();
1119 unsigned SrcReg, DstReg;
1124 SrcReg = DstReg = ARM::SP;
1128 case ARM::t2MOVTi16:
1135 DstReg =
MI->getOperand(0).getReg();
1138 SrcReg =
MI->getOperand(1).getReg();
1139 DstReg =
MI->getOperand(0).getReg();
1144 if (
MI->mayStore()) {
1146 assert(DstReg == ARM::SP &&
1147 "Only stack pointer as a destination reg is supported");
1151 unsigned StartOp = 2 + 2;
1153 unsigned NumOffset = 0;
1156 unsigned PadBefore = 0;
1159 unsigned PadAfter = 0;
1167 StartOp = 2; NumOffset = 2;
1169 case ARM::STMDB_UPD:
1170 case ARM::t2STMDB_UPD:
1171 case ARM::VSTMDDB_UPD:
1172 assert(SrcReg == ARM::SP &&
1173 "Only stack pointer as a source reg is supported");
1174 for (
unsigned i = StartOp, NumOps =
MI->getNumOperands() - NumOffset;
1186 assert(RegList.empty() &&
1187 "Pad registers must come before restored ones");
1198 RegList.push_back(
Reg);
1201 case ARM::STR_PRE_IMM:
1202 case ARM::STR_PRE_REG:
1203 case ARM::t2STR_PRE:
1204 assert(
MI->getOperand(2).getReg() == ARM::SP &&
1205 "Only stack pointer as a source reg is supported");
1207 SrcReg = RemappedReg;
1209 RegList.push_back(SrcReg);
1211 case ARM::t2STRD_PRE:
1212 assert(
MI->getOperand(3).getReg() == ARM::SP &&
1213 "Only stack pointer as a source reg is supported");
1214 SrcReg =
MI->getOperand(1).getReg();
1216 SrcReg = RemappedReg;
1217 RegList.push_back(SrcReg);
1218 SrcReg =
MI->getOperand(2).getReg();
1220 SrcReg = RemappedReg;
1221 RegList.push_back(SrcReg);
1222 PadBefore = -
MI->getOperand(4).getImm() - 8;
1228 ATS.
emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1235 if (SrcReg == ARM::SP) {
1247 case ARM::t2ADDri12:
1248 case ARM::t2ADDspImm:
1249 case ARM::t2ADDspImm12:
1250 Offset = -
MI->getOperand(2).getImm();
1254 case ARM::t2SUBri12:
1255 case ARM::t2SUBspImm:
1256 case ARM::t2SUBspImm12:
1257 Offset =
MI->getOperand(2).getImm();
1260 Offset =
MI->getOperand(2).getImm()*4;
1264 Offset = -
MI->getOperand(2).getImm()*4;
1277 else if (DstReg == ARM::SP) {
1287 }
else if (DstReg == ARM::SP) {
1299 case ARM::tLDRpci: {
1302 unsigned CPI =
MI->getOperand(1).getIndex();
1306 assert(CPI != -1U &&
"Invalid constpool index");
1316 Offset =
MI->getOperand(1).getImm();
1319 case ARM::t2MOVTi16:
1320 Offset =
MI->getOperand(2).getImm();
1337 #include "ARMGenMCPseudoLowering.inc"
1345 if (InConstantPool &&
MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1347 InConstantPool =
false;
1353 EmitUnwindingInstruction(
MI);
1360 "Pseudo flag setting opcode should be expanded early");
1363 unsigned Opc =
MI->getOpcode();
1365 case ARM::t2MOVi32imm:
llvm_unreachable(
"Should be lowered by thumb2it pass");
1366 case ARM::DBG_VALUE:
llvm_unreachable(
"Should be handled by generic printing");
1368 case ARM::tLEApcrel:
1369 case ARM::t2LEApcrel: {
1373 ARM::t2LEApcrel ? ARM::t2ADR
1374 : (
MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1376 .
addReg(
MI->getOperand(0).getReg())
1379 .
addImm(
MI->getOperand(2).getImm())
1380 .
addReg(
MI->getOperand(3).getReg()));
1383 case ARM::LEApcrelJT:
1384 case ARM::tLEApcrelJT:
1385 case ARM::t2LEApcrelJT: {
1387 GetARMJTIPICJumpTableLabel(
MI->getOperand(1).getIndex());
1389 ARM::t2LEApcrelJT ? ARM::t2ADR
1390 : (
MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1392 .
addReg(
MI->getOperand(0).getReg())
1395 .
addImm(
MI->getOperand(2).getImm())
1396 .
addReg(
MI->getOperand(3).getReg()));
1401 case ARM::BX_CALL: {
1411 assert(Subtarget->hasV4TOps());
1413 .addReg(
MI->getOperand(0).getReg()));
1416 case ARM::tBX_CALL: {
1417 if (Subtarget->hasV5TOps())
1428 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
1429 if (TIP.first == TReg) {
1430 TRegSym = TIP.second;
1437 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1447 case ARM::BMOVPCRX_CALL: {
1459 .addReg(
MI->getOperand(0).getReg())
1467 case ARM::BMOVPCB_CALL: {
1479 const unsigned TF =
Op.getTargetFlags();
1480 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1489 case ARM::MOVi16_ga_pcrel:
1490 case ARM::t2MOVi16_ga_pcrel: {
1492 TmpInst.
setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1495 unsigned TF =
MI->getOperand(1).getTargetFlags();
1497 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1504 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1505 const MCExpr *PCRelExpr =
1520 case ARM::MOVTi16_ga_pcrel:
1521 case ARM::t2MOVTi16_ga_pcrel: {
1523 TmpInst.
setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1524 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1528 unsigned TF =
MI->getOperand(2).getTargetFlags();
1530 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1537 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1538 const MCExpr *PCRelExpr =
1565 if (
MI->getOperand(1).isReg()) {
1567 MCInst.addReg(
MI->getOperand(1).getReg());
1571 if (
MI->getOperand(1).isMBB())
1574 else if (
MI->getOperand(1).isGlobal()) {
1577 GetARMGVSymbol(GV,
MI->getOperand(1).getTargetFlags()),
OutContext);
1578 }
else if (
MI->getOperand(1).isSymbol()) {
1588 if (Opc == ARM::t2BFic) {
1593 MCInst.addExpr(ElseLabel);
1594 MCInst.addImm(
MI->getOperand(3).getImm());
1596 MCInst.addImm(
MI->getOperand(2).getImm())
1597 .addReg(
MI->getOperand(3).getReg());
1603 case ARM::t2BF_LabelPseudo: {
1612 case ARM::tPICADD: {
1625 .addReg(
MI->getOperand(0).getReg())
1626 .
addReg(
MI->getOperand(0).getReg())
1646 .addReg(
MI->getOperand(0).getReg())
1648 .
addReg(
MI->getOperand(1).getReg())
1650 .
addImm(
MI->getOperand(3).getImm())
1651 .
addReg(
MI->getOperand(4).getReg())
1663 case ARM::PICLDRSH: {
1677 switch (
MI->getOpcode()) {
1680 case ARM::PICSTR: Opcode = ARM::STRrs;
break;
1681 case ARM::PICSTRB: Opcode = ARM::STRBrs;
break;
1682 case ARM::PICSTRH: Opcode = ARM::STRH;
break;
1683 case ARM::PICLDR: Opcode = ARM::LDRrs;
break;
1684 case ARM::PICLDRB: Opcode = ARM::LDRBrs;
break;
1685 case ARM::PICLDRH: Opcode = ARM::LDRH;
break;
1686 case ARM::PICLDRSB: Opcode = ARM::LDRSB;
break;
1687 case ARM::PICLDRSH: Opcode = ARM::LDRSH;
break;
1690 .addReg(
MI->getOperand(0).getReg())
1692 .
addReg(
MI->getOperand(1).getReg())
1695 .
addImm(
MI->getOperand(3).getImm())
1696 .
addReg(
MI->getOperand(4).getReg()));
1700 case ARM::CONSTPOOL_ENTRY: {
1701 if (Subtarget->genExecuteOnly())
1709 unsigned LabelId = (unsigned)
MI->getOperand(0).getImm();
1710 unsigned CPIdx = (unsigned)
MI->getOperand(1).getIndex();
1713 if (!InConstantPool) {
1715 InConstantPool =
true;
1727 case ARM::JUMPTABLE_ADDRS:
1730 case ARM::JUMPTABLE_INSTS:
1733 case ARM::JUMPTABLE_TBB:
1734 case ARM::JUMPTABLE_TBH:
1737 case ARM::t2BR_JT: {
1740 .addReg(
MI->getOperand(0).getReg())
1747 case ARM::t2TBH_JT: {
1748 unsigned Opc =
MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1752 .addReg(
MI->getOperand(0).getReg())
1753 .
addReg(
MI->getOperand(1).getReg())
1760 case ARM::tTBH_JT: {
1762 bool Is8Bit =
MI->getOpcode() == ARM::tTBB_JT;
1765 assert(
MI->getOperand(1).isKill() &&
"We need the index register as scratch!");
1778 if (
Base == ARM::PC) {
1801 unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1805 .addImm(Is8Bit ? 4 : 2)
1815 unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1848 unsigned Opc =
MI->getOpcode() == ARM::BR_JTr ?
1849 ARM::MOVr : ARM::tMOVr;
1857 if (Opc == ARM::MOVr)
1862 case ARM::BR_JTm_i12: {
1875 case ARM::BR_JTm_rs: {
1889 case ARM::BR_JTadd: {
1893 .addReg(
MI->getOperand(0).getReg())
1894 .
addReg(
MI->getOperand(1).getReg())
1916 case ARM::TRAPNaCl: {
1933 case ARM::t2Int_eh_sjlj_setjmp:
1934 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1935 case ARM::tInt_eh_sjlj_setjmp: {
1944 Register SrcReg =
MI->getOperand(0).getReg();
1945 Register ValReg =
MI->getOperand(1).getReg();
1985 .addExpr(SymbolExpr)
2002 case ARM::Int_eh_sjlj_setjmp_nofp:
2003 case ARM::Int_eh_sjlj_setjmp: {
2010 Register SrcReg =
MI->getOperand(0).getReg();
2011 Register ValReg =
MI->getOperand(1).getReg();
2062 case ARM::Int_eh_sjlj_longjmp: {
2067 Register SrcReg =
MI->getOperand(0).getReg();
2068 Register ScratchReg =
MI->getOperand(1).getReg();
2116 assert(Subtarget->hasV4TOps());
2124 case ARM::tInt_eh_sjlj_longjmp: {
2130 Register SrcReg =
MI->getOperand(0).getReg();
2131 Register ScratchReg =
MI->getOperand(1).getReg();
2196 case ARM::tInt_WIN_eh_sjlj_longjmp: {
2201 Register SrcReg =
MI->getOperand(0).getReg();
2226 case ARM::PATCHABLE_FUNCTION_ENTER:
2229 case ARM::PATCHABLE_FUNCTION_EXIT:
2232 case ARM::PATCHABLE_TAIL_CALL:
2235 case ARM::SpeculationBarrierISBDSBEndBB: {
2247 case ARM::t2SpeculationBarrierISBDSBEndBB: {
2263 case ARM::SpeculationBarrierSBEndBB: {
2270 case ARM::t2SpeculationBarrierSBEndBB: {
2278 case ARM::SEH_StackAlloc:
2280 MI->getOperand(1).getImm());
2283 case ARM::SEH_SaveRegs:
2284 case ARM::SEH_SaveRegs_Ret:
2286 MI->getOperand(1).getImm());
2289 case ARM::SEH_SaveSP:
2293 case ARM::SEH_SaveFRegs:
2295 MI->getOperand(1).getImm());
2298 case ARM::SEH_SaveLR:
2303 case ARM::SEH_Nop_Ret:
2307 case ARM::SEH_PrologEnd:
2311 case ARM::SEH_EpilogStart:
2315 case ARM::SEH_EpilogEnd:
static bool checkDenormalAttributeConsistency(const Module &M, StringRef Attr, DenormalMode Value)
unsigned char getPCAdjustment() const
unsigned HonorSignDependentRoundingFPMathOption
HonorSignDependentRoundingFPMath - This returns true when the -enable-sign-dependent-rounding-fp-math...
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
bool isPositionIndependent() const
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
@ MO_Immediate
Immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMAsmPrinter()
@ MO_HI16
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address.
void printOffset(int64_t Offset, raw_ostream &OS) const
This is just convenient handler for printing offsets.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
ARMConstantPoolValue - ARM specific constantpool value.
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This uses the emitInstruction() method to print assembly for each instruction.
A parsed version of the target data layout string in and methods for querying it.
static MCOperand createExpr(const MCExpr *Val)
@ TPOFF
Global Offset Table, Thread Pointer Offset.
Target & getTheARMBETarget()
@ IMAGE_SYM_CLASS_STATIC
Static.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const GlobalValue * getGlobal() const
static MCOperand createImm(int64_t Val)
Context object for machine code objects.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
MachineConstantPoolValue * MachineCPVal
const MCAsmInfo * MAI
Target Asm Printer information.
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
return AArch64::GPR64RegClass contains(Reg)
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
void emitGlobalConstant(const DataLayout &DL, const Constant *CV)
Print a general LLVM constant to the .s file.
DenseMap< unsigned, unsigned > EHPrologueOffsetInRegs
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
MCSection * getThreadLocalPointerSection() const
@ IMAGE_SYM_CLASS_EXTERNAL
External symbol.
Reg
All possible values of the reg field in the ModR/M byte.
unsigned getOriginalCPIdx(unsigned CloneIdx) const
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
@ SCT_COMPLEX_TYPE_SHIFT
Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT))
Triple - Helper class for working with autoconf configuration names.
virtual void emitARMWinCFINop(bool Wide)
void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O)
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
std::vector< std::pair< MCSymbol *, StubValueTy > > SymbolListTy
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=ARM::NoRegAltName)
Abstract base class for all machine specific constantpool value subclasses.
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
The instances of the Type class are immutable: once they are created, they are never changed.
union llvm::MachineConstantPoolEntry::@189 Val
The constant itself.
void emitAlignment(Align Alignment, const GlobalObject *GV=nullptr, unsigned MaxBytesToEmit=0) const
Emit an alignment directive to the specified power of two boundary.
virtual void emitARMWinCFIAllocStack(unsigned Size, bool Wide)
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
Instances of this class represent a single low-level machine instruction.
bool isGlobalValue() const
int64_t getOffset() const
Return the offset from the symbol in this operand.
unsigned const TargetRegisterInfo * TRI
@ SECREL
Thread Pointer Offset.
virtual void emitPad(int64_t Offset)
static const ARMMCExpr * createUpper16(const MCExpr *Expr, MCContext &Ctx)
virtual void emitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
@ MO_Register
Register operand.
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
@ MCDR_DataRegionJT16
.data_region jt16
SymbolStorageClass
Storage class tells where and what the symbol represents.
static MCSymbol * getBFLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
void setOpcode(unsigned Op)
DenormalMode parseDenormalFPAttribute(StringRef Str)
Returns the denormal mode to use for inputs and outputs.
DenseMap< unsigned, unsigned > EHPrologueRemappedRegs
bool isCmseNSEntryFunction() const
Target & getTheARMLETarget()
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Streaming machine code generation interface.
bool isTargetMuslAEABI() const
SymbolListTy GetThreadLocalGVStubList()
void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file.
@ MCDR_DataRegion
.data_region
const MachineBasicBlock & front() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP)
virtual void emitRegSave(const SmallVectorImpl< unsigned > &RegList, bool isVector)
unsigned NoInfsFPMath
NoInfsFPMath - This flag is enabled when the -enable-no-infs-fp-math flag is specified on the command...
virtual void emitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const
This emits linkage information about GVSym based on GV, if this is supported by the target.
virtual void emitInst(uint32_t Inst, char Suffix='\0')
Target & getTheThumbLETarget()
@ MO_GlobalAddress
Address of a global value.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
virtual void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
@ MCAF_Code16
.code16 (X86) / .code 16 (ARM)
static const unsigned FramePtr
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
bool isLittleEndian() const
const FeatureBitset & getFeatureBits() const
MCSymbol * CurrentFnSym
The symbol for the current function.
This class implements an extremely fast bulk output stream that can only output to a stream.
bool isTargetAEABI() const
void emitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
Target specific streamer interface.
ARMCP::ARMCPModifier getModifier() const
bool hasInternalLinkage() const
StringRef getName() const
getName - Get the symbol name.
static bool isThumb(const MCSubtargetInfo &STI)
bool isThumbFunction() const
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
virtual void emitARMWinCFIPrologEnd(bool Fragment)
void addOperand(const MCOperand Op)
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
void emitXXStructor(const DataLayout &DL, const Constant *CV) override
Targets can override this to change how global constants that are part of a C++ static/global constru...
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
@ MCDR_DataRegionJT32
.data_region jt32
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset=0)
unsigned NoTrappingFPMath
NoTrappingFPMath - This flag is enabled when the -enable-no-trapping-fp-math is specified on the comm...
virtual void emitARMWinCFISaveRegMask(unsigned Mask, bool Wide)
PointerTy getPointer() const
virtual void emitARMWinCFIEpilogStart(unsigned Condition)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static constexpr DenormalMode getPositiveZero()
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
const std::vector< MachineJumpTableEntry > & getJumpTables() const
This is an important base class in LLVM.
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
bool isThumb1Only() const
unsigned getTargetFlags() const
@ MCAF_SubsectionsViaSymbols
.subsections_via_symbols (MachO)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
@ GOT_PREL
Thread Local Storage (General Dynamic Mode)
#define LLVM_EXTERNAL_VISIBILITY
@ TRAP
TRAP - Trapping instruction.
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
virtual void emitARMWinCFIEpilogEnd()
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
void emitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
MCSection * getNonLazySymbolPointerSection() const
@ MO_NONLAZY
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which,...
MCPhysReg getFramePointerReg() const
Represent subnormal handling kind for floating point instruction inputs and outputs.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isTargetCOFF() const
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
MCSymbol * getSymbol(const GlobalValue *GV) const
Primary interface to the complete machine description for the target machine.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
virtual void emitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers.
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
MCSymbol * getMBBExceptionSym(const MachineBasicBlock &MBB)
MachineFunction * MF
The current machine function.
virtual void switchVendor(StringRef Vendor)
MCContext & OutContext
This is the context for the output file that we are streaming.
MCSuperRegIterator enumerates all super-registers of Reg.
MCSymbol * GetCPISymbol(unsigned CPID) const override
Return the symbol for the specified constant pool entry.
Register getReg() const
getReg - Returns the register number.
A Module instance is used to store all the information related to an LLVM module.
SmallPtrSet< const GlobalVariable *, 2 > & getGlobalsPromotedToConstantPool()
ARMAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
The address of a basic block.
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
MachineBasicBlock * getMBB() const
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
StringRef - Represent a constant reference to a string, i.e.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static MCOperand createReg(unsigned Reg)
Type * getType() const
All values are typed, get the type of this value.
StubValueTy & getGVStubEntry(MCSymbol *Sym)
@ MO_MachineBasicBlock
MachineBasicBlock reference.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
StringRef getTargetFeatureString() const
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
static MCSymbolRefExpr::VariantKind getModifierVariantKind(ARMCP::ARMCPModifier Modifier)
@ MCSA_IndirectSymbol
.indirect_symbol (MachO)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
void emitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
const Constant * stripPointerCasts() const
unsigned getLabelId() const
bool isTargetWindows() const
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const override
Let the target do anything it needs to do after emitting inlineasm.
@ MCAF_Code32
.code32 (X86) / .code 32 (ARM)
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
static constexpr DenormalMode getPreserveSign()
void emitTargetAttributes(const MCSubtargetInfo &STI)
Emit the build attributes that only depend on the hardware that we expect.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
@ MCAF_SyntaxUnified
.syntax (ARM/ELF)
virtual void emitTextAttribute(unsigned Attribute, StringRef String)
This class is a data container for one entry in a MachineConstantPool.
Function & getFunction()
Return the LLVM function that this machine code represents.
bool isTargetDarwin() const
@ MO_LO16
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address.
bool isBlockAddress() const
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
bool mustAddCurrentAddress() const
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const std::vector< MachineConstantPoolEntry > & getConstants() const
virtual void emitMovSP(unsigned Reg, int64_t Offset=0)
void emitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
virtual bool emitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override
Print the MachineOperand as a symbol.
const MCSubtargetInfo & getSubtargetInfo() const
Return information about subtarget.
SymbolListTy GetGVStubList()
Accessor methods to return the set of stubs in sorted order.
bool isTargetMachO() const
static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr, StringRef Value)
bool isPromotedGlobal() const
This class is intended to be used as a driving class for all asm writers.
virtual void emitAttribute(unsigned Attribute, unsigned Value)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
static MCSymbol * getPICLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
void emitJumpTableInsts(const MachineInstr *MI)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
@ MCSA_ELF_TypeFunction
.type _foo, STT_FUNC # aka @function
@ GOTTPOFF
Global Offset Table, PC Relative.
ExceptionHandling getExceptionHandlingType() const
virtual void emitARMWinCFISaveFRegs(unsigned First, unsigned Last)
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
PointerIntPair - This class implements a pair of a pointer and small integer.
StringRef getTargetCPU() const
MCContext & getContext() const
TargetMachine & TM
Target machine description.
@ MCDR_DataRegionJT8
.data_region jt8
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
MCSymbol * getSymbolWithGlobalValueBase(const GlobalValue *GV, StringRef Suffix) const
Return the MCSymbol for a private symbol with global value name as its base, with the specified suffi...
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
bool isTargetEHABICompatible() const
virtual void emitARMWinCFISaveSP(unsigned Reg)
void emitFunctionBody()
This method emits the body and trailer for a function.
const Triple & getTargetTriple() const
A raw_ostream that writes to an SmallVector or SmallString.
virtual void emitARMWinCFISaveLR(unsigned Offset)
const DataLayout & getDataLayout() const
Return information about data layout.
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
static const ARMMCExpr * createLower16(const MCExpr *Expr, MCContext &Ctx)
void emitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
const char LLVMTargetMachineRef TM
StubValueTy & getThreadLocalGVStubEntry(MCSymbol *Sym)
virtual void finishAttributeSection()
void emitXRayTable()
Emit a table with all XRay instrumentation points.
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
Target & getTheThumbBETarget()
void emitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth)
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...
bool isMachineBasicBlock() const
void emitJumpTableAddrs(const MachineInstr *MI)
@ IMAGE_SYM_DTYPE_FUNCTION
A function that returns a base type.
@ MCDR_DataRegionEnd
.end_data_region
Generic base class for all target subtargets.
unsigned getFunctionNumber() const
Return a unique ID for the current function.
const Constant * ConstVal
const Module * getModule() const
LLVM Value Representation.
Base class for the full range of assembler expressions which are needed for parsing.
static void emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, MachineModuleInfoImpl::StubValueTy &MCSym)
bool isTargetGNUAEABI() const
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Ty & getObjFileInfo()
Keep track of various per-module pieces of information for backends that would like to do so.
@ SBREL
Section Relative (Windows TLS)
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets.
Wrapper class representing physical registers. Should be passed by value.
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)