LLVM  13.0.0git
ARMAsmPrinter.cpp
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1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format ARM assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ARMAsmPrinter.h"
15 #include "ARM.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMTargetObjectFile.h"
22 #include "MCTargetDesc/ARMMCExpr.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/BinaryFormat/COFF.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/Mangler.h"
33 #include "llvm/IR/Module.h"
34 #include "llvm/IR/Type.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCAssembler.h"
37 #include "llvm/MC/MCContext.h"
38 #include "llvm/MC/MCELFStreamer.h"
39 #include "llvm/MC/MCInst.h"
40 #include "llvm/MC/MCInstBuilder.h"
42 #include "llvm/MC/MCStreamer.h"
43 #include "llvm/MC/MCSymbol.h"
45 #include "llvm/Support/Debug.h"
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "asm-printer"
54 
56  std::unique_ptr<MCStreamer> Streamer)
57  : AsmPrinter(TM, std::move(Streamer)), Subtarget(nullptr), AFI(nullptr),
58  MCP(nullptr), InConstantPool(false), OptimizationGoals(-1) {}
59 
61  // Make sure to terminate any constant pools that were at the end
62  // of the function.
63  if (!InConstantPool)
64  return;
65  InConstantPool = false;
66  OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
67 }
68 
70  if (AFI->isThumbFunction()) {
71  OutStreamer->emitAssemblerFlag(MCAF_Code16);
72  OutStreamer->emitThumbFunc(CurrentFnSym);
73  } else {
74  OutStreamer->emitAssemblerFlag(MCAF_Code32);
75  }
76 
77  // Emit symbol for CMSE non-secure entry point
78  if (AFI->isCmseNSEntryFunction()) {
79  MCSymbol *S =
82  OutStreamer->emitSymbolAttribute(S, MCSA_ELF_TypeFunction);
83  OutStreamer->emitLabel(S);
84  }
85 
86  OutStreamer->emitLabel(CurrentFnSym);
87 }
88 
90  uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
91  assert(Size && "C++ constructor pointer had zero size!");
92 
93  const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
94  assert(GV && "C++ constructor pointer was not a GlobalValue!");
95 
96  const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
98  (Subtarget->isTargetELF()
101  OutContext);
102 
103  OutStreamer->emitValue(E, Size);
104 }
105 
107  if (PromotedGlobals.count(GV))
108  // The global was promoted into a constant pool. It should not be emitted.
109  return;
111 }
112 
113 /// runOnMachineFunction - This uses the emitInstruction()
114 /// method to print assembly for each instruction.
115 ///
117  AFI = MF.getInfo<ARMFunctionInfo>();
118  MCP = MF.getConstantPool();
119  Subtarget = &MF.getSubtarget<ARMSubtarget>();
120 
122  const Function &F = MF.getFunction();
123  const TargetMachine& TM = MF.getTarget();
124 
125  // Collect all globals that had their storage promoted to a constant pool.
126  // Functions are emitted before variables, so this accumulates promoted
127  // globals from all functions in PromotedGlobals.
128  for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
129  PromotedGlobals.insert(GV);
130 
131  // Calculate this function's optimization goal.
132  unsigned OptimizationGoal;
133  if (F.hasOptNone())
134  // For best debugging illusion, speed and small size sacrificed
135  OptimizationGoal = 6;
136  else if (F.hasMinSize())
137  // Aggressively for small size, speed and debug illusion sacrificed
138  OptimizationGoal = 4;
139  else if (F.hasOptSize())
140  // For small size, but speed and debugging illusion preserved
141  OptimizationGoal = 3;
142  else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
143  // Aggressively for speed, small size and debug illusion sacrificed
144  OptimizationGoal = 2;
145  else if (TM.getOptLevel() > CodeGenOpt::None)
146  // For speed, but small size and good debug illusion preserved
147  OptimizationGoal = 1;
148  else // TM.getOptLevel() == CodeGenOpt::None
149  // For good debugging, but speed and small size preserved
150  OptimizationGoal = 5;
151 
152  // Combine a new optimization goal with existing ones.
153  if (OptimizationGoals == -1) // uninitialized goals
154  OptimizationGoals = OptimizationGoal;
155  else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
156  OptimizationGoals = 0;
157 
158  if (Subtarget->isTargetCOFF()) {
159  bool Internal = F.hasInternalLinkage();
163 
164  OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
165  OutStreamer->EmitCOFFSymbolStorageClass(Scl);
166  OutStreamer->EmitCOFFSymbolType(Type);
167  OutStreamer->EndCOFFSymbolDef();
168  }
169 
170  // Emit the rest of the function body.
172 
173  // Emit the XRay table for this function.
174  emitXRayTable();
175 
176  // If we need V4T thumb mode Register Indirect Jump pads, emit them.
177  // These are created per function, rather than per TU, since it's
178  // relatively easy to exceed the thumb branch range within a TU.
179  if (! ThumbIndirectPads.empty()) {
180  OutStreamer->emitAssemblerFlag(MCAF_Code16);
181  emitAlignment(Align(2));
182  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
183  OutStreamer->emitLabel(TIP.second);
185  .addReg(TIP.first)
186  // Add predicate operands.
187  .addImm(ARMCC::AL)
188  .addReg(0));
189  }
190  ThumbIndirectPads.clear();
191  }
192 
193  // We didn't modify anything.
194  return false;
195 }
196 
198  raw_ostream &O) {
199  assert(MO.isGlobal() && "caller should check MO.isGlobal");
200  unsigned TF = MO.getTargetFlags();
201  if (TF & ARMII::MO_LO16)
202  O << ":lower16:";
203  else if (TF & ARMII::MO_HI16)
204  O << ":upper16:";
205  GetARMGVSymbol(MO.getGlobal(), TF)->print(O, MAI);
206  printOffset(MO.getOffset(), O);
207 }
208 
210  raw_ostream &O) {
211  const MachineOperand &MO = MI->getOperand(OpNum);
212 
213  switch (MO.getType()) {
214  default: llvm_unreachable("<unknown operand type>");
216  Register Reg = MO.getReg();
218  assert(!MO.getSubReg() && "Subregs should be eliminated!");
219  if(ARM::GPRPairRegClass.contains(Reg)) {
220  const MachineFunction &MF = *MI->getParent()->getParent();
222  Reg = TRI->getSubReg(Reg, ARM::gsub_0);
223  }
225  break;
226  }
228  O << '#';
229  unsigned TF = MO.getTargetFlags();
230  if (TF == ARMII::MO_LO16)
231  O << ":lower16:";
232  else if (TF == ARMII::MO_HI16)
233  O << ":upper16:";
234  O << MO.getImm();
235  break;
236  }
238  MO.getMBB()->getSymbol()->print(O, MAI);
239  return;
241  PrintSymbolOperand(MO, O);
242  break;
243  }
245  if (Subtarget->genExecuteOnly())
246  llvm_unreachable("execute-only should not generate constant pools");
247  GetCPISymbol(MO.getIndex())->print(O, MAI);
248  break;
249  }
250 }
251 
252 MCSymbol *ARMAsmPrinter::GetCPISymbol(unsigned CPID) const {
253  // The AsmPrinter::GetCPISymbol superclass method tries to use CPID as
254  // indexes in MachineConstantPool, which isn't in sync with indexes used here.
255  const DataLayout &DL = getDataLayout();
256  return OutContext.getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
257  "CPI" + Twine(getFunctionNumber()) + "_" +
258  Twine(CPID));
259 }
260 
261 //===--------------------------------------------------------------------===//
262 
263 MCSymbol *ARMAsmPrinter::
264 GetARMJTIPICJumpTableLabel(unsigned uid) const {
265  const DataLayout &DL = getDataLayout();
267  raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
268  << getFunctionNumber() << '_' << uid;
270 }
271 
272 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
273  const char *ExtraCode, raw_ostream &O) {
274  // Does this asm operand have a single letter operand modifier?
275  if (ExtraCode && ExtraCode[0]) {
276  if (ExtraCode[1] != 0) return true; // Unknown modifier.
277 
278  switch (ExtraCode[0]) {
279  default:
280  // See if this is a generic print operand
281  return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
282  case 'P': // Print a VFP double precision register.
283  case 'q': // Print a NEON quad precision register.
284  printOperand(MI, OpNum, O);
285  return false;
286  case 'y': // Print a VFP single precision register as indexed double.
287  if (MI->getOperand(OpNum).isReg()) {
288  MCRegister Reg = MI->getOperand(OpNum).getReg().asMCReg();
290  // Find the 'd' register that has this 's' register as a sub-register,
291  // and determine the lane number.
292  for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
293  if (!ARM::DPRRegClass.contains(*SR))
294  continue;
295  bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
296  O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
297  return false;
298  }
299  }
300  return true;
301  case 'B': // Bitwise inverse of integer or symbol without a preceding #.
302  if (!MI->getOperand(OpNum).isImm())
303  return true;
304  O << ~(MI->getOperand(OpNum).getImm());
305  return false;
306  case 'L': // The low 16 bits of an immediate constant.
307  if (!MI->getOperand(OpNum).isImm())
308  return true;
309  O << (MI->getOperand(OpNum).getImm() & 0xffff);
310  return false;
311  case 'M': { // A register range suitable for LDM/STM.
312  if (!MI->getOperand(OpNum).isReg())
313  return true;
314  const MachineOperand &MO = MI->getOperand(OpNum);
315  Register RegBegin = MO.getReg();
316  // This takes advantage of the 2 operand-ness of ldm/stm and that we've
317  // already got the operands in registers that are operands to the
318  // inline asm statement.
319  O << "{";
320  if (ARM::GPRPairRegClass.contains(RegBegin)) {
322  Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
323  O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
324  RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
325  }
326  O << ARMInstPrinter::getRegisterName(RegBegin);
327 
328  // FIXME: The register allocator not only may not have given us the
329  // registers in sequence, but may not be in ascending registers. This
330  // will require changes in the register allocator that'll need to be
331  // propagated down here if the operands change.
332  unsigned RegOps = OpNum + 1;
333  while (MI->getOperand(RegOps).isReg()) {
334  O << ", "
335  << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
336  RegOps++;
337  }
338 
339  O << "}";
340 
341  return false;
342  }
343  case 'R': // The most significant register of a pair.
344  case 'Q': { // The least significant register of a pair.
345  if (OpNum == 0)
346  return true;
347  const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
348  if (!FlagsOP.isImm())
349  return true;
350  unsigned Flags = FlagsOP.getImm();
351 
352  // This operand may not be the one that actually provides the register. If
353  // it's tied to a previous one then we should refer instead to that one
354  // for registers and their classes.
355  unsigned TiedIdx;
356  if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
357  for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
358  unsigned OpFlags = MI->getOperand(OpNum).getImm();
359  OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
360  }
361  Flags = MI->getOperand(OpNum).getImm();
362 
363  // Later code expects OpNum to be pointing at the register rather than
364  // the flags.
365  OpNum += 1;
366  }
367 
368  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
369  unsigned RC;
370  bool FirstHalf;
371  const ARMBaseTargetMachine &ATM =
372  static_cast<const ARMBaseTargetMachine &>(TM);
373 
374  // 'Q' should correspond to the low order register and 'R' to the high
375  // order register. Whether this corresponds to the upper or lower half
376  // depends on the endianess mode.
377  if (ExtraCode[0] == 'Q')
378  FirstHalf = ATM.isLittleEndian();
379  else
380  // ExtraCode[0] == 'R'.
381  FirstHalf = !ATM.isLittleEndian();
383  if (InlineAsm::hasRegClassConstraint(Flags, RC) &&
384  ARM::GPRPairRegClass.hasSubClassEq(TRI->getRegClass(RC))) {
385  if (NumVals != 1)
386  return true;
387  const MachineOperand &MO = MI->getOperand(OpNum);
388  if (!MO.isReg())
389  return true;
391  Register Reg =
392  TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1);
394  return false;
395  }
396  if (NumVals != 2)
397  return true;
398  unsigned RegOp = FirstHalf ? OpNum : OpNum + 1;
399  if (RegOp >= MI->getNumOperands())
400  return true;
401  const MachineOperand &MO = MI->getOperand(RegOp);
402  if (!MO.isReg())
403  return true;
404  Register Reg = MO.getReg();
406  return false;
407  }
408 
409  case 'e': // The low doubleword register of a NEON quad register.
410  case 'f': { // The high doubleword register of a NEON quad register.
411  if (!MI->getOperand(OpNum).isReg())
412  return true;
413  Register Reg = MI->getOperand(OpNum).getReg();
414  if (!ARM::QPRRegClass.contains(Reg))
415  return true;
417  Register SubReg =
418  TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1);
420  return false;
421  }
422 
423  // This modifier is not yet supported.
424  case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
425  return true;
426  case 'H': { // The highest-numbered register of a pair.
427  const MachineOperand &MO = MI->getOperand(OpNum);
428  if (!MO.isReg())
429  return true;
430  const MachineFunction &MF = *MI->getParent()->getParent();
432  Register Reg = MO.getReg();
433  if(!ARM::GPRPairRegClass.contains(Reg))
434  return false;
435  Reg = TRI->getSubReg(Reg, ARM::gsub_1);
437  return false;
438  }
439  }
440  }
441 
442  printOperand(MI, OpNum, O);
443  return false;
444 }
445 
447  unsigned OpNum, const char *ExtraCode,
448  raw_ostream &O) {
449  // Does this asm operand have a single letter operand modifier?
450  if (ExtraCode && ExtraCode[0]) {
451  if (ExtraCode[1] != 0) return true; // Unknown modifier.
452 
453  switch (ExtraCode[0]) {
454  case 'A': // A memory operand for a VLD1/VST1 instruction.
455  default: return true; // Unknown modifier.
456  case 'm': // The base register of a memory operand.
457  if (!MI->getOperand(OpNum).isReg())
458  return true;
459  O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
460  return false;
461  }
462  }
463 
464  const MachineOperand &MO = MI->getOperand(OpNum);
465  assert(MO.isReg() && "unexpected inline asm memory operand");
466  O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
467  return false;
468 }
469 
470 static bool isThumb(const MCSubtargetInfo& STI) {
471  return STI.getFeatureBits()[ARM::ModeThumb];
472 }
473 
475  const MCSubtargetInfo *EndInfo) const {
476  // If either end mode is unknown (EndInfo == NULL) or different than
477  // the start mode, then restore the start mode.
478  const bool WasThumb = isThumb(StartInfo);
479  if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
480  OutStreamer->emitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
481  }
482 }
483 
485  const Triple &TT = TM.getTargetTriple();
486  // Use unified assembler syntax.
487  OutStreamer->emitAssemblerFlag(MCAF_SyntaxUnified);
488 
489  // Emit ARM Build Attributes
490  if (TT.isOSBinFormatELF())
491  emitAttributes();
492 
493  // Use the triple's architecture and subarchitecture to determine
494  // if we're thumb for the purposes of the top level code16 assembler
495  // flag.
496  if (!M.getModuleInlineAsm().empty() && TT.isThumb())
497  OutStreamer->emitAssemblerFlag(MCAF_Code16);
498 }
499 
500 static void
503  // L_foo$stub:
504  OutStreamer.emitLabel(StubLabel);
505  // .indirect_symbol _foo
506  OutStreamer.emitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
507 
508  if (MCSym.getInt())
509  // External to current translation unit.
510  OutStreamer.emitIntValue(0, 4/*size*/);
511  else
512  // Internal to current translation unit.
513  //
514  // When we place the LSDA into the TEXT section, the type info
515  // pointers need to be indirect and pc-rel. We accomplish this by
516  // using NLPs; however, sometimes the types are local to the file.
517  // We need to fill in the value for the NLP in those cases.
518  OutStreamer.emitValue(
519  MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
520  4 /*size*/);
521 }
522 
523 
525  const Triple &TT = TM.getTargetTriple();
526  if (TT.isOSBinFormatMachO()) {
527  // All darwin targets use mach-o.
528  const TargetLoweringObjectFileMachO &TLOFMacho =
529  static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
530  MachineModuleInfoMachO &MMIMacho =
532 
533  // Output non-lazy-pointers for external and common global variables.
535 
536  if (!Stubs.empty()) {
537  // Switch with ".non_lazy_symbol_pointer" directive.
538  OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
539  emitAlignment(Align(4));
540 
541  for (auto &Stub : Stubs)
542  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
543 
544  Stubs.clear();
545  OutStreamer->AddBlankLine();
546  }
547 
548  Stubs = MMIMacho.GetThreadLocalGVStubList();
549  if (!Stubs.empty()) {
550  // Switch with ".non_lazy_symbol_pointer" directive.
551  OutStreamer->SwitchSection(TLOFMacho.getThreadLocalPointerSection());
552  emitAlignment(Align(4));
553 
554  for (auto &Stub : Stubs)
555  emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
556 
557  Stubs.clear();
558  OutStreamer->AddBlankLine();
559  }
560 
561  // Funny Darwin hack: This flag tells the linker that no global symbols
562  // contain code that falls through to other global symbols (e.g. the obvious
563  // implementation of multiple entry points). If this doesn't occur, the
564  // linker can safely perform dead code stripping. Since LLVM never
565  // generates code that does this, it is always safe to set.
566  OutStreamer->emitAssemblerFlag(MCAF_SubsectionsViaSymbols);
567  }
568 
569  // The last attribute to be emitted is ABI_optimization_goals
570  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
571  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
572 
573  if (OptimizationGoals > 0 &&
574  (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
575  Subtarget->isTargetMuslAEABI()))
577  OptimizationGoals = -1;
578 
580 }
581 
582 //===----------------------------------------------------------------------===//
583 // Helper routines for emitStartOfAsmFile() and emitEndOfAsmFile()
584 // FIXME:
585 // The following seem like one-off assembler flags, but they actually need
586 // to appear in the .ARM.attributes section in ELF.
587 // Instead of subclassing the MCELFStreamer, we do the work here.
588 
589  // Returns true if all functions have the same function attribute value.
590  // It also returns true when the module has no functions.
592  StringRef Value) {
593  return !any_of(M, [&](const Function &F) {
594  return F.getFnAttribute(Attr).getValueAsString() != Value;
595  });
596 }
597 // Returns true if all functions have the same denormal mode.
598 // It also returns true when the module has no functions.
600  StringRef Attr,
602  return !any_of(M, [&](const Function &F) {
603  StringRef AttrVal = F.getFnAttribute(Attr).getValueAsString();
604  return parseDenormalFPAttribute(AttrVal) != Value;
605  });
606 }
607 
608 void ARMAsmPrinter::emitAttributes() {
609  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
610  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
611 
613 
614  ATS.switchVendor("aeabi");
615 
616  // Compute ARM ELF Attributes based on the default subtarget that
617  // we'd have constructed. The existing ARM behavior isn't LTO clean
618  // anyhow.
619  // FIXME: For ifunc related functions we could iterate over and look
620  // for a feature string that doesn't match the default one.
621  const Triple &TT = TM.getTargetTriple();
622  StringRef CPU = TM.getTargetCPU();
624  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
625  if (!FS.empty()) {
626  if (!ArchFS.empty())
627  ArchFS = (Twine(ArchFS) + "," + FS).str();
628  else
629  ArchFS = std::string(FS);
630  }
631  const ARMBaseTargetMachine &ATM =
632  static_cast<const ARMBaseTargetMachine &>(TM);
633  const ARMSubtarget STI(TT, std::string(CPU), ArchFS, ATM,
634  ATM.isLittleEndian());
635 
636  // Emit build attributes for the available hardware.
637  ATS.emitTargetAttributes(STI);
638 
639  // RW data addressing.
640  if (isPositionIndependent()) {
643  } else if (STI.isRWPI()) {
644  // RWPI specific attributes.
647  }
648 
649  // RO data addressing.
650  if (isPositionIndependent() || STI.isROPI()) {
653  }
654 
655  // GOT use.
656  if (isPositionIndependent()) {
659  } else {
662  }
663 
664  // Set FP Denormals.
665  if (checkDenormalAttributeConsistency(*MMI->getModule(), "denormal-fp-math",
670  "denormal-fp-math",
674  else if (!TM.Options.UnsafeFPMath)
677  else {
678  if (!STI.hasVFP2Base()) {
679  // When the target doesn't have an FPU (by design or
680  // intention), the assumptions made on the software support
681  // mirror that of the equivalent hardware support *if it
682  // existed*. For v7 and better we indicate that denormals are
683  // flushed preserving sign, and for V6 we indicate that
684  // denormals are flushed to positive zero.
685  if (STI.hasV7Ops())
688  } else if (STI.hasVFP3Base()) {
689  // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
690  // the sign bit of the zero matches the sign bit of the input or
691  // result that is being flushed to zero.
694  }
695  // For VFPv2 implementations it is implementation defined as
696  // to whether denormals are flushed to positive zero or to
697  // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
698  // LLVM has chosen to flush this to positive zero (most likely for
699  // GCC compatibility), so that's the chosen value here (the
700  // absence of its emission implies zero).
701  }
702 
703  // Set FP exceptions and rounding
705  "no-trapping-math", "true") ||
709  else if (!TM.Options.UnsafeFPMath) {
711 
712  // If the user has permitted this code to choose the IEEE 754
713  // rounding at run-time, emit the rounding attribute.
716  }
717 
718  // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
719  // equivalent of GCC's -ffinite-math-only flag.
723  else
726 
727  // FIXME: add more flags to ARMBuildAttributes.h
728  // 8-bytes alignment stuff.
731 
732  // Hard float. Use both S and D registers and conform to AAPCS-VFP.
733  if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
735 
736  // FIXME: To support emitting this build attribute as GCC does, the
737  // -mfp16-format option and associated plumbing must be
738  // supported. For now the __fp16 type is exposed by default, so this
739  // attribute should be emitted with value 1.
742 
743  if (MMI) {
744  if (const Module *SourceModule = MMI->getModule()) {
745  // ABI_PCS_wchar_t to indicate wchar_t width
746  // FIXME: There is no way to emit value 0 (wchar_t prohibited).
747  if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
748  SourceModule->getModuleFlag("wchar_size"))) {
749  int WCharWidth = WCharWidthValue->getZExtValue();
750  assert((WCharWidth == 2 || WCharWidth == 4) &&
751  "wchar_t width must be 2 or 4 bytes");
753  }
754 
755  // ABI_enum_size to indicate enum width
756  // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
757  // (all enums contain a value needing 32 bits to encode).
758  if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
759  SourceModule->getModuleFlag("min_enum_size"))) {
760  int EnumWidth = EnumWidthValue->getZExtValue();
761  assert((EnumWidth == 1 || EnumWidth == 4) &&
762  "Minimum enum width must be 1 or 4 bytes");
763  int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
764  ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
765  }
766  }
767  }
768 
769  // We currently do not support using R9 as the TLS pointer.
770  if (STI.isRWPI())
773  else if (STI.isR9Reserved())
776  else
779 }
780 
781 //===----------------------------------------------------------------------===//
782 
783 static MCSymbol *getBFLabel(StringRef Prefix, unsigned FunctionNumber,
784  unsigned LabelId, MCContext &Ctx) {
785 
786  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
787  + "BF" + Twine(FunctionNumber) + "_" + Twine(LabelId));
788  return Label;
789 }
790 
791 static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
792  unsigned LabelId, MCContext &Ctx) {
793 
794  MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
795  + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
796  return Label;
797 }
798 
801  switch (Modifier) {
802  case ARMCP::no_modifier:
804  case ARMCP::TLSGD:
806  case ARMCP::TPOFF:
808  case ARMCP::GOTTPOFF:
810  case ARMCP::SBREL:
812  case ARMCP::GOT_PREL:
814  case ARMCP::SECREL:
816  }
817  llvm_unreachable("Invalid ARMCPModifier!");
818 }
819 
820 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
821  unsigned char TargetFlags) {
822  if (Subtarget->isTargetMachO()) {
823  bool IsIndirect =
824  (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
825 
826  if (!IsIndirect)
827  return getSymbol(GV);
828 
829  // FIXME: Remove this when Darwin transition to @GOT like syntax.
830  MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
831  MachineModuleInfoMachO &MMIMachO =
834  GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
835  : MMIMachO.getGVStubEntry(MCSym);
836 
837  if (!StubSym.getPointer())
839  !GV->hasInternalLinkage());
840  return MCSym;
841  } else if (Subtarget->isTargetCOFF()) {
842  assert(Subtarget->isTargetWindows() &&
843  "Windows is the only supported COFF target");
844 
845  bool IsIndirect =
846  (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB));
847  if (!IsIndirect)
848  return getSymbol(GV);
849 
851  if (TargetFlags & ARMII::MO_DLLIMPORT)
852  Name = "__imp_";
853  else if (TargetFlags & ARMII::MO_COFFSTUB)
854  Name = ".refptr.";
855  getNameWithPrefix(Name, GV);
856 
858 
859  if (TargetFlags & ARMII::MO_COFFSTUB) {
860  MachineModuleInfoCOFF &MMICOFF =
863  MMICOFF.getGVStubEntry(MCSym);
864 
865  if (!StubSym.getPointer())
866  StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV), true);
867  }
868 
869  return MCSym;
870  } else if (Subtarget->isTargetELF()) {
871  return getSymbol(GV);
872  }
873  llvm_unreachable("unexpected target");
874 }
875 
877  MachineConstantPoolValue *MCPV) {
878  const DataLayout &DL = getDataLayout();
879  int Size = DL.getTypeAllocSize(MCPV->getType());
880 
881  ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
882 
883  if (ACPV->isPromotedGlobal()) {
884  // This constant pool entry is actually a global whose storage has been
885  // promoted into the constant pool. This global may be referenced still
886  // by debug information, and due to the way AsmPrinter is set up, the debug
887  // info is immutable by the time we decide to promote globals to constant
888  // pools. Because of this, we need to ensure we emit a symbol for the global
889  // with private linkage (the default) so debug info can refer to it.
890  //
891  // However, if this global is promoted into several functions we must ensure
892  // we don't try and emit duplicate symbols!
893  auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
894  for (const auto *GV : ACPC->promotedGlobals()) {
895  if (!EmittedPromotedGlobalLabels.count(GV)) {
896  MCSymbol *GVSym = getSymbol(GV);
897  OutStreamer->emitLabel(GVSym);
898  EmittedPromotedGlobalLabels.insert(GV);
899  }
900  }
901  return emitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
902  }
903 
904  MCSymbol *MCSym;
905  if (ACPV->isLSDA()) {
906  MCSym = getMBBExceptionSym(MF->front());
907  } else if (ACPV->isBlockAddress()) {
908  const BlockAddress *BA =
909  cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
910  MCSym = GetBlockAddressSymbol(BA);
911  } else if (ACPV->isGlobalValue()) {
912  const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
913 
914  // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
915  // flag the global as MO_NONLAZY.
916  unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
917  MCSym = GetARMGVSymbol(GV, TF);
918  } else if (ACPV->isMachineBasicBlock()) {
919  const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
920  MCSym = MBB->getSymbol();
921  } else {
922  assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
923  auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
924  MCSym = GetExternalSymbolSymbol(Sym);
925  }
926 
927  // Create an MCSymbol for the reference.
928  const MCExpr *Expr =
930  OutContext);
931 
932  if (ACPV->getPCAdjustment()) {
933  MCSymbol *PCLabel =
934  getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
935  ACPV->getLabelId(), OutContext);
936  const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
937  PCRelExpr =
938  MCBinaryExpr::createAdd(PCRelExpr,
940  OutContext),
941  OutContext);
942  if (ACPV->mustAddCurrentAddress()) {
943  // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
944  // label, so just emit a local label end reference that instead.
946  OutStreamer->emitLabel(DotSym);
947  const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
948  PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
949  }
950  Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
951  }
952  OutStreamer->emitValue(Expr, Size);
953 }
954 
956  const MachineOperand &MO1 = MI->getOperand(1);
957  unsigned JTI = MO1.getIndex();
958 
959  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
960  // ARM mode tables.
961  emitAlignment(Align(4));
962 
963  // Emit a label for the jump table.
964  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
965  OutStreamer->emitLabel(JTISymbol);
966 
967  // Mark the jump table as data-in-code.
968  OutStreamer->emitDataRegion(MCDR_DataRegionJT32);
969 
970  // Emit each entry of the table.
971  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
972  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
973  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
974 
975  for (MachineBasicBlock *MBB : JTBBs) {
976  // Construct an MCExpr for the entry. We want a value of the form:
977  // (BasicBlockAddr - TableBeginAddr)
978  //
979  // For example, a table with entries jumping to basic blocks BB0 and BB1
980  // would look like:
981  // LJTI_0_0:
982  // .word (LBB0 - LJTI_0_0)
983  // .word (LBB1 - LJTI_0_0)
985 
986  if (isPositionIndependent() || Subtarget->isROPI())
987  Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
988  OutContext),
989  OutContext);
990  // If we're generating a table of Thumb addresses in static relocation
991  // model, we need to add one to keep interworking correctly.
992  else if (AFI->isThumbFunction())
994  OutContext);
995  OutStreamer->emitValue(Expr, 4);
996  }
997  // Mark the end of jump table data-in-code region.
998  OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
999 }
1000 
1002  const MachineOperand &MO1 = MI->getOperand(1);
1003  unsigned JTI = MO1.getIndex();
1004 
1005  // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
1006  // ARM mode tables.
1007  emitAlignment(Align(4));
1008 
1009  // Emit a label for the jump table.
1010  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1011  OutStreamer->emitLabel(JTISymbol);
1012 
1013  // Emit each entry of the table.
1014  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1015  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1016  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1017 
1018  for (MachineBasicBlock *MBB : JTBBs) {
1019  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1020  OutContext);
1021  // If this isn't a TBB or TBH, the entries are direct branch instructions.
1023  .addExpr(MBBSymbolExpr)
1024  .addImm(ARMCC::AL)
1025  .addReg(0));
1026  }
1027 }
1028 
1030  unsigned OffsetWidth) {
1031  assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1032  const MachineOperand &MO1 = MI->getOperand(1);
1033  unsigned JTI = MO1.getIndex();
1034 
1035  if (Subtarget->isThumb1Only())
1036  emitAlignment(Align(4));
1037 
1038  MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1039  OutStreamer->emitLabel(JTISymbol);
1040 
1041  // Emit each entry of the table.
1042  const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1043  const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1044  const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1045 
1046  // Mark the jump table as data-in-code.
1047  OutStreamer->emitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1049 
1050  for (auto MBB : JTBBs) {
1051  const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1052  OutContext);
1053  // Otherwise it's an offset from the dispatch instruction. Construct an
1054  // MCExpr for the entry. We want a value of the form:
1055  // (BasicBlockAddr - TBBInstAddr + 4) / 2
1056  //
1057  // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1058  // would look like:
1059  // LJTI_0_0:
1060  // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1061  // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1062  // where LCPI0_0 is a label defined just before the TBB instruction using
1063  // this table.
1064  MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1065  const MCExpr *Expr = MCBinaryExpr::createAdd(
1068  Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1070  OutContext);
1071  OutStreamer->emitValue(Expr, OffsetWidth);
1072  }
1073  // Mark the end of jump table data-in-code region. 32-bit offsets use
1074  // actual branch instructions here, so we don't mark those as a data-region
1075  // at all.
1076  OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1077 
1078  // Make sure the next instruction is 2-byte aligned.
1079  emitAlignment(Align(2));
1080 }
1081 
1082 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1083  assert(MI->getFlag(MachineInstr::FrameSetup) &&
1084  "Only instruction which are involved into frame setup code are allowed");
1085 
1086  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1087  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1088  const MachineFunction &MF = *MI->getParent()->getParent();
1089  const TargetRegisterInfo *TargetRegInfo =
1091  const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
1092 
1093  Register FramePtr = TargetRegInfo->getFrameRegister(MF);
1094  unsigned Opc = MI->getOpcode();
1095  unsigned SrcReg, DstReg;
1096 
1097  switch (Opc) {
1098  case ARM::tPUSH:
1099  // special case: tPUSH does not have src/dst regs.
1100  SrcReg = DstReg = ARM::SP;
1101  break;
1102  case ARM::tLDRpci:
1103  case ARM::t2MOVi16:
1104  case ARM::t2MOVTi16:
1105  // special cases:
1106  // 1) for Thumb1 code we sometimes materialize the constant via constpool
1107  // load.
1108  // 2) for Thumb2 execute only code we materialize the constant via
1109  // immediate constants in 2 separate instructions (MOVW/MOVT).
1110  SrcReg = ~0U;
1111  DstReg = MI->getOperand(0).getReg();
1112  break;
1113  default:
1114  SrcReg = MI->getOperand(1).getReg();
1115  DstReg = MI->getOperand(0).getReg();
1116  break;
1117  }
1118 
1119  // Try to figure out the unwinding opcode out of src / dst regs.
1120  if (MI->mayStore()) {
1121  // Register saves.
1122  assert(DstReg == ARM::SP &&
1123  "Only stack pointer as a destination reg is supported");
1124 
1125  SmallVector<unsigned, 4> RegList;
1126  // Skip src & dst reg, and pred ops.
1127  unsigned StartOp = 2 + 2;
1128  // Use all the operands.
1129  unsigned NumOffset = 0;
1130  // Amount of SP adjustment folded into a push.
1131  unsigned Pad = 0;
1132 
1133  switch (Opc) {
1134  default:
1135  MI->print(errs());
1136  llvm_unreachable("Unsupported opcode for unwinding information");
1137  case ARM::tPUSH:
1138  // Special case here: no src & dst reg, but two extra imp ops.
1139  StartOp = 2; NumOffset = 2;
1141  case ARM::STMDB_UPD:
1142  case ARM::t2STMDB_UPD:
1143  case ARM::VSTMDDB_UPD:
1144  assert(SrcReg == ARM::SP &&
1145  "Only stack pointer as a source reg is supported");
1146  for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1147  i != NumOps; ++i) {
1148  const MachineOperand &MO = MI->getOperand(i);
1149  // Actually, there should never be any impdef stuff here. Skip it
1150  // temporary to workaround PR11902.
1151  if (MO.isImplicit())
1152  continue;
1153  // Registers, pushed as a part of folding an SP update into the
1154  // push instruction are marked as undef and should not be
1155  // restored when unwinding, because the function can modify the
1156  // corresponding stack slots.
1157  if (MO.isUndef()) {
1158  assert(RegList.empty() &&
1159  "Pad registers must come before restored ones");
1160  unsigned Width =
1161  TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
1162  Pad += Width;
1163  continue;
1164  }
1165  // Check for registers that are remapped (for a Thumb1 prologue that
1166  // saves high registers).
1167  Register Reg = MO.getReg();
1168  if (unsigned RemappedReg = AFI->EHPrologueRemappedRegs.lookup(Reg))
1169  Reg = RemappedReg;
1170  RegList.push_back(Reg);
1171  }
1172  break;
1173  case ARM::STR_PRE_IMM:
1174  case ARM::STR_PRE_REG:
1175  case ARM::t2STR_PRE:
1176  assert(MI->getOperand(2).getReg() == ARM::SP &&
1177  "Only stack pointer as a source reg is supported");
1178  RegList.push_back(SrcReg);
1179  break;
1180  }
1182  ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1183  // Account for the SP adjustment, folded into the push.
1184  if (Pad)
1185  ATS.emitPad(Pad);
1186  }
1187  } else {
1188  // Changes of stack / frame pointer.
1189  if (SrcReg == ARM::SP) {
1190  int64_t Offset = 0;
1191  switch (Opc) {
1192  default:
1193  MI->print(errs());
1194  llvm_unreachable("Unsupported opcode for unwinding information");
1195  case ARM::MOVr:
1196  case ARM::tMOVr:
1197  Offset = 0;
1198  break;
1199  case ARM::ADDri:
1200  case ARM::t2ADDri:
1201  case ARM::t2ADDri12:
1202  case ARM::t2ADDspImm:
1203  case ARM::t2ADDspImm12:
1204  Offset = -MI->getOperand(2).getImm();
1205  break;
1206  case ARM::SUBri:
1207  case ARM::t2SUBri:
1208  case ARM::t2SUBri12:
1209  case ARM::t2SUBspImm:
1210  case ARM::t2SUBspImm12:
1211  Offset = MI->getOperand(2).getImm();
1212  break;
1213  case ARM::tSUBspi:
1214  Offset = MI->getOperand(2).getImm()*4;
1215  break;
1216  case ARM::tADDspi:
1217  case ARM::tADDrSPi:
1218  Offset = -MI->getOperand(2).getImm()*4;
1219  break;
1220  case ARM::tADDhirr:
1221  Offset =
1222  -AFI->EHPrologueOffsetInRegs.lookup(MI->getOperand(2).getReg());
1223  break;
1224  }
1225 
1227  if (DstReg == FramePtr && FramePtr != ARM::SP)
1228  // Set-up of the frame pointer. Positive values correspond to "add"
1229  // instruction.
1230  ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1231  else if (DstReg == ARM::SP) {
1232  // Change of SP by an offset. Positive values correspond to "sub"
1233  // instruction.
1234  ATS.emitPad(Offset);
1235  } else {
1236  // Move of SP to a register. Positive values correspond to an "add"
1237  // instruction.
1238  ATS.emitMovSP(DstReg, -Offset);
1239  }
1240  }
1241  } else if (DstReg == ARM::SP) {
1242  MI->print(errs());
1243  llvm_unreachable("Unsupported opcode for unwinding information");
1244  } else {
1245  int64_t Offset = 0;
1246  switch (Opc) {
1247  case ARM::tMOVr:
1248  // If a Thumb1 function spills r8-r11, we copy the values to low
1249  // registers before pushing them. Record the copy so we can emit the
1250  // correct ".save" later.
1251  AFI->EHPrologueRemappedRegs[DstReg] = SrcReg;
1252  break;
1253  case ARM::tLDRpci: {
1254  // Grab the constpool index and check, whether it corresponds to
1255  // original or cloned constpool entry.
1256  unsigned CPI = MI->getOperand(1).getIndex();
1257  const MachineConstantPool *MCP = MF.getConstantPool();
1258  if (CPI >= MCP->getConstants().size())
1259  CPI = AFI->getOriginalCPIdx(CPI);
1260  assert(CPI != -1U && "Invalid constpool index");
1261 
1262  // Derive the actual offset.
1263  const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1264  assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1265  Offset = cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1266  AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1267  break;
1268  }
1269  case ARM::t2MOVi16:
1270  Offset = MI->getOperand(1).getImm();
1271  AFI->EHPrologueOffsetInRegs[DstReg] = Offset;
1272  break;
1273  case ARM::t2MOVTi16:
1274  Offset = MI->getOperand(2).getImm();
1275  AFI->EHPrologueOffsetInRegs[DstReg] |= (Offset << 16);
1276  break;
1277  default:
1278  MI->print(errs());
1279  llvm_unreachable("Unsupported opcode for unwinding information");
1280  }
1281  }
1282  }
1283 }
1284 
1285 // Simple pseudo-instructions have their lowering (with expansion to real
1286 // instructions) auto-generated.
1287 #include "ARMGenMCPseudoLowering.inc"
1288 
1290  const DataLayout &DL = getDataLayout();
1291  MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1292  ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1293 
1294  const MachineFunction &MF = *MI->getParent()->getParent();
1295  const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
1296  unsigned FramePtr = STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
1297 
1298  // If we just ended a constant pool, mark it as such.
1299  if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1300  OutStreamer->emitDataRegion(MCDR_DataRegionEnd);
1301  InConstantPool = false;
1302  }
1303 
1304  // Emit unwinding stuff for frame-related instructions
1305  if (Subtarget->isTargetEHABICompatible() &&
1306  MI->getFlag(MachineInstr::FrameSetup))
1307  EmitUnwindingInstruction(MI);
1308 
1309  // Do any auto-generated pseudo lowerings.
1310  if (emitPseudoExpansionLowering(*OutStreamer, MI))
1311  return;
1312 
1313  assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1314  "Pseudo flag setting opcode should be expanded early");
1315 
1316  // Check for manual lowerings.
1317  unsigned Opc = MI->getOpcode();
1318  switch (Opc) {
1319  case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1320  case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1321  case ARM::LEApcrel:
1322  case ARM::tLEApcrel:
1323  case ARM::t2LEApcrel: {
1324  // FIXME: Need to also handle globals and externals
1325  MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1326  EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1327  ARM::t2LEApcrel ? ARM::t2ADR
1328  : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1329  : ARM::ADR))
1330  .addReg(MI->getOperand(0).getReg())
1332  // Add predicate operands.
1333  .addImm(MI->getOperand(2).getImm())
1334  .addReg(MI->getOperand(3).getReg()));
1335  return;
1336  }
1337  case ARM::LEApcrelJT:
1338  case ARM::tLEApcrelJT:
1339  case ARM::t2LEApcrelJT: {
1340  MCSymbol *JTIPICSymbol =
1341  GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1342  EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1343  ARM::t2LEApcrelJT ? ARM::t2ADR
1344  : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1345  : ARM::ADR))
1346  .addReg(MI->getOperand(0).getReg())
1347  .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1348  // Add predicate operands.
1349  .addImm(MI->getOperand(2).getImm())
1350  .addReg(MI->getOperand(3).getReg()));
1351  return;
1352  }
1353  // Darwin call instructions are just normal call instructions with different
1354  // clobber semantics (they clobber R9).
1355  case ARM::BX_CALL: {
1357  .addReg(ARM::LR)
1358  .addReg(ARM::PC)
1359  // Add predicate operands.
1360  .addImm(ARMCC::AL)
1361  .addReg(0)
1362  // Add 's' bit operand (always reg0 for this)
1363  .addReg(0));
1364 
1365  assert(Subtarget->hasV4TOps());
1367  .addReg(MI->getOperand(0).getReg()));
1368  return;
1369  }
1370  case ARM::tBX_CALL: {
1371  if (Subtarget->hasV5TOps())
1372  llvm_unreachable("Expected BLX to be selected for v5t+");
1373 
1374  // On ARM v4t, when doing a call from thumb mode, we need to ensure
1375  // that the saved lr has its LSB set correctly (the arch doesn't
1376  // have blx).
1377  // So here we generate a bl to a small jump pad that does bx rN.
1378  // The jump pads are emitted after the function body.
1379 
1380  Register TReg = MI->getOperand(0).getReg();
1381  MCSymbol *TRegSym = nullptr;
1382  for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
1383  if (TIP.first == TReg) {
1384  TRegSym = TIP.second;
1385  break;
1386  }
1387  }
1388 
1389  if (!TRegSym) {
1390  TRegSym = OutContext.createTempSymbol();
1391  ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1392  }
1393 
1394  // Create a link-saving branch to the Reg Indirect Jump Pad.
1396  // Predicate comes first here.
1397  .addImm(ARMCC::AL).addReg(0)
1398  .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1399  return;
1400  }
1401  case ARM::BMOVPCRX_CALL: {
1403  .addReg(ARM::LR)
1404  .addReg(ARM::PC)
1405  // Add predicate operands.
1406  .addImm(ARMCC::AL)
1407  .addReg(0)
1408  // Add 's' bit operand (always reg0 for this)
1409  .addReg(0));
1410 
1412  .addReg(ARM::PC)
1413  .addReg(MI->getOperand(0).getReg())
1414  // Add predicate operands.
1415  .addImm(ARMCC::AL)
1416  .addReg(0)
1417  // Add 's' bit operand (always reg0 for this)
1418  .addReg(0));
1419  return;
1420  }
1421  case ARM::BMOVPCB_CALL: {
1423  .addReg(ARM::LR)
1424  .addReg(ARM::PC)
1425  // Add predicate operands.
1426  .addImm(ARMCC::AL)
1427  .addReg(0)
1428  // Add 's' bit operand (always reg0 for this)
1429  .addReg(0));
1430 
1431  const MachineOperand &Op = MI->getOperand(0);
1432  const GlobalValue *GV = Op.getGlobal();
1433  const unsigned TF = Op.getTargetFlags();
1434  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1435  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1437  .addExpr(GVSymExpr)
1438  // Add predicate operands.
1439  .addImm(ARMCC::AL)
1440  .addReg(0));
1441  return;
1442  }
1443  case ARM::MOVi16_ga_pcrel:
1444  case ARM::t2MOVi16_ga_pcrel: {
1445  MCInst TmpInst;
1446  TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1447  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1448 
1449  unsigned TF = MI->getOperand(1).getTargetFlags();
1450  const GlobalValue *GV = MI->getOperand(1).getGlobal();
1451  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1452  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1453 
1454  MCSymbol *LabelSym =
1455  getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1456  MI->getOperand(2).getImm(), OutContext);
1457  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1458  unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1459  const MCExpr *PCRelExpr =
1461  MCBinaryExpr::createAdd(LabelSymExpr,
1464  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1465 
1466  // Add predicate operands.
1468  TmpInst.addOperand(MCOperand::createReg(0));
1469  // Add 's' bit operand (always reg0 for this)
1470  TmpInst.addOperand(MCOperand::createReg(0));
1471  EmitToStreamer(*OutStreamer, TmpInst);
1472  return;
1473  }
1474  case ARM::MOVTi16_ga_pcrel:
1475  case ARM::t2MOVTi16_ga_pcrel: {
1476  MCInst TmpInst;
1477  TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1478  ? ARM::MOVTi16 : ARM::t2MOVTi16);
1479  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1480  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1481 
1482  unsigned TF = MI->getOperand(2).getTargetFlags();
1483  const GlobalValue *GV = MI->getOperand(2).getGlobal();
1484  MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1485  const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1486 
1487  MCSymbol *LabelSym =
1488  getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1489  MI->getOperand(3).getImm(), OutContext);
1490  const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1491  unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1492  const MCExpr *PCRelExpr =
1494  MCBinaryExpr::createAdd(LabelSymExpr,
1497  TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1498  // Add predicate operands.
1500  TmpInst.addOperand(MCOperand::createReg(0));
1501  // Add 's' bit operand (always reg0 for this)
1502  TmpInst.addOperand(MCOperand::createReg(0));
1503  EmitToStreamer(*OutStreamer, TmpInst);
1504  return;
1505  }
1506  case ARM::t2BFi:
1507  case ARM::t2BFic:
1508  case ARM::t2BFLi:
1509  case ARM::t2BFr:
1510  case ARM::t2BFLr: {
1511  // This is a Branch Future instruction.
1512 
1513  const MCExpr *BranchLabel = MCSymbolRefExpr::create(
1514  getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1515  MI->getOperand(0).getIndex(), OutContext),
1516  OutContext);
1517 
1518  auto MCInst = MCInstBuilder(Opc).addExpr(BranchLabel);
1519  if (MI->getOperand(1).isReg()) {
1520  // For BFr/BFLr
1521  MCInst.addReg(MI->getOperand(1).getReg());
1522  } else {
1523  // For BFi/BFLi/BFic
1524  const MCExpr *BranchTarget;
1525  if (MI->getOperand(1).isMBB())
1527  MI->getOperand(1).getMBB()->getSymbol(), OutContext);
1528  else if (MI->getOperand(1).isGlobal()) {
1529  const GlobalValue *GV = MI->getOperand(1).getGlobal();
1531  GetARMGVSymbol(GV, MI->getOperand(1).getTargetFlags()), OutContext);
1532  } else if (MI->getOperand(1).isSymbol()) {
1534  GetExternalSymbolSymbol(MI->getOperand(1).getSymbolName()),
1535  OutContext);
1536  } else
1537  llvm_unreachable("Unhandled operand kind in Branch Future instruction");
1538 
1539  MCInst.addExpr(BranchTarget);
1540  }
1541 
1542  if (Opc == ARM::t2BFic) {
1543  const MCExpr *ElseLabel = MCSymbolRefExpr::create(
1544  getBFLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1545  MI->getOperand(2).getIndex(), OutContext),
1546  OutContext);
1547  MCInst.addExpr(ElseLabel);
1548  MCInst.addImm(MI->getOperand(3).getImm());
1549  } else {
1550  MCInst.addImm(MI->getOperand(2).getImm())
1551  .addReg(MI->getOperand(3).getReg());
1552  }
1553 
1555  return;
1556  }
1557  case ARM::t2BF_LabelPseudo: {
1558  // This is a pseudo op for a label used by a branch future instruction
1559 
1560  // Emit the label.
1561  OutStreamer->emitLabel(getBFLabel(DL.getPrivateGlobalPrefix(),
1563  MI->getOperand(0).getIndex(), OutContext));
1564  return;
1565  }
1566  case ARM::tPICADD: {
1567  // This is a pseudo op for a label + instruction sequence, which looks like:
1568  // LPC0:
1569  // add r0, pc
1570  // This adds the address of LPC0 to r0.
1571 
1572  // Emit the label.
1573  OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1575  MI->getOperand(2).getImm(), OutContext));
1576 
1577  // Form and emit the add.
1578  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1579  .addReg(MI->getOperand(0).getReg())
1580  .addReg(MI->getOperand(0).getReg())
1581  .addReg(ARM::PC)
1582  // Add predicate operands.
1583  .addImm(ARMCC::AL)
1584  .addReg(0));
1585  return;
1586  }
1587  case ARM::PICADD: {
1588  // This is a pseudo op for a label + instruction sequence, which looks like:
1589  // LPC0:
1590  // add r0, pc, r0
1591  // This adds the address of LPC0 to r0.
1592 
1593  // Emit the label.
1594  OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1596  MI->getOperand(2).getImm(), OutContext));
1597 
1598  // Form and emit the add.
1600  .addReg(MI->getOperand(0).getReg())
1601  .addReg(ARM::PC)
1602  .addReg(MI->getOperand(1).getReg())
1603  // Add predicate operands.
1604  .addImm(MI->getOperand(3).getImm())
1605  .addReg(MI->getOperand(4).getReg())
1606  // Add 's' bit operand (always reg0 for this)
1607  .addReg(0));
1608  return;
1609  }
1610  case ARM::PICSTR:
1611  case ARM::PICSTRB:
1612  case ARM::PICSTRH:
1613  case ARM::PICLDR:
1614  case ARM::PICLDRB:
1615  case ARM::PICLDRH:
1616  case ARM::PICLDRSB:
1617  case ARM::PICLDRSH: {
1618  // This is a pseudo op for a label + instruction sequence, which looks like:
1619  // LPC0:
1620  // OP r0, [pc, r0]
1621  // The LCP0 label is referenced by a constant pool entry in order to get
1622  // a PC-relative address at the ldr instruction.
1623 
1624  // Emit the label.
1625  OutStreamer->emitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1627  MI->getOperand(2).getImm(), OutContext));
1628 
1629  // Form and emit the load
1630  unsigned Opcode;
1631  switch (MI->getOpcode()) {
1632  default:
1633  llvm_unreachable("Unexpected opcode!");
1634  case ARM::PICSTR: Opcode = ARM::STRrs; break;
1635  case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1636  case ARM::PICSTRH: Opcode = ARM::STRH; break;
1637  case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1638  case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1639  case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1640  case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1641  case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1642  }
1644  .addReg(MI->getOperand(0).getReg())
1645  .addReg(ARM::PC)
1646  .addReg(MI->getOperand(1).getReg())
1647  .addImm(0)
1648  // Add predicate operands.
1649  .addImm(MI->getOperand(3).getImm())
1650  .addReg(MI->getOperand(4).getReg()));
1651 
1652  return;
1653  }
1654  case ARM::CONSTPOOL_ENTRY: {
1655  if (Subtarget->genExecuteOnly())
1656  llvm_unreachable("execute-only should not generate constant pools");
1657 
1658  /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1659  /// in the function. The first operand is the ID# for this instruction, the
1660  /// second is the index into the MachineConstantPool that this is, the third
1661  /// is the size in bytes of this constant pool entry.
1662  /// The required alignment is specified on the basic block holding this MI.
1663  unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1664  unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1665 
1666  // If this is the first entry of the pool, mark it.
1667  if (!InConstantPool) {
1668  OutStreamer->emitDataRegion(MCDR_DataRegion);
1669  InConstantPool = true;
1670  }
1671 
1672  OutStreamer->emitLabel(GetCPISymbol(LabelId));
1673 
1674  const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1675  if (MCPE.isMachineConstantPoolEntry())
1677  else
1679  return;
1680  }
1681  case ARM::JUMPTABLE_ADDRS:
1683  return;
1684  case ARM::JUMPTABLE_INSTS:
1686  return;
1687  case ARM::JUMPTABLE_TBB:
1688  case ARM::JUMPTABLE_TBH:
1689  emitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1690  return;
1691  case ARM::t2BR_JT: {
1693  .addReg(ARM::PC)
1694  .addReg(MI->getOperand(0).getReg())
1695  // Add predicate operands.
1696  .addImm(ARMCC::AL)
1697  .addReg(0));
1698  return;
1699  }
1700  case ARM::t2TBB_JT:
1701  case ARM::t2TBH_JT: {
1702  unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1703  // Lower and emit the PC label, then the instruction itself.
1704  OutStreamer->emitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1706  .addReg(MI->getOperand(0).getReg())
1707  .addReg(MI->getOperand(1).getReg())
1708  // Add predicate operands.
1709  .addImm(ARMCC::AL)
1710  .addReg(0));
1711  return;
1712  }
1713  case ARM::tTBB_JT:
1714  case ARM::tTBH_JT: {
1715 
1716  bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1717  Register Base = MI->getOperand(0).getReg();
1718  Register Idx = MI->getOperand(1).getReg();
1719  assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1720 
1721  // Multiply up idx if necessary.
1722  if (!Is8Bit)
1724  .addReg(Idx)
1725  .addReg(ARM::CPSR)
1726  .addReg(Idx)
1727  .addImm(1)
1728  // Add predicate operands.
1729  .addImm(ARMCC::AL)
1730  .addReg(0));
1731 
1732  if (Base == ARM::PC) {
1733  // TBB [base, idx] =
1734  // ADDS idx, idx, base
1735  // LDRB idx, [idx, #4] ; or LDRH if TBH
1736  // LSLS idx, #1
1737  // ADDS pc, pc, idx
1738 
1739  // When using PC as the base, it's important that there is no padding
1740  // between the last ADDS and the start of the jump table. The jump table
1741  // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1742  //
1743  // FIXME: Ideally we could vary the LDRB index based on the padding
1744  // between the sequence and jump table, however that relies on MCExprs
1745  // for load indexes which are currently not supported.
1746  OutStreamer->emitCodeAlignment(4);
1747  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1748  .addReg(Idx)
1749  .addReg(Idx)
1750  .addReg(Base)
1751  // Add predicate operands.
1752  .addImm(ARMCC::AL)
1753  .addReg(0));
1754 
1755  unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1757  .addReg(Idx)
1758  .addReg(Idx)
1759  .addImm(Is8Bit ? 4 : 2)
1760  // Add predicate operands.
1761  .addImm(ARMCC::AL)
1762  .addReg(0));
1763  } else {
1764  // TBB [base, idx] =
1765  // LDRB idx, [base, idx] ; or LDRH if TBH
1766  // LSLS idx, #1
1767  // ADDS pc, pc, idx
1768 
1769  unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1771  .addReg(Idx)
1772  .addReg(Base)
1773  .addReg(Idx)
1774  // Add predicate operands.
1775  .addImm(ARMCC::AL)
1776  .addReg(0));
1777  }
1778 
1780  .addReg(Idx)
1781  .addReg(ARM::CPSR)
1782  .addReg(Idx)
1783  .addImm(1)
1784  // Add predicate operands.
1785  .addImm(ARMCC::AL)
1786  .addReg(0));
1787 
1788  OutStreamer->emitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1789  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1790  .addReg(ARM::PC)
1791  .addReg(ARM::PC)
1792  .addReg(Idx)
1793  // Add predicate operands.
1794  .addImm(ARMCC::AL)
1795  .addReg(0));
1796  return;
1797  }
1798  case ARM::tBR_JTr:
1799  case ARM::BR_JTr: {
1800  // mov pc, target
1801  MCInst TmpInst;
1802  unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1803  ARM::MOVr : ARM::tMOVr;
1804  TmpInst.setOpcode(Opc);
1805  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1806  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1807  // Add predicate operands.
1809  TmpInst.addOperand(MCOperand::createReg(0));
1810  // Add 's' bit operand (always reg0 for this)
1811  if (Opc == ARM::MOVr)
1812  TmpInst.addOperand(MCOperand::createReg(0));
1813  EmitToStreamer(*OutStreamer, TmpInst);
1814  return;
1815  }
1816  case ARM::BR_JTm_i12: {
1817  // ldr pc, target
1818  MCInst TmpInst;
1819  TmpInst.setOpcode(ARM::LDRi12);
1820  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1821  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1822  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1823  // Add predicate operands.
1825  TmpInst.addOperand(MCOperand::createReg(0));
1826  EmitToStreamer(*OutStreamer, TmpInst);
1827  return;
1828  }
1829  case ARM::BR_JTm_rs: {
1830  // ldr pc, target
1831  MCInst TmpInst;
1832  TmpInst.setOpcode(ARM::LDRrs);
1833  TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1834  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1835  TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1836  TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1837  // Add predicate operands.
1839  TmpInst.addOperand(MCOperand::createReg(0));
1840  EmitToStreamer(*OutStreamer, TmpInst);
1841  return;
1842  }
1843  case ARM::BR_JTadd: {
1844  // add pc, target, idx
1846  .addReg(ARM::PC)
1847  .addReg(MI->getOperand(0).getReg())
1848  .addReg(MI->getOperand(1).getReg())
1849  // Add predicate operands.
1850  .addImm(ARMCC::AL)
1851  .addReg(0)
1852  // Add 's' bit operand (always reg0 for this)
1853  .addReg(0));
1854  return;
1855  }
1856  case ARM::SPACE:
1857  OutStreamer->emitZeros(MI->getOperand(1).getImm());
1858  return;
1859  case ARM::TRAP: {
1860  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1861  // FIXME: Remove this special case when they do.
1862  if (!Subtarget->isTargetMachO()) {
1863  uint32_t Val = 0xe7ffdefeUL;
1864  OutStreamer->AddComment("trap");
1865  ATS.emitInst(Val);
1866  return;
1867  }
1868  break;
1869  }
1870  case ARM::TRAPNaCl: {
1871  uint32_t Val = 0xe7fedef0UL;
1872  OutStreamer->AddComment("trap");
1873  ATS.emitInst(Val);
1874  return;
1875  }
1876  case ARM::tTRAP: {
1877  // Non-Darwin binutils don't yet support the "trap" mnemonic.
1878  // FIXME: Remove this special case when they do.
1879  if (!Subtarget->isTargetMachO()) {
1880  uint16_t Val = 0xdefe;
1881  OutStreamer->AddComment("trap");
1882  ATS.emitInst(Val, 'n');
1883  return;
1884  }
1885  break;
1886  }
1887  case ARM::t2Int_eh_sjlj_setjmp:
1888  case ARM::t2Int_eh_sjlj_setjmp_nofp:
1889  case ARM::tInt_eh_sjlj_setjmp: {
1890  // Two incoming args: GPR:$src, GPR:$val
1891  // mov $val, pc
1892  // adds $val, #7
1893  // str $val, [$src, #4]
1894  // movs r0, #0
1895  // b LSJLJEH
1896  // movs r0, #1
1897  // LSJLJEH:
1898  Register SrcReg = MI->getOperand(0).getReg();
1899  Register ValReg = MI->getOperand(1).getReg();
1900  MCSymbol *Label = OutContext.createTempSymbol("SJLJEH");
1901  OutStreamer->AddComment("eh_setjmp begin");
1903  .addReg(ValReg)
1904  .addReg(ARM::PC)
1905  // Predicate.
1906  .addImm(ARMCC::AL)
1907  .addReg(0));
1908 
1910  .addReg(ValReg)
1911  // 's' bit operand
1912  .addReg(ARM::CPSR)
1913  .addReg(ValReg)
1914  .addImm(7)
1915  // Predicate.
1916  .addImm(ARMCC::AL)
1917  .addReg(0));
1918 
1920  .addReg(ValReg)
1921  .addReg(SrcReg)
1922  // The offset immediate is #4. The operand value is scaled by 4 for the
1923  // tSTR instruction.
1924  .addImm(1)
1925  // Predicate.
1926  .addImm(ARMCC::AL)
1927  .addReg(0));
1928 
1930  .addReg(ARM::R0)
1931  .addReg(ARM::CPSR)
1932  .addImm(0)
1933  // Predicate.
1934  .addImm(ARMCC::AL)
1935  .addReg(0));
1936 
1937  const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1939  .addExpr(SymbolExpr)
1940  .addImm(ARMCC::AL)
1941  .addReg(0));
1942 
1943  OutStreamer->AddComment("eh_setjmp end");
1945  .addReg(ARM::R0)
1946  .addReg(ARM::CPSR)
1947  .addImm(1)
1948  // Predicate.
1949  .addImm(ARMCC::AL)
1950  .addReg(0));
1951 
1952  OutStreamer->emitLabel(Label);
1953  return;
1954  }
1955 
1956  case ARM::Int_eh_sjlj_setjmp_nofp:
1957  case ARM::Int_eh_sjlj_setjmp: {
1958  // Two incoming args: GPR:$src, GPR:$val
1959  // add $val, pc, #8
1960  // str $val, [$src, #+4]
1961  // mov r0, #0
1962  // add pc, pc, #0
1963  // mov r0, #1
1964  Register SrcReg = MI->getOperand(0).getReg();
1965  Register ValReg = MI->getOperand(1).getReg();
1966 
1967  OutStreamer->AddComment("eh_setjmp begin");
1969  .addReg(ValReg)
1970  .addReg(ARM::PC)
1971  .addImm(8)
1972  // Predicate.
1973  .addImm(ARMCC::AL)
1974  .addReg(0)
1975  // 's' bit operand (always reg0 for this).
1976  .addReg(0));
1977 
1979  .addReg(ValReg)
1980  .addReg(SrcReg)
1981  .addImm(4)
1982  // Predicate.
1983  .addImm(ARMCC::AL)
1984  .addReg(0));
1985 
1987  .addReg(ARM::R0)
1988  .addImm(0)
1989  // Predicate.
1990  .addImm(ARMCC::AL)
1991  .addReg(0)
1992  // 's' bit operand (always reg0 for this).
1993  .addReg(0));
1994 
1996  .addReg(ARM::PC)
1997  .addReg(ARM::PC)
1998  .addImm(0)
1999  // Predicate.
2000  .addImm(ARMCC::AL)
2001  .addReg(0)
2002  // 's' bit operand (always reg0 for this).
2003  .addReg(0));
2004 
2005  OutStreamer->AddComment("eh_setjmp end");
2007  .addReg(ARM::R0)
2008  .addImm(1)
2009  // Predicate.
2010  .addImm(ARMCC::AL)
2011  .addReg(0)
2012  // 's' bit operand (always reg0 for this).
2013  .addReg(0));
2014  return;
2015  }
2016  case ARM::Int_eh_sjlj_longjmp: {
2017  // ldr sp, [$src, #8]
2018  // ldr $scratch, [$src, #4]
2019  // ldr r7, [$src]
2020  // bx $scratch
2021  Register SrcReg = MI->getOperand(0).getReg();
2022  Register ScratchReg = MI->getOperand(1).getReg();
2024  .addReg(ARM::SP)
2025  .addReg(SrcReg)
2026  .addImm(8)
2027  // Predicate.
2028  .addImm(ARMCC::AL)
2029  .addReg(0));
2030 
2032  .addReg(ScratchReg)
2033  .addReg(SrcReg)
2034  .addImm(4)
2035  // Predicate.
2036  .addImm(ARMCC::AL)
2037  .addReg(0));
2038 
2039  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2040  // These platforms always use the same frame register
2042  .addReg(FramePtr)
2043  .addReg(SrcReg)
2044  .addImm(0)
2045  // Predicate.
2046  .addImm(ARMCC::AL)
2047  .addReg(0));
2048  } else {
2049  // If the calling code might use either R7 or R11 as
2050  // frame pointer register, restore it into both.
2052  .addReg(ARM::R7)
2053  .addReg(SrcReg)
2054  .addImm(0)
2055  // Predicate.
2056  .addImm(ARMCC::AL)
2057  .addReg(0));
2059  .addReg(ARM::R11)
2060  .addReg(SrcReg)
2061  .addImm(0)
2062  // Predicate.
2063  .addImm(ARMCC::AL)
2064  .addReg(0));
2065  }
2066 
2067  assert(Subtarget->hasV4TOps());
2069  .addReg(ScratchReg)
2070  // Predicate.
2071  .addImm(ARMCC::AL)
2072  .addReg(0));
2073  return;
2074  }
2075  case ARM::tInt_eh_sjlj_longjmp: {
2076  // ldr $scratch, [$src, #8]
2077  // mov sp, $scratch
2078  // ldr $scratch, [$src, #4]
2079  // ldr r7, [$src]
2080  // bx $scratch
2081  Register SrcReg = MI->getOperand(0).getReg();
2082  Register ScratchReg = MI->getOperand(1).getReg();
2083 
2085  .addReg(ScratchReg)
2086  .addReg(SrcReg)
2087  // The offset immediate is #8. The operand value is scaled by 4 for the
2088  // tLDR instruction.
2089  .addImm(2)
2090  // Predicate.
2091  .addImm(ARMCC::AL)
2092  .addReg(0));
2093 
2095  .addReg(ARM::SP)
2096  .addReg(ScratchReg)
2097  // Predicate.
2098  .addImm(ARMCC::AL)
2099  .addReg(0));
2100 
2102  .addReg(ScratchReg)
2103  .addReg(SrcReg)
2104  .addImm(1)
2105  // Predicate.
2106  .addImm(ARMCC::AL)
2107  .addReg(0));
2108 
2109  if (STI.isTargetDarwin() || STI.isTargetWindows()) {
2110  // These platforms always use the same frame register
2112  .addReg(FramePtr)
2113  .addReg(SrcReg)
2114  .addImm(0)
2115  // Predicate.
2116  .addImm(ARMCC::AL)
2117  .addReg(0));
2118  } else {
2119  // If the calling code might use either R7 or R11 as
2120  // frame pointer register, restore it into both.
2122  .addReg(ARM::R7)
2123  .addReg(SrcReg)
2124  .addImm(0)
2125  // Predicate.
2126  .addImm(ARMCC::AL)
2127  .addReg(0));
2129  .addReg(ARM::R11)
2130  .addReg(SrcReg)
2131  .addImm(0)
2132  // Predicate.
2133  .addImm(ARMCC::AL)
2134  .addReg(0));
2135  }
2136 
2138  .addReg(ScratchReg)
2139  // Predicate.
2140  .addImm(ARMCC::AL)
2141  .addReg(0));
2142  return;
2143  }
2144  case ARM::tInt_WIN_eh_sjlj_longjmp: {
2145  // ldr.w r11, [$src, #0]
2146  // ldr.w sp, [$src, #8]
2147  // ldr.w pc, [$src, #4]
2148 
2149  Register SrcReg = MI->getOperand(0).getReg();
2150 
2151  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2152  .addReg(ARM::R11)
2153  .addReg(SrcReg)
2154  .addImm(0)
2155  // Predicate
2156  .addImm(ARMCC::AL)
2157  .addReg(0));
2158  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2159  .addReg(ARM::SP)
2160  .addReg(SrcReg)
2161  .addImm(8)
2162  // Predicate
2163  .addImm(ARMCC::AL)
2164  .addReg(0));
2165  EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2166  .addReg(ARM::PC)
2167  .addReg(SrcReg)
2168  .addImm(4)
2169  // Predicate
2170  .addImm(ARMCC::AL)
2171  .addReg(0));
2172  return;
2173  }
2174  case ARM::PATCHABLE_FUNCTION_ENTER:
2176  return;
2177  case ARM::PATCHABLE_FUNCTION_EXIT:
2179  return;
2180  case ARM::PATCHABLE_TAIL_CALL:
2182  return;
2183  case ARM::SpeculationBarrierISBDSBEndBB: {
2184  // Print DSB SYS + ISB
2185  MCInst TmpInstDSB;
2186  TmpInstDSB.setOpcode(ARM::DSB);
2187  TmpInstDSB.addOperand(MCOperand::createImm(0xf));
2188  EmitToStreamer(*OutStreamer, TmpInstDSB);
2189  MCInst TmpInstISB;
2190  TmpInstISB.setOpcode(ARM::ISB);
2191  TmpInstISB.addOperand(MCOperand::createImm(0xf));
2192  EmitToStreamer(*OutStreamer, TmpInstISB);
2193  return;
2194  }
2195  case ARM::t2SpeculationBarrierISBDSBEndBB: {
2196  // Print DSB SYS + ISB
2197  MCInst TmpInstDSB;
2198  TmpInstDSB.setOpcode(ARM::t2DSB);
2199  TmpInstDSB.addOperand(MCOperand::createImm(0xf));
2201  TmpInstDSB.addOperand(MCOperand::createReg(0));
2202  EmitToStreamer(*OutStreamer, TmpInstDSB);
2203  MCInst TmpInstISB;
2204  TmpInstISB.setOpcode(ARM::t2ISB);
2205  TmpInstISB.addOperand(MCOperand::createImm(0xf));
2207  TmpInstISB.addOperand(MCOperand::createReg(0));
2208  EmitToStreamer(*OutStreamer, TmpInstISB);
2209  return;
2210  }
2211  case ARM::SpeculationBarrierSBEndBB: {
2212  // Print SB
2213  MCInst TmpInstSB;
2214  TmpInstSB.setOpcode(ARM::SB);
2215  EmitToStreamer(*OutStreamer, TmpInstSB);
2216  return;
2217  }
2218  case ARM::t2SpeculationBarrierSBEndBB: {
2219  // Print SB
2220  MCInst TmpInstSB;
2221  TmpInstSB.setOpcode(ARM::t2SB);
2222  EmitToStreamer(*OutStreamer, TmpInstSB);
2223  return;
2224  }
2225  }
2226 
2227  MCInst TmpInst;
2228  LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2229 
2230  EmitToStreamer(*OutStreamer, TmpInst);
2231 }
2232 
2233 //===----------------------------------------------------------------------===//
2234 // Target Registry Stuff
2235 //===----------------------------------------------------------------------===//
2236 
2237 // Force static initialization.
2243 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
i
i
Definition: README.txt:29
llvm::ARMCP::ARMCPModifier
ARMCPModifier
Definition: ARMConstantPoolValue.h:46
checkDenormalAttributeConsistency
static bool checkDenormalAttributeConsistency(const Module &M, StringRef Attr, DenormalMode Value)
Definition: ARMAsmPrinter.cpp:599
llvm::ARMConstantPoolValue::getPCAdjustment
unsigned char getPCAdjustment() const
Definition: ARMConstantPoolValue.h:105
llvm::TargetOptions::HonorSignDependentRoundingFPMathOption
unsigned HonorSignDependentRoundingFPMathOption
HonorSignDependentRoundingFPMath - This returns true when the -enable-sign-dependent-rounding-fp-math...
Definition: TargetOptions.h:197
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:198
llvm::AsmPrinter::isPositionIndependent
bool isPositionIndependent() const
Definition: AsmPrinter.cpp:213
MachineModuleInfoImpls.h
llvm::ARMFunctionInfo
ARMFunctionInfo - This class is derived from MachineFunctionInfo and contains private ARM-specific in...
Definition: ARMMachineFunctionInfo.h:27
llvm::MCBinaryExpr::createDiv
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:531
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
llvm::ARMSubtarget::hasV5TOps
bool hasV5TOps() const
Definition: ARMSubtarget.h:597
llvm
Definition: AllocatorList.h:23
llvm::ARMBuildAttrs::ABI_PCS_R9_use
@ ABI_PCS_R9_use
Definition: ARMBuildAttributes.h:47
LLVMInitializeARMAsmPrinter
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMAsmPrinter()
Definition: ARMAsmPrinter.cpp:2238
llvm::ARMII::MO_HI16
@ MO_HI16
MO_HI16 - On a symbol operand, this represents a relocation containing higher 16 bit of the address.
Definition: ARMBaseInfo.h:250
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::AsmPrinter::printOffset
void printOffset(int64_t Offset, raw_ostream &OS) const
This is just convenient handler for printing offsets.
Definition: AsmPrinter.cpp:3009
llvm::MCSymbol
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::ARMConstantPoolValue
ARMConstantPoolValue - ARM specific constantpool value.
Definition: ARMConstantPoolValue.h:61
ARMTargetInfo.h
llvm::SystemZISD::TM
@ TM
Definition: SystemZISelLowering.h:65
llvm::ARM_MC::ParseARMTriple
std::string ParseARMTriple(const Triple &TT, StringRef CPU)
Definition: ARMMCTargetDesc.cpp:153
llvm::ARMBuildAttrs::R9IsGPR
@ R9IsGPR
Definition: ARMBuildAttributes.h:154
llvm::ARMAsmPrinter::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This uses the emitInstruction() method to print assembly for each instruction.
Definition: ARMAsmPrinter.cpp:116
llvm::ARM::PredBlockMask::TT
@ TT
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:112
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:161
llvm::ARMBuildAttrs::Allowed
@ Allowed
Definition: ARMBuildAttributes.h:121
llvm::ARMCP::TPOFF
@ TPOFF
Global Offset Table, Thread Pointer Offset.
Definition: ARMConstantPoolValue.h:51
llvm::MCSymbolRefExpr::VK_ARM_GOT_PREL
@ VK_ARM_GOT_PREL
Definition: MCExpr.h:230
llvm::getTheARMBETarget
Target & getTheARMBETarget()
Definition: ARMTargetInfo.cpp:17
llvm::COFF::IMAGE_SYM_CLASS_STATIC
@ IMAGE_SYM_CLASS_STATIC
Static.
Definition: COFF.h:210
llvm::cl::Prefix
@ Prefix
Definition: CommandLine.h:161
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
llvm::ARMBuildAttrs::ABI_align_preserved
@ ABI_align_preserved
Definition: ARMBuildAttributes.h:58
llvm::ARMBuildAttrs::ABI_enum_size
@ ABI_enum_size
Definition: ARMBuildAttributes.h:59
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition: MachineOperand.h:560
llvm::HexagonISD::JT
@ JT
Definition: HexagonISelLowering.h:52
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:140
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:71
llvm::Function
Definition: Function.h:61
ARMInstPrinter.h
llvm::DenseMapBase::lookup
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:197
llvm::ARMTargetStreamer
Definition: MCStreamer.h:131
llvm::MachineConstantPoolEntry::MachineCPVal
MachineConstantPoolValue * MachineCPVal
Definition: MachineConstantPool.h:72
llvm::AsmPrinter::MAI
const MCAsmInfo * MAI
Target Asm Printer information.
Definition: AsmPrinter.h:88
llvm::MCConstantExpr::create
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::convertAddSubFlagsOpcode
unsigned convertAddSubFlagsOpcode(unsigned OldOpc)
Map pseudo instructions that imply an 'S' bit onto real opcodes.
Definition: ARMBaseInstrInfo.cpp:2445
llvm::MCSymbolRefExpr::VK_ARM_TARGET1
@ VK_ARM_TARGET1
Definition: MCExpr.h:231
llvm::AsmPrinter::emitGlobalConstant
void emitGlobalConstant(const DataLayout &DL, const Constant *CV)
Print a general LLVM constant to the .s file.
Definition: AsmPrinter.cpp:2993
llvm::SmallVector< unsigned, 4 >
llvm::ARMFunctionInfo::EHPrologueOffsetInRegs
DenseMap< unsigned, unsigned > EHPrologueOffsetInRegs
Definition: ARMMachineFunctionInfo.h:258
llvm::ARMII::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: ARMBaseInfo.h:259
llvm::MCObjectFileInfo::getThreadLocalPointerSection
MCSection * getThreadLocalPointerSection() const
Definition: MCObjectFileInfo.h:400
llvm::MCSymbolRefExpr::VK_ARM_SBREL
@ VK_ARM_SBREL
Definition: MCExpr.h:234
llvm::COFF::IMAGE_SYM_CLASS_EXTERNAL
@ IMAGE_SYM_CLASS_EXTERNAL
External symbol.
Definition: COFF.h:209
ErrorHandling.h
llvm::GlobalVariable
Definition: GlobalVariable.h:40
ARMMachineFunctionInfo.h
llvm::ARMFunctionInfo::getOriginalCPIdx
unsigned getOriginalCPIdx(unsigned CloneIdx) const
Definition: ARMMachineFunctionInfo.h:224
llvm::AsmPrinter::getNameWithPrefix
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
Definition: AsmPrinter.cpp:467
MCInstBuilder.h
llvm::COFF::SCT_COMPLEX_TYPE_SHIFT
@ SCT_COMPLEX_TYPE_SHIFT
Type is formed as (base + (derived << SCT_COMPLEX_TYPE_SHIFT))
Definition: COFF.h:265
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
MCAssembler.h
llvm::ARMAsmPrinter::printOperand
void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O)
Definition: ARMAsmPrinter.cpp:209
COFF.h
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::ARMBuildAttrs::AddressRWPCRel
@ AddressRWPCRel
Definition: ARMBuildAttributes.h:160
llvm::MachineModuleInfoImpl::SymbolListTy
std::vector< std::pair< MCSymbol *, StubValueTy > > SymbolListTy
Definition: MachineModuleInfo.h:63
llvm::MCStreamer::emitValue
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:176
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::ARMInstPrinter::getRegisterName
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=ARM::NoRegAltName)
llvm::MachineConstantPoolValue
Abstract base class for all machine specific constantpool value subclasses.
Definition: MachineConstantPool.h:35
llvm::ARMConstantPoolValue::isLSDA
bool isLSDA() const
Definition: ARMConstantPoolValue.h:110
llvm::ARMII::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
Definition: ARMBaseInfo.h:271
MachineJumpTableInfo.h
llvm::InlineAsm::isUseOperandTiedToDef
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
Definition: InlineAsm.h:343
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
Module.h
llvm::ARMAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER
void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
Definition: ARMMCInstLower.cpp:216
llvm::ExceptionHandling::ARM
@ ARM
ARM EHABI.
llvm::ARMCP::no_modifier
@ no_modifier
Definition: ARMConstantPoolValue.h:47
llvm::FloatABI::Hard
@ Hard
Definition: TargetOptions.h:31
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
ARMMCExpr.h
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:892
llvm::MachineModuleInfoMachO::getGVStubEntry
StubValueTy & getGVStubEntry(MCSymbol *Sym)
Definition: MachineModuleInfoImpls.h:43
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:183
TargetParser.h
llvm::ARMBuildAttrs::Not_Allowed
@ Not_Allowed
Definition: ARMBuildAttributes.h:120
llvm::ARMConstantPoolValue::isGlobalValue
bool isGlobalValue() const
Definition: ARMConstantPoolValue.h:107
llvm::ARMSubtarget::useR7AsFramePointer
bool useR7AsFramePointer() const
Definition: ARMSubtarget.h:814
llvm::ARMBuildAttrs::AddressRWSBRel
@ AddressRWSBRel
Definition: ARMBuildAttributes.h:161
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition: MachineOperand.h:597
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::ARMCP::SECREL
@ SECREL
Thread Pointer Offset.
Definition: ARMConstantPoolValue.h:52
llvm::TargetLoweringObjectFileMachO
Definition: TargetLoweringObjectFileImpl.h:114
llvm::ARMTargetStreamer::emitPad
virtual void emitPad(int64_t Offset)
Definition: ARMTargetStreamer.cpp:97
llvm::ARMMCExpr::createUpper16
static const ARMMCExpr * createUpper16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:38
MCELFStreamer.h
llvm::AsmPrinter::emitGlobalVariable
virtual void emitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
Definition: AsmPrinter.cpp:494
llvm::MachineOperand::MO_Register
@ MO_Register
Register operand.
Definition: MachineOperand.h:52
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AsmPrinter::EmitToStreamer
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
Definition: AsmPrinter.cpp:241
llvm::MCDR_DataRegionJT16
@ MCDR_DataRegionJT16
.data_region jt16
Definition: MCDirectives.h:61
llvm::COFF::SymbolStorageClass
SymbolStorageClass
Storage class tells where and what the symbol represents.
Definition: COFF.h:203
getBFLabel
static MCSymbol * getBFLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
Definition: ARMAsmPrinter.cpp:783
llvm::ARMBuildAttrs::conformance
@ conformance
Definition: ARMBuildAttributes.h:74
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:196
llvm::MachineConstantPoolValue::getType
Type * getType() const
Definition: MachineConstantPool.h:44
llvm::parseDenormalFPAttribute
DenormalMode parseDenormalFPAttribute(StringRef Str)
Returns the denormal mode to use for inputs and outputs.
Definition: FloatingPointMode.h:174
llvm::ARMFunctionInfo::EHPrologueRemappedRegs
DenseMap< unsigned, unsigned > EHPrologueRemappedRegs
Definition: ARMMachineFunctionInfo.h:257
llvm::ARMConstantPoolValue::isExtSymbol
bool isExtSymbol() const
Definition: ARMConstantPoolValue.h:108
llvm::ARMFunctionInfo::isCmseNSEntryFunction
bool isCmseNSEntryFunction() const
Definition: ARMMachineFunctionInfo.h:148
llvm::getTheARMLETarget
Target & getTheARMLETarget()
Definition: ARMTargetInfo.cpp:13
MCObjectStreamer.h
llvm::MachineBasicBlock::getSymbol
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
Definition: MachineBasicBlock.cpp:59
llvm::ARMBuildAttrs::ABI_FP_exceptions
@ ABI_FP_exceptions
Definition: ARMBuildAttributes.h:54
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:197
llvm::ARMSubtarget::isTargetMuslAEABI
bool isTargetMuslAEABI() const
Definition: ARMSubtarget.h:765
ARMConstantPoolValue.h
llvm::ARMII::MO_NO_FLAG
@ MO_NO_FLAG
Definition: ARMBaseInfo.h:242
llvm::MachineModuleInfoMachO::GetThreadLocalGVStubList
SymbolListTy GetThreadLocalGVStubList()
Definition: MachineModuleInfoImpls.h:55
llvm::ARMAsmPrinter::emitMachineConstantPoolValue
void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override
EmitMachineConstantPoolValue - Print a machine constantpool value to the .s file.
Definition: ARMAsmPrinter.cpp:876
llvm::MCDR_DataRegion
@ MCDR_DataRegion
.data_region
Definition: MCDirectives.h:59
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:749
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:565
llvm::ARMAsmPrinter::emitInstruction
void emitInstruction(const MachineInstr *MI) override
Targets should implement this to emit instructions.
Definition: ARMAsmPrinter.cpp:1289
llvm::MCContext::getOrCreateSymbol
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:157
llvm::LowerARMMachineInstrToMCInst
void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, ARMAsmPrinter &AP)
Definition: ARMMCInstLower.cpp:123
llvm::ARMTargetStreamer::emitRegSave
virtual void emitRegSave(const SmallVectorImpl< unsigned > &RegList, bool isVector)
Definition: ARMTargetStreamer.cpp:98
llvm::ARMBuildAttrs::IEEEDenormals
@ IEEEDenormals
Definition: ARMBuildAttributes.h:189
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:377
llvm::TargetOptions::NoInfsFPMath
unsigned NoInfsFPMath
NoInfsFPMath - This flag is enabled when the -enable-no-infs-fp-math flag is specified on the command...
Definition: TargetOptions.h:165
TargetMachine.h
llvm::AsmPrinter::emitLinkage
virtual void emitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const
This emits linkage information about GVSym based on GV, if this is supported by the target.
Definition: AsmPrinter.cpp:427
Constants.h
llvm::ARMTargetStreamer::emitInst
virtual void emitInst(uint32_t Inst, char Suffix='\0')
Definition: ARMTargetStreamer.cpp:51
SmallString.h
llvm::getTheThumbLETarget
Target & getTheThumbLETarget()
Definition: ARMTargetInfo.cpp:21
llvm::X86AS::FS
@ FS
Definition: X86.h:183
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:62
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:534
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:653
llvm::AsmPrinter::OutStreamer
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
Definition: AsmPrinter.h:97
MCContext.h
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::MCStreamer::emitLabel
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:414
llvm::AsmPrinter::SetupMachineFunction
virtual void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
Definition: AsmPrinter.cpp:1886
MCSymbol.h
llvm::MCAF_Code16
@ MCAF_Code16
.code16 (X86) / .code 16 (ARM)
Definition: MCDirectives.h:53
MCInst.h
false
Definition: StackSlotColoring.cpp:142
ARMAsmPrinter.h
FramePtr
static const unsigned FramePtr
Definition: XCoreFrameLowering.cpp:34
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::ARMBaseTargetMachine::isLittleEndian
bool isLittleEndian() const
Definition: ARMTargetMachine.h:53
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
llvm::MachineInstr::FrameSetup
@ FrameSetup
Definition: MachineInstr.h:82
llvm::ARMBuildAttrs::AddressDirect
@ AddressDirect
Definition: ARMBuildAttributes.h:169
llvm::AsmPrinter::CurrentFnSym
MCSymbol * CurrentFnSym
The symbol for the current function.
Definition: AsmPrinter.h:119
llvm::AsmPrinter::emitAlignment
void emitAlignment(Align Alignment, const GlobalObject *GV=nullptr) const
Emit an alignment directive to the specified power of two boundary.
Definition: AsmPrinter.cpp:2369
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
llvm::ARMSubtarget::isTargetAEABI
bool isTargetAEABI() const
Definition: ARMSubtarget.h:755
llvm::MCOI::BranchTarget
@ BranchTarget
Definition: MCInstrDesc.h:53
llvm::ARMAsmPrinter::emitFunctionBodyEnd
void emitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
Definition: ARMAsmPrinter.cpp:60
llvm::ARMBuildAttrs::ABI_FP_rounding
@ ABI_FP_rounding
Definition: ARMBuildAttributes.h:52
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:91
llvm::ARMConstantPoolValue::getModifier
ARMCP::ARMCPModifier getModifier() const
Definition: ARMConstantPoolValue.h:98
llvm::GlobalValue::hasInternalLinkage
bool hasInternalLinkage() const
Definition: GlobalValue.h:443
llvm::MCSymbol::getName
StringRef getName() const
getName - Get the symbol name.
Definition: MCSymbol.h:197
isThumb
static bool isThumb(const MCSubtargetInfo &STI)
Definition: ARMAsmPrinter.cpp:470
llvm::ARMFunctionInfo::isThumbFunction
bool isThumbFunction() const
Definition: ARMMachineFunctionInfo.h:144
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::MCSymbol::print
void print(raw_ostream &OS, const MCAsmInfo *MAI) const
print - Print the value to the stream OS.
Definition: MCSymbol.cpp:59
llvm::ARMBuildAttrs::AddressROPCRel
@ AddressROPCRel
Definition: ARMBuildAttributes.h:165
llvm::TargetOptions::FloatABIType
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line.
Definition: TargetOptions.h:350
Type.h
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:209
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
llvm::ARMAsmPrinter::emitXXStructor
void emitXXStructor(const DataLayout &DL, const Constant *CV) override
Targets can override this to change how global constants that are part of a C++ static/global constru...
Definition: ARMAsmPrinter.cpp:89
llvm::Pass::print
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:125
llvm::MCDR_DataRegionJT32
@ MCDR_DataRegionJT32
.data_region jt32
Definition: MCDirectives.h:62
llvm::MachineModuleInfoCOFF
MachineModuleInfoCOFF - This is a MachineModuleInfoImpl implementation for COFF targets.
Definition: MachineModuleInfoImpls.h:84
llvm::ARMTargetStreamer::emitSetFP
virtual void emitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset=0)
Definition: ARMTargetStreamer.cpp:94
llvm::TargetOptions::NoTrappingFPMath
unsigned NoTrappingFPMath
NoTrappingFPMath - This flag is enabled when the -enable-no-trapping-fp-math is specified on the comm...
Definition: TargetOptions.h:176
llvm::ARMCC::AL
@ AL
Definition: ARMBaseInfo.h:45
llvm::PointerIntPair::getPointer
PointerTy getPointer() const
Definition: PointerIntPair.h:59
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:555
llvm::DenormalMode::getPositiveZero
static constexpr DenormalMode getPositiveZero()
Definition: FloatingPointMode.h:110
llvm::ARMBuildAttrs::ABI_FP_denormal
@ ABI_FP_denormal
Definition: ARMBuildAttributes.h:53
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:128
llvm::ARMBuildAttrs::ABI_VFP_args
@ ABI_VFP_args
Definition: ARMBuildAttributes.h:61
llvm::ARMAsmPrinter::PrintAsmMemoryOperand
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
Definition: ARMAsmPrinter.cpp:446
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::MachineJumpTableInfo::getJumpTables
const std::vector< MachineJumpTableEntry > & getJumpTables() const
Definition: MachineJumpTableInfo.h:99
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:392
llvm::InlineAsm::MIOp_FirstOperand
@ MIOp_FirstOperand
Definition: InlineAsm.h:218
llvm::TargetRegisterInfo::getRegClass
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: TargetRegisterInfo.h:723
llvm::ARMSubtarget::isThumb1Only
bool isThumb1Only() const
Definition: ARMSubtarget.h:802
llvm::MCSymbolRefExpr::VariantKind
VariantKind
Definition: MCExpr.h:194
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition: MachineOperand.h:218
llvm::MCAF_SubsectionsViaSymbols
@ MCAF_SubsectionsViaSymbols
.subsections_via_symbols (MachO)
Definition: MCDirectives.h:52
llvm::ARMCP::TLSGD
@ TLSGD
None.
Definition: ARMConstantPoolValue.h:48
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:318
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::ARMCP::GOT_PREL
@ GOT_PREL
Thread Local Storage (General Dynamic Mode)
Definition: ARMConstantPoolValue.h:49
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
ARMTargetObjectFile.h
llvm::ISD::TRAP
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1073
llvm::AsmPrinter::GetBlockAddressSymbol
MCSymbol * GetBlockAddressSymbol(const BlockAddress *BA) const
Return the MCSymbol used to satisfy BlockAddress uses of the specified basic block.
Definition: AsmPrinter.cpp:3030
llvm::TargetRegisterInfo::getFrameRegister
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
llvm::ARMAsmPrinter::emitGlobalVariable
void emitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
Definition: ARMAsmPrinter.cpp:106
llvm::MachineConstantPool
The MachineConstantPool class keeps track of constants referenced by a function which must be spilled...
Definition: MachineConstantPool.h:117
llvm::MCObjectFileInfo::getNonLazySymbolPointerSection
MCSection * getNonLazySymbolPointerSection() const
Definition: MCObjectFileInfo.h:397
llvm::ARMII::MO_NONLAZY
@ MO_NONLAZY
MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it represents a symbol which,...
Definition: ARMBaseInfo.h:284
llvm::ARMBuildAttrs::PositiveZero
@ PositiveZero
Definition: ARMBuildAttributes.h:188
llvm::PointerIntPair::getInt
IntType getInt() const
Definition: PointerIntPair.h:61
llvm::DenormalMode
Represent subnormal handling kind for floating point instruction inputs and outputs.
Definition: FloatingPointMode.h:67
llvm::MCInstBuilder
Definition: MCInstBuilder.h:21
llvm::ARMSubtarget::isTargetELF
bool isTargetELF() const
Definition: ARMSubtarget.h:745
llvm::MachineOperand::getType
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Definition: MachineOperand.h:216
MachineFunctionPass.h
llvm::ARMSubtarget::isTargetCOFF
bool isTargetCOFF() const
Definition: ARMSubtarget.h:744
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:115
llvm::ARMSubtarget::isROPI
bool isROPI() const
Definition: ARMSubtarget.cpp:347
llvm::MachineFunction::getConstantPool
MachineConstantPool * getConstantPool()
getConstantPool - Return the constant pool object for the current function.
Definition: MachineFunction.h:587
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineConstantPoolEntry::isMachineConstantPoolEntry
bool isMachineConstantPoolEntry() const
isMachineConstantPoolEntry - Return true if the MachineConstantPoolEntry is indeed a target specific ...
Definition: MachineConstantPool.h:93
llvm::AsmPrinter::getSymbol
MCSymbol * getSymbol(const GlobalValue *GV) const
Definition: AsmPrinter.cpp:472
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1563
llvm::MCStreamer::emitIntValue
virtual void emitIntValue(uint64_t Value, unsigned Size)
Special case of EmitValue that avoids the client having to pass in a MCExpr for constant integers.
Definition: MCStreamer.cpp:132
llvm::MCBinaryExpr::createSub
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:606
llvm::GlobalValue::isThreadLocal
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
Definition: GlobalValue.h:244
llvm::ARMBuildAttrs::ABI_FP_number_model
@ ABI_FP_number_model
Definition: ARMBuildAttributes.h:56
llvm::AsmPrinter::getMBBExceptionSym
MCSymbol * getMBBExceptionSym(const MachineBasicBlock &MBB)
Definition: AsmPrinter.cpp:1879
llvm::AsmPrinter::MF
MachineFunction * MF
The current machine function.
Definition: AsmPrinter.h:100
llvm::ARMTargetStreamer::switchVendor
virtual void switchVendor(StringRef Vendor)
Definition: ARMTargetStreamer.cpp:103
llvm::AsmPrinter::OutContext
MCContext & OutContext
This is the context for the output file that we are streaming.
Definition: AsmPrinter.h:92
llvm::MCSuperRegIterator
MCSuperRegIterator enumerates all super-registers of Reg.
Definition: MCRegisterInfo.h:641
llvm::ARMAsmPrinter::GetCPISymbol
MCSymbol * GetCPISymbol(unsigned CPID) const override
Return the symbol for the specified constant pool entry.
Definition: ARMAsmPrinter.cpp:252
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:357
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
ARM.h
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::MCSymbolRefExpr::VK_TPOFF
@ VK_TPOFF
Definition: MCExpr.h:211
llvm::ARMBuildAttrs::AddressGOT
@ AddressGOT
Definition: ARMBuildAttributes.h:170
llvm::ARMFunctionInfo::getGlobalsPromotedToConstantPool
SmallPtrSet< const GlobalVariable *, 2 > & getGlobalsPromotedToConstantPool()
Definition: ARMMachineFunctionInfo.h:247
llvm::ARMBuildAttrs::ABI_align_needed
@ ABI_align_needed
Definition: ARMBuildAttributes.h:57
llvm::MachineFunction
Definition: MachineFunction.h:227
llvm::ARMAsmPrinter::ARMAsmPrinter
ARMAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
Definition: ARMAsmPrinter.cpp:55
Mangler.h
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::MCBinaryExpr::createAdd
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:521
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:847
llvm::AsmPrinter::GetExternalSymbolSymbol
MCSymbol * GetExternalSymbolSymbol(StringRef Sym) const
Return the MCSymbol for the specified ExternalSymbol.
Definition: AsmPrinter.cpp:3086
ARMAddressingModes.h
llvm::MachineOperand::getMBB
MachineBasicBlock * getMBB() const
Definition: MachineOperand.h:549
MCAsmInfo.h
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1512
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MCInstBuilder::addImm
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:133
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
llvm::ARMBuildAttrs::ABI_optimization_goals
@ ABI_optimization_goals
Definition: ARMBuildAttributes.h:63
A
* A
Definition: README_ALTIVEC.txt:89
uint32_t
llvm::AArch64ISD::ADR
@ ADR
Definition: AArch64ISelLowering.h:62
llvm::MachineModuleInfoCOFF::getGVStubEntry
StubValueTy & getGVStubEntry(MCSymbol *Sym)
Definition: MachineModuleInfoImpls.h:94
llvm::MachineOperand::MO_MachineBasicBlock
@ MO_MachineBasicBlock
MachineBasicBlock reference.
Definition: MachineOperand.h:56
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetMachine::getTargetFeatureString
StringRef getTargetFeatureString() const
Definition: TargetMachine.h:125
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::MCInstBuilder::addExpr
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Definition: MCInstBuilder.h:55
getModifierVariantKind
static MCSymbolRefExpr::VariantKind getModifierVariantKind(ARMCP::ARMCPModifier Modifier)
Definition: ARMAsmPrinter.cpp:800
llvm::MCSA_IndirectSymbol
@ MCSA_IndirectSymbol
.indirect_symbol (MachO)
Definition: MCDirectives.h:34
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:281
llvm::MCContext::createTempSymbol
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
Definition: MCContext.cpp:268
llvm::ARMAsmPrinter::emitFunctionEntryLabel
void emitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
Definition: ARMAsmPrinter.cpp:69
llvm::ARMSubtarget::hasV4TOps
bool hasV4TOps() const
Definition: ARMSubtarget.h:596
llvm::Constant::stripPointerCasts
const Constant * stripPointerCasts() const
Definition: Constant.h:201
llvm::ARMBuildAttrs::ABI_PCS_RO_data
@ ABI_PCS_RO_data
Definition: ARMBuildAttributes.h:49
llvm::ARMConstantPoolValue::getLabelId
unsigned getLabelId() const
Definition: ARMConstantPoolValue.h:104
llvm::ARMSubtarget::isTargetWindows
bool isTargetWindows() const
Definition: ARMSubtarget.h:742
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::getSubReg
unsigned getSubReg() const
Definition: MachineOperand.h:362
llvm::AsmPrinter::MMI
MachineModuleInfo * MMI
This is a pointer to the current MachineModuleInfo.
Definition: AsmPrinter.h:103
llvm::ARMAsmPrinter::emitInlineAsmEnd
void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo, const MCSubtargetInfo *EndInfo) const override
Let the target do anything it needs to do after emitting inlineasm.
Definition: ARMAsmPrinter.cpp:474
llvm::MCAF_Code32
@ MCAF_Code32
.code32 (X86) / .code 32 (ARM)
Definition: MCDirectives.h:54
llvm::ARMAsmPrinter::PrintAsmOperand
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Definition: ARMAsmPrinter.cpp:272
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::DenormalMode::getPreserveSign
static constexpr DenormalMode getPreserveSign()
Definition: FloatingPointMode.h:105
llvm::ARMBuildAttrs::HardFPAAPCS
@ HardFPAAPCS
Definition: ARMBuildAttributes.h:213
llvm::ARMTargetStreamer::emitTargetAttributes
void emitTargetAttributes(const MCSubtargetInfo &STI)
Emit the build attributes that only depend on the hardware that we expect.
Definition: ARMTargetStreamer.cpp:162
llvm::ARMBuildAttrs::FP16FormatIEEE
@ FP16FormatIEEE
Definition: ARMBuildAttributes.h:221
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
llvm::MCAF_SyntaxUnified
@ MCAF_SyntaxUnified
.syntax (ARM/ELF)
Definition: MCDirectives.h:51
llvm::ARMTargetStreamer::emitTextAttribute
virtual void emitTextAttribute(unsigned Attribute, StringRef String)
Definition: ARMTargetStreamer.cpp:105
llvm::MachineConstantPoolEntry
This class is a data container for one entry in a MachineConstantPool.
Definition: MachineConstantPool.h:67
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
std
Definition: BitVector.h:838
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:521
llvm::ARMSubtarget::isTargetDarwin
bool isTargetDarwin() const
Definition: ARMSubtarget.h:735
llvm::ARMII::MO_LO16
@ MO_LO16
MO_LO16 - On a symbol operand, this represents a relocation containing lower 16 bit of the address.
Definition: ARMBaseInfo.h:246
llvm::ARMConstantPoolValue::isBlockAddress
bool isBlockAddress() const
Definition: ARMConstantPoolValue.h:109
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:274
llvm::InlineAsm::hasRegClassConstraint
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
Definition: InlineAsm.h:352
uint16_t
llvm::ARMAsmPrinter::LowerPATCHABLE_TAIL_CALL
void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
Definition: ARMMCInstLower.cpp:226
llvm::ARMConstantPoolValue::mustAddCurrentAddress
bool mustAddCurrentAddress() const
Definition: ARMConstantPoolValue.h:102
llvm::ARMBuildAttrs::ABI_PCS_RW_data
@ ABI_PCS_RW_data
Definition: ARMBuildAttributes.h:48
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:551
llvm::MachineConstantPool::getConstants
const std::vector< MachineConstantPoolEntry > & getConstants() const
Definition: MachineConstantPool.h:145
llvm::ARMTargetStreamer::emitMovSP
virtual void emitMovSP(unsigned Reg, int64_t Offset=0)
Definition: ARMTargetStreamer.cpp:96
llvm::ARMAsmPrinter::emitEndOfAsmFile
void emitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
Definition: ARMAsmPrinter.cpp:524
llvm::MCStreamer::emitSymbolAttribute
virtual bool emitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
llvm::ARMBuildAttrs::R9IsSB
@ R9IsSB
Definition: ARMBuildAttributes.h:155
llvm::ARMAsmPrinter::PrintSymbolOperand
void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override
Print the MachineOperand as a symbol.
Definition: ARMAsmPrinter.cpp:197
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::MachineOperand::getIndex
int getIndex() const
Definition: MachineOperand.h:554
llvm::MachineModuleInfoMachO::GetGVStubList
SymbolListTy GetGVStubList()
Accessor methods to return the set of stubs in sorted order.
Definition: MachineModuleInfoImpls.h:54
llvm::ARMSubtarget::isTargetMachO
bool isTargetMachO() const
Definition: ARMSubtarget.h:746
checkFunctionsAttributeConsistency
static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr, StringRef Value)
Definition: ARMAsmPrinter.cpp:591
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::ARMBuildAttrs::ABI_PCS_wchar_t
@ ABI_PCS_wchar_t
Definition: ARMBuildAttributes.h:51
llvm::ARMConstantPoolValue::isPromotedGlobal
bool isPromotedGlobal() const
Definition: ARMConstantPoolValue.h:112
llvm::ARMBuildAttrs::ABI_PCS_GOT_use
@ ABI_PCS_GOT_use
Definition: ARMBuildAttributes.h:50
llvm::AsmPrinter
This class is intended to be used as a driving class for all asm writers.
Definition: AsmPrinter.h:82
llvm::MCSymbolRefExpr::VK_TLSGD
@ VK_TLSGD
Definition: MCExpr.h:208
llvm::ARMTargetStreamer::emitAttribute
virtual void emitAttribute(unsigned Attribute, unsigned Value)
Definition: ARMTargetStreamer.cpp:104
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:382
getPICLabel
static MCSymbol * getPICLabel(StringRef Prefix, unsigned FunctionNumber, unsigned LabelId, MCContext &Ctx)
Definition: ARMAsmPrinter.cpp:791
llvm::ARMAsmPrinter::emitJumpTableInsts
void emitJumpTableInsts(const MachineInstr *MI)
Definition: ARMAsmPrinter.cpp:1001
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:320
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:403
ARMBuildAttributes.h
llvm::MCSA_ELF_TypeFunction
@ MCSA_ELF_TypeFunction
.type _foo, STT_FUNC # aka @function
Definition: MCDirectives.h:23
llvm::ARMCP::GOTTPOFF
@ GOTTPOFF
Global Offset Table, PC Relative.
Definition: ARMConstantPoolValue.h:50
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:672
llvm::TargetOptions::NoNaNsFPMath
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
Definition: TargetOptions.h:171
llvm::PointerIntPair
PointerIntPair - This class implements a pair of a pointer and small integer.
Definition: PointerIntPair.h:45
llvm::TargetMachine::getTargetCPU
StringRef getTargetCPU() const
Definition: TargetMachine.h:124
llvm::MCStreamer::getContext
MCContext & getContext() const
Definition: MCStreamer.h:278
llvm::AsmPrinter::TM
TargetMachine & TM
Target machine description.
Definition: AsmPrinter.h:85
llvm::MCDR_DataRegionJT8
@ MCDR_DataRegionJT8
.data_region jt8
Definition: MCDirectives.h:60
llvm::MachineConstantPoolEntry::Val
union llvm::MachineConstantPoolEntry::@176 Val
The constant itself.
llvm::InlineAsm::getNumOperandRegisters
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
Definition: InlineAsm.h:337
llvm::AsmPrinter::getSymbolWithGlobalValueBase
MCSymbol * getSymbolWithGlobalValueBase(const GlobalValue *GV, StringRef Suffix) const
Return the MCSymbol for a private symbol with global value name as its base, with the specified suffi...
Definition: AsmPrinter.cpp:3080
llvm::AsmPrinter::getObjFileLowering
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
Definition: AsmPrinter.cpp:222
llvm::MCRegisterInfo::DiffListIterator::isValid
bool isValid() const
isValid - returns true if this iterator is not yet at the end.
Definition: MCRegisterInfo.h:224
MCStreamer.h
llvm::ARMSubtarget::isTargetEHABICompatible
bool isTargetEHABICompatible() const
Definition: ARMSubtarget.h:773
llvm::AsmPrinter::emitFunctionBody
void emitFunctionBody()
This method emits the body and trailer for a function.
Definition: AsmPrinter.cpp:1181
llvm::TargetMachine::getTargetTriple
const Triple & getTargetTriple() const
Definition: TargetMachine.h:123
llvm::ARMBuildAttrs::R9Reserved
@ R9Reserved
Definition: ARMBuildAttributes.h:157
llvm::raw_svector_ostream
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:647
llvm::AsmPrinter::getDataLayout
const DataLayout & getDataLayout() const
Return information about data layout.
Definition: AsmPrinter.cpp:226
llvm::ARMSubtarget::isGVIndirectSymbol
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
Definition: ARMSubtarget.cpp:356
llvm::MCInstBuilder::addReg
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
llvm::TargetOptions::UnsafeFPMath
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
Definition: TargetOptions.h:159
llvm::ARMMCExpr::createLower16
static const ARMMCExpr * createLower16(const MCExpr *Expr, MCContext &Ctx)
Definition: ARMMCExpr.h:42
llvm::ARMAsmPrinter::emitStartOfAsmFile
void emitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
Definition: ARMAsmPrinter.cpp:484
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1078
llvm::MachineModuleInfoMachO::getThreadLocalGVStubEntry
StubValueTy & getThreadLocalGVStubEntry(MCSymbol *Sym)
Definition: MachineModuleInfoImpls.h:48
llvm::MCSymbolRefExpr::VK_None
@ VK_None
Definition: MCExpr.h:195
llvm::ARMTargetStreamer::finishAttributeSection
virtual void finishAttributeSection()
Definition: ARMTargetStreamer.cpp:114
llvm::AsmPrinter::emitXRayTable
void emitXRayTable()
Emit a table with all XRay instrumentation points.
Definition: AsmPrinter.cpp:3388
llvm::MachineFunction::getJumpTableInfo
const MachineJumpTableInfo * getJumpTableInfo() const
getJumpTableInfo - Return the jump table info object for the current function.
Definition: MachineFunction.h:578
llvm::getTheThumbBETarget
Target & getTheThumbBETarget()
Definition: ARMTargetInfo.cpp:25
llvm::ARMAsmPrinter::emitJumpTableTBInst
void emitJumpTableTBInst(const MachineInstr *MI, unsigned OffsetWidth)
Definition: ARMAsmPrinter.cpp:1029
llvm::RegisterAsmPrinter
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...
Definition: TargetRegistry.h:1181
llvm::ARMConstantPoolValue::isMachineBasicBlock
bool isMachineBasicBlock() const
Definition: ARMConstantPoolValue.h:111
llvm::MachineJumpTableInfo
Definition: MachineJumpTableInfo.h:42
raw_ostream.h
llvm::ARMAsmPrinter::emitJumpTableAddrs
void emitJumpTableAddrs(const MachineInstr *MI)
Definition: ARMAsmPrinter.cpp:955
ARMTargetMachine.h
llvm::ARMBuildAttrs::PreserveFPSign
@ PreserveFPSign
Definition: ARMBuildAttributes.h:190
llvm::COFF::IMAGE_SYM_DTYPE_FUNCTION
@ IMAGE_SYM_DTYPE_FUNCTION
A function that returns a base type.
Definition: COFF.h:261
llvm::MCDR_DataRegionEnd
@ MCDR_DataRegionEnd
.end_data_region
Definition: MCDirectives.h:63
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::AsmPrinter::getFunctionNumber
unsigned getFunctionNumber() const
Return a unique ID for the current function.
Definition: AsmPrinter.cpp:218
llvm::MachineConstantPoolEntry::ConstVal
const Constant * ConstVal
Definition: MachineConstantPool.h:71
llvm::MachineModuleInfo::getModule
const Module * getModule() const
Definition: MachineModuleInfo.h:174
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::MCExpr
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Debug.h
llvm::ARMBuildAttrs::ABI_FP_16bit_format
@ ABI_FP_16bit_format
Definition: ARMBuildAttributes.h:68
llvm::MCSymbolRefExpr::VK_SECREL
@ VK_SECREL
Definition: MCExpr.h:222
emitNonLazySymbolPointer
static void emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel, MachineModuleInfoImpl::StubValueTy &MCSym)
Definition: ARMAsmPrinter.cpp:501
llvm::ARMSubtarget::isTargetGNUAEABI
bool isTargetGNUAEABI() const
Definition: ARMSubtarget.h:760
SubReg
unsigned SubReg
Definition: AArch64AdvSIMDScalarPass.cpp:104
llvm::AsmPrinter::PrintAsmOperand
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
Definition: AsmPrinterInlineAsm.cpp:600
llvm::MachineModuleInfo::getObjFileInfo
Ty & getObjFileInfo()
Keep track of various per-function pieces of information for backends that would like to do so.
Definition: MachineModuleInfo.h:191
llvm::ARMCP::SBREL
@ SBREL
Section Relative (Windows TLS)
Definition: ARMConstantPoolValue.h:53
llvm::MCSymbolRefExpr::VK_GOTTPOFF
@ VK_GOTTPOFF
Definition: MCExpr.h:203
llvm::ARMSubtarget::genExecuteOnly
bool genExecuteOnly() const
Definition: ARMSubtarget.h:712
llvm::MachineModuleInfoMachO
MachineModuleInfoMachO - This is a MachineModuleInfoImpl implementation for MachO targets.
Definition: MachineModuleInfoImpls.h:27
SetVector.h
llvm::ARMBuildAttrs::AllowIEEE754
@ AllowIEEE754
Definition: ARMBuildAttributes.h:195
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition: MachineOperand.h:336
llvm::MachineOperand::MO_ConstantPoolIndex
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
Definition: MachineOperand.h:58
llvm::DataLayout::getTypeAllocSize
TypeSize getTypeAllocSize(Type *Ty) const
Returns the offset in bytes between successive objects of the specified type, including alignment pad...
Definition: DataLayout.h:498
llvm::ARMAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT
void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
Definition: ARMMCInstLower.cpp:221