LLVM 19.0.0git
Thumb1InstrInfo.cpp
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1//===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "Thumb1InstrInfo.h"
14#include "ARMSubtarget.h"
15#include "llvm/ADT/BitVector.h"
20#include "llvm/MC/MCInst.h"
22
23using namespace llvm;
24
26 : ARMBaseInstrInfo(STI) {}
27
28/// Return the noop instruction to use for a noop.
30 return MCInstBuilder(ARM::tMOVr)
31 .addReg(ARM::R8)
32 .addReg(ARM::R8)
34 .addReg(0);
35}
36
37unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
38 return 0;
39}
40
43 const DebugLoc &DL, MCRegister DestReg,
44 MCRegister SrcReg, bool KillSrc) const {
45 // Need to check the arch.
47 const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
48
49 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
50 "Thumb1 can only copy GPR registers");
51
52 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) ||
53 !ARM::tGPRRegClass.contains(DestReg))
54 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
55 .addReg(SrcReg, getKillRegState(KillSrc))
57 else {
58 const TargetRegisterInfo *RegInfo = st.getRegisterInfo();
59 LiveRegUnits UsedRegs(*RegInfo);
60 UsedRegs.addLiveOuts(MBB);
61
62 auto InstUpToI = MBB.end();
63 while (InstUpToI != I)
64 // The pre-decrement is on purpose here.
65 // We want to have the liveness right before I.
66 UsedRegs.stepBackward(*--InstUpToI);
67
68 if (UsedRegs.available(ARM::CPSR)) {
69 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
70 .addReg(SrcReg, getKillRegState(KillSrc))
71 ->addRegisterDead(ARM::CPSR, RegInfo);
72 return;
73 }
74
75 // Use high register to move source to destination
76 // if movs is not an option.
77 BitVector Allocatable = RegInfo->getAllocatableSet(
78 MF, RegInfo->getRegClass(ARM::hGPRRegClassID));
79
80 Register TmpReg = ARM::NoRegister;
81 // Prefer R12 as it is known to not be preserved anyway
82 if (UsedRegs.available(ARM::R12) && Allocatable.test(ARM::R12)) {
83 TmpReg = ARM::R12;
84 } else {
85 for (Register Reg : Allocatable.set_bits()) {
86 if (UsedRegs.available(Reg)) {
87 TmpReg = Reg;
88 break;
89 }
90 }
91 }
92
93 if (TmpReg) {
94 BuildMI(MBB, I, DL, get(ARM::tMOVr), TmpReg)
95 .addReg(SrcReg, getKillRegState(KillSrc))
97 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
98 .addReg(TmpReg, getKillRegState(true))
100 return;
101 }
102
103 // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
104 BuildMI(MBB, I, DL, get(ARM::tPUSH))
106 .addReg(SrcReg, getKillRegState(KillSrc));
107 BuildMI(MBB, I, DL, get(ARM::tPOP))
109 .addReg(DestReg, getDefRegState(true));
110 }
111}
112
115 Register SrcReg, bool isKill, int FI,
116 const TargetRegisterClass *RC,
117 const TargetRegisterInfo *TRI,
118 Register VReg) const {
119 assert((RC == &ARM::tGPRRegClass ||
120 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) &&
121 "Unknown regclass!");
122
123 if (RC == &ARM::tGPRRegClass ||
124 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) {
125 DebugLoc DL;
126 if (I != MBB.end()) DL = I->getDebugLoc();
127
129 MachineFrameInfo &MFI = MF.getFrameInfo();
132 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
133 BuildMI(MBB, I, DL, get(ARM::tSTRspi))
134 .addReg(SrcReg, getKillRegState(isKill))
135 .addFrameIndex(FI)
136 .addImm(0)
137 .addMemOperand(MMO)
139 }
140}
141
144 Register DestReg, int FI,
145 const TargetRegisterClass *RC,
146 const TargetRegisterInfo *TRI,
147 Register VReg) const {
148 assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
149 (DestReg.isPhysical() && isARMLowRegister(DestReg))) &&
150 "Unknown regclass!");
151
152 if (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
153 (DestReg.isPhysical() && isARMLowRegister(DestReg))) {
154 DebugLoc DL;
155 if (I != MBB.end()) DL = I->getDebugLoc();
156
158 MachineFrameInfo &MFI = MF.getFrameInfo();
161 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
162 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
163 .addFrameIndex(FI)
164 .addImm(0)
165 .addMemOperand(MMO)
167 }
168}
169
170void Thumb1InstrInfo::expandLoadStackGuard(
172 MachineFunction &MF = *MI->getParent()->getParent();
173 const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>();
174 const auto *GV = cast<GlobalValue>((*MI->memoperands_begin())->getValue());
175
177 "TLS stack protector not supported for Thumb1 targets");
178
179 unsigned Instr;
180 if (!GV->isDSOLocal())
181 Instr = ARM::tLDRLIT_ga_pcrel;
182 else if (ST.genExecuteOnly() && ST.hasV8MBaselineOps())
183 Instr = ARM::t2MOVi32imm;
184 else if (ST.genExecuteOnly())
185 Instr = ARM::tMOVi32imm;
186 else
187 Instr = ARM::tLDRLIT_ga_abs;
188 expandLoadStackGuardBase(MI, Instr, ARM::tLDRi);
189}
190
192 // In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR
193 // but this is not always possible there, so allow the Scheduler to clone tADCS and tSBCS
194 // even if they have glue.
195 // FIXME. Actually implement the cross-copy where it is possible (post v6)
196 // because these copies entail more spilling.
197 unsigned Opcode = N->getMachineOpcode();
198 if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)
199 return true;
200
201 return false;
202}
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
This file implements the BitVector class.
IRTranslator LLVM IR MI
A set of register units.
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:208
bool test(unsigned Idx) const
Definition: BitVector.h:461
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:140
A debug info location.
Definition: DebugLoc.h:33
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:655
A set of register units used to track register liveness.
Definition: LiveRegUnits.h:30
bool available(MCPhysReg Reg) const
Returns true if no part of physical register Reg is live.
Definition: LiveRegUnits.h:116
void stepBackward(const MachineInstr &MI)
Updates liveness when stepping backwards over the instruction MI.
void addLiveOuts(const MachineBasicBlock &MBB)
Adds registers living out of block MBB.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:37
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:43
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
StringRef getStackProtectorGuard() const
Get/set what kind of stack protector guard to use.
Definition: Module.cpp:733
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
Represents one node in the SelectionDAG.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Thumb1InstrInfo(const ARMSubtarget &STI)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
MCInst getNop() const override
Return the noop instruction to use for a noop.
unsigned getUnindexedOpcode(unsigned Opc) const override
bool canCopyGluedNodeDuringSchedule(SDNode *N) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:160
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
unsigned getDefRegState(bool B)
unsigned getKillRegState(bool B)
#define N
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.