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48 "Thumb1 can only copy GPR registers");
50 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
51 || !ARM::tGPRRegClass.contains(DestReg))
80 Register SrcReg,
bool isKill,
int FI,
83 assert((RC == &ARM::tGPRRegClass ||
87 if (RC == &ARM::tGPRRegClass ||
114 "Unknown regclass!");
134 void Thumb1InstrInfo::expandLoadStackGuard(
140 "TLS stack protector not supported for Thumb1 targets");
142 if (
TM.isPositionIndependent())
154 unsigned Opcode =
N->getMachineOpcode();
155 if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
StringRef getStackProtectorGuard() const
Get/set what kind of stack protector guard to use.
const MachineInstrBuilder & add(const MachineOperand &MO) const
return AArch64::GPR64RegClass contains(Reg)
unsigned getUnindexedOpcode(unsigned Opc) const override
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Represents one node in the SelectionDAG.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A description of a memory reference used in the backend.
Instances of this class represent a single low-level machine instruction.
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
unsigned const TargetRegisterInfo * TRI
unsigned getDefRegState(bool B)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const MachineInstrBuilder & addFrameIndex(int Idx) const
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Module * getParent()
Get the module that this global value is contained inside of...
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Primary interface to the complete machine description for the target machine.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
@ LQR_Dead
Register is known to be fully dead.
const ARMBaseRegisterInfo * getRegisterInfo() const override
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
@ MOLoad
The memory access reads data.
Wrapper class representing virtual and physical registers.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Should compile to something r4 addze r3 instead we get
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, MCRegister Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been defined and not killed as of just before Before.
@ MOStore
The memory access writes data.
unsigned getKillRegState(bool B)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
bool canCopyGluedNodeDuringSchedule(SDNode *N) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
MCInst getNop() const override
Return the noop instruction to use for a noop.
const char LLVMTargetMachineRef TM
Thumb1InstrInfo(const ARMSubtarget &STI)
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
Wrapper class representing physical registers. Should be passed by value.