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1//===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
13#include "Thumb1InstrInfo.h"
14#include "ARMSubtarget.h"
18#include "llvm/MC/MCInst.h"
21using namespace llvm;
24 : ARMBaseInstrInfo(STI) {}
26/// Return the noop instruction to use for a noop.
28 return MCInstBuilder(ARM::tMOVr)
29 .addReg(ARM::R8)
30 .addReg(ARM::R8)
32 .addReg(0);
35unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
36 return 0;
41 const DebugLoc &DL, MCRegister DestReg,
42 MCRegister SrcReg, bool KillSrc) const {
43 // Need to check the arch.
45 const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
48 "Thumb1 can only copy GPR registers");
50 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
51 || !ARM::tGPRRegClass.contains(DestReg))
52 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
53 .addReg(SrcReg, getKillRegState(KillSrc))
55 else {
56 // FIXME: Can also use 'mov hi, $src; mov $dst, hi',
57 // with hi as either r10 or r11.
59 const TargetRegisterInfo *RegInfo = st.getRegisterInfo();
60 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)
62 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
63 .addReg(SrcReg, getKillRegState(KillSrc))
64 ->addRegisterDead(ARM::CPSR, RegInfo);
65 return;
66 }
68 // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
69 BuildMI(MBB, I, DL, get(ARM::tPUSH))
71 .addReg(SrcReg, getKillRegState(KillSrc));
72 BuildMI(MBB, I, DL, get(ARM::tPOP))
74 .addReg(DestReg, getDefRegState(true));
75 }
80 Register SrcReg, bool isKill, int FI,
81 const TargetRegisterClass *RC,
83 Register VReg) const {
84 assert((RC == &ARM::tGPRRegClass ||
85 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) &&
86 "Unknown regclass!");
88 if (RC == &ARM::tGPRRegClass ||
89 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) {
91 if (I != MBB.end()) DL = I->getDebugLoc();
97 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
98 BuildMI(MBB, I, DL, get(ARM::tSTRspi))
99 .addReg(SrcReg, getKillRegState(isKill))
100 .addFrameIndex(FI)
101 .addImm(0)
102 .addMemOperand(MMO)
104 }
109 Register DestReg, int FI,
110 const TargetRegisterClass *RC,
111 const TargetRegisterInfo *TRI,
112 Register VReg) const {
113 assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
114 (DestReg.isPhysical() && isARMLowRegister(DestReg))) &&
115 "Unknown regclass!");
117 if (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
118 (DestReg.isPhysical() && isARMLowRegister(DestReg))) {
119 DebugLoc DL;
120 if (I != MBB.end()) DL = I->getDebugLoc();
123 MachineFrameInfo &MFI = MF.getFrameInfo();
126 MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
127 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
128 .addFrameIndex(FI)
129 .addImm(0)
130 .addMemOperand(MMO)
132 }
135void Thumb1InstrInfo::expandLoadStackGuard(
137 MachineFunction &MF = *MI->getParent()->getParent();
138 const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>();
139 const auto *GV = cast<GlobalValue>((*MI->memoperands_begin())->getValue());
142 "TLS stack protector not supported for Thumb1 targets");
144 unsigned Instr;
145 if (!GV->isDSOLocal())
146 Instr = ARM::tLDRLIT_ga_pcrel;
147 else if (ST.genExecuteOnly() && ST.hasV8MBaselineOps())
148 Instr = ARM::t2MOVi32imm;
149 else if (ST.genExecuteOnly())
150 Instr = ARM::tMOVi32imm;
151 else
152 Instr = ARM::tLDRLIT_ga_abs;
153 expandLoadStackGuardBase(MI, Instr, ARM::tLDRi);
157 // In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR
158 // but this is not always possible there, so allow the Scheduler to clone tADCS and tSBCS
159 // even if they have glue.
160 // FIXME. Actually implement the cross-copy where it is possible (post v6)
161 // because these copies entail more spilling.
162 unsigned Opcode = N->getMachineOpcode();
163 if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)
164 return true;
166 return false;
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
void expandLoadStackGuardBase(MachineBasicBlock::iterator MI, unsigned LoadImmOpc, unsigned LoadOpc) const
const ARMBaseRegisterInfo * getRegisterInfo() const override
Definition: ARMSubtarget.h:277
A debug info location.
Definition: DebugLoc.h:33
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:655
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
Definition: MCInstBuilder.h:31
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
Definition: MCInstBuilder.h:37
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI, MCRegister Reg, const_iterator Before, unsigned Neighborhood=10) const
Return whether (physical) register Reg has been defined and not killed as of just before Before.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
@ LQR_Dead
Register is known to be fully dead.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
A description of a memory reference used in the backend.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
StringRef getStackProtectorGuard() const
Get/set what kind of stack protector guard to use.
Definition: Module.cpp:709
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
Represents one node in the SelectionDAG.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Thumb1InstrInfo(const ARMSubtarget &STI)
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
MCInst getNop() const override
Return the noop instruction to use for a noop.
unsigned getUnindexedOpcode(unsigned Opc) const override
bool canCopyGluedNodeDuringSchedule(SDNode *N) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static std::array< MachineOperand, 2 > predOps(ARMCC::CondCodes Pred, unsigned PredReg=0)
Get the operands corresponding to the given Pred value.
static bool isARMLowRegister(unsigned Reg)
isARMLowRegister - Returns true if the register is a low register (r0-r7).
Definition: ARMBaseInfo.h:160
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
unsigned getDefRegState(bool B)
unsigned getKillRegState(bool B)
#define N
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.