LLVM 20.0.0git
AMDGPUCallLowering.h
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1//===- lib/Target/AMDGPU/AMDGPUCallLowering.h - Call lowering -*- C++ -*---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file describes how to lower LLVM calls to machine code calls.
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUCALLLOWERING_H
15#define LLVM_LIB_TARGET_AMDGPU_AMDGPUCALLLOWERING_H
16
18
19namespace llvm {
20
21class AMDGPUTargetLowering;
22class GCNSubtarget;
23class MachineInstrBuilder;
24class SIMachineFunctionInfo;
25
26class AMDGPUCallLowering final : public CallLowering {
27 void lowerParameterPtr(Register DstReg, MachineIRBuilder &B,
28 uint64_t Offset) const;
29
30 void lowerParameter(MachineIRBuilder &B, ArgInfo &AI, uint64_t Offset,
31 Align Alignment) const;
32
33 bool canLowerReturn(MachineFunction &MF, CallingConv::ID CallConv,
35 bool IsVarArg) const override;
36
37 bool lowerReturnVal(MachineIRBuilder &B, const Value *Val,
38 ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
39
40public:
42
43 bool lowerReturn(MachineIRBuilder &B, const Value *Val,
45 FunctionLoweringInfo &FLI) const override;
46
48 ArrayRef<ArrayRef<Register>> VRegs) const;
49
52 FunctionLoweringInfo &FLI) const override;
53
54 bool passSpecialInputs(MachineIRBuilder &MIRBuilder,
55 CCState &CCInfo,
56 SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs,
57 CallLoweringInfo &Info) const;
58
59 bool
62 SmallVectorImpl<ArgInfo> &InArgs) const;
63
64 bool
66 SmallVectorImpl<ArgInfo> &OutArgs) const;
67
68 /// Returns true if the call can be lowered as a tail call.
69 bool
73 SmallVectorImpl<ArgInfo> &OutArgs) const;
74
77 const GCNSubtarget &ST, const SIMachineFunctionInfo &MFI,
78 CallingConv::ID CalleeCC,
79 ArrayRef<std::pair<MCRegister, Register>> ImplicitArgRegs) const;
80
82 SmallVectorImpl<ArgInfo> &OutArgs) const;
83 bool lowerChainCall(MachineIRBuilder &MIRBuilder,
84 CallLoweringInfo &Info) const;
85 bool lowerCall(MachineIRBuilder &MIRBuilder,
86 CallLoweringInfo &Info) const override;
87
88 static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
89 static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
90};
91} // End of namespace llvm;
92#endif
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
This file describes how to lower LLVM calls to machine code calls.
#define F(x, y, z)
Definition: MD5.cpp:55
bool lowerTailCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &OutArgs) const
bool isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &InArgs, SmallVectorImpl< ArgInfo > &OutArgs) const
Returns true if the call can be lowered as a tail call.
bool lowerFormalArgumentsKernel(MachineIRBuilder &B, const Function &F, ArrayRef< ArrayRef< Register > > VRegs) const
bool lowerReturn(MachineIRBuilder &B, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
void handleImplicitCallArguments(MachineIRBuilder &MIRBuilder, MachineInstrBuilder &CallInst, const GCNSubtarget &ST, const SIMachineFunctionInfo &MFI, CallingConv::ID CalleeCC, ArrayRef< std::pair< MCRegister, Register > > ImplicitArgRegs) const
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
bool areCalleeOutgoingArgsTailCallable(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &OutArgs) const
bool lowerChainCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const
Lower a call to the @llvm.amdgcn.cs.chain intrinsic.
bool passSpecialInputs(MachineIRBuilder &MIRBuilder, CCState &CCInfo, SmallVectorImpl< std::pair< MCRegister, Register > > &ArgRegs, CallLoweringInfo &Info) const
bool lowerFormalArguments(MachineIRBuilder &B, const Function &F, ArrayRef< ArrayRef< Register > > VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
bool doCallerAndCalleePassArgsTheSameWay(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
CCState - This class holds information needed while lowering arguments and return values.
This class represents a function call, abstracting a target machine's calling convention.
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Helper class to build MachineInstr.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
LLVM Value Representation.
Definition: Value.h:74
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39