LLVM  14.0.0git
AMDGPUCallLowering.cpp
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1 //===-- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp - Call lowering -----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file implements the lowering of LLVM calls to machine code calls for
11 /// GlobalISel.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "AMDGPUCallLowering.h"
16 #include "AMDGPU.h"
17 #include "AMDGPULegalizerInfo.h"
18 #include "AMDGPUTargetMachine.h"
19 #include "SIMachineFunctionInfo.h"
20 #include "SIRegisterInfo.h"
21 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/IR/IntrinsicsAMDGPU.h"
25 
26 #define DEBUG_TYPE "amdgpu-call-lowering"
27 
28 using namespace llvm;
29 
30 namespace {
31 
32 /// Wrapper around extendRegister to ensure we extend to a full 32-bit register.
33 static Register extendRegisterMin32(CallLowering::ValueHandler &Handler,
34  Register ValVReg, CCValAssign &VA) {
35  if (VA.getLocVT().getSizeInBits() < 32) {
36  // 16-bit types are reported as legal for 32-bit registers. We need to
37  // extend and do a 32-bit copy to avoid the verifier complaining about it.
38  return Handler.MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0);
39  }
40 
41  return Handler.extendRegister(ValVReg, VA);
42 }
43 
44 struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
45  AMDGPUOutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
47  : OutgoingValueHandler(B, MRI), MIB(MIB) {}
48 
50 
51  Register getStackAddress(uint64_t Size, int64_t Offset,
52  MachinePointerInfo &MPO,
53  ISD::ArgFlagsTy Flags) override {
54  llvm_unreachable("not implemented");
55  }
56 
57  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
58  MachinePointerInfo &MPO, CCValAssign &VA) override {
59  llvm_unreachable("not implemented");
60  }
61 
62  void assignValueToReg(Register ValVReg, Register PhysReg,
63  CCValAssign VA) override {
64  Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
65 
66  // If this is a scalar return, insert a readfirstlane just in case the value
67  // ends up in a VGPR.
68  // FIXME: Assert this is a shader return.
69  const SIRegisterInfo *TRI
70  = static_cast<const SIRegisterInfo *>(MRI.getTargetRegisterInfo());
71  if (TRI->isSGPRReg(MRI, PhysReg)) {
72  auto ToSGPR = MIRBuilder.buildIntrinsic(Intrinsic::amdgcn_readfirstlane,
73  {MRI.getType(ExtReg)}, false)
74  .addReg(ExtReg);
75  ExtReg = ToSGPR.getReg(0);
76  }
77 
78  MIRBuilder.buildCopy(PhysReg, ExtReg);
79  MIB.addUse(PhysReg, RegState::Implicit);
80  }
81 };
82 
83 struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler {
84  uint64_t StackUsed = 0;
85 
86  AMDGPUIncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI)
87  : IncomingValueHandler(B, MRI) {}
88 
89  Register getStackAddress(uint64_t Size, int64_t Offset,
90  MachinePointerInfo &MPO,
91  ISD::ArgFlagsTy Flags) override {
92  auto &MFI = MIRBuilder.getMF().getFrameInfo();
93 
94  // Byval is assumed to be writable memory, but other stack passed arguments
95  // are not.
96  const bool IsImmutable = !Flags.isByVal();
97  int FI = MFI.CreateFixedObject(Size, Offset, IsImmutable);
98  MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
99  auto AddrReg = MIRBuilder.buildFrameIndex(
101  StackUsed = std::max(StackUsed, Size + Offset);
102  return AddrReg.getReg(0);
103  }
104 
105  void assignValueToReg(Register ValVReg, Register PhysReg,
106  CCValAssign VA) override {
107  markPhysRegUsed(PhysReg);
108 
109  if (VA.getLocVT().getSizeInBits() < 32) {
110  // 16-bit types are reported as legal for 32-bit registers. We need to do
111  // a 32-bit copy, and truncate to avoid the verifier complaining about it.
112  auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg);
113 
114  // If we have signext/zeroext, it applies to the whole 32-bit register
115  // before truncation.
116  auto Extended =
117  buildExtensionHint(VA, Copy.getReg(0), LLT(VA.getLocVT()));
118  MIRBuilder.buildTrunc(ValVReg, Extended);
119  return;
120  }
121 
122  IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
123  }
124 
125  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
126  MachinePointerInfo &MPO, CCValAssign &VA) override {
127  MachineFunction &MF = MIRBuilder.getMF();
128 
129  auto MMO = MF.getMachineMemOperand(
131  inferAlignFromPtrInfo(MF, MPO));
132  MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
133  }
134 
135  /// How the physical register gets marked varies between formal
136  /// parameters (it's a basic-block live-in), and a call instruction
137  /// (it's an implicit-def of the BL).
138  virtual void markPhysRegUsed(unsigned PhysReg) = 0;
139 };
140 
141 struct FormalArgHandler : public AMDGPUIncomingArgHandler {
143  : AMDGPUIncomingArgHandler(B, MRI) {}
144 
145  void markPhysRegUsed(unsigned PhysReg) override {
146  MIRBuilder.getMBB().addLiveIn(PhysReg);
147  }
148 };
149 
150 struct CallReturnHandler : public AMDGPUIncomingArgHandler {
151  CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
153  : AMDGPUIncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {}
154 
155  void markPhysRegUsed(unsigned PhysReg) override {
156  MIB.addDef(PhysReg, RegState::Implicit);
157  }
158 
160 };
161 
162 struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
163  /// For tail calls, the byte offset of the call's argument area from the
164  /// callee's. Unused elsewhere.
165  int FPDiff;
166 
167  // Cache the SP register vreg if we need it more than once in this call site.
168  Register SPReg;
169 
170  bool IsTailCall;
171 
172  AMDGPUOutgoingArgHandler(MachineIRBuilder &MIRBuilder,
174  bool IsTailCall = false, int FPDiff = 0)
175  : AMDGPUOutgoingValueHandler(MIRBuilder, MRI, MIB), FPDiff(FPDiff),
176  IsTailCall(IsTailCall) {}
177 
178  Register getStackAddress(uint64_t Size, int64_t Offset,
179  MachinePointerInfo &MPO,
180  ISD::ArgFlagsTy Flags) override {
181  MachineFunction &MF = MIRBuilder.getMF();
182  const LLT PtrTy = LLT::pointer(AMDGPUAS::PRIVATE_ADDRESS, 32);
183  const LLT S32 = LLT::scalar(32);
184 
185  if (IsTailCall) {
186  Offset += FPDiff;
187  int FI = MF.getFrameInfo().CreateFixedObject(Size, Offset, true);
188  auto FIReg = MIRBuilder.buildFrameIndex(PtrTy, FI);
189  MPO = MachinePointerInfo::getFixedStack(MF, FI);
190  return FIReg.getReg(0);
191  }
192 
194 
195  if (!SPReg)
196  SPReg = MIRBuilder.buildCopy(PtrTy, MFI->getStackPtrOffsetReg()).getReg(0);
197 
198  auto OffsetReg = MIRBuilder.buildConstant(S32, Offset);
199 
200  auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg);
202  return AddrReg.getReg(0);
203  }
204 
205  void assignValueToReg(Register ValVReg, Register PhysReg,
206  CCValAssign VA) override {
207  MIB.addUse(PhysReg, RegState::Implicit);
208  Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
209  MIRBuilder.buildCopy(PhysReg, ExtReg);
210  }
211 
212  void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
213  MachinePointerInfo &MPO, CCValAssign &VA) override {
214  MachineFunction &MF = MIRBuilder.getMF();
215  uint64_t LocMemOffset = VA.getLocMemOffset();
216  const auto &ST = MF.getSubtarget<GCNSubtarget>();
217 
218  auto MMO = MF.getMachineMemOperand(
219  MPO, MachineMemOperand::MOStore, MemTy,
220  commonAlignment(ST.getStackAlignment(), LocMemOffset));
221  MIRBuilder.buildStore(ValVReg, Addr, *MMO);
222  }
223 
224  void assignValueToAddress(const CallLowering::ArgInfo &Arg,
225  unsigned ValRegIndex, Register Addr, LLT MemTy,
226  MachinePointerInfo &MPO, CCValAssign &VA) override {
227  Register ValVReg = VA.getLocInfo() != CCValAssign::LocInfo::FPExt
228  ? extendRegister(Arg.Regs[ValRegIndex], VA)
229  : Arg.Regs[ValRegIndex];
230  assignValueToAddress(ValVReg, Addr, MemTy, MPO, VA);
231  }
232 };
233 }
234 
236  : CallLowering(&TLI) {
237 }
238 
239 // FIXME: Compatibility shim
240 static ISD::NodeType extOpcodeToISDExtOpcode(unsigned MIOpc) {
241  switch (MIOpc) {
242  case TargetOpcode::G_SEXT:
243  return ISD::SIGN_EXTEND;
244  case TargetOpcode::G_ZEXT:
245  return ISD::ZERO_EXTEND;
246  case TargetOpcode::G_ANYEXT:
247  return ISD::ANY_EXTEND;
248  default:
249  llvm_unreachable("not an extend opcode");
250  }
251 }
252 
253 bool AMDGPUCallLowering::canLowerReturn(MachineFunction &MF,
254  CallingConv::ID CallConv,
256  bool IsVarArg) const {
257  // For shaders. Vector types should be explicitly handled by CC.
258  if (AMDGPU::isEntryFunctionCC(CallConv))
259  return true;
260 
262  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
263  CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs,
264  MF.getFunction().getContext());
265 
266  return checkReturn(CCInfo, Outs, TLI.CCAssignFnForReturn(CallConv, IsVarArg));
267 }
268 
269 /// Lower the return value for the already existing \p Ret. This assumes that
270 /// \p B's insertion point is correct.
271 bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
272  const Value *Val, ArrayRef<Register> VRegs,
273  MachineInstrBuilder &Ret) const {
274  if (!Val)
275  return true;
276 
277  auto &MF = B.getMF();
278  const auto &F = MF.getFunction();
279  const DataLayout &DL = MF.getDataLayout();
280  MachineRegisterInfo *MRI = B.getMRI();
281  LLVMContext &Ctx = F.getContext();
282 
283  CallingConv::ID CC = F.getCallingConv();
284  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
285 
286  SmallVector<EVT, 8> SplitEVTs;
287  ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
288  assert(VRegs.size() == SplitEVTs.size() &&
289  "For each split Type there should be exactly one VReg.");
290 
291  SmallVector<ArgInfo, 8> SplitRetInfos;
292 
293  for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
294  EVT VT = SplitEVTs[i];
295  Register Reg = VRegs[i];
296  ArgInfo RetInfo(Reg, VT.getTypeForEVT(Ctx), 0);
298 
299  if (VT.isScalarInteger()) {
300  unsigned ExtendOp = TargetOpcode::G_ANYEXT;
301  if (RetInfo.Flags[0].isSExt()) {
302  assert(RetInfo.Regs.size() == 1 && "expect only simple return values");
303  ExtendOp = TargetOpcode::G_SEXT;
304  } else if (RetInfo.Flags[0].isZExt()) {
305  assert(RetInfo.Regs.size() == 1 && "expect only simple return values");
306  ExtendOp = TargetOpcode::G_ZEXT;
307  }
308 
309  EVT ExtVT = TLI.getTypeForExtReturn(Ctx, VT,
310  extOpcodeToISDExtOpcode(ExtendOp));
311  if (ExtVT != VT) {
312  RetInfo.Ty = ExtVT.getTypeForEVT(Ctx);
313  LLT ExtTy = getLLTForType(*RetInfo.Ty, DL);
314  Reg = B.buildInstr(ExtendOp, {ExtTy}, {Reg}).getReg(0);
315  }
316  }
317 
318  if (Reg != RetInfo.Regs[0]) {
319  RetInfo.Regs[0] = Reg;
320  // Reset the arg flags after modifying Reg.
322  }
323 
324  splitToValueTypes(RetInfo, SplitRetInfos, DL, CC);
325  }
326 
327  CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(CC, F.isVarArg());
328 
329  OutgoingValueAssigner Assigner(AssignFn);
330  AMDGPUOutgoingValueHandler RetHandler(B, *MRI, Ret);
331  return determineAndHandleAssignments(RetHandler, Assigner, SplitRetInfos, B,
332  CC, F.isVarArg());
333 }
334 
336  ArrayRef<Register> VRegs,
337  FunctionLoweringInfo &FLI) const {
338 
339  MachineFunction &MF = B.getMF();
342  MFI->setIfReturnsVoid(!Val);
343 
344  assert(!Val == VRegs.empty() && "Return value without a vreg");
345 
346  CallingConv::ID CC = B.getMF().getFunction().getCallingConv();
347  const bool IsShader = AMDGPU::isShader(CC);
348  const bool IsWaveEnd =
349  (IsShader && MFI->returnsVoid()) || AMDGPU::isKernel(CC);
350  if (IsWaveEnd) {
351  B.buildInstr(AMDGPU::S_ENDPGM)
352  .addImm(0);
353  return true;
354  }
355 
356  auto const &ST = MF.getSubtarget<GCNSubtarget>();
357 
358  unsigned ReturnOpc = 0;
359  if (IsShader)
360  ReturnOpc = AMDGPU::SI_RETURN_TO_EPILOG;
361  else if (CC == CallingConv::AMDGPU_Gfx)
362  ReturnOpc = AMDGPU::S_SETPC_B64_return_gfx;
363  else
364  ReturnOpc = AMDGPU::S_SETPC_B64_return;
365 
366  auto Ret = B.buildInstrNoInsert(ReturnOpc);
367  Register ReturnAddrVReg;
368  if (ReturnOpc == AMDGPU::S_SETPC_B64_return) {
369  ReturnAddrVReg = MRI.createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass);
370  Ret.addUse(ReturnAddrVReg);
371  } else if (ReturnOpc == AMDGPU::S_SETPC_B64_return_gfx) {
372  ReturnAddrVReg =
373  MRI.createVirtualRegister(&AMDGPU::Gfx_CCR_SGPR_64RegClass);
374  Ret.addUse(ReturnAddrVReg);
375  }
376 
377  if (!FLI.CanLowerReturn)
378  insertSRetStores(B, Val->getType(), VRegs, FLI.DemoteRegister);
379  else if (!lowerReturnVal(B, Val, VRegs, Ret))
380  return false;
381 
382  if (ReturnOpc == AMDGPU::S_SETPC_B64_return ||
383  ReturnOpc == AMDGPU::S_SETPC_B64_return_gfx) {
384  const SIRegisterInfo *TRI = ST.getRegisterInfo();
385  Register LiveInReturn = MF.addLiveIn(TRI->getReturnAddressReg(MF),
386  &AMDGPU::SGPR_64RegClass);
387  B.buildCopy(ReturnAddrVReg, LiveInReturn);
388  }
389 
390  // TODO: Handle CalleeSavedRegsViaCopy.
391 
392  B.insertInstr(Ret);
393  return true;
394 }
395 
396 void AMDGPUCallLowering::lowerParameterPtr(Register DstReg, MachineIRBuilder &B,
397  uint64_t Offset) const {
398  MachineFunction &MF = B.getMF();
401  Register KernArgSegmentPtr =
403  Register KernArgSegmentVReg = MRI.getLiveInVirtReg(KernArgSegmentPtr);
404 
405  auto OffsetReg = B.buildConstant(LLT::scalar(64), Offset);
406 
407  B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg);
408 }
409 
410 void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B, ArgInfo &OrigArg,
412  Align Alignment) const {
413  MachineFunction &MF = B.getMF();
414  const Function &F = MF.getFunction();
415  const DataLayout &DL = F.getParent()->getDataLayout();
417 
419 
420  SmallVector<ArgInfo, 32> SplitArgs;
421  SmallVector<uint64_t> FieldOffsets;
422  splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv(), &FieldOffsets);
423 
424  unsigned Idx = 0;
425  for (ArgInfo &SplitArg : SplitArgs) {
426  Register PtrReg = B.getMRI()->createGenericVirtualRegister(PtrTy);
427  lowerParameterPtr(PtrReg, B, Offset + FieldOffsets[Idx]);
428 
429  LLT ArgTy = getLLTForType(*SplitArg.Ty, DL);
430  if (SplitArg.Flags[0].isPointer()) {
431  // Compensate for losing pointeriness in splitValueTypes.
432  LLT PtrTy = LLT::pointer(SplitArg.Flags[0].getPointerAddrSpace(),
433  ArgTy.getScalarSizeInBits());
434  ArgTy = ArgTy.isVector() ? LLT::vector(ArgTy.getElementCount(), PtrTy)
435  : PtrTy;
436  }
437 
439  PtrInfo,
442  ArgTy, commonAlignment(Alignment, FieldOffsets[Idx]));
443 
444  assert(SplitArg.Regs.size() == 1);
445 
446  B.buildLoad(SplitArg.Regs[0], PtrReg, *MMO);
447  ++Idx;
448  }
449 }
450 
451 // Allocate special inputs passed in user SGPRs.
452 static void allocateHSAUserSGPRs(CCState &CCInfo,
454  MachineFunction &MF,
455  const SIRegisterInfo &TRI,
457  // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
458  if (Info.hasPrivateSegmentBuffer()) {
459  Register PrivateSegmentBufferReg = Info.addPrivateSegmentBuffer(TRI);
460  MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
461  CCInfo.AllocateReg(PrivateSegmentBufferReg);
462  }
463 
464  if (Info.hasDispatchPtr()) {
465  Register DispatchPtrReg = Info.addDispatchPtr(TRI);
466  MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
467  CCInfo.AllocateReg(DispatchPtrReg);
468  }
469 
470  if (Info.hasQueuePtr()) {
471  Register QueuePtrReg = Info.addQueuePtr(TRI);
472  MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
473  CCInfo.AllocateReg(QueuePtrReg);
474  }
475 
476  if (Info.hasKernargSegmentPtr()) {
478  Register InputPtrReg = Info.addKernargSegmentPtr(TRI);
481  MRI.addLiveIn(InputPtrReg, VReg);
482  B.getMBB().addLiveIn(InputPtrReg);
483  B.buildCopy(VReg, InputPtrReg);
484  CCInfo.AllocateReg(InputPtrReg);
485  }
486 
487  if (Info.hasDispatchID()) {
488  Register DispatchIDReg = Info.addDispatchID(TRI);
489  MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
490  CCInfo.AllocateReg(DispatchIDReg);
491  }
492 
493  if (Info.hasFlatScratchInit()) {
494  Register FlatScratchInitReg = Info.addFlatScratchInit(TRI);
495  MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
496  CCInfo.AllocateReg(FlatScratchInitReg);
497  }
498 
499  // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
500  // these from the dispatch pointer.
501 }
502 
504  MachineIRBuilder &B, const Function &F,
505  ArrayRef<ArrayRef<Register>> VRegs) const {
506  MachineFunction &MF = B.getMF();
507  const GCNSubtarget *Subtarget = &MF.getSubtarget<GCNSubtarget>();
510  const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
511  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
512  const DataLayout &DL = F.getParent()->getDataLayout();
513 
514  Info->allocateModuleLDSGlobal(F.getParent());
515 
517  CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
518 
519  allocateHSAUserSGPRs(CCInfo, B, MF, *TRI, *Info);
520 
521  unsigned i = 0;
522  const Align KernArgBaseAlign(16);
523  const unsigned BaseOffset = Subtarget->getExplicitKernelArgOffset(F);
524  uint64_t ExplicitArgOffset = 0;
525 
526  // TODO: Align down to dword alignment and extract bits for extending loads.
527  for (auto &Arg : F.args()) {
528  const bool IsByRef = Arg.hasByRefAttr();
529  Type *ArgTy = IsByRef ? Arg.getParamByRefType() : Arg.getType();
530  unsigned AllocSize = DL.getTypeAllocSize(ArgTy);
531  if (AllocSize == 0)
532  continue;
533 
534  MaybeAlign ABIAlign = IsByRef ? Arg.getParamAlign() : None;
535  if (!ABIAlign)
536  ABIAlign = DL.getABITypeAlign(ArgTy);
537 
538  uint64_t ArgOffset = alignTo(ExplicitArgOffset, ABIAlign) + BaseOffset;
539  ExplicitArgOffset = alignTo(ExplicitArgOffset, ABIAlign) + AllocSize;
540 
541  if (Arg.use_empty()) {
542  ++i;
543  continue;
544  }
545 
546  Align Alignment = commonAlignment(KernArgBaseAlign, ArgOffset);
547 
548  if (IsByRef) {
549  unsigned ByRefAS = cast<PointerType>(Arg.getType())->getAddressSpace();
550 
551  assert(VRegs[i].size() == 1 &&
552  "expected only one register for byval pointers");
553  if (ByRefAS == AMDGPUAS::CONSTANT_ADDRESS) {
554  lowerParameterPtr(VRegs[i][0], B, ArgOffset);
555  } else {
556  const LLT ConstPtrTy = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
557  Register PtrReg = MRI.createGenericVirtualRegister(ConstPtrTy);
558  lowerParameterPtr(PtrReg, B, ArgOffset);
559 
560  B.buildAddrSpaceCast(VRegs[i][0], PtrReg);
561  }
562  } else {
563  ArgInfo OrigArg(VRegs[i], Arg, i);
564  const unsigned OrigArgIdx = i + AttributeList::FirstArgIndex;
565  setArgFlags(OrigArg, OrigArgIdx, DL, F);
566  lowerParameter(B, OrigArg, ArgOffset, Alignment);
567  }
568 
569  ++i;
570  }
571 
572  TLI.allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
573  TLI.allocateSystemSGPRs(CCInfo, MF, *Info, F.getCallingConv(), false);
574  return true;
575 }
576 
579  FunctionLoweringInfo &FLI) const {
580  CallingConv::ID CC = F.getCallingConv();
581 
582  // The infrastructure for normal calling convention lowering is essentially
583  // useless for kernels. We want to avoid any kind of legalization or argument
584  // splitting.
585  if (CC == CallingConv::AMDGPU_KERNEL)
586  return lowerFormalArgumentsKernel(B, F, VRegs);
587 
588  const bool IsGraphics = AMDGPU::isGraphics(CC);
589  const bool IsEntryFunc = AMDGPU::isEntryFunctionCC(CC);
590 
591  MachineFunction &MF = B.getMF();
592  MachineBasicBlock &MBB = B.getMBB();
595  const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
596  const SIRegisterInfo *TRI = Subtarget.getRegisterInfo();
597  const DataLayout &DL = F.getParent()->getDataLayout();
598 
599  Info->allocateModuleLDSGlobal(F.getParent());
600 
602  CCState CCInfo(CC, F.isVarArg(), MF, ArgLocs, F.getContext());
603 
604  if (!IsEntryFunc) {
605  Register ReturnAddrReg = TRI->getReturnAddressReg(MF);
606  Register LiveInReturn = MF.addLiveIn(ReturnAddrReg,
607  &AMDGPU::SGPR_64RegClass);
608  MBB.addLiveIn(ReturnAddrReg);
609  B.buildCopy(LiveInReturn, ReturnAddrReg);
610  }
611 
612  if (Info->hasImplicitBufferPtr()) {
613  Register ImplicitBufferPtrReg = Info->addImplicitBufferPtr(*TRI);
614  MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
615  CCInfo.AllocateReg(ImplicitBufferPtrReg);
616  }
617 
618  SmallVector<ArgInfo, 32> SplitArgs;
619  unsigned Idx = 0;
620  unsigned PSInputNum = 0;
621 
622  // Insert the hidden sret parameter if the return value won't fit in the
623  // return registers.
624  if (!FLI.CanLowerReturn)
625  insertSRetIncomingArgument(F, SplitArgs, FLI.DemoteRegister, MRI, DL);
626 
627  for (auto &Arg : F.args()) {
628  if (DL.getTypeStoreSize(Arg.getType()) == 0)
629  continue;
630 
631  const bool InReg = Arg.hasAttribute(Attribute::InReg);
632 
633  // SGPR arguments to functions not implemented.
634  if (!IsGraphics && InReg)
635  return false;
636 
637  if (Arg.hasAttribute(Attribute::SwiftSelf) ||
638  Arg.hasAttribute(Attribute::SwiftError) ||
639  Arg.hasAttribute(Attribute::Nest))
640  return false;
641 
642  if (CC == CallingConv::AMDGPU_PS && !InReg && PSInputNum <= 15) {
643  const bool ArgUsed = !Arg.use_empty();
644  bool SkipArg = !ArgUsed && !Info->isPSInputAllocated(PSInputNum);
645 
646  if (!SkipArg) {
647  Info->markPSInputAllocated(PSInputNum);
648  if (ArgUsed)
649  Info->markPSInputEnabled(PSInputNum);
650  }
651 
652  ++PSInputNum;
653 
654  if (SkipArg) {
655  for (Register R : VRegs[Idx])
656  B.buildUndef(R);
657 
658  ++Idx;
659  continue;
660  }
661  }
662 
663  ArgInfo OrigArg(VRegs[Idx], Arg, Idx);
664  const unsigned OrigArgIdx = Idx + AttributeList::FirstArgIndex;
665  setArgFlags(OrigArg, OrigArgIdx, DL, F);
666 
667  splitToValueTypes(OrigArg, SplitArgs, DL, CC);
668  ++Idx;
669  }
670 
671  // At least one interpolation mode must be enabled or else the GPU will
672  // hang.
673  //
674  // Check PSInputAddr instead of PSInputEnable. The idea is that if the user
675  // set PSInputAddr, the user wants to enable some bits after the compilation
676  // based on run-time states. Since we can't know what the final PSInputEna
677  // will look like, so we shouldn't do anything here and the user should take
678  // responsibility for the correct programming.
679  //
680  // Otherwise, the following restrictions apply:
681  // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
682  // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
683  // enabled too.
684  if (CC == CallingConv::AMDGPU_PS) {
685  if ((Info->getPSInputAddr() & 0x7F) == 0 ||
686  ((Info->getPSInputAddr() & 0xF) == 0 &&
687  Info->isPSInputAllocated(11))) {
688  CCInfo.AllocateReg(AMDGPU::VGPR0);
689  CCInfo.AllocateReg(AMDGPU::VGPR1);
690  Info->markPSInputAllocated(0);
691  Info->markPSInputEnabled(0);
692  }
693 
694  if (Subtarget.isAmdPalOS()) {
695  // For isAmdPalOS, the user does not enable some bits after compilation
696  // based on run-time states; the register values being generated here are
697  // the final ones set in hardware. Therefore we need to apply the
698  // workaround to PSInputAddr and PSInputEnable together. (The case where
699  // a bit is set in PSInputAddr but not PSInputEnable is where the frontend
700  // set up an input arg for a particular interpolation mode, but nothing
701  // uses that input arg. Really we should have an earlier pass that removes
702  // such an arg.)
703  unsigned PsInputBits = Info->getPSInputAddr() & Info->getPSInputEnable();
704  if ((PsInputBits & 0x7F) == 0 ||
705  ((PsInputBits & 0xF) == 0 &&
706  (PsInputBits >> 11 & 1)))
707  Info->markPSInputEnabled(
708  countTrailingZeros(Info->getPSInputAddr(), ZB_Undefined));
709  }
710  }
711 
712  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
713  CCAssignFn *AssignFn = TLI.CCAssignFnForCall(CC, F.isVarArg());
714 
715  if (!MBB.empty())
716  B.setInstr(*MBB.begin());
717 
718  if (!IsEntryFunc && !IsGraphics) {
719  // For the fixed ABI, pass workitem IDs in the last argument register.
720  TLI.allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info);
721  }
722 
723  IncomingValueAssigner Assigner(AssignFn);
724  if (!determineAssignments(Assigner, SplitArgs, CCInfo))
725  return false;
726 
727  FormalArgHandler Handler(B, MRI);
728  if (!handleAssignments(Handler, SplitArgs, CCInfo, ArgLocs, B))
729  return false;
730 
731  uint64_t StackOffset = Assigner.StackOffset;
732 
733  // Start adding system SGPRs.
734  if (IsEntryFunc) {
735  TLI.allocateSystemSGPRs(CCInfo, MF, *Info, CC, IsGraphics);
736  } else {
737  if (!Subtarget.enableFlatScratch())
738  CCInfo.AllocateReg(Info->getScratchRSrcReg());
739  TLI.allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
740  }
741 
742  // When we tail call, we need to check if the callee's arguments will fit on
743  // the caller's stack. So, whenever we lower formal arguments, we should keep
744  // track of this information, since we might lower a tail call in this
745  // function later.
746  Info->setBytesInStackArgArea(StackOffset);
747 
748  // Move back to the end of the basic block.
749  B.setMBB(MBB);
750 
751  return true;
752 }
753 
755  CCState &CCInfo,
756  SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs,
757  CallLoweringInfo &Info) const {
758  MachineFunction &MF = MIRBuilder.getMF();
759 
760  // If there's no call site, this doesn't correspond to a call from the IR and
761  // doesn't need implicit inputs.
762  if (!Info.CB)
763  return true;
764 
765  const AMDGPUFunctionArgInfo *CalleeArgInfo
767 
769  const AMDGPUFunctionArgInfo &CallerArgInfo = MFI->getArgInfo();
770 
771 
772  // TODO: Unify with private memory register handling. This is complicated by
773  // the fact that at least in kernels, the input argument is not necessarily
774  // in the same location as the input.
783  };
784 
785  static constexpr StringLiteral ImplicitAttrNames[] = {
786  "amdgpu-no-dispatch-ptr",
787  "amdgpu-no-queue-ptr",
788  "amdgpu-no-implicitarg-ptr",
789  "amdgpu-no-dispatch-id",
790  "amdgpu-no-workgroup-id-x",
791  "amdgpu-no-workgroup-id-y",
792  "amdgpu-no-workgroup-id-z"
793  };
794 
796 
797  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
798  const AMDGPULegalizerInfo *LI
799  = static_cast<const AMDGPULegalizerInfo*>(ST.getLegalizerInfo());
800 
801  unsigned I = 0;
802  for (auto InputID : InputRegs) {
803  const ArgDescriptor *OutgoingArg;
804  const TargetRegisterClass *ArgRC;
805  LLT ArgTy;
806 
807  // If the callee does not use the attribute value, skip copying the value.
808  if (Info.CB->hasFnAttr(ImplicitAttrNames[I++]))
809  continue;
810 
811  std::tie(OutgoingArg, ArgRC, ArgTy) =
812  CalleeArgInfo->getPreloadedValue(InputID);
813  if (!OutgoingArg)
814  continue;
815 
816  const ArgDescriptor *IncomingArg;
817  const TargetRegisterClass *IncomingArgRC;
818  std::tie(IncomingArg, IncomingArgRC, ArgTy) =
819  CallerArgInfo.getPreloadedValue(InputID);
820  assert(IncomingArgRC == ArgRC);
821 
822  Register InputReg = MRI.createGenericVirtualRegister(ArgTy);
823 
824  if (IncomingArg) {
825  LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy);
826  } else if (InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR) {
827  LI->getImplicitArgPtr(InputReg, MRI, MIRBuilder);
828  } else {
829  // We may have proven the input wasn't needed, although the ABI is
830  // requiring it. We just need to allocate the register appropriately.
831  MIRBuilder.buildUndef(InputReg);
832  }
833 
834  if (OutgoingArg->isRegister()) {
835  ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg);
836  if (!CCInfo.AllocateReg(OutgoingArg->getRegister()))
837  report_fatal_error("failed to allocate implicit input argument");
838  } else {
839  LLVM_DEBUG(dbgs() << "Unhandled stack passed implicit input argument\n");
840  return false;
841  }
842  }
843 
844  // Pack workitem IDs into a single register or pass it as is if already
845  // packed.
846  const ArgDescriptor *OutgoingArg;
847  const TargetRegisterClass *ArgRC;
848  LLT ArgTy;
849 
850  std::tie(OutgoingArg, ArgRC, ArgTy) =
852  if (!OutgoingArg)
853  std::tie(OutgoingArg, ArgRC, ArgTy) =
855  if (!OutgoingArg)
856  std::tie(OutgoingArg, ArgRC, ArgTy) =
858  if (!OutgoingArg)
859  return false;
860 
861  auto WorkitemIDX =
862  CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X);
863  auto WorkitemIDY =
864  CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y);
865  auto WorkitemIDZ =
866  CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
867 
868  const ArgDescriptor *IncomingArgX = std::get<0>(WorkitemIDX);
869  const ArgDescriptor *IncomingArgY = std::get<0>(WorkitemIDY);
870  const ArgDescriptor *IncomingArgZ = std::get<0>(WorkitemIDZ);
871  const LLT S32 = LLT::scalar(32);
872 
873  const bool NeedWorkItemIDX = !Info.CB->hasFnAttr("amdgpu-no-workitem-id-x");
874  const bool NeedWorkItemIDY = !Info.CB->hasFnAttr("amdgpu-no-workitem-id-y");
875  const bool NeedWorkItemIDZ = !Info.CB->hasFnAttr("amdgpu-no-workitem-id-z");
876 
877  // If incoming ids are not packed we need to pack them.
878  // FIXME: Should consider known workgroup size to eliminate known 0 cases.
879  Register InputReg;
880  if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo->WorkItemIDX &&
881  NeedWorkItemIDX) {
882  if (ST.getMaxWorkitemID(MF.getFunction(), 0) != 0) {
883  InputReg = MRI.createGenericVirtualRegister(S32);
884  LI->loadInputValue(InputReg, MIRBuilder, IncomingArgX,
885  std::get<1>(WorkitemIDX), std::get<2>(WorkitemIDX));
886  } else {
887  InputReg = MIRBuilder.buildConstant(S32, 0).getReg(0);
888  }
889  }
890 
891  if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo->WorkItemIDY &&
892  NeedWorkItemIDY && ST.getMaxWorkitemID(MF.getFunction(), 1) != 0) {
894  LI->loadInputValue(Y, MIRBuilder, IncomingArgY, std::get<1>(WorkitemIDY),
895  std::get<2>(WorkitemIDY));
896 
897  Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0);
898  InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y;
899  }
900 
901  if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo->WorkItemIDZ &&
902  NeedWorkItemIDZ && ST.getMaxWorkitemID(MF.getFunction(), 2) != 0) {
904  LI->loadInputValue(Z, MIRBuilder, IncomingArgZ, std::get<1>(WorkitemIDZ),
905  std::get<2>(WorkitemIDZ));
906 
907  Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0);
908  InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z;
909  }
910 
911  if (!InputReg &&
912  (NeedWorkItemIDX || NeedWorkItemIDY || NeedWorkItemIDZ)) {
913  InputReg = MRI.createGenericVirtualRegister(S32);
914  if (!IncomingArgX && !IncomingArgY && !IncomingArgZ) {
915  // We're in a situation where the outgoing function requires the workitem
916  // ID, but the calling function does not have it (e.g a graphics function
917  // calling a C calling convention function). This is illegal, but we need
918  // to produce something.
919  MIRBuilder.buildUndef(InputReg);
920  } else {
921  // Workitem ids are already packed, any of present incoming arguments will
922  // carry all required fields.
924  IncomingArgX ? *IncomingArgX :
925  IncomingArgY ? *IncomingArgY : *IncomingArgZ, ~0u);
926  LI->loadInputValue(InputReg, MIRBuilder, &IncomingArg,
927  &AMDGPU::VGPR_32RegClass, S32);
928  }
929  }
930 
931  if (OutgoingArg->isRegister()) {
932  if (InputReg)
933  ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg);
934 
935  if (!CCInfo.AllocateReg(OutgoingArg->getRegister()))
936  report_fatal_error("failed to allocate implicit input argument");
937  } else {
938  LLVM_DEBUG(dbgs() << "Unhandled stack passed implicit input argument\n");
939  return false;
940  }
941 
942  return true;
943 }
944 
945 /// Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for
946 /// CC.
947 static std::pair<CCAssignFn *, CCAssignFn *>
949  return {TLI.CCAssignFnForCall(CC, false), TLI.CCAssignFnForCall(CC, true)};
950 }
951 
952 static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect,
953  bool IsTailCall) {
954  assert(!(IsIndirect && IsTailCall) && "Indirect calls can't be tail calls, "
955  "because the address can be divergent");
956  return IsTailCall ? AMDGPU::SI_TCRETURN : AMDGPU::G_SI_CALL;
957 }
958 
959 // Add operands to call instruction to track the callee.
961  MachineIRBuilder &MIRBuilder,
962  AMDGPUCallLowering::CallLoweringInfo &Info) {
963  if (Info.Callee.isReg()) {
964  CallInst.addReg(Info.Callee.getReg());
965  CallInst.addImm(0);
966  } else if (Info.Callee.isGlobal() && Info.Callee.getOffset() == 0) {
967  // The call lowering lightly assumed we can directly encode a call target in
968  // the instruction, which is not the case. Materialize the address here.
969  const GlobalValue *GV = Info.Callee.getGlobal();
970  auto Ptr = MIRBuilder.buildGlobalValue(
971  LLT::pointer(GV->getAddressSpace(), 64), GV);
972  CallInst.addReg(Ptr.getReg(0));
973  CallInst.add(Info.Callee);
974  } else
975  return false;
976 
977  return true;
978 }
979 
982  SmallVectorImpl<ArgInfo> &InArgs) const {
983  const Function &CallerF = MF.getFunction();
984  CallingConv::ID CalleeCC = Info.CallConv;
985  CallingConv::ID CallerCC = CallerF.getCallingConv();
986 
987  // If the calling conventions match, then everything must be the same.
988  if (CalleeCC == CallerCC)
989  return true;
990 
991  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
992 
993  // Make sure that the caller and callee preserve all of the same registers.
994  auto TRI = ST.getRegisterInfo();
995 
996  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
997  const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
998  if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
999  return false;
1000 
1001  // Check if the caller and callee will handle arguments in the same way.
1002  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
1003  CCAssignFn *CalleeAssignFnFixed;
1004  CCAssignFn *CalleeAssignFnVarArg;
1005  std::tie(CalleeAssignFnFixed, CalleeAssignFnVarArg) =
1006  getAssignFnsForCC(CalleeCC, TLI);
1007 
1008  CCAssignFn *CallerAssignFnFixed;
1009  CCAssignFn *CallerAssignFnVarArg;
1010  std::tie(CallerAssignFnFixed, CallerAssignFnVarArg) =
1011  getAssignFnsForCC(CallerCC, TLI);
1012 
1013  // FIXME: We are not accounting for potential differences in implicitly passed
1014  // inputs, but only the fixed ABI is supported now anyway.
1015  IncomingValueAssigner CalleeAssigner(CalleeAssignFnFixed,
1016  CalleeAssignFnVarArg);
1017  IncomingValueAssigner CallerAssigner(CallerAssignFnFixed,
1018  CallerAssignFnVarArg);
1019  return resultsCompatible(Info, MF, InArgs, CalleeAssigner, CallerAssigner);
1020 }
1021 
1024  SmallVectorImpl<ArgInfo> &OutArgs) const {
1025  // If there are no outgoing arguments, then we are done.
1026  if (OutArgs.empty())
1027  return true;
1028 
1029  const Function &CallerF = MF.getFunction();
1030  CallingConv::ID CalleeCC = Info.CallConv;
1031  CallingConv::ID CallerCC = CallerF.getCallingConv();
1032  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
1033 
1034  CCAssignFn *AssignFnFixed;
1035  CCAssignFn *AssignFnVarArg;
1036  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
1037 
1038  // We have outgoing arguments. Make sure that we can tail call with them.
1040  CCState OutInfo(CalleeCC, false, MF, OutLocs, CallerF.getContext());
1041  OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg);
1042 
1043  if (!determineAssignments(Assigner, OutArgs, OutInfo)) {
1044  LLVM_DEBUG(dbgs() << "... Could not analyze call operands.\n");
1045  return false;
1046  }
1047 
1048  // Make sure that they can fit on the caller's stack.
1049  const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
1050  if (OutInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea()) {
1051  LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
1052  return false;
1053  }
1054 
1055  // Verify that the parameters in callee-saved registers match.
1056  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1057  const SIRegisterInfo *TRI = ST.getRegisterInfo();
1058  const uint32_t *CallerPreservedMask = TRI->getCallPreservedMask(MF, CallerCC);
1060  return parametersInCSRMatch(MRI, CallerPreservedMask, OutLocs, OutArgs);
1061 }
1062 
1063 /// Return true if the calling convention is one that we can guarantee TCO for.
1065  return CC == CallingConv::Fast;
1066 }
1067 
1068 /// Return true if we might ever do TCO for calls with this calling convention.
1070  switch (CC) {
1071  case CallingConv::C:
1073  return true;
1074  default:
1075  return canGuaranteeTCO(CC);
1076  }
1077 }
1078 
1081  SmallVectorImpl<ArgInfo> &InArgs, SmallVectorImpl<ArgInfo> &OutArgs) const {
1082  // Must pass all target-independent checks in order to tail call optimize.
1083  if (!Info.IsTailCall)
1084  return false;
1085 
1086  // Indirect calls can't be tail calls, because the address can be divergent.
1087  // TODO Check divergence info if the call really is divergent.
1088  if (Info.Callee.isReg())
1089  return false;
1090 
1091  MachineFunction &MF = B.getMF();
1092  const Function &CallerF = MF.getFunction();
1093  CallingConv::ID CalleeCC = Info.CallConv;
1094  CallingConv::ID CallerCC = CallerF.getCallingConv();
1095 
1096  const SIRegisterInfo *TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
1097  const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
1098  // Kernels aren't callable, and don't have a live in return address so it
1099  // doesn't make sense to do a tail call with entry functions.
1100  if (!CallerPreserved)
1101  return false;
1102 
1103  if (!mayTailCallThisCC(CalleeCC)) {
1104  LLVM_DEBUG(dbgs() << "... Calling convention cannot be tail called.\n");
1105  return false;
1106  }
1107 
1108  if (any_of(CallerF.args(), [](const Argument &A) {
1109  return A.hasByValAttr() || A.hasSwiftErrorAttr();
1110  })) {
1111  LLVM_DEBUG(dbgs() << "... Cannot tail call from callers with byval "
1112  "or swifterror arguments\n");
1113  return false;
1114  }
1115 
1116  // If we have -tailcallopt, then we're done.
1118  return canGuaranteeTCO(CalleeCC) && CalleeCC == CallerF.getCallingConv();
1119 
1120  // Verify that the incoming and outgoing arguments from the callee are
1121  // safe to tail call.
1122  if (!doCallerAndCalleePassArgsTheSameWay(Info, MF, InArgs)) {
1123  LLVM_DEBUG(
1124  dbgs()
1125  << "... Caller and callee have incompatible calling conventions.\n");
1126  return false;
1127  }
1128 
1129  if (!areCalleeOutgoingArgsTailCallable(Info, MF, OutArgs))
1130  return false;
1131 
1132  LLVM_DEBUG(dbgs() << "... Call is eligible for tail call optimization.\n");
1133  return true;
1134 }
1135 
1136 // Insert outgoing implicit arguments for a call, by inserting copies to the
1137 // implicit argument registers and adding the necessary implicit uses to the
1138 // call instruction.
1141  const GCNSubtarget &ST, const SIMachineFunctionInfo &FuncInfo,
1142  ArrayRef<std::pair<MCRegister, Register>> ImplicitArgRegs) const {
1143  if (!ST.enableFlatScratch()) {
1144  // Insert copies for the SRD. In the HSA case, this should be an identity
1145  // copy.
1146  auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::fixed_vector(4, 32),
1147  FuncInfo.getScratchRSrcReg());
1148  MIRBuilder.buildCopy(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);
1149  CallInst.addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Implicit);
1150  }
1151 
1152  for (std::pair<MCRegister, Register> ArgReg : ImplicitArgRegs) {
1153  MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second);
1154  CallInst.addReg(ArgReg.first, RegState::Implicit);
1155  }
1156 }
1157 
1159  MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info,
1160  SmallVectorImpl<ArgInfo> &OutArgs) const {
1161  MachineFunction &MF = MIRBuilder.getMF();
1162  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1164  const Function &F = MF.getFunction();
1166  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
1167 
1168  // True when we're tail calling, but without -tailcallopt.
1169  bool IsSibCall = !MF.getTarget().Options.GuaranteedTailCallOpt;
1170 
1171  // Find out which ABI gets to decide where things go.
1172  CallingConv::ID CalleeCC = Info.CallConv;
1173  CCAssignFn *AssignFnFixed;
1174  CCAssignFn *AssignFnVarArg;
1175  std::tie(AssignFnFixed, AssignFnVarArg) = getAssignFnsForCC(CalleeCC, TLI);
1176 
1177  MachineInstrBuilder CallSeqStart;
1178  if (!IsSibCall)
1179  CallSeqStart = MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP);
1180 
1181  unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), true);
1182  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1183  if (!addCallTargetOperands(MIB, MIRBuilder, Info))
1184  return false;
1185 
1186  // Byte offset for the tail call. When we are sibcalling, this will always
1187  // be 0.
1188  MIB.addImm(0);
1189 
1190  // Tell the call which registers are clobbered.
1191  const SIRegisterInfo *TRI = ST.getRegisterInfo();
1192  const uint32_t *Mask = TRI->getCallPreservedMask(MF, CalleeCC);
1193  MIB.addRegMask(Mask);
1194 
1195  // FPDiff is the byte offset of the call's argument area from the callee's.
1196  // Stores to callee stack arguments will be placed in FixedStackSlots offset
1197  // by this amount for a tail call. In a sibling call it must be 0 because the
1198  // caller will deallocate the entire stack and the callee still expects its
1199  // arguments to begin at SP+0.
1200  int FPDiff = 0;
1201 
1202  // This will be 0 for sibcalls, potentially nonzero for tail calls produced
1203  // by -tailcallopt. For sibcalls, the memory operands for the call are
1204  // already available in the caller's incoming argument space.
1205  unsigned NumBytes = 0;
1206  if (!IsSibCall) {
1207  // We aren't sibcalling, so we need to compute FPDiff. We need to do this
1208  // before handling assignments, because FPDiff must be known for memory
1209  // arguments.
1210  unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
1212  CCState OutInfo(CalleeCC, false, MF, OutLocs, F.getContext());
1213 
1214  // FIXME: Not accounting for callee implicit inputs
1215  OutgoingValueAssigner CalleeAssigner(AssignFnFixed, AssignFnVarArg);
1216  if (!determineAssignments(CalleeAssigner, OutArgs, OutInfo))
1217  return false;
1218 
1219  // The callee will pop the argument stack as a tail call. Thus, we must
1220  // keep it 16-byte aligned.
1221  NumBytes = alignTo(OutInfo.getNextStackOffset(), ST.getStackAlignment());
1222 
1223  // FPDiff will be negative if this tail call requires more space than we
1224  // would automatically have in our incoming argument space. Positive if we
1225  // actually shrink the stack.
1226  FPDiff = NumReusableBytes - NumBytes;
1227 
1228  // The stack pointer must be 16-byte aligned at all times it's used for a
1229  // memory operation, which in practice means at *all* times and in
1230  // particular across call boundaries. Therefore our own arguments started at
1231  // a 16-byte aligned SP and the delta applied for the tail call should
1232  // satisfy the same constraint.
1233  assert(isAligned(ST.getStackAlignment(), FPDiff) &&
1234  "unaligned stack on tail call");
1235  }
1236 
1238  CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext());
1239 
1240  // We could pass MIB and directly add the implicit uses to the call
1241  // now. However, as an aesthetic choice, place implicit argument operands
1242  // after the ordinary user argument registers.
1243  SmallVector<std::pair<MCRegister, Register>, 12> ImplicitArgRegs;
1244 
1245  if (Info.CallConv != CallingConv::AMDGPU_Gfx) {
1246  // With a fixed ABI, allocate fixed registers before user arguments.
1247  if (!passSpecialInputs(MIRBuilder, CCInfo, ImplicitArgRegs, Info))
1248  return false;
1249  }
1250 
1251  OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg);
1252 
1253  if (!determineAssignments(Assigner, OutArgs, CCInfo))
1254  return false;
1255 
1256  // Do the actual argument marshalling.
1257  AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, true, FPDiff);
1258  if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder))
1259  return false;
1260 
1261  handleImplicitCallArguments(MIRBuilder, MIB, ST, *FuncInfo, ImplicitArgRegs);
1262 
1263  // If we have -tailcallopt, we need to adjust the stack. We'll do the call
1264  // sequence start and end here.
1265  if (!IsSibCall) {
1266  MIB->getOperand(1).setImm(FPDiff);
1267  CallSeqStart.addImm(NumBytes).addImm(0);
1268  // End the call sequence *before* emitting the call. Normally, we would
1269  // tidy the frame up after the call. However, here, we've laid out the
1270  // parameters so that when SP is reset, they will be in the correct
1271  // location.
1272  MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN).addImm(NumBytes).addImm(0);
1273  }
1274 
1275  // Now we can add the actual call instruction to the correct basic block.
1276  MIRBuilder.insertInstr(MIB);
1277 
1278  // If Callee is a reg, since it is used by a target specific
1279  // instruction, it must have a register class matching the
1280  // constraint of that instruction.
1281 
1282  // FIXME: We should define regbankselectable call instructions to handle
1283  // divergent call targets.
1284  if (MIB->getOperand(0).isReg()) {
1286  MF, *TRI, MRI, *ST.getInstrInfo(), *ST.getRegBankInfo(), *MIB,
1287  MIB->getDesc(), MIB->getOperand(0), 0));
1288  }
1289 
1291  Info.LoweredTailCall = true;
1292  return true;
1293 }
1294 
1296  CallLoweringInfo &Info) const {
1297  if (Info.IsVarArg) {
1298  LLVM_DEBUG(dbgs() << "Variadic functions not implemented\n");
1299  return false;
1300  }
1301 
1302  MachineFunction &MF = MIRBuilder.getMF();
1303  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1304  const SIRegisterInfo *TRI = ST.getRegisterInfo();
1305 
1306  const Function &F = MF.getFunction();
1308  const SITargetLowering &TLI = *getTLI<SITargetLowering>();
1309  const DataLayout &DL = F.getParent()->getDataLayout();
1310 
1311  SmallVector<ArgInfo, 8> OutArgs;
1312  for (auto &OrigArg : Info.OrigArgs)
1313  splitToValueTypes(OrigArg, OutArgs, DL, Info.CallConv);
1314 
1315  SmallVector<ArgInfo, 8> InArgs;
1316  if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy())
1317  splitToValueTypes(Info.OrigRet, InArgs, DL, Info.CallConv);
1318 
1319  // If we can lower as a tail call, do that instead.
1320  bool CanTailCallOpt =
1321  isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs);
1322 
1323  // We must emit a tail call if we have musttail.
1324  if (Info.IsMustTailCall && !CanTailCallOpt) {
1325  LLVM_DEBUG(dbgs() << "Failed to lower musttail call as tail call\n");
1326  return false;
1327  }
1328 
1329  if (CanTailCallOpt)
1330  return lowerTailCall(MIRBuilder, Info, OutArgs);
1331 
1332  // Find out which ABI gets to decide where things go.
1333  CCAssignFn *AssignFnFixed;
1334  CCAssignFn *AssignFnVarArg;
1335  std::tie(AssignFnFixed, AssignFnVarArg) =
1336  getAssignFnsForCC(Info.CallConv, TLI);
1337 
1338  MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP)
1339  .addImm(0)
1340  .addImm(0);
1341 
1342  // Create a temporarily-floating call instruction so we can add the implicit
1343  // uses of arg registers.
1344  unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), false);
1345 
1346  auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
1347  MIB.addDef(TRI->getReturnAddressReg(MF));
1348 
1349  if (!addCallTargetOperands(MIB, MIRBuilder, Info))
1350  return false;
1351 
1352  // Tell the call which registers are clobbered.
1353  const uint32_t *Mask = TRI->getCallPreservedMask(MF, Info.CallConv);
1354  MIB.addRegMask(Mask);
1355 
1357  CCState CCInfo(Info.CallConv, Info.IsVarArg, MF, ArgLocs, F.getContext());
1358 
1359  // We could pass MIB and directly add the implicit uses to the call
1360  // now. However, as an aesthetic choice, place implicit argument operands
1361  // after the ordinary user argument registers.
1362  SmallVector<std::pair<MCRegister, Register>, 12> ImplicitArgRegs;
1363 
1364  if (Info.CallConv != CallingConv::AMDGPU_Gfx) {
1365  // With a fixed ABI, allocate fixed registers before user arguments.
1366  if (!passSpecialInputs(MIRBuilder, CCInfo, ImplicitArgRegs, Info))
1367  return false;
1368  }
1369 
1370  // Do the actual argument marshalling.
1371  SmallVector<Register, 8> PhysRegs;
1372 
1373  OutgoingValueAssigner Assigner(AssignFnFixed, AssignFnVarArg);
1374  if (!determineAssignments(Assigner, OutArgs, CCInfo))
1375  return false;
1376 
1377  AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, false);
1378  if (!handleAssignments(Handler, OutArgs, CCInfo, ArgLocs, MIRBuilder))
1379  return false;
1380 
1382 
1383  handleImplicitCallArguments(MIRBuilder, MIB, ST, *MFI, ImplicitArgRegs);
1384 
1385  // Get a count of how many bytes are to be pushed on the stack.
1386  unsigned NumBytes = CCInfo.getNextStackOffset();
1387 
1388  // If Callee is a reg, since it is used by a target specific
1389  // instruction, it must have a register class matching the
1390  // constraint of that instruction.
1391 
1392  // FIXME: We should define regbankselectable call instructions to handle
1393  // divergent call targets.
1394  if (MIB->getOperand(1).isReg()) {
1395  MIB->getOperand(1).setReg(constrainOperandRegClass(
1396  MF, *TRI, MRI, *ST.getInstrInfo(),
1397  *ST.getRegBankInfo(), *MIB, MIB->getDesc(), MIB->getOperand(1),
1398  1));
1399  }
1400 
1401  // Now we can add the actual call instruction to the correct position.
1402  MIRBuilder.insertInstr(MIB);
1403 
1404  // Finally we can copy the returned value back into its virtual-register. In
1405  // symmetry with the arguments, the physical register must be an
1406  // implicit-define of the call instruction.
1407  if (Info.CanLowerReturn && !Info.OrigRet.Ty->isVoidTy()) {
1408  CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(Info.CallConv,
1409  Info.IsVarArg);
1410  IncomingValueAssigner Assigner(RetAssignFn);
1411  CallReturnHandler Handler(MIRBuilder, MRI, MIB);
1412  if (!determineAndHandleAssignments(Handler, Assigner, InArgs, MIRBuilder,
1413  Info.CallConv, Info.IsVarArg))
1414  return false;
1415  }
1416 
1417  uint64_t CalleePopBytes = NumBytes;
1418 
1419  MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN)
1420  .addImm(0)
1421  .addImm(CalleePopBytes);
1422 
1423  if (!Info.CanLowerReturn) {
1424  insertSRetLoads(MIRBuilder, Info.OrigRet.Ty, Info.OrigRet.Regs,
1425  Info.DemoteRegister, Info.DemoteStackIndex);
1426  }
1427 
1428  return true;
1429 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::CCValAssign::getLocVT
MVT getLocVT() const
Definition: CallingConvLower.h:153
llvm::MachineRegisterInfo::addLiveIn
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
Definition: MachineRegisterInfo.h:957
i
i
Definition: README.txt:29
llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:148
llvm::AMDGPUFunctionArgInfo::PreloadedValue
PreloadedValue
Definition: AMDGPUArgumentUsageInfo.h:98
llvm::SIMachineFunctionInfo::setIfReturnsVoid
void setIfReturnsVoid(bool Value)
Definition: SIMachineFunctionInfo.h:854
llvm::AMDGPUFunctionArgInfo::QUEUE_PTR
@ QUEUE_PTR
Definition: AMDGPUArgumentUsageInfo.h:102
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::AMDGPUCallLowering::handleImplicitCallArguments
void handleImplicitCallArguments(MachineIRBuilder &MIRBuilder, MachineInstrBuilder &CallInst, const GCNSubtarget &ST, const SIMachineFunctionInfo &MFI, ArrayRef< std::pair< MCRegister, Register >> ImplicitArgRegs) const
Definition: AMDGPUCallLowering.cpp:1139
llvm::isAligned
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
Definition: Alignment.h:138
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::TargetOptions::GuaranteedTailCallOpt
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
Definition: TargetOptions.h:219
llvm::MachineIRBuilder::buildGlobalValue
MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV)
Build and insert Res = G_GLOBAL_VALUE GV.
Definition: MachineIRBuilder.cpp:146
Reg
unsigned Reg
Definition: MachineSink.cpp:1558
llvm::Function::args
iterator_range< arg_iterator > args()
Definition: Function.h:762
llvm::MachineIRBuilder::buildOr
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Build and insert Res = G_OR Op0, Op1.
Definition: MachineIRBuilder.h:1548
llvm::EVT::isScalarInteger
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
Definition: ValueTypes.h:150
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::SIMachineFunctionInfo::getPreloadedReg
MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const
Definition: SIMachineFunctionInfo.h:710
llvm::LLT::getScalarSizeInBits
unsigned getScalarSizeInBits() const
Definition: LowLevelTypeImpl.h:212
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::AMDGPUTargetLowering
Definition: AMDGPUISelLowering.h:27
llvm::CallLowering::handleAssignments
bool handleAssignments(ValueHandler &Handler, SmallVectorImpl< ArgInfo > &Args, CCState &CCState, SmallVectorImpl< CCValAssign > &ArgLocs, MachineIRBuilder &MIRBuilder, Register ThisReturnReg=Register()) const
Use Handler to insert code to handle the argument/return values represented by Args.
Definition: CallLowering.cpp:594
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:191
SIMachineFunctionInfo.h
llvm::ArgDescriptor::createArg
static constexpr ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask)
Definition: AMDGPUArgumentUsageInfo.h:54
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::SITargetLowering::allocateSystemSGPRs
void allocateSystemSGPRs(CCState &CCInfo, MachineFunction &MF, SIMachineFunctionInfo &Info, CallingConv::ID CallConv, bool IsShader) const
Definition: SIISelLowering.cpp:2145
llvm::ArgDescriptor
Definition: AMDGPUArgumentUsageInfo.h:23
llvm::Function
Definition: Function.h:62
allocateHSAUserSGPRs
static void allocateHSAUserSGPRs(CCState &CCInfo, MachineIRBuilder &B, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info)
Definition: AMDGPUCallLowering.cpp:452
llvm::AMDGPUCallLowering::AMDGPUCallLowering
AMDGPUCallLowering(const AMDGPUTargetLowering &TLI)
Definition: AMDGPUCallLowering.cpp:235
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
llvm::SIMachineFunctionInfo::getArgInfo
AMDGPUFunctionArgInfo & getArgInfo()
Definition: SIMachineFunctionInfo.h:697
llvm::MachineFunction::getMachineMemOperand
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Definition: MachineFunction.cpp:435
llvm::CallLowering::ValueHandler::extendRegister
Register extendRegister(Register ValReg, CCValAssign &VA, unsigned MaxSizeBits=0)
Extend a register to the location type given in VA, capped at extending to at most MaxSize bits.
Definition: CallLowering.cpp:1078
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:210
llvm::MachineRegisterInfo::getTargetRegisterInfo
const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:145
llvm::AMDGPUArgumentUsageInfo::FixedABIFunctionInfo
static const AMDGPUFunctionArgInfo FixedABIFunctionInfo
Definition: AMDGPUArgumentUsageInfo.h:166
llvm::CallLowering::ValueHandler
Definition: CallLowering.h:225
llvm::ISD::ANY_EXTEND
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:732
llvm::Function::getContext
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:321
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::CallLowering::OutgoingValueHandler
Base class for ValueHandlers used for arguments passed to a function call, or for return values.
Definition: CallLowering.h:329
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:128
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:143
llvm::MachineRegisterInfo::getLiveInVirtReg
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in virtual r...
Definition: MachineRegisterInfo.cpp:452
llvm::CallLowering::splitToValueTypes
void splitToValueTypes(const ArgInfo &OrigArgInfo, SmallVectorImpl< ArgInfo > &SplitArgs, const DataLayout &DL, CallingConv::ID CallConv, SmallVectorImpl< uint64_t > *Offsets=nullptr) const
Break OrigArgInfo into one or more pieces the calling convention can process, returned in SplitArgs.
Definition: CallLowering.cpp:212
addCallTargetOperands
static bool addCallTargetOperands(MachineInstrBuilder &CallInst, MachineIRBuilder &MIRBuilder, AMDGPUCallLowering::CallLoweringInfo &Info)
Definition: AMDGPUCallLowering.cpp:960
llvm::AMDGPUCallLowering::lowerCall
bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override
This hook must be implemented to lower the given call instruction, including argument and return valu...
Definition: AMDGPUCallLowering.cpp:1295
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:80
llvm::LLT::vector
static LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:56
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
llvm::MachineIRBuilder::buildInstrNoInsert
MachineInstrBuilder buildInstrNoInsert(unsigned Opcode)
Build but don't insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.cpp:40
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
MachineIRBuilder.h
llvm::AMDGPUCallLowering::isEligibleForTailCallOptimization
bool isEligibleForTailCallOptimization(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &InArgs, SmallVectorImpl< ArgInfo > &OutArgs) const
Returns true if the call can be lowered as a tail call.
Definition: AMDGPUCallLowering.cpp:1079
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::FunctionLoweringInfo::CanLowerReturn
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
Definition: FunctionLoweringInfo.h:62
llvm::ZB_Undefined
@ ZB_Undefined
The returned value is undefined.
Definition: MathExtras.h:46
llvm::GCNSubtarget::getRegisterInfo
const SIRegisterInfo * getRegisterInfo() const override
Definition: GCNSubtarget.h:219
llvm::ArrayRef::empty
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:158
extOpcodeToISDExtOpcode
static ISD::NodeType extOpcodeToISDExtOpcode(unsigned MIOpc)
Definition: AMDGPUCallLowering.cpp:240
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_X
@ WORKGROUP_ID_X
Definition: AMDGPUArgumentUsageInfo.h:106
llvm::AMDGPULegalizerInfo
This class provides the information for the target register banks.
Definition: AMDGPULegalizerInfo.h:31
llvm::MachineIRBuilder::buildConstant
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
Definition: MachineIRBuilder.cpp:297
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::ComputeValueVTs
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:124
llvm::AMDGPU::isKernel
LLVM_READNONE bool isKernel(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.h:723
llvm::getLLTForType
LLT getLLTForType(Type &Ty, const DataLayout &DL)
Construct a low-level type based on an LLVM type.
Definition: LowLevelType.cpp:21
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::LLT::fixed_vector
static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
Definition: LowLevelTypeImpl.h:74
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:185
llvm::SIMachineFunctionInfo::returnsVoid
bool returnsVoid() const
Definition: SIMachineFunctionInfo.h:850
llvm::MachineInstrBuilder::addDef
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Definition: MachineInstrBuilder.h:116
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:890
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
llvm::FunctionLoweringInfo::DemoteRegister
Register DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
Definition: FunctionLoweringInfo.h:69
llvm::AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR
@ KERNARG_SEGMENT_PTR
Definition: AMDGPUArgumentUsageInfo.h:103
llvm::AMDGPUFunctionArgInfo
Definition: AMDGPUArgumentUsageInfo.h:97
llvm::CallLowering::resultsCompatible
bool resultsCompatible(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs, ValueAssigner &CalleeAssigner, ValueAssigner &CallerAssigner) const
Definition: CallLowering.cpp:978
llvm::CCValAssign
CCValAssign - Represent assignment of one arg/retval to a location.
Definition: CallingConvLower.h:33
llvm::AMDGPU::isShader
bool isShader(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1369
llvm::AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR
@ IMPLICIT_ARG_PTR
Definition: AMDGPUArgumentUsageInfo.h:111
llvm::CallingConv::Fast
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
llvm::ISD::ZERO_EXTEND
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:729
llvm::MachineIRBuilder::buildShl
MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, Optional< unsigned > Flags=None)
Definition: MachineIRBuilder.h:1504
llvm::ISD::ArgFlagsTy::isByVal
bool isByVal() const
Definition: TargetCallingConv.h:85
FunctionLoweringInfo.h
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:739
llvm::AMDGPUFunctionArgInfo::WorkItemIDX
ArgDescriptor WorkItemIDX
Definition: AMDGPUArgumentUsageInfo.h:148
llvm::CallLowering::ArgInfo
Definition: CallLowering.h:61
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:499
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Y
@ WORKITEM_ID_Y
Definition: AMDGPUArgumentUsageInfo.h:115
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:364
llvm::FormalArgHandler
Definition: M68kCallLowering.h:65
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:109
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::CallLowering::OutgoingValueAssigner
Definition: CallLowering.h:219
llvm::AMDGPUCallLowering::lowerFormalArgumentsKernel
bool lowerFormalArgumentsKernel(MachineIRBuilder &B, const Function &F, ArrayRef< ArrayRef< Register >> VRegs) const
Definition: AMDGPUCallLowering.cpp:503
llvm::CallLowering::determineAssignments
bool determineAssignments(ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, CCState &CCInfo) const
Analyze the argument list in Args, using Assigner to populate CCInfo.
Definition: CallLowering.cpp:533
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:362
llvm::SIMachineFunctionInfo::getStackPtrOffsetReg
Register getStackPtrOffsetReg() const
Definition: SIMachineFunctionInfo.h:770
llvm::MachineIRBuilder::getMF
MachineFunction & getMF()
Getter for the function we currently build.
Definition: MachineIRBuilder.h:262
llvm::CallLowering::IncomingValueHandler
Base class for ValueHandlers used for arguments coming into the current function, or for return value...
Definition: CallLowering.h:314
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::AMDGPUCallLowering::passSpecialInputs
bool passSpecialInputs(MachineIRBuilder &MIRBuilder, CCState &CCInfo, SmallVectorImpl< std::pair< MCRegister, Register >> &ArgRegs, CallLoweringInfo &Info) const
Definition: AMDGPUCallLowering.cpp:754
llvm::CCValAssign::getLocInfo
LocInfo getLocInfo() const
Definition: CallingConvLower.h:155
llvm::CCValAssign::getLocMemOffset
unsigned getLocMemOffset() const
Definition: CallingConvLower.h:151
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::None
const NoneType None
Definition: None.h:23
llvm::EVT::getTypeForEVT
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:181
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineInstrBuilder::getReg
Register getReg(unsigned Idx) const
Get the register for the operand index.
Definition: MachineInstrBuilder.h:94
llvm::AMDGPUTargetLowering::getTypeForExtReturn
EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType ExtendKind) const override
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
Definition: AMDGPUISelLowering.cpp:731
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::SITargetLowering::allocateSpecialInputVGPRsFixed
void allocateSpecialInputVGPRsFixed(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Allocate implicit function VGPR arguments in fixed registers.
Definition: SIISelLowering.cpp:2042
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1392
llvm::AMDGPUCallLowering::lowerTailCall
bool lowerTailCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, SmallVectorImpl< ArgInfo > &OutArgs) const
Definition: AMDGPUCallLowering.cpp:1158
llvm::CCAssignFn
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change.
Definition: CallingConvLower.h:177
llvm::TargetRegisterInfo::regmaskSubsetEqual
bool regmaskSubsetEqual(const uint32_t *mask0, const uint32_t *mask1) const
Return true if all bits that are set in mask mask0 are also set in mask1.
Definition: TargetRegisterInfo.cpp:491
llvm::LLT::pointer
static LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
Definition: LowLevelTypeImpl.h:49
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
llvm::AttributeList::ReturnIndex
@ ReturnIndex
Definition: Attributes.h:407
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::AMDGPUFunctionArgInfo::getPreloadedValue
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(PreloadedValue Value) const
Definition: AMDGPUArgumentUsageInfo.cpp:89
llvm::MachineIRBuilder
Helper class to build MachineInstr.
Definition: MachineIRBuilder.h:212
llvm::AMDGPUCallLowering::doCallerAndCalleePassArgsTheSameWay
bool doCallerAndCalleePassArgsTheSameWay(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &InArgs) const
Definition: AMDGPUCallLowering.cpp:980
llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Z
@ WORKGROUP_ID_Z
Definition: AMDGPUArgumentUsageInfo.h:108
canGuaranteeTCO
static bool canGuaranteeTCO(CallingConv::ID CC)
Return true if the calling convention is one that we can guarantee TCO for.
Definition: AMDGPUCallLowering.cpp:1064
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_Z
@ WORKITEM_ID_Z
Definition: AMDGPUArgumentUsageInfo.h:116
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:240
llvm::CallLowering::checkReturn
bool checkReturn(CCState &CCInfo, SmallVectorImpl< BaseArgInfo > &Outs, CCAssignFn *Fn) const
Definition: CallLowering.cpp:881
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:79
llvm::AMDGPUTargetLowering::CCAssignFnForReturn
static CCAssignFn * CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg)
Definition: AMDGPUISelLowering.cpp:1192
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::AMDGPUFunctionArgInfo::WORKITEM_ID_X
@ WORKITEM_ID_X
Definition: AMDGPUArgumentUsageInfo.h:114
llvm::MachineIRBuilder::buildPtrAdd
MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1)
Build and insert Res = G_PTR_ADD Op0, Op1.
Definition: MachineIRBuilder.cpp:182
llvm::inferAlignFromPtrInfo
Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO)
Definition: Utils.cpp:686
I
#define I(x, y, z)
Definition: MD5.cpp:58
Analysis.h
llvm::LLT::isVector
bool isVector() const
Definition: LowLevelTypeImpl.h:122
llvm::MachineFrameInfo::setHasTailCall
void setHasTailCall(bool V=true)
Definition: MachineFrameInfo.h:607
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:121
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineFrameInfo::CreateFixedObject
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
Definition: MachineFrameInfo.cpp:83
llvm::FunctionLoweringInfo
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
Definition: FunctionLoweringInfo.h:52
llvm::MVT::getSizeInBits
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
Definition: MachineValueType.h:864
llvm::MachineIRBuilder::getMBB
const MachineBasicBlock & getMBB() const
Getter for the basic block we currently build.
Definition: MachineIRBuilder.h:287
llvm::AMDGPUTargetLowering::CCAssignFnForCall
static CCAssignFn * CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg)
Selects the correct CCAssignFn for a given CallingConvention value.
Definition: AMDGPUISelLowering.cpp:1187
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:657
llvm::MachineRegisterInfo::createGenericVirtualRegister
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Definition: MachineRegisterInfo.cpp:188
llvm::MachineInstrBuilder::addUse
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Definition: MachineInstrBuilder.h:123
llvm::AMDGPUSubtarget::getExplicitKernelArgOffset
unsigned getExplicitKernelArgOffset(const Function &F) const
Returns the offset in bytes from the start of the input buffer of the first explicit kernel argument.
Definition: AMDGPUSubtarget.h:214
llvm::AMDGPUFunctionArgInfo::WorkItemIDZ
ArgDescriptor WorkItemIDZ
Definition: AMDGPUArgumentUsageInfo.h:150
llvm::ArgDescriptor::isRegister
bool isRegister() const
Definition: AMDGPUArgumentUsageInfo.h:67
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineFunction::addLiveIn
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Definition: MachineFunction.cpp:658
llvm::size
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1630
llvm::MachineIRBuilder::buildInstr
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
Definition: MachineIRBuilder.h:367
llvm::AMDGPUFunctionArgInfo::DISPATCH_ID
@ DISPATCH_ID
Definition: AMDGPUArgumentUsageInfo.h:104
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::CCState::AllocateReg
MCRegister AllocateReg(MCPhysReg Reg)
AllocateReg - Attempt to allocate one register.
Definition: CallingConvLower.h:351
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1656
llvm::countTrailingZeros
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
Definition: MathExtras.h:156
AMDGPU.h
llvm::MachineIRBuilder::insertInstr
MachineInstrBuilder insertInstr(MachineInstrBuilder MIB)
Insert an existing instruction at the insertion point.
Definition: MachineIRBuilder.cpp:45
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
llvm::CallLowering::insertSRetLoads
void insertSRetLoads(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg, int FI) const
Load the returned value from the stack into virtual registers in VRegs.
Definition: CallLowering.cpp:776
llvm::MachineIRBuilder::buildCopy
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
Definition: MachineIRBuilder.cpp:280
llvm::ArgDescriptor::isMasked
bool isMasked() const
Definition: AMDGPUArgumentUsageInfo.h:85
uint32_t
llvm::StackOffset
StackOffset is a class to represent an offset with 2 dimensions, named fixed and scalable,...
Definition: TypeSize.h:134
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::AMDGPU::isGraphics
bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1384
getAssignFnsForCC
static std::pair< CCAssignFn *, CCAssignFn * > getAssignFnsForCC(CallingConv::ID CC, const SITargetLowering &TLI)
Returns a pair containing the fixed CCAssignFn and the vararg CCAssignFn for CC.
Definition: AMDGPUCallLowering.cpp:948
llvm::SIMachineFunctionInfo::getScratchRSrcReg
Register getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses.
Definition: SIMachineFunctionInfo.h:743
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::MachineIRBuilder::buildAnyExt
MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op)
Build and insert Res = G_ANYEXT Op0.
Definition: MachineIRBuilder.cpp:456
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineBasicBlock::addLiveIn
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Definition: MachineBasicBlock.h:371
llvm::MachineIRBuilder::buildFrameIndex
MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx)
Build and insert Res = G_FRAME_INDEX Idx.
Definition: MachineIRBuilder.cpp:137
llvm::CallLowering::insertSRetIncomingArgument
void insertSRetIncomingArgument(const Function &F, SmallVectorImpl< ArgInfo > &SplitArgs, Register &DemoteReg, MachineRegisterInfo &MRI, const DataLayout &DL) const
Insert the hidden sret ArgInfo to the beginning of SplitArgs.
Definition: CallLowering.cpp:837
llvm::SITargetLowering::allocateSpecialEntryInputVGPRs
void allocateSpecialEntryInputVGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:1899
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
mayTailCallThisCC
static bool mayTailCallThisCC(CallingConv::ID CC)
Return true if we might ever do TCO for calls with this calling convention.
Definition: AMDGPUCallLowering.cpp:1069
llvm::CallLowering::insertSRetStores
void insertSRetStores(MachineIRBuilder &MIRBuilder, Type *RetTy, ArrayRef< Register > VRegs, Register DemoteReg) const
Store the return value given by VRegs into stack starting at the offset specified in DemoteReg.
Definition: CallLowering.cpp:806
llvm::commonAlignment
Align commonAlignment(Align A, Align B)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:211
llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Y
@ WORKGROUP_ID_Y
Definition: AMDGPUArgumentUsageInfo.h:107
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:607
llvm::CallLowering::ValueHandler::MRI
MachineRegisterInfo & MRI
Definition: CallLowering.h:227
llvm::MachineFunction::getTarget
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Definition: MachineFunction.h:637
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::MachineIRBuilder::buildUndef
MachineInstrBuilder buildUndef(const DstOp &Res)
Build and insert Res = IMPLICIT_DEF.
Definition: MachineIRBuilder.cpp:624
llvm::CallLowering::determineAndHandleAssignments
bool determineAndHandleAssignments(ValueHandler &Handler, ValueAssigner &Assigner, SmallVectorImpl< ArgInfo > &Args, MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv, bool IsVarArg, Register ThisReturnReg=Register()) const
Invoke ValueAssigner::assignArg on each of the given Args and then use Handler to move them to the as...
Definition: CallLowering.cpp:509
llvm::CallLowering::IncomingValueAssigner
Definition: CallLowering.h:213
llvm::SITargetLowering
Definition: SIISelLowering.h:31
llvm::CCState::getNextStackOffset
unsigned getNextStackOffset() const
getNextStackOffset - Return the next stack offset such that all stack slots satisfy their alignment r...
Definition: CallingConvLower.h:264
llvm::CallLowering::CallLoweringInfo
Definition: CallLowering.h:101
llvm::CallLowering::ValueAssigner::StackOffset
uint64_t StackOffset
Stack offset for next argument.
Definition: CallLowering.h:200
llvm::CallLowering::ValueHandler::MIRBuilder
MachineIRBuilder & MIRBuilder
Definition: CallLowering.h:226
llvm::SIMachineFunctionInfo::getBytesInStackArgArea
unsigned getBytesInStackArgArea() const
Definition: SIMachineFunctionInfo.h:567
llvm::AMDGPUFunctionArgInfo::DISPATCH_PTR
@ DISPATCH_PTR
Definition: AMDGPUArgumentUsageInfo.h:101
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:137
llvm::GlobalValue::getAddressSpace
unsigned getAddressSpace() const
Definition: Globals.cpp:119
AMDGPULegalizerInfo.h
AMDGPUCallLowering.h
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Calling convention used for AMD graphics targets.
Definition: CallingConv.h:250
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1008
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:272
llvm::MachineRegisterInfo::getType
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
Definition: MachineRegisterInfo.h:732
llvm::AMDGPUFunctionArgInfo::WorkItemIDY
ArgDescriptor WorkItemIDY
Definition: AMDGPUArgumentUsageInfo.h:149
llvm::LLT::getElementCount
ElementCount getElementCount() const
Definition: LowLevelTypeImpl.h:143
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::ArgDescriptor::getRegister
MCRegister getRegister() const
Definition: AMDGPUArgumentUsageInfo.h:71
llvm::SIMachineFunctionInfo
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
Definition: SIMachineFunctionInfo.h:335
llvm::constrainOperandRegClass
Register constrainOperandRegClass(const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, MachineOperand &RegMO)
Constrain the Register operand OpIdx, so that it is now constrained to the TargetRegisterClass passed...
Definition: Utils.cpp:50
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::MachineFunction::getDataLayout
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Definition: MachineFunction.cpp:266
llvm::MachineBasicBlock::empty
bool empty() const
Definition: MachineBasicBlock.h:244
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:216
llvm::AMDGPUCallLowering::lowerFormalArguments
bool lowerFormalArguments(MachineIRBuilder &B, const Function &F, ArrayRef< ArrayRef< Register >> VRegs, FunctionLoweringInfo &FLI) const override
This hook must be implemented to lower the incoming (formal) arguments, described by VRegs,...
Definition: AMDGPUCallLowering.cpp:577
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1478
llvm::MachineIRBuilder::buildStore
MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr, MachineMemOperand &MMO)
Build and insert G_STORE Val, Addr, MMO.
Definition: MachineIRBuilder.cpp:429
getCallOpcode
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall)
Definition: AMDGPUCallLowering.cpp:952
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:726
llvm::SITargetLowering::allocateSpecialInputSGPRs
void allocateSpecialInputSGPRs(CCState &CCInfo, MachineFunction &MF, const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const
Definition: SIISelLowering.cpp:2055
llvm::AMDGPUCallLowering::areCalleeOutgoingArgsTailCallable
bool areCalleeOutgoingArgsTailCallable(CallLoweringInfo &Info, MachineFunction &MF, SmallVectorImpl< ArgInfo > &OutArgs) const
Definition: AMDGPUCallLowering.cpp:1022
llvm::CallLowering::parametersInCSRMatch
bool parametersInCSRMatch(const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl< CCValAssign > &ArgLocs, const SmallVectorImpl< ArgInfo > &OutVals) const
Check whether parameters to a call that are passed in callee saved registers are the same as from the...
Definition: CallLowering.cpp:926
llvm::LLT::scalar
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
Definition: LowLevelTypeImpl.h:42
llvm::CallLowering
Definition: CallLowering.h:43
llvm::AMDGPUCallLowering::lowerReturn
bool lowerReturn(MachineIRBuilder &B, const Value *Val, ArrayRef< Register > VRegs, FunctionLoweringInfo &FLI) const override
This hook behaves as the extended lowerReturn function, but for targets that do not support swifterro...
Definition: AMDGPUCallLowering.cpp:335
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1021
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AttributeList::FirstArgIndex
@ FirstArgIndex
Definition: Attributes.h:409
SIRegisterInfo.h
llvm::TargetRegisterInfo::getCallPreservedMask
virtual const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const
Return a mask of call-preserved registers for the given calling convention on the current function.
Definition: TargetRegisterInfo.h:487
AMDGPUTargetMachine.h
llvm::FormalArgHandler::FormalArgHandler
FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
Definition: M68kCallLowering.h:66
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:572
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::CallLowering::setArgFlags
void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL, const FuncInfoTy &FuncInfo) const
Definition: CallLowering.cpp:154