LLVM 20.0.0git
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This is the parent TargetLowering class for hardware code gen targets. More...
#include "AMDGPUISelLowering.h"
#include "AMDGPU.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUMachineFunction.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Target/TargetMachine.h"
#include "AMDGPUGenCallingConv.inc"
Go to the source code of this file.
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#define | NODE_NAME_CASE(node) case AMDGPUISD::node: return #node; |
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static cl::opt< bool > | AMDGPUBypassSlowDiv ("amdgpu-bypass-slow-div", cl::desc("Skip 64-bit divide for dynamic 32-bit values"), cl::init(true)) |
This is the parent TargetLowering class for hardware code gen targets.
Definition in file AMDGPUISelLowering.cpp.
#define NODE_NAME_CASE | ( | node | ) | case AMDGPUISD::node: return #node; |
Definition at line 5399 of file AMDGPUISelLowering.cpp.
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Definition at line 3751 of file AMDGPUISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), and llvm::Offset.
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Definition at line 4511 of file AMDGPUISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), and llvm::ISD::SELECT.
Referenced by llvm::AMDGPUTargetLowering::foldFreeOpFromSelect().
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Definition at line 2386 of file AMDGPUISelLowering.cpp.
References llvm::AMDGPUISD::BFE_U32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::Hi, and llvm::ISD::SUB.
Referenced by llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), and llvm::AMDGPUTargetLowering::LowerFTRUNC().
Definition at line 683 of file AMDGPUISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, fnegFoldsIntoOpcode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), N, and llvm::ISD::SELECT.
Referenced by llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), llvm::AMDGPUTargetLowering::performFNegCombine(), and llvm::AMDGPUTargetLowering::shouldFoldFNegIntoSrc().
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Definition at line 646 of file AMDGPUISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::FADD, llvm::ISD::FCANONICALIZE, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::AMDGPUISD::FMAX_LEGACY, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::AMDGPUISD::FMED3, llvm::AMDGPUISD::FMIN_LEGACY, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FMUL, llvm::AMDGPUISD::FMUL_LEGACY, llvm::ISD::FNEARBYINT, llvm::ISD::FRINT, llvm::ISD::FROUNDEVEN, llvm::ISD::FSIN, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm_unreachable, llvm::AMDGPUISD::RCP, llvm::AMDGPUISD::RCP_IFLAG, llvm::AMDGPUISD::RCP_LEGACY, llvm::ISD::SELECT, and llvm::AMDGPUISD::SIN_HW.
Referenced by fnegFoldsIntoOp().
If V
is an add of a constant 1, returns the other operand.
Otherwise return SDValue().
Definition at line 4249 of file AMDGPUISelLowering.cpp.
References llvm::ISD::ADD, and llvm::isOneConstant().
Referenced by llvm::AMDGPUTargetLowering::performMulCombine().
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Definition at line 2681 of file AMDGPUISelLowering.cpp.
References llvm::CallingConv::C, llvm::ISD::FADD, llvm::ISD::FMUL, llvm::SelectionDAG::getNode(), llvm::Mul, X, and Y.
Referenced by llvm::AMDGPULegalizerInfo::legalizeFExp(), llvm::AMDGPULegalizerInfo::legalizeFlogCommon(), llvm::AMDGPUTargetLowering::lowerFEXP(), and llvm::AMDGPUTargetLowering::LowerFLOGCommon().
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Definition at line 4231 of file AMDGPUISelLowering.cpp.
References llvm::ISD::BUILD_PAIR, llvm::SelectionDAG::getNode(), llvm::AMDGPUISD::MUL_I24, llvm::AMDGPUISD::MUL_U24, llvm::AMDGPUISD::MULHI_I24, llvm::AMDGPUISD::MULHI_U24, Signed, and Size.
Referenced by llvm::AMDGPUTargetLowering::performMulCombine().
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Definition at line 5306 of file AMDGPUISelLowering.cpp.
References assert(), llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineFrameInfo::getObjectIndexBegin(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), I, llvm::Offset, and Size.
Referenced by llvm::AMDGPUTargetLowering::loadStackInputValue().
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Definition at line 720 of file AMDGPUISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::CopyToReg, llvm::AMDGPUISD::DIV_SCALE, llvm::ISD::FDIV, llvm::ISD::FREM, llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, N, llvm::ISD::SELECT, and selectSupportsSourceMods().
Definition at line 3762 of file AMDGPUISelLowering.cpp.
References llvm::SDNode::uses().
Referenced by llvm::AMDGPUTargetLowering::performLoadCombine().
Definition at line 4692 of file AMDGPUISelLowering.cpp.
References llvm::AMDGPUISD::FMAX_LEGACY, llvm::ISD::FMAXIMUM, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::AMDGPUISD::FMIN_LEGACY, llvm::ISD::FMINIMUM, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, and llvm_unreachable.
Definition at line 3105 of file AMDGPUISelLowering.cpp.
References llvm::ISD::CTLZ, and llvm::ISD::CTLZ_ZERO_UNDEF.
Referenced by llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), llvm::AMDGPUTargetLowering::lowerCTLZResults(), and llvm::AMDGPUTargetLowering::performCtlz_CttzCombine().
Definition at line 3109 of file AMDGPUISelLowering.cpp.
References llvm::ISD::CTTZ, and llvm::ISD::CTTZ_ZERO_UNDEF.
Referenced by llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), and llvm::AMDGPUTargetLowering::performCtlz_CttzCombine().
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Definition at line 3692 of file AMDGPUISelLowering.cpp.
References llvm::EVT::getSizeInBits(), and llvm::AMDGPUTargetLowering::numBitsSigned().
Referenced by llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), and llvm::AMDGPUTargetLowering::performMulLoHiCombine().
Definition at line 4657 of file AMDGPUISelLowering.cpp.
References llvm::APFloat::bitwiseIsEqual(), llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), and llvm::APFloatBase::IEEEsingle().
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Definition at line 3688 of file AMDGPUISelLowering.cpp.
References llvm::AMDGPUTargetLowering::numBitsUnsigned().
Referenced by llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), and llvm::AMDGPUTargetLowering::performMulLoHiCombine().
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returns
true if the operation will definitely need to use a 64-bit encoding, and thus will use a VOP3 encoding regardless of the source modifiers.
Definition at line 704 of file AMDGPUISelLowering.cpp.
References N, and llvm::ISD::SELECT.
Definition at line 1575 of file AMDGPUISelLowering.cpp.
References llvm::ISD::FNEG, llvm::SDValue::getOpcode(), and llvm::SDValue::getOperand().
Referenced by llvm::AMDGPUTargetLowering::combineFMinMaxLegacy().
Definition at line 1582 of file AMDGPUISelLowering.cpp.
References llvm::ISD::FABS, llvm::ISD::FCOPYSIGN, llvm::ISD::FNEG, llvm::SDValue::getOpcode(), and llvm::SDValue::getOperand().
Referenced by llvm::AMDGPUTargetLowering::performIntrinsicWOChainCombine().
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Return true if v_cndmask_b32 will support fabs/fneg source modifiers for the type for ISD::SELECT.
Definition at line 712 of file AMDGPUISelLowering.cpp.
References N.
Referenced by llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), and hasSourceMods().
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Definition at line 3699 of file AMDGPUISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDNode::getConstantOperandVal(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getVTList(), llvm::ISD::INTRINSIC_WO_CHAIN, LHS, llvm_unreachable, llvm::AMDGPUISD::MUL_I24, llvm::AMDGPUISD::MUL_U24, llvm::AMDGPUISD::MULHI_I24, llvm::AMDGPUISD::MULHI_U24, RHS, llvm::TargetLowering::SimplifyDemandedBits(), and llvm::TargetLowering::SimplifyMultipleUseDemandedBits().
Referenced by llvm::AMDGPUTargetLowering::PerformDAGCombine(), and llvm::AMDGPUTargetLowering::performIntrinsicWOChainCombine().
Return true if it's known that Src
can never be an f32 denormal value.
Definition at line 2548 of file AMDGPUISelLowering.cpp.
References llvm::ISD::FFREXP, llvm::ISD::FP16_TO_FP, llvm::ISD::FP_EXTEND, llvm::ISD::INTRINSIC_WO_CHAIN, and llvm_unreachable.
Referenced by needsDenormHandlingF32(), and llvm::AMDGPUTargetLowering::needsDenormHandlingF32().
Definition at line 5607 of file AMDGPUISelLowering.cpp.
References llvm_unreachable.
Referenced by llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode().
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Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering().