AMDGPUISelLowering.cpp File Reference

#include "AMDGPUISelLowering.h"
#include "AMDGPU.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUMachineFunction.h"
#include "GCNSubtarget.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Target/TargetMachine.h"
#include "AMDGPUGenCallingConv.inc"

Include dependency graph for AMDGPUISelLowering.cpp:

Go to the source code of this file.

Macros
#define	NODE_NAME_CASE(node)   case AMDGPUISD::node: return #node;

Functions
static LLVM_READNONE bool	fnegFoldsIntoOp (unsigned Opc)
static LLVM_READONLY bool	opMustUseVOP3Encoding (const SDNode *N, MVT VT)
	returns true if the operation will definitely need to use a 64-bit encoding, and thus will use a VOP3 encoding regardless of the source modifiers. More...
static LLVM_READONLY bool	hasSourceMods (const SDNode *N)
static SDValue	extractF64Exponent (SDValue Hi, const SDLoc &SL, SelectionDAG &DAG)
static bool	isCtlzOpc (unsigned Opc)
static bool	isCttzOpc (unsigned Opc)
static bool	isU24 (SDValue Op, SelectionDAG &DAG)
static bool	isI24 (SDValue Op, SelectionDAG &DAG)
static SDValue	simplifyMul24 (SDNode *Node24, TargetLowering::DAGCombinerInfo &DCI)
template<typename IntTy >
static SDValue	constantFoldBFE (SelectionDAG &DAG, IntTy Src0, uint32_t Offset, uint32_t Width, const SDLoc &DL)
static bool	hasVolatileUser (SDNode *Val)
static SDValue	getMul24 (SelectionDAG &DAG, const SDLoc &SL, SDValue N0, SDValue N1, unsigned Size, bool Signed)
static bool	isNegativeOne (SDValue Val)
static SDValue	distributeOpThroughSelect (TargetLowering::DAGCombinerInfo &DCI, unsigned Op, const SDLoc &SL, SDValue Cond, SDValue N1, SDValue N2)
static SDValue	foldFreeOpFromSelect (TargetLowering::DAGCombinerInfo &DCI, SDValue N)
static bool	isInv2Pi (const APFloat &APF)
static unsigned	inverseMinMax (unsigned Opc)
static int	getOrCreateFixedStackObject (MachineFrameInfo &MFI, unsigned Size, int64_t Offset)

Variables
static cl::opt< bool >	AMDGPUBypassSlowDiv ("amdgpu-bypass-slow-div", cl::desc("Skip 64-bit divide for dynamic 32-bit values"), cl::init(true))

Detailed Description

This is the parent TargetLowering class for hardware code gen targets.

Definition in file AMDGPUISelLowering.cpp.

Macro Definition Documentation

NODE_NAME_CASE

#define NODE_NAME_CASE

(

node

)

case AMDGPUISD::node: return #node;

Definition at line 4384 of file AMDGPUISelLowering.cpp.

Function Documentation

constantFoldBFE()

template<typename IntTy >

static SDValue constantFoldBFE ( SelectionDAG &  DAG, IntTy  Src0, uint32_t  Offset, uint32_t  Width, const SDLoc &  DL  )

static

Definition at line 2932 of file AMDGPUISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::MVT::i32, and Offset.

distributeOpThroughSelect()

static SDValue distributeOpThroughSelect ( TargetLowering::DAGCombinerInfo &  DCI, unsigned  Op, const SDLoc &  SL, SDValue  Cond, SDValue  N1, SDValue  N2  )

static

Definition at line 3645 of file AMDGPUISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), and llvm::ISD::SELECT.

Referenced by foldFreeOpFromSelect().

extractF64Exponent()

static SDValue extractF64Exponent ( SDValue  Hi, const SDLoc &  SL, SelectionDAG &  DAG  )

static

Definition at line 2176 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUISD::BFE_U32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::MipsISD::Hi, llvm::MVT::i32, and llvm::ISD::SUB.

Referenced by llvm::AMDGPUTargetLowering::LowerFTRUNC().

fnegFoldsIntoOp()

static LLVM_READNONE bool fnegFoldsIntoOp ( unsigned  Opc )

static

Definition at line 629 of file AMDGPUISelLowering.cpp.

References llvm::ISD::FADD, llvm::ISD::FCANONICALIZE, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::AMDGPUISD::FMAX_LEGACY, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::AMDGPUISD::FMED3, llvm::AMDGPUISD::FMIN_LEGACY, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FMUL, llvm::AMDGPUISD::FMUL_LEGACY, llvm::ISD::FNEARBYINT, llvm::ISD::FRINT, llvm::ISD::FSIN, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::AMDGPUISD::RCP, llvm::AMDGPUISD::RCP_IFLAG, llvm::AMDGPUISD::RCP_LEGACY, and llvm::AMDGPUISD::SIN_HW.

Referenced by foldFreeOpFromSelect(), and llvm::AMDGPUTargetLowering::performFNegCombine().

foldFreeOpFromSelect()

static SDValue foldFreeOpFromSelect ( TargetLowering::DAGCombinerInfo &  DCI, SDValue  N  )

static

Definition at line 3667 of file AMDGPUISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, distributeOpThroughSelect(), llvm::ISD::FABS, llvm::ISD::FMUL, llvm::ISD::FNEG, fnegFoldsIntoOp(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::hasOneUse(), llvm::ConstantFPSDNode::isNegative(), LHS, N, RHS, llvm::ISD::SELECT, and std::swap().

Referenced by llvm::AMDGPUTargetLowering::performSelectCombine().

getMul24()

static SDValue getMul24 ( SelectionDAG &  DAG, const SDLoc &  SL, SDValue  N0, SDValue  N1, unsigned  Size, bool  Signed  )

static

Definition at line 3397 of file AMDGPUISelLowering.cpp.

References llvm::ISD::BUILD_PAIR, llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::MVT::i64, llvm::AMDGPUISD::MUL_I24, llvm::AMDGPUISD::MUL_U24, llvm::AMDGPUISD::MULHI_I24, llvm::AMDGPUISD::MULHI_U24, Signed, and llvm::Check::Size.

Referenced by llvm::AMDGPUTargetLowering::performMulCombine().

getOrCreateFixedStackObject()

static int getOrCreateFixedStackObject ( MachineFrameInfo &  MFI, unsigned  Size, int64_t  Offset  )

static

Definition at line 4298 of file AMDGPUISelLowering.cpp.

References assert(), llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineFrameInfo::getObjectIndexBegin(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), I, Offset, and llvm::Check::Size.

Referenced by llvm::AMDGPUTargetLowering::loadStackInputValue().

hasSourceMods()

static LLVM_READONLY bool hasSourceMods ( const SDNode *  N )

static

Definition at line 671 of file AMDGPUISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::CopyToReg, llvm::AMDGPUISD::DIV_SCALE, llvm::ISD::FDIV, llvm::ISD::FREM, llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, N, and llvm::ISD::SELECT.

Referenced by llvm::AMDGPUTargetLowering::allUsesHaveSourceMods().

hasVolatileUser()

static bool hasVolatileUser ( SDNode *  Val )

static

Definition at line 2943 of file AMDGPUISelLowering.cpp.

References M, and llvm::SDNode::uses().

Referenced by llvm::AMDGPUTargetLowering::performLoadCombine().

inverseMinMax()

static unsigned inverseMinMax ( unsigned  Opc )

static

Definition at line 3797 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUISD::FMAX_LEGACY, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::AMDGPUISD::FMIN_LEGACY, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, and llvm_unreachable.

Referenced by llvm::AMDGPUTargetLowering::performFNegCombine().

isCtlzOpc()

static bool isCtlzOpc ( unsigned  Opc )

static

Definition at line 2353 of file AMDGPUISelLowering.cpp.

References llvm::ISD::CTLZ, and llvm::ISD::CTLZ_ZERO_UNDEF.

Referenced by llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), and llvm::AMDGPUTargetLowering::performCtlz_CttzCombine().

isCttzOpc()

static bool isCttzOpc ( unsigned  Opc )

static

Definition at line 2357 of file AMDGPUISelLowering.cpp.

References llvm::ISD::CTTZ, and llvm::ISD::CTTZ_ZERO_UNDEF.

Referenced by llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), and llvm::AMDGPUTargetLowering::performCtlz_CttzCombine().

isI24()

static bool isI24 ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 2873 of file AMDGPUISelLowering.cpp.

References llvm::EVT::getSizeInBits(), and llvm::AMDGPUTargetLowering::numBitsSigned().

Referenced by llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), and llvm::AMDGPUTargetLowering::performMulLoHiCombine().

isInv2Pi()

static bool isInv2Pi ( const APFloat &  APF )

static

Definition at line 3773 of file AMDGPUISelLowering.cpp.

References llvm::APFloat::bitwiseIsEqual(), llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), and llvm::APFloatBase::IEEEsingle().

Referenced by llvm::AMDGPUTargetLowering::isConstantCostlierToNegate().

isNegativeOne()

static bool isNegativeOne ( SDValue  Val )

static

Definition at line 3577 of file AMDGPUISelLowering.cpp.

Referenced by llvm::AMDGPUTargetLowering::performCtlz_CttzCombine().

isU24()

static bool isU24 ( SDValue  Op, SelectionDAG &  DAG  )

static

Definition at line 2869 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUTargetLowering::numBitsUnsigned().

Referenced by llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), and llvm::AMDGPUTargetLowering::performMulLoHiCombine().

opMustUseVOP3Encoding()

static LLVM_READONLY bool opMustUseVOP3Encoding ( const SDNode *  N, MVT  VT  )

static

returns true if the operation will definitely need to use a 64-bit encoding, and thus will use a VOP3 encoding regardless of the source modifiers.

Definition at line 664 of file AMDGPUISelLowering.cpp.

References llvm::MVT::f64, and N.

Referenced by llvm::AMDGPUTargetLowering::allUsesHaveSourceMods().

simplifyMul24()

static SDValue simplifyMul24 ( SDNode *  Node24, TargetLowering::DAGCombinerInfo &  DCI  )

static

Definition at line 2880 of file AMDGPUISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getVTList(), llvm::ISD::INTRINSIC_WO_CHAIN, LHS, llvm_unreachable, llvm::AMDGPUISD::MUL_I24, llvm::AMDGPUISD::MUL_U24, llvm::AMDGPUISD::MULHI_I24, llvm::AMDGPUISD::MULHI_U24, RHS, llvm::TargetLowering::SimplifyDemandedBits(), and llvm::TargetLowering::SimplifyMultipleUseDemandedBits().

Referenced by llvm::AMDGPUTargetLowering::PerformDAGCombine(), and llvm::AMDGPUTargetLowering::performIntrinsicWOChainCombine().

Variable Documentation

AMDGPUBypassSlowDiv

cl::opt<bool> AMDGPUBypassSlowDiv("amdgpu-bypass-slow-div", cl::desc("Skip 64-bit divide for dynamic 32-bit values"), cl::init(true))

static

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering().