This is the parent TargetLowering class for hardware code gen targets. More...

#include "AMDGPUISelLowering.h"
#include "AMDGPU.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUMachineFunction.h"
#include "GCNSubtarget.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Target/TargetMachine.h"
#include "AMDGPUGenCallingConv.inc"

Include dependency graph for AMDGPUISelLowering.cpp:

Go to the source code of this file.

Macros
#define	NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;

Functions
static LLVM_READNONE bool	fnegFoldsIntoOp (unsigned Opc)

static LLVM_READONLY bool	opMustUseVOP3Encoding (const SDNode *N, MVT VT)
	`returns` true if the operation will definitely need to use a 64-bit encoding, and thus will use a VOP3 encoding regardless of the source modifiers.

static LLVM_READONLY bool	selectSupportsSourceMods (const SDNode *N)
	Return true if v_cndmask_b32 will support fabs/fneg source modifiers for the type for ISD::SELECT.

static LLVM_READONLY bool	hasSourceMods (const SDNode *N)

static SDValue	peekFNeg (SDValue Val)

static SDValue	extractF64Exponent (SDValue Hi, const SDLoc &SL, SelectionDAG &DAG)

static bool	isCtlzOpc (unsigned Opc)

static bool	isCttzOpc (unsigned Opc)

static bool	isU24 (SDValue Op, SelectionDAG &DAG)

static bool	isI24 (SDValue Op, SelectionDAG &DAG)

static SDValue	simplifyMul24 (SDNode *Node24, TargetLowering::DAGCombinerInfo &DCI)

template<typename IntTy >
static SDValue	constantFoldBFE (SelectionDAG &DAG, IntTy Src0, uint32_t Offset, uint32_t Width, const SDLoc &DL)

static bool	hasVolatileUser (SDNode *Val)

static SDValue	getMul24 (SelectionDAG &DAG, const SDLoc &SL, SDValue N0, SDValue N1, unsigned Size, bool Signed)

static SDValue	distributeOpThroughSelect (TargetLowering::DAGCombinerInfo &DCI, unsigned Op, const SDLoc &SL, SDValue Cond, SDValue N1, SDValue N2)

static bool	isInv2Pi (const APFloat &APF)

static unsigned	inverseMinMax (unsigned Opc)

static int	getOrCreateFixedStackObject (MachineFrameInfo &MFI, unsigned Size, int64_t Offset)

static unsigned	workitemIntrinsicDim (unsigned ID)

Variables
static cl::opt< bool >	AMDGPUBypassSlowDiv ("amdgpu-bypass-slow-div", cl::desc("Skip 64-bit divide for dynamic 32-bit values"), cl::init(true))

Detailed Description

This is the parent TargetLowering class for hardware code gen targets.

Definition in file AMDGPUISelLowering.cpp.

Macro Definition Documentation

◆ NODE_NAME_CASE

#define NODE_NAME_CASE ( node ) case AMDGPUISD::node: return #node;

Definition at line 4505 of file AMDGPUISelLowering.cpp.

Function Documentation

◆ constantFoldBFE()

template<typename IntTy >

static SDValue constantFoldBFE	(	SelectionDAG &	DAG,
		IntTy	Src0,
		uint32_t	Offset,
		uint32_t	Width,
		const SDLoc &	DL
	)

static

Definition at line 3005 of file AMDGPUISelLowering.cpp.

References DL, llvm::SelectionDAG::getConstant(), llvm::MVT::i32, and llvm::Offset.

◆ distributeOpThroughSelect()

static SDValue distributeOpThroughSelect	(	TargetLowering::DAGCombinerInfo &	DCI,
		unsigned	Op,
		const SDLoc &	SL,
		SDValue	Cond,
		SDValue	N1,
		SDValue	N2
	)

static

Definition at line 3717 of file AMDGPUISelLowering.cpp.

References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), and llvm::ISD::SELECT.

Referenced by llvm::AMDGPUTargetLowering::foldFreeOpFromSelect().

◆ extractF64Exponent()

static SDValue extractF64Exponent	(	SDValue	Hi,
		const SDLoc &	SL,
		SelectionDAG &	DAG
	)

static

Definition at line 2238 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUISD::BFE_U32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::Hi, llvm::MVT::i32, and llvm::ISD::SUB.

Referenced by llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), and llvm::AMDGPUTargetLowering::LowerFTRUNC().

◆ fnegFoldsIntoOp()

static LLVM_READNONE bool fnegFoldsIntoOp ( unsigned Opc )

static

◆ getMul24()

static SDValue getMul24	(	SelectionDAG &	DAG,
		const SDLoc &	SL,
		SDValue	N0,
		SDValue	N1,
		unsigned	Size,
		bool	Signed
	)

static

Definition at line 3475 of file AMDGPUISelLowering.cpp.

References llvm::ISD::BUILD_PAIR, llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::MVT::i64, llvm::AMDGPUISD::MUL_I24, llvm::AMDGPUISD::MUL_U24, llvm::AMDGPUISD::MULHI_I24, llvm::AMDGPUISD::MULHI_U24, Signed, and Size.

◆ getOrCreateFixedStackObject()

static int getOrCreateFixedStackObject	(	MachineFrameInfo &	MFI,
		unsigned	Size,
		int64_t	Offset
	)

static

Definition at line 4415 of file AMDGPUISelLowering.cpp.

References assert(), llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineFrameInfo::getObjectIndexBegin(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), I, llvm::Offset, and Size.

Referenced by llvm::AMDGPUTargetLowering::loadStackInputValue().

◆ hasSourceMods()

static LLVM_READONLY bool hasSourceMods ( const SDNode * N )

static

Definition at line 611 of file AMDGPUISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::ISD::CopyToReg, llvm::AMDGPUISD::DIV_SCALE, llvm::ISD::FDIV, llvm::ISD::FREM, llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, N, llvm::ISD::SELECT, and selectSupportsSourceMods().

◆ hasVolatileUser()

static bool hasVolatileUser ( SDNode * Val )

static

Definition at line 3016 of file AMDGPUISelLowering.cpp.

References llvm::SDNode::uses().

Referenced by llvm::AMDGPUTargetLowering::performLoadCombine().

◆ inverseMinMax()

static unsigned inverseMinMax ( unsigned Opc )

static

Definition at line 3898 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUISD::FMAX_LEGACY, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::AMDGPUISD::FMIN_LEGACY, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, and llvm_unreachable.

◆ isCtlzOpc()

static bool isCtlzOpc ( unsigned Opc )

static

Definition at line 2422 of file AMDGPUISelLowering.cpp.

References llvm::ISD::CTLZ, and llvm::ISD::CTLZ_ZERO_UNDEF.

Referenced by llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), and llvm::AMDGPUTargetLowering::performCtlz_CttzCombine().

◆ isCttzOpc()

static bool isCttzOpc ( unsigned Opc )

static

Definition at line 2426 of file AMDGPUISelLowering.cpp.

References llvm::ISD::CTTZ, and llvm::ISD::CTTZ_ZERO_UNDEF.

Referenced by llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), and llvm::AMDGPUTargetLowering::performCtlz_CttzCombine().

◆ isI24()

static bool isI24	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 2946 of file AMDGPUISelLowering.cpp.

References llvm::EVT::getSizeInBits(), and llvm::AMDGPUTargetLowering::numBitsSigned().

Referenced by llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), and llvm::AMDGPUTargetLowering::performMulLoHiCombine().

◆ isInv2Pi()

static bool isInv2Pi ( const APFloat & APF )

static

Definition at line 3863 of file AMDGPUISelLowering.cpp.

References llvm::APFloat::bitwiseIsEqual(), llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), and llvm::APFloatBase::IEEEsingle().

◆ isU24()

static bool isU24	(	SDValue	Op,
		SelectionDAG &	DAG
	)

static

Definition at line 2942 of file AMDGPUISelLowering.cpp.

References llvm::AMDGPUTargetLowering::numBitsUnsigned().

Referenced by llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), and llvm::AMDGPUTargetLowering::performMulLoHiCombine().

◆ opMustUseVOP3Encoding()

static LLVM_READONLY bool opMustUseVOP3Encoding	(	const SDNode *	N,
		MVT	VT
	)

static

returns true if the operation will definitely need to use a 64-bit encoding, and thus will use a VOP3 encoding regardless of the source modifiers.

Definition at line 595 of file AMDGPUISelLowering.cpp.

References llvm::MVT::f64, N, and llvm::ISD::SELECT.

◆ peekFNeg()

static SDValue peekFNeg ( SDValue Val )

static

Definition at line 1437 of file AMDGPUISelLowering.cpp.

References llvm::ISD::FNEG, llvm::SDValue::getOpcode(), and llvm::SDValue::getOperand().

Referenced by llvm::AMDGPUTargetLowering::combineFMinMaxLegacy().

◆ selectSupportsSourceMods()

static LLVM_READONLY bool selectSupportsSourceMods ( const SDNode * N )

static

Return true if v_cndmask_b32 will support fabs/fneg source modifiers for the type for ISD::SELECT.

Definition at line 603 of file AMDGPUISelLowering.cpp.

References llvm::MVT::f32, and N.

Referenced by llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), and hasSourceMods().

◆ simplifyMul24()

static SDValue simplifyMul24	(	SDNode *	Node24,
		TargetLowering::DAGCombinerInfo &	DCI
	)

static

◆ workitemIntrinsicDim()

static unsigned workitemIntrinsicDim ( unsigned ID )

static

Definition at line 4697 of file AMDGPUISelLowering.cpp.

References llvm_unreachable.

Referenced by llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode().

Variable Documentation

◆ AMDGPUBypassSlowDiv

cl::opt< bool > AMDGPUBypassSlowDiv("amdgpu-bypass-slow-div", cl::desc("Skip 64-bit divide for dynamic 32-bit values"), cl::init(true))	(	"amdgpu-bypass-slow-div"	,
		cl::desc("Skip 64-bit divide for dynamic 32-bit values")	,
		cl::init(true)
	)

static

Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering().

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ NODE_NAME_CASE

Function Documentation

◆ constantFoldBFE()

◆ distributeOpThroughSelect()

◆ extractF64Exponent()

◆ fnegFoldsIntoOp()

◆ getMul24()

◆ getOrCreateFixedStackObject()

◆ hasSourceMods()

◆ hasVolatileUser()

◆ inverseMinMax()

◆ isCtlzOpc()

◆ isCttzOpc()

◆ isI24()

◆ isInv2Pi()

◆ isU24()

◆ opMustUseVOP3Encoding()

◆ peekFNeg()

◆ selectSupportsSourceMods()

◆ simplifyMul24()

◆ workitemIntrinsicDim()

Variable Documentation

◆ AMDGPUBypassSlowDiv