LLVM 17.0.0git
|
This is the parent TargetLowering class for hardware code gen targets. More...
#include "AMDGPUISelLowering.h"
#include "AMDGPU.h"
#include "AMDGPUInstrInfo.h"
#include "AMDGPUMachineFunction.h"
#include "GCNSubtarget.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/Analysis.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Target/TargetMachine.h"
#include "AMDGPUGenCallingConv.inc"
Go to the source code of this file.
Macros | |
#define | NODE_NAME_CASE(node) case AMDGPUISD::node: return #node; |
Variables | |
static cl::opt< bool > | AMDGPUBypassSlowDiv ("amdgpu-bypass-slow-div", cl::desc("Skip 64-bit divide for dynamic 32-bit values"), cl::init(true)) |
This is the parent TargetLowering class for hardware code gen targets.
Definition in file AMDGPUISelLowering.cpp.
#define NODE_NAME_CASE | ( | node | ) | case AMDGPUISD::node: return #node; |
Definition at line 4505 of file AMDGPUISelLowering.cpp.
|
static |
Definition at line 3005 of file AMDGPUISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::MVT::i32, and llvm::Offset.
|
static |
Definition at line 3717 of file AMDGPUISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), and llvm::ISD::SELECT.
Referenced by llvm::AMDGPUTargetLowering::foldFreeOpFromSelect().
|
static |
Definition at line 2238 of file AMDGPUISelLowering.cpp.
References llvm::AMDGPUISD::BFE_U32, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::Hi, llvm::MVT::i32, and llvm::ISD::SUB.
Referenced by llvm::AMDGPULegalizerInfo::legalizeIntrinsicTrunc(), and llvm::AMDGPUTargetLowering::LowerFTRUNC().
|
static |
Definition at line 559 of file AMDGPUISelLowering.cpp.
References llvm::ISD::FADD, llvm::ISD::FCANONICALIZE, llvm::ISD::FMA, llvm::ISD::FMAD, llvm::AMDGPUISD::FMAX_LEGACY, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::AMDGPUISD::FMED3, llvm::AMDGPUISD::FMIN_LEGACY, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, llvm::ISD::FMUL, llvm::AMDGPUISD::FMUL_LEGACY, llvm::ISD::FNEARBYINT, llvm::ISD::FRINT, llvm::ISD::FSIN, llvm::ISD::FSUB, llvm::ISD::FTRUNC, llvm::AMDGPUISD::RCP, llvm::AMDGPUISD::RCP_IFLAG, llvm::AMDGPUISD::RCP_LEGACY, llvm::ISD::SELECT, and llvm::AMDGPUISD::SIN_HW.
Referenced by llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), and llvm::AMDGPUTargetLowering::shouldFoldFNegIntoSrc().
|
static |
Definition at line 3475 of file AMDGPUISelLowering.cpp.
References llvm::ISD::BUILD_PAIR, llvm::SelectionDAG::getNode(), llvm::MVT::i32, llvm::MVT::i64, llvm::AMDGPUISD::MUL_I24, llvm::AMDGPUISD::MUL_U24, llvm::AMDGPUISD::MULHI_I24, llvm::AMDGPUISD::MULHI_U24, Signed, and Size.
|
static |
Definition at line 4415 of file AMDGPUISelLowering.cpp.
References assert(), llvm::MachineFrameInfo::CreateFixedObject(), llvm::MachineFrameInfo::getObjectIndexBegin(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), I, llvm::Offset, and Size.
Referenced by llvm::AMDGPUTargetLowering::loadStackInputValue().
|
static |
Definition at line 611 of file AMDGPUISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::CopyToReg, llvm::AMDGPUISD::DIV_SCALE, llvm::ISD::FDIV, llvm::ISD::FREM, llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, N, llvm::ISD::SELECT, and selectSupportsSourceMods().
Definition at line 3016 of file AMDGPUISelLowering.cpp.
References llvm::SDNode::uses().
Referenced by llvm::AMDGPUTargetLowering::performLoadCombine().
Definition at line 3898 of file AMDGPUISelLowering.cpp.
References llvm::AMDGPUISD::FMAX_LEGACY, llvm::ISD::FMAXNUM, llvm::ISD::FMAXNUM_IEEE, llvm::AMDGPUISD::FMIN_LEGACY, llvm::ISD::FMINNUM, llvm::ISD::FMINNUM_IEEE, and llvm_unreachable.
Definition at line 2422 of file AMDGPUISelLowering.cpp.
References llvm::ISD::CTLZ, and llvm::ISD::CTLZ_ZERO_UNDEF.
Referenced by llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), and llvm::AMDGPUTargetLowering::performCtlz_CttzCombine().
Definition at line 2426 of file AMDGPUISelLowering.cpp.
References llvm::ISD::CTTZ, and llvm::ISD::CTTZ_ZERO_UNDEF.
Referenced by llvm::AMDGPUTargetLowering::LowerCTLZ_CTTZ(), and llvm::AMDGPUTargetLowering::performCtlz_CttzCombine().
|
static |
Definition at line 2946 of file AMDGPUISelLowering.cpp.
References llvm::EVT::getSizeInBits(), and llvm::AMDGPUTargetLowering::numBitsSigned().
Referenced by llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhsCombine(), and llvm::AMDGPUTargetLowering::performMulLoHiCombine().
Definition at line 3863 of file AMDGPUISelLowering.cpp.
References llvm::APFloat::bitwiseIsEqual(), llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), and llvm::APFloatBase::IEEEsingle().
|
static |
Definition at line 2942 of file AMDGPUISelLowering.cpp.
References llvm::AMDGPUTargetLowering::numBitsUnsigned().
Referenced by llvm::AMDGPUTargetLowering::performMulCombine(), llvm::AMDGPUTargetLowering::performMulhuCombine(), and llvm::AMDGPUTargetLowering::performMulLoHiCombine().
|
static |
returns
true if the operation will definitely need to use a 64-bit encoding, and thus will use a VOP3 encoding regardless of the source modifiers.
Definition at line 595 of file AMDGPUISelLowering.cpp.
References llvm::MVT::f64, N, and llvm::ISD::SELECT.
Definition at line 1437 of file AMDGPUISelLowering.cpp.
References llvm::ISD::FNEG, llvm::SDValue::getOpcode(), and llvm::SDValue::getOperand().
Referenced by llvm::AMDGPUTargetLowering::combineFMinMaxLegacy().
|
static |
Return true if v_cndmask_b32 will support fabs/fneg source modifiers for the type for ISD::SELECT.
Definition at line 603 of file AMDGPUISelLowering.cpp.
References llvm::MVT::f32, and N.
Referenced by llvm::AMDGPUTargetLowering::foldFreeOpFromSelect(), and hasSourceMods().
|
static |
Definition at line 2953 of file AMDGPUISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getVTList(), llvm::ISD::INTRINSIC_WO_CHAIN, LHS, llvm_unreachable, llvm::AMDGPUISD::MUL_I24, llvm::AMDGPUISD::MUL_U24, llvm::AMDGPUISD::MULHI_I24, llvm::AMDGPUISD::MULHI_U24, RHS, llvm::TargetLowering::SimplifyDemandedBits(), and llvm::TargetLowering::SimplifyMultipleUseDemandedBits().
Referenced by llvm::AMDGPUTargetLowering::PerformDAGCombine(), and llvm::AMDGPUTargetLowering::performIntrinsicWOChainCombine().
Definition at line 4697 of file AMDGPUISelLowering.cpp.
References llvm_unreachable.
Referenced by llvm::AMDGPUTargetLowering::computeKnownBitsForTargetNode().
|
static |
Referenced by llvm::AMDGPUTargetLowering::AMDGPUTargetLowering().