58 if (
F.getFnAttribute(
"disable-tail-calls").getValueAsBool())
64 AttrBuilder CallerAttrs(
F.getContext(),
F.getAttributes().getRetAttrs());
65 for (
const auto &Attr : {Attribute::Alignment, Attribute::Dereferenceable,
66 Attribute::DereferenceableOrNull, Attribute::NoAlias,
67 Attribute::NonNull, Attribute::NoUndef})
74 if (CallerAttrs.
contains(Attribute::ZExt) ||
75 CallerAttrs.
contains(Attribute::SExt))
86 for (
unsigned I = 0,
E = ArgLocs.
size();
I !=
E; ++
I) {
102 Register ArgReg = cast<RegisterSDNode>(
Value->getOperand(1))->getReg();
103 if (
MRI.getLiveInPhysReg(ArgReg) != Reg)
113 IsSExt = Call->paramHasAttr(ArgIdx, Attribute::SExt);
114 IsZExt = Call->paramHasAttr(ArgIdx, Attribute::ZExt);
115 IsInReg = Call->paramHasAttr(ArgIdx, Attribute::InReg);
116 IsSRet = Call->paramHasAttr(ArgIdx, Attribute::StructRet);
117 IsNest = Call->paramHasAttr(ArgIdx, Attribute::Nest);
118 IsByVal = Call->paramHasAttr(ArgIdx, Attribute::ByVal);
119 IsPreallocated = Call->paramHasAttr(ArgIdx, Attribute::Preallocated);
120 IsInAlloca = Call->paramHasAttr(ArgIdx, Attribute::InAlloca);
121 IsReturned = Call->paramHasAttr(ArgIdx, Attribute::Returned);
122 IsSwiftSelf = Call->paramHasAttr(ArgIdx, Attribute::SwiftSelf);
123 IsSwiftAsync = Call->paramHasAttr(ArgIdx, Attribute::SwiftAsync);
124 IsSwiftError = Call->paramHasAttr(ArgIdx, Attribute::SwiftError);
125 Alignment = Call->getParamStackAlign(ArgIdx);
128 "multiple ABI attributes?");
144std::pair<SDValue, SDValue>
154 Args.reserve(Ops.
size());
157 for (
unsigned i = 0; i < Ops.
size(); ++i) {
160 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.
getContext());
163 Entry.IsZExt = !Entry.IsSExt;
167 Entry.IsSExt = Entry.IsZExt =
false;
169 Args.push_back(Entry);
172 if (LC == RTLIB::UNKNOWN_LIBCALL)
180 bool zeroExtend = !signExtend;
184 signExtend = zeroExtend =
false;
195 return LowerCallTo(CLI);
199 std::vector<EVT> &MemOps,
unsigned Limit,
const MemOp &
Op,
unsigned DstAS,
201 if (Limit != ~
unsigned(0) &&
Op.isMemcpyWithFixedDstAlign() &&
202 Op.getSrcAlign() <
Op.getDstAlign())
207 if (VT == MVT::Other) {
212 if (
Op.isFixedDstAlign())
230 unsigned NumMemOps = 0;
234 while (VTSize >
Size) {
245 else if (NewVT == MVT::i64 &&
257 if (NewVT == MVT::i8)
266 if (NumMemOps &&
Op.allowOverlap() && NewVTSize <
Size &&
268 VT, DstAS,
Op.isFixedDstAlign() ?
Op.getDstAlign() :
Align(1),
278 if (++NumMemOps > Limit)
281 MemOps.push_back(VT);
296 return softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, dl, OldLHS,
306 bool IsSignaling)
const {
311 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128)
312 &&
"Unsupported setcc type!");
315 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
316 bool ShouldInvertCC =
false;
320 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
321 (VT == MVT::f64) ? RTLIB::OEQ_F64 :
322 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
326 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
327 (VT == MVT::f64) ? RTLIB::UNE_F64 :
328 (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128;
332 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
333 (VT == MVT::f64) ? RTLIB::OGE_F64 :
334 (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
338 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
339 (VT == MVT::f64) ? RTLIB::OLT_F64 :
340 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
344 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
345 (VT == MVT::f64) ? RTLIB::OLE_F64 :
346 (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
350 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
351 (VT == MVT::f64) ? RTLIB::OGT_F64 :
352 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
355 ShouldInvertCC =
true;
358 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
359 (VT == MVT::f64) ? RTLIB::UO_F64 :
360 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
364 ShouldInvertCC =
true;
367 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
368 (VT == MVT::f64) ? RTLIB::UO_F64 :
369 (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
370 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
371 (VT == MVT::f64) ? RTLIB::OEQ_F64 :
372 (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
376 ShouldInvertCC =
true;
379 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
380 (VT == MVT::f64) ? RTLIB::OGE_F64 :
381 (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128;
384 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
385 (VT == MVT::f64) ? RTLIB::OGT_F64 :
386 (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128;
389 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
390 (VT == MVT::f64) ? RTLIB::OLE_F64 :
391 (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128;
394 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
395 (VT == MVT::f64) ? RTLIB::OLT_F64 :
396 (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128;
404 SDValue Ops[2] = {NewLHS, NewRHS};
409 auto Call = makeLibCall(DAG, LC1, RetVT, Ops, CallOptions, dl, Chain);
414 if (ShouldInvertCC) {
416 CCCode = getSetCCInverse(CCCode, RetVT);
419 if (LC2 == RTLIB::UNKNOWN_LIBCALL) {
426 auto Call2 = makeLibCall(DAG, LC2, RetVT, Ops, CallOptions, dl, Chain);
429 CCCode = getSetCCInverse(CCCode, RetVT);
430 NewLHS = DAG.
getSetCC(dl, SetCCVT, Call2.first, NewRHS, CCCode);
444 if (!isPositionIndependent())
458 unsigned JTEncoding = getJumpTableEncoding();
494 if (!
TM.shouldAssumeDSOLocal(*GV->
getParent(), GV))
498 if (isPositionIndependent())
514 const APInt &DemandedElts,
517 unsigned Opcode =
Op.getOpcode();
525 if (targetShrinkDemandedConstant(
Op,
DemandedBits, DemandedElts, TLO))
535 auto *Op1C = dyn_cast<ConstantSDNode>(
Op.getOperand(1));
536 if (!Op1C || Op1C->isOpaque())
540 const APInt &
C = Op1C->getAPIntValue();
545 EVT VT =
Op.getValueType();
561 EVT VT =
Op.getValueType();
575 "ShrinkDemandedOp only supports binary operators!");
576 assert(
Op.getNode()->getNumValues() == 1 &&
577 "ShrinkDemandedOp only supports nodes with one result!");
579 EVT VT =
Op.getValueType();
589 if (!
Op.getNode()->hasOneUse())
602 Op.getOpcode(), dl, SmallVT,
605 assert(DemandedSize <= SmallVTBits &&
"Narrowed below demanded bits?");
620 bool Simplified = SimplifyDemandedBits(
Op,
DemandedBits, Known, TLO);
629 const APInt &DemandedElts,
649 bool AssumeSingleUse)
const {
650 EVT VT =
Op.getValueType();
666 EVT VT =
Op.getValueType();
684 switch (
Op.getOpcode()) {
690 EVT SrcVT = Src.getValueType();
691 EVT DstVT =
Op.getValueType();
697 if (NumSrcEltBits == NumDstEltBits)
698 if (
SDValue V = SimplifyMultipleUseDemandedBits(
702 if (SrcVT.
isVector() && (NumDstEltBits % NumSrcEltBits) == 0) {
703 unsigned Scale = NumDstEltBits / NumSrcEltBits;
707 for (
unsigned i = 0; i != Scale; ++i) {
708 unsigned EltOffset = IsLE ? i : (Scale - 1 - i);
709 unsigned BitOffset = EltOffset * NumSrcEltBits;
712 DemandedSrcBits |= Sub;
713 for (
unsigned j = 0; j != NumElts; ++j)
715 DemandedSrcElts.
setBit((j * Scale) + i);
719 if (
SDValue V = SimplifyMultipleUseDemandedBits(
720 Src, DemandedSrcBits, DemandedSrcElts, DAG,
Depth + 1))
725 if (IsLE && (NumSrcEltBits % NumDstEltBits) == 0) {
726 unsigned Scale = NumSrcEltBits / NumDstEltBits;
730 for (
unsigned i = 0; i != NumElts; ++i)
731 if (DemandedElts[i]) {
732 unsigned Offset = (i % Scale) * NumDstEltBits;
734 DemandedSrcElts.
setBit(i / Scale);
737 if (
SDValue V = SimplifyMultipleUseDemandedBits(
738 Src, DemandedSrcBits, DemandedSrcElts, DAG,
Depth + 1))
752 return Op.getOperand(0);
754 return Op.getOperand(1);
765 return Op.getOperand(0);
767 return Op.getOperand(1);
777 return Op.getOperand(0);
779 return Op.getOperand(1);
785 if (
const APInt *MaxSA =
788 unsigned ShAmt = MaxSA->getZExtValue();
789 unsigned NumSignBits =
792 if (NumSignBits > ShAmt && (NumSignBits - ShAmt) >= (UpperDemandedBits))
821 EVT ExVT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
828 if (NumSignBits >= (
BitWidth - ExBits + 1))
841 EVT SrcVT = Src.getValueType();
842 EVT DstVT =
Op.getValueType();
843 if (IsLE && DemandedElts == 1 &&
856 auto *CIdx = dyn_cast<ConstantSDNode>(
Op.getOperand(2));
859 !DemandedElts[CIdx->getZExtValue()])
873 if (DemandedSubElts == 0)
883 bool AllUndef =
true, IdentityLHS =
true, IdentityRHS =
true;
884 for (
unsigned i = 0; i != NumElts; ++i) {
885 int M = ShuffleMask[i];
886 if (M < 0 || !DemandedElts[i])
889 IdentityLHS &= (M == (int)i);
890 IdentityRHS &= ((M - NumElts) == i);
896 return Op.getOperand(0);
898 return Op.getOperand(1);
908 if (
SDValue V = SimplifyMultipleUseDemandedBitsForTargetNode(
918 unsigned Depth)
const {
919 EVT VT =
Op.getValueType();
926 return SimplifyMultipleUseDemandedBits(
Op,
DemandedBits, DemandedElts, DAG,
932 unsigned Depth)
const {
934 return SimplifyMultipleUseDemandedBits(
Op,
DemandedBits, DemandedElts, DAG,
943 const APInt &DemandedElts,
946 "SRL or SRA node is required here!");
949 if (!N1C || !N1C->
isOne())
995 unsigned ShiftOpc =
Op.getOpcode();
996 bool IsSigned =
false;
1000 unsigned NumSigned = std::min(NumSignedA, NumSignedB) - 1;
1005 unsigned NumZero = std::min(NumZeroA, NumZeroB);
1011 if (NumZero >= 2 && NumSigned < NumZero) {
1016 if (NumSigned >= 1) {
1024 if (NumZero >= 1 && NumSigned < NumZero) {
1044 EVT VT =
Op.getValueType();
1056 Add.getOperand(1)) &&
1082 unsigned Depth,
bool AssumeSingleUse)
const {
1085 "Mask size mismatches value type size!");
1090 EVT VT =
Op.getValueType();
1092 unsigned NumElts = OriginalDemandedElts.
getBitWidth();
1094 "Unexpected vector size");
1097 APInt DemandedElts = OriginalDemandedElts;
1118 cast<ConstantFPSDNode>(
Op)->getValueAPF().bitcastToAPInt());
1123 bool HasMultiUse =
false;
1124 if (!AssumeSingleUse && !
Op.getNode()->hasOneUse()) {
1133 }
else if (OriginalDemandedBits == 0 || OriginalDemandedElts == 0) {
1142 switch (
Op.getOpcode()) {
1146 if (!DemandedElts[0])
1151 unsigned SrcBitWidth = Src.getScalarValueSizeInBits();
1153 if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcKnown, TLO,
Depth + 1))
1158 if (DemandedElts == 1)
1171 if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO,
Depth + 1))
1180 auto *LD = cast<LoadSDNode>(
Op);
1181 if (getTargetConstantFromLoad(LD)) {
1187 EVT MemVT = LD->getMemoryVT();
1199 auto *CIdx = dyn_cast<ConstantSDNode>(
Op.getOperand(2));
1204 APInt DemandedVecElts(DemandedElts);
1206 unsigned Idx = CIdx->getZExtValue();
1210 if (!DemandedElts[
Idx])
1217 if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO,
Depth + 1))
1223 if (SimplifyDemandedBits(Vec,
DemandedBits, DemandedVecElts, KnownVec, TLO,
1227 if (!!DemandedVecElts)
1242 APInt DemandedSrcElts = DemandedElts;
1246 if (SimplifyDemandedBits(Sub,
DemandedBits, DemandedSubElts, KnownSub, TLO,
1249 if (SimplifyDemandedBits(Src,
DemandedBits, DemandedSrcElts, KnownSrc, TLO,
1255 if (!!DemandedSubElts)
1257 if (!!DemandedSrcElts)
1263 SDValue NewSub = SimplifyMultipleUseDemandedBits(
1265 SDValue NewSrc = SimplifyMultipleUseDemandedBits(
1267 if (NewSub || NewSrc) {
1268 NewSub = NewSub ? NewSub : Sub;
1269 NewSrc = NewSrc ? NewSrc : Src;
1282 if (Src.getValueType().isScalableVector())
1285 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
1288 if (SimplifyDemandedBits(Src,
DemandedBits, DemandedSrcElts, Known, TLO,
1294 SDValue DemandedSrc = SimplifyMultipleUseDemandedBits(
1309 EVT SubVT =
Op.getOperand(0).getValueType();
1312 for (
unsigned i = 0; i != NumSubVecs; ++i) {
1313 APInt DemandedSubElts =
1314 DemandedElts.
extractBits(NumSubElts, i * NumSubElts);
1315 if (SimplifyDemandedBits(
Op.getOperand(i),
DemandedBits, DemandedSubElts,
1316 Known2, TLO,
Depth + 1))
1319 if (!!DemandedSubElts)
1329 APInt DemandedLHS, DemandedRHS;
1334 if (!!DemandedLHS || !!DemandedRHS) {
1340 if (!!DemandedLHS) {
1341 if (SimplifyDemandedBits(Op0,
DemandedBits, DemandedLHS, Known2, TLO,
1346 if (!!DemandedRHS) {
1347 if (SimplifyDemandedBits(Op1,
DemandedBits, DemandedRHS, Known2, TLO,
1354 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1356 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
1358 if (DemandedOp0 || DemandedOp1) {
1359 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1360 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
1395 LHSKnown.
One == ~RHSC->getAPIntValue()) {
1407 unsigned NumSubElts =
1424 if (SimplifyDemandedBits(Op1,
DemandedBits, DemandedElts, Known, TLO,
1429 Known2, TLO,
Depth + 1))
1452 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1454 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
1456 if (DemandedOp0 || DemandedOp1) {
1457 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1458 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
1471 if (SimplifyDemandedBits(Op1,
DemandedBits, DemandedElts, Known, TLO,
1475 if (SimplifyDemandedBits(Op0, ~Known.
One &
DemandedBits, DemandedElts,
1476 Known2, TLO,
Depth + 1))
1495 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1497 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
1499 if (DemandedOp0 || DemandedOp1) {
1500 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1501 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
1512 for (
int I = 0;
I != 2; ++
I) {
1515 SDValue Alt =
Op.getOperand(1 -
I).getOperand(0);
1516 SDValue C2 =
Op.getOperand(1 -
I).getOperand(1);
1518 for (
int J = 0; J != 2; ++J) {
1541 if (SimplifyDemandedBits(Op1,
DemandedBits, DemandedElts, Known, TLO,
1545 if (SimplifyDemandedBits(Op0,
DemandedBits, DemandedElts, Known2, TLO,
1573 if (
C->getAPIntValue() == Known2.
One) {
1582 if (!
C->isAllOnes() &&
DemandedBits.isSubsetOf(
C->getAPIntValue())) {
1594 if (ShiftC->getAPIntValue().ult(
BitWidth)) {
1595 uint64_t ShiftAmt = ShiftC->getZExtValue();
1598 : Ones.
lshr(ShiftAmt);
1616 if (!
C || !
C->isAllOnes())
1622 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1624 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
1626 if (DemandedOp0 || DemandedOp1) {
1627 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
1628 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
1638 if (SimplifyDemandedBits(
Op.getOperand(2),
DemandedBits, Known, TLO,
1641 if (SimplifyDemandedBits(
Op.getOperand(1),
DemandedBits, Known2, TLO,
1655 if (SimplifyDemandedBits(
Op.getOperand(2),
DemandedBits, DemandedElts,
1656 Known, TLO,
Depth + 1))
1658 if (SimplifyDemandedBits(
Op.getOperand(1),
DemandedBits, DemandedElts,
1659 Known2, TLO,
Depth + 1))
1668 if (SimplifyDemandedBits(
Op.getOperand(3),
DemandedBits, Known, TLO,
1671 if (SimplifyDemandedBits(
Op.getOperand(2),
DemandedBits, Known2, TLO,
1717 if (
const APInt *SA =
1719 unsigned ShAmt = SA->getZExtValue();
1729 if (
const APInt *SA2 =
1731 unsigned C1 = SA2->getZExtValue();
1733 int Diff = ShAmt - C1;
1752 if (ShAmt < InnerBits &&
DemandedBits.getActiveBits() <= InnerBits &&
1753 isTypeDesirableForOp(
ISD::SHL, InnerVT)) {
1769 if (
const APInt *SA2 =
1771 unsigned InnerShAmt = SA2->getZExtValue();
1772 if (InnerShAmt < ShAmt && InnerShAmt < InnerBits &&
1774 (InnerBits - InnerShAmt + ShAmt) &&
1788 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1792 Known.
Zero <<= ShAmt;
1793 Known.
One <<= ShAmt;
1799 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1800 Op0, InDemandedMask, DemandedElts, TLO.
DAG,
Depth + 1);
1818 if (SimplifyDemandedBits(Op0, DemandedFromOp, DemandedElts, Known, TLO,
1821 if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) {
1824 Flags.setNoSignedWrap(
false);
1825 Flags.setNoUnsignedWrap(
false);
1826 Op->setFlags(Flags);
1836 if (
const APInt *MaxSA =
1838 unsigned ShAmt = MaxSA->getZExtValue();
1839 unsigned NumSignBits =
1842 if (NumSignBits > ShAmt && (NumSignBits - ShAmt) >= (UpperDemandedBits))
1854 DemandedElts,
Depth + 1))
1857 if (
const APInt *SA =
1859 unsigned ShAmt = SA->getZExtValue();
1869 if (
const APInt *SA2 =
1871 unsigned C1 = SA2->getZExtValue();
1873 int Diff = ShAmt - C1;
1889 if (
Op->getFlags().hasExact())
1898 isTypeDesirableForOp(
ISD::SRL, HalfVT) &&
1914 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
1925 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
1926 Op0, InDemandedMask, DemandedElts, TLO.
DAG,
Depth + 1);
1960 DemandedElts,
Depth + 1))
1963 if (
const APInt *SA =
1965 unsigned ShAmt = SA->getZExtValue();
1972 if (
const APInt *InnerSA =
1974 unsigned LowBits =
BitWidth - ShAmt;
1980 if (*InnerSA == ShAmt) {
1990 unsigned NumSignBits =
1992 if (NumSignBits > ShAmt)
2002 if (
Op->getFlags().hasExact())
2010 if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
2022 Flags.setExact(
Op->getFlags().hasExact());
2040 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
2041 Op0, InDemandedMask, DemandedElts, TLO.
DAG,
Depth + 1);
2058 unsigned Amt = SA->getAPIntValue().urem(
BitWidth);
2063 if (SimplifyDemandedBits(IsFSHL ? Op0 : Op1,
DemandedBits, DemandedElts,
2064 Known, TLO,
Depth + 1))
2073 if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO,
2076 if (SimplifyDemandedBits(Op1, Demanded1, DemandedElts, Known, TLO,
2089 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
2090 Op0, Demanded0, DemandedElts, TLO.
DAG,
Depth + 1);
2091 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
2092 Op1, Demanded1, DemandedElts, TLO.
DAG,
Depth + 1);
2093 if (DemandedOp0 || DemandedOp1) {
2094 DemandedOp0 = DemandedOp0 ? DemandedOp0 : Op0;
2095 DemandedOp1 = DemandedOp1 ? DemandedOp1 : Op1;
2106 if (SimplifyDemandedBits(Op2, DemandedAmtBits, DemandedElts,
2107 Known2, TLO,
Depth + 1))
2123 unsigned Amt = SA->getAPIntValue().urem(
BitWidth);
2129 if (SimplifyDemandedBits(Op0, Demanded0, DemandedElts, Known2, TLO,
2139 DemandedBits.countr_zero() >= (IsROTL ? Amt : RevAmt)) {
2144 DemandedBits.countl_zero() >= (IsROTL ? RevAmt : Amt)) {
2153 if (SimplifyDemandedBits(Op1, DemandedAmtBits, DemandedElts, Known2, TLO,
2163 unsigned Opc =
Op.getOpcode();
2170 unsigned NumSignBits =
2174 if (NumSignBits >= NumDemandedUpperBits)
2215 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
2242 unsigned ShiftAmount = NLZ > NTZ ? NLZ - NTZ : NTZ - NLZ;
2250 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedElts, Known2, TLO,
2270 EVT ExVT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
2275 unsigned MinSignedBits =
2277 bool AlreadySignExtended = ExVTBits >= MinSignedBits;
2280 if (!AlreadySignExtended) {
2298 InputDemandedBits.
setBit(ExVTBits - 1);
2300 if (SimplifyDemandedBits(Op0, InputDemandedBits, DemandedElts, Known, TLO,
2309 if (Known.
Zero[ExVTBits - 1])
2313 if (Known.
One[ExVTBits - 1]) {
2323 EVT HalfVT =
Op.getOperand(0).getValueType();
2331 if (SimplifyDemandedBits(
Op.getOperand(0), MaskLo, KnownLo, TLO,
Depth + 1))
2334 if (SimplifyDemandedBits(
Op.getOperand(1), MaskHi, KnownHi, TLO,
Depth + 1))
2337 Known = KnownHi.
concat(KnownLo);
2346 EVT SrcVT = Src.getValueType();
2355 if (IsLE && IsVecInReg && DemandedElts == 1 &&
2366 APInt InDemandedElts = DemandedElts.
zext(InElts);
2367 if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
2375 if (
SDValue NewSrc = SimplifyMultipleUseDemandedBits(
2376 Src, InDemandedBits, InDemandedElts, TLO.
DAG,
Depth + 1))
2386 EVT SrcVT = Src.getValueType();
2395 if (IsLE && IsVecInReg && DemandedElts == 1 &&
2406 APInt InDemandedElts = DemandedElts.
zext(InElts);
2410 InDemandedBits.
setBit(InBits - 1);
2412 if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
2430 if (
SDValue NewSrc = SimplifyMultipleUseDemandedBits(
2431 Src, InDemandedBits, InDemandedElts, TLO.
DAG,
Depth + 1))
2441 EVT SrcVT = Src.getValueType();
2448 if (IsLE && IsVecInReg && DemandedElts == 1 &&
2453 APInt InDemandedElts = DemandedElts.
zext(InElts);
2454 if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
2462 if (
SDValue NewSrc = SimplifyMultipleUseDemandedBits(
2463 Src, InDemandedBits, InDemandedElts, TLO.
DAG,
Depth + 1))
2472 unsigned OperandBitWidth = Src.getScalarValueSizeInBits();
2474 if (SimplifyDemandedBits(Src, TruncMask, DemandedElts, Known, TLO,
2480 if (
SDValue NewSrc = SimplifyMultipleUseDemandedBits(
2481 Src, TruncMask, DemandedElts, TLO.
DAG,
Depth + 1))
2486 switch (Src.getOpcode()) {
2497 if (Src.getNode()->hasOneUse()) {
2498 const APInt *ShAmtC =
2529 EVT ZVT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
2531 if (SimplifyDemandedBits(
Op.getOperand(0), ~InMask |
DemandedBits, Known,
2536 Known.
Zero |= ~InMask;
2537 Known.
One &= (~Known.Zero);
2543 ElementCount SrcEltCnt = Src.getValueType().getVectorElementCount();
2544 unsigned EltBitWidth = Src.getScalarValueSizeInBits();
2552 if (
auto *CIdx = dyn_cast<ConstantSDNode>(
Idx))
2553 if (CIdx->getAPIntValue().ult(NumSrcElts))
2560 DemandedSrcBits = DemandedSrcBits.
trunc(EltBitWidth);
2562 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, Known2, TLO,
2568 if (
SDValue DemandedSrc = SimplifyMultipleUseDemandedBits(
2569 Src, DemandedSrcBits, DemandedSrcElts, TLO.
DAG,
Depth + 1)) {
2585 EVT SrcVT = Src.getValueType();
2595 if ((OpVTLegal || i32Legal) && VT.
isSimple() && SrcVT != MVT::f16 &&
2596 SrcVT != MVT::f128) {
2598 EVT Ty = OpVTLegal ? VT : MVT::i32;
2602 unsigned OpVTSizeInBits =
Op.getValueSizeInBits();
2603 if (!OpVTLegal && OpVTSizeInBits > 32)
2605 unsigned ShVal =
Op.getValueSizeInBits() - 1;
2615 unsigned Scale =
BitWidth / NumSrcEltBits;
2619 for (
unsigned i = 0; i != Scale; ++i) {
2620 unsigned EltOffset = IsLE ? i : (Scale - 1 - i);
2621 unsigned BitOffset = EltOffset * NumSrcEltBits;
2624 DemandedSrcBits |= Sub;
2625 for (
unsigned j = 0; j != NumElts; ++j)
2626 if (DemandedElts[j])
2627 DemandedSrcElts.
setBit((j * Scale) + i);
2631 APInt KnownSrcUndef, KnownSrcZero;
2632 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef,
2633 KnownSrcZero, TLO,
Depth + 1))
2637 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts,
2638 KnownSrcBits, TLO,
Depth + 1))
2640 }
else if (IsLE && (NumSrcEltBits %
BitWidth) == 0) {
2642 unsigned Scale = NumSrcEltBits /
BitWidth;
2646 for (
unsigned i = 0; i != NumElts; ++i)
2647 if (DemandedElts[i]) {
2650 DemandedSrcElts.
setBit(i / Scale);
2654 APInt KnownSrcUndef, KnownSrcZero;
2655 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownSrcUndef,
2656 KnownSrcZero, TLO,
Depth + 1))
2661 if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts,
2662 KnownSrcBits, TLO,
Depth + 1))
2667 if (
SDValue DemandedSrc = SimplifyMultipleUseDemandedBits(
2668 Src, DemandedSrcBits, DemandedSrcElts, TLO.
DAG,
Depth + 1)) {
2690 if (
C &&
C->getAPIntValue().countr_zero() == CTZ) {
2710 SDValue Op0 =
Op.getOperand(0), Op1 =
Op.getOperand(1);
2715 if (SimplifyDemandedBits(Op0, LoMask, DemandedElts, KnownOp0, TLO,
2717 SimplifyDemandedBits(Op1, LoMask, DemandedElts, KnownOp1, TLO,
2721 if (Flags.hasNoSignedWrap() || Flags.hasNoUnsignedWrap()) {
2724 Flags.setNoSignedWrap(
false);
2725 Flags.setNoUnsignedWrap(
false);
2726 Op->setFlags(Flags);
2738 SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits(
2739 Op0, LoMask, DemandedElts, TLO.
DAG,
Depth + 1);
2740 SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits(
2741 Op1, LoMask, DemandedElts, TLO.
DAG,
Depth + 1);
2742 if (DemandedOp0 || DemandedOp1) {
2743 Flags.setNoSignedWrap(
false);
2744 Flags.setNoUnsignedWrap(
false);
2745 Op0 = DemandedOp0 ? DemandedOp0 : Op0;
2746 Op1 = DemandedOp1 ? DemandedOp1 : Op1;
2748 TLO.
DAG.
getNode(
Op.getOpcode(), dl, VT, Op0, Op1, Flags);
2760 if (
C && !
C->isAllOnes() && !
C->isOne() &&
2761 (
C->getAPIntValue() | HighMask).isAllOnes()) {
2765 Flags.setNoSignedWrap(
false);
2766 Flags.setNoUnsignedWrap(
false);
2774 auto getShiftLeftAmt = [&HighMask](
SDValue Mul) ->
unsigned {
2801 if (
unsigned ShAmt = getShiftLeftAmt(Op0))
2804 if (
unsigned ShAmt = getShiftLeftAmt(Op1))
2805 return foldMul(
ISD::SUB, Op1.getOperand(0), Op0, ShAmt);
2809 if (
unsigned ShAmt = getShiftLeftAmt(Op1))
2810 return foldMul(
ISD::ADD, Op1.getOperand(0), Op0, ShAmt);
2818 Flags.hasNoSignedWrap(), KnownOp0,
2829 if (
Op.getValueType().isScalableVector())
2831 if (SimplifyDemandedBitsForTargetNode(
Op,
DemandedBits, DemandedElts,
2844 if (!isTargetCanonicalConstantNode(
Op) &&
2873 const APInt &DemandedElts,
2879 APInt KnownUndef, KnownZero;
2881 SimplifyDemandedVectorElts(
Op, DemandedElts, KnownUndef, KnownZero, TLO);
2893 const APInt &UndefOp0,
2894 const APInt &UndefOp1) {
2897 "Vector binop only");
2902 UndefOp1.
getBitWidth() == NumElts &&
"Bad type for undef analysis");
2904 auto getUndefOrConstantElt = [&](
SDValue V,
unsigned Index,
2905 const APInt &UndefVals) {
2906 if (UndefVals[
Index])
2909 if (
auto *BV = dyn_cast<BuildVectorSDNode>(V)) {
2913 auto *
C = dyn_cast<ConstantSDNode>(Elt);
2914 if (isa<ConstantFPSDNode>(Elt) || Elt.
isUndef() || (
C && !
C->isOpaque()))
2922 for (
unsigned i = 0; i != NumElts; ++i) {
2941 bool AssumeSingleUse)
const {
2942 EVT VT =
Op.getValueType();
2943 unsigned Opcode =
Op.getOpcode();
2944 APInt DemandedElts = OriginalDemandedElts;
2959 "Mask size mismatches value type element count!");
2968 if (!AssumeSingleUse && !
Op.getNode()->hasOneUse())
2972 if (DemandedElts == 0) {
2987 auto SimplifyDemandedVectorEltsBinOp = [&](
SDValue Op0,
SDValue Op1) {
2988 SDValue NewOp0 = SimplifyMultipleUseDemandedVectorElts(Op0, DemandedElts,
2990 SDValue NewOp1 = SimplifyMultipleUseDemandedVectorElts(Op1, DemandedElts,
2992 if (NewOp0 || NewOp1) {
2995 NewOp1 ? NewOp1 : Op1,
Op->getFlags());
3003 if (!DemandedElts[0]) {
3011 EVT SrcVT = Src.getValueType();
3023 if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero,
3033 EVT SrcVT = Src.getValueType();
3042 if (NumSrcElts == NumElts)
3043 return SimplifyDemandedVectorElts(Src, DemandedElts, KnownUndef,
3044 KnownZero, TLO,
Depth + 1);
3046 APInt SrcDemandedElts, SrcZero, SrcUndef;
3050 if ((NumElts % NumSrcElts) == 0) {
3051 unsigned Scale = NumElts / NumSrcElts;
3053 if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero,
3063 for (
unsigned i = 0; i != NumElts; ++i)
3064 if (DemandedElts[i]) {
3065 unsigned Ofs = (i % Scale) * EltSizeInBits;
3066 SrcDemandedBits.
setBits(Ofs, Ofs + EltSizeInBits);
3070 if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcDemandedElts, Known,
3078 for (
unsigned SubElt = 0; SubElt != Scale; ++SubElt) {
3082 for (
unsigned SrcElt = 0; SrcElt != NumSrcElts; ++SrcElt) {
3083 unsigned Elt = Scale * SrcElt + SubElt;
3084 if (DemandedElts[Elt])
3092 for (
unsigned i = 0; i != NumSrcElts; ++i) {
3093 if (SrcDemandedElts[i]) {
3095 KnownZero.
setBits(i * Scale, (i + 1) * Scale);
3097 KnownUndef.
setBits(i * Scale, (i + 1) * Scale);
3105 if ((NumSrcElts % NumElts) == 0) {
3106 unsigned Scale = NumSrcElts / NumElts;
3108 if (SimplifyDemandedVectorElts(Src, SrcDemandedElts, SrcUndef, SrcZero,
3114 for (
unsigned i = 0; i != NumElts; ++i) {
3115 if (DemandedElts[i]) {
3130 [&](
SDValue Elt) { return Op.getOperand(0) != Elt; })) {
3132 bool Updated =
false;
3133 for (
unsigned i = 0; i != NumElts; ++i) {
3134 if (!DemandedElts[i] && !Ops[i].
isUndef()) {
3144 for (
unsigned i = 0; i != NumElts; ++i) {
3146 if (
SrcOp.isUndef()) {
3148 }
else if (EltSizeInBits ==
SrcOp.getScalarValueSizeInBits() &&
3156 EVT SubVT =
Op.getOperand(0).getValueType();
3159 for (
unsigned i = 0; i != NumSubVecs; ++i) {
3162 APInt SubUndef, SubZero;
3163 if (SimplifyDemandedVectorElts(SubOp, SubElts, SubUndef, SubZero, TLO,
3166 KnownUndef.
insertBits(SubUndef, i * NumSubElts);
3167 KnownZero.
insertBits(SubZero, i * NumSubElts);
3172 bool FoundNewSub =
false;
3174 for (
unsigned i = 0; i != NumSubVecs; ++i) {
3177 SDValue NewSubOp = SimplifyMultipleUseDemandedVectorElts(
3178 SubOp, SubElts, TLO.
DAG,
Depth + 1);
3179 DemandedSubOps.
push_back(NewSubOp ? NewSubOp : SubOp);
3180 FoundNewSub = NewSubOp ?
true : FoundNewSub;
3198 APInt DemandedSrcElts = DemandedElts;
3201 APInt SubUndef, SubZero;
3202 if (SimplifyDemandedVectorElts(Sub, DemandedSubElts, SubUndef, SubZero, TLO,
3207 if (!DemandedSrcElts && !Src.isUndef())
3212 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, KnownUndef, KnownZero,
3220 SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts(
3221 Src, DemandedSrcElts, TLO.
DAG,
Depth + 1);
3222 SDValue NewSub = SimplifyMultipleUseDemandedVectorElts(
3223 Sub, DemandedSubElts, TLO.
DAG,
Depth + 1);
3224 if (NewSrc || NewSub) {
3225 NewSrc = NewSrc ? NewSrc : Src;
3226 NewSub = NewSub ? NewSub : Sub;
3228 NewSub,
Op.getOperand(2));
3237 if (Src.getValueType().isScalableVector())
3240 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
3243 APInt SrcUndef, SrcZero;
3244 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO,
3252 SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts(
3253 Src, DemandedSrcElts, TLO.
DAG,
Depth + 1);
3265 auto *CIdx = dyn_cast<ConstantSDNode>(
Op.getOperand(2));
3269 if (CIdx && CIdx->getAPIntValue().ult(NumElts)) {
3270 unsigned Idx = CIdx->getZExtValue();
3271 if (!DemandedElts[
Idx])
3274 APInt DemandedVecElts(DemandedElts);
3276 if (SimplifyDemandedVectorElts(Vec, DemandedVecElts, KnownUndef,
3277 KnownZero, TLO,
Depth + 1))
3286 APInt VecUndef, VecZero;
3287 if (SimplifyDemandedVectorElts(Vec, DemandedElts, VecUndef, VecZero, TLO,
3300 APInt UndefSel, UndefZero;
3301 if (SimplifyDemandedVectorElts(Sel, DemandedElts, UndefSel, UndefZero, TLO,
3306 APInt DemandedLHS(DemandedElts);
3307 APInt DemandedRHS(DemandedElts);
3308 APInt UndefLHS, ZeroLHS;
3309 APInt UndefRHS, ZeroRHS;
3310 if (SimplifyDemandedVectorElts(
LHS, DemandedLHS, UndefLHS, ZeroLHS, TLO,
3313 if (SimplifyDemandedVectorElts(
RHS, DemandedRHS, UndefRHS, ZeroRHS, TLO,
3317 KnownUndef = UndefLHS & UndefRHS;
3318 KnownZero = ZeroLHS & ZeroRHS;
3322 APInt DemandedSel = DemandedElts & ~KnownZero;
3323 if (DemandedSel != DemandedElts)
3324 if (SimplifyDemandedVectorElts(Sel, DemandedSel, UndefSel, UndefZero, TLO,
3336 APInt DemandedLHS(NumElts, 0);
3337 APInt DemandedRHS(NumElts, 0);
3338 for (
unsigned i = 0; i != NumElts; ++i) {
3339 int M = ShuffleMask[i];
3340 if (M < 0 || !DemandedElts[i])
3342 assert(0 <= M && M < (
int)(2 * NumElts) &&
"Shuffle index out of range");
3343 if (M < (
int)NumElts)
3346 DemandedRHS.
setBit(M - NumElts);
3350 APInt UndefLHS, ZeroLHS;
3351 APInt UndefRHS, ZeroRHS;
3352 if (SimplifyDemandedVectorElts(
LHS, DemandedLHS, UndefLHS, ZeroLHS, TLO,
3355 if (SimplifyDemandedVectorElts(
RHS, DemandedRHS, UndefRHS, ZeroRHS, TLO,
3360 bool Updated =
false;
3361 bool IdentityLHS =
true, IdentityRHS =
true;
3363 for (
unsigned i = 0; i != NumElts; ++i) {
3364 int &M = NewMask[i];
3367 if (!DemandedElts[i] || (M < (
int)NumElts && UndefLHS[M]) ||
3368 (M >= (
int)NumElts && UndefRHS[M - NumElts])) {
3372 IdentityLHS &= (M < 0) || (M == (
int)i);
3373 IdentityRHS &= (M < 0) || ((M - NumElts) == i);
3378 if (Updated && !IdentityLHS && !IdentityRHS && !TLO.
LegalOps) {
3380 buildLegalVectorShuffle(VT,
DL,
LHS,
RHS, NewMask, TLO.
DAG);
3386 for (
unsigned i = 0; i != NumElts; ++i) {
3387 int M = ShuffleMask[i];
3390 }
else if (M < (
int)NumElts) {
3396 if (UndefRHS[M - NumElts])
3398 if (ZeroRHS[M - NumElts])
3407 APInt SrcUndef, SrcZero;
3409 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
3410 APInt DemandedSrcElts = DemandedElts.
zext(NumSrcElts);
3411 if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO,
3418 Op.getValueSizeInBits() == Src.getValueSizeInBits() &&
3419 DemandedSrcElts == 1) {
3432 if (IsLE && DemandedSrcElts == 1 && Src.getOpcode() ==
ISD::AND &&
3433 Op->isOnlyUserOf(Src.getNode()) &&
3434 Op.getValueSizeInBits() == Src.getValueSizeInBits()) {
3436 EVT SrcVT = Src.getValueType();
3443 ISD::AND,
DL, SrcVT, {Src.getOperand(1), Mask})) {
3457 if (Op0 == Op1 &&
Op->isOnlyUserOf(Op0.
getNode())) {
3458 APInt UndefLHS, ZeroLHS;
3459 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO,
3476 APInt UndefRHS, ZeroRHS;
3477 if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO,
3480 APInt UndefLHS, ZeroLHS;
3481 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO,
3485 KnownZero = ZeroLHS & ZeroRHS;
3491 if (SimplifyDemandedVectorEltsBinOp(Op0, Op1))
3503 APInt UndefRHS, ZeroRHS;
3504 if (SimplifyDemandedVectorElts(Op1, DemandedElts, UndefRHS, ZeroRHS, TLO,
3507 APInt UndefLHS, ZeroLHS;
3508 if (SimplifyDemandedVectorElts(Op0, DemandedElts, UndefLHS, ZeroLHS, TLO,
3512 KnownZero = ZeroLHS;
3513 KnownUndef = UndefLHS & UndefRHS;
3518 if (SimplifyDemandedVectorEltsBinOp(Op0, Op1))
3529 APInt SrcUndef, SrcZero;
3530 if (SimplifyDemandedVectorElts(Op1, DemandedElts, SrcUndef, SrcZero, TLO,
3535 APInt DemandedElts0 = DemandedElts & ~SrcZero;
3536 if (SimplifyDemandedVectorElts(Op0, DemandedElts0, KnownUndef, KnownZero,
3540 KnownUndef &= DemandedElts0;
3541 KnownZero &= DemandedElts0;
3546 if (DemandedElts.
isSubsetOf(SrcZero | KnownZero | SrcUndef | KnownUndef))
3553 KnownZero |= SrcZero;
3554 KnownUndef &= SrcUndef;
3555 KnownUndef &= ~KnownZero;
3559 if (SimplifyDemandedVectorEltsBinOp(Op0, Op1))
3566 if (SimplifyDemandedVectorElts(
Op.getOperand(0), DemandedElts, KnownUndef,
3567 KnownZero, TLO,
Depth + 1))
3579 if (SimplifyDemandedVectorEltsForTargetNode(
Op, DemandedElts, KnownUndef,
3580 KnownZero, TLO,
Depth))
3585 if (SimplifyDemandedBits(
Op,
DemandedBits, OriginalDemandedElts, Known,
3586 TLO,
Depth, AssumeSingleUse))
3592 assert((KnownUndef & KnownZero) == 0 &&
"Elements flagged as undef AND zero");
3606 const APInt &DemandedElts,
3608 unsigned Depth)
const {
3613 "Should use MaskedValueIsZero if you don't know whether Op"
3614 " is a target node!");
3621 unsigned Depth)
const {
3633 unsigned Depth)
const {
3642 unsigned Depth)
const {
3647 "Should use ComputeNumSignBits if you don't know whether Op"
3648 " is a target node!");
3665 "Should use SimplifyDemandedVectorElts if you don't know whether Op"
3666 " is a target node!");
3677 "Should use SimplifyDemandedBits if you don't know whether Op"
3678 " is a target node!");
3679 computeKnownBitsForTargetNode(
Op, Known, DemandedElts, TLO.
DAG,
Depth);
3691 "Should use SimplifyMultipleUseDemandedBits if you don't know whether Op"
3692 " is a target node!");
3719 bool PoisonOnly,
unsigned Depth)
const {
3725 "Should use isGuaranteedNotToBeUndefOrPoison if you don't know whether Op"
3726 " is a target node!");
3732 bool PoisonOnly,
bool ConsiderFlags,
unsigned Depth)
const {
3737 "Should use canCreateUndefOrPoison if you don't know whether Op"
3738 " is a target node!");
3746 unsigned Depth)
const {
3751 "Should use isKnownNeverNaN if you don't know whether Op"
3752 " is a target node!");
3757 const APInt &DemandedElts,
3760 unsigned Depth)
const {
3765 "Should use isSplatValue if you don't know whether Op"
3766 " is a target node!");
3781 CVal = CN->getAPIntValue();
3782 EltWidth =
N.getValueType().getScalarSizeInBits();
3789 CVal = CVal.
trunc(EltWidth);
3795 return CVal.
isOne();
3837 return (
N->isOne() && !SExt) || (SExt && (
N->getValueType(0) != MVT::i1));
3840 return N->isAllOnes() && SExt;
3849 DAGCombinerInfo &DCI)
const {
3877 auto *AndC = dyn_cast<ConstantSDNode>(N0.
getOperand(1));
3878 if (AndC &&
isNullConstant(N1) && AndC->getAPIntValue().isPowerOf2() &&
3881 AndC->getAPIntValue().getActiveBits());
3908 if (isXAndYEqZeroPreferableToXAndYEqY(
Cond, OpVT) &&
3916 if (DCI.isBeforeLegalizeOps() ||
3950SDValue TargetLowering::optimizeSetCCOfSignedTruncationCheck(
3955 if (!(C1 = dyn_cast<ConstantSDNode>(N1)))
3964 if (!(C01 = dyn_cast<ConstantSDNode>(N0->
getOperand(1))))
3968 EVT XVT =
X.getValueType();
3992 auto checkConstants = [&
I1, &I01]() ->
bool {
3997 if (checkConstants()) {
4005 if (!checkConstants())
4011 const unsigned KeptBits =
I1.logBase2();
4012 const unsigned KeptBitsMinusOne = I01.
logBase2();
4015 if (KeptBits != (KeptBitsMinusOne + 1))
4039SDValue TargetLowering::optimizeSetCCByHoistingAndByConstFromLogicalShift(
4041 DAGCombinerInfo &DCI,
const SDLoc &
DL)
const {
4043 "Should be a comparison with 0.");
4045 "Valid only for [in]equality comparisons.");
4047 unsigned NewShiftOpcode;
4058 unsigned OldShiftOpcode =
V.getOpcode();
4059 switch (OldShiftOpcode) {
4071 C =
V.getOperand(0);
4076 Y =
V.getOperand(1);
4080 return TLI.shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
4081 X, XC,
CC,
Y, OldShiftOpcode, NewShiftOpcode, DAG);
4098 EVT VT =
X.getValueType();
4113 DAGCombinerInfo &DCI)
const {
4116 "Unexpected binop");
4143 !DCI.isBeforeLegalize());
4146 if (!DCI.isCalledByLegalizer())
4147 DCI.AddToWorklist(YShl1.
getNode());
4162 if (CTPOP.getOpcode() !=
ISD::CTPOP || !CTPOP.hasOneUse())
4165 EVT CTVT = CTPOP.getValueType();
4166 SDValue CTOp = CTPOP.getOperand(0);
4186 for (
unsigned i = 0; i <
Passes; i++) {
4231 auto getRotateSource = [](
SDValue X) {
4233 return X.getOperand(0);
4240 if (
SDValue R = getRotateSource(N0))
4273 if (!C1 || !C1->
isZero())
4282 if (!ShAmtC || ShAmtC->getAPIntValue().uge(
BitWidth))
4286 unsigned ShAmt = ShAmtC->getZExtValue();
4295 if (
Or.getOperand(0) ==
Other) {
4296 X =
Or.getOperand(0);
4297 Y =
Or.getOperand(1);
4300 if (
Or.getOperand(1) ==
Other) {
4301 X =
Or.getOperand(1);
4302 Y =
Or.getOperand(0);
4312 if (matchOr(F0, F1)) {
4319 if (matchOr(F1, F0)) {