LLVM 19.0.0git
BPFAsmParser.cpp
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1//===-- BPFAsmParser.cpp - Parse BPF assembly to MCInst instructions --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
11#include "llvm/ADT/STLExtras.h"
13#include "llvm/MC/MCContext.h"
14#include "llvm/MC/MCExpr.h"
15#include "llvm/MC/MCInst.h"
16#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCStreamer.h"
25
26using namespace llvm;
27
28namespace {
29struct BPFOperand;
30
31class BPFAsmParser : public MCTargetAsmParser {
32
33 SMLoc getLoc() const { return getParser().getTok().getLoc(); }
34
35 bool PreMatchCheck(OperandVector &Operands);
36
37 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
40 bool MatchingInlineAsm) override;
41
42 bool parseRegister(MCRegister &Reo, SMLoc &StartLoc, SMLoc &EndLoc) override;
44 SMLoc &EndLoc) override;
45
47 SMLoc NameLoc, OperandVector &Operands) override;
48
49 // "=" is used as assignment operator for assembly statment, so can't be used
50 // for symbol assignment.
51 bool equalIsAsmAssignment() override { return false; }
52 // "*" is used for dereferencing memory that it will be the start of
53 // statement.
54 bool starIsStartOfStatement() override { return true; }
55
56#define GET_ASSEMBLER_HEADER
57#include "BPFGenAsmMatcher.inc"
58
61 ParseStatus parseOperandAsOperator(OperandVector &Operands);
62
63public:
64 enum BPFMatchResultTy {
65 Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
66#define GET_OPERAND_DIAGNOSTIC_TYPES
67#include "BPFGenAsmMatcher.inc"
68#undef GET_OPERAND_DIAGNOSTIC_TYPES
69 };
70
71 BPFAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
72 const MCInstrInfo &MII, const MCTargetOptions &Options)
73 : MCTargetAsmParser(Options, STI, MII) {
74 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
75 }
76};
77
78/// BPFOperand - Instances of this class represent a parsed machine
79/// instruction
80struct BPFOperand : public MCParsedAsmOperand {
81
82 enum KindTy {
83 Token,
85 Immediate,
86 } Kind;
87
88 struct RegOp {
89 unsigned RegNum;
90 };
91
92 struct ImmOp {
93 const MCExpr *Val;
94 };
95
96 SMLoc StartLoc, EndLoc;
97 union {
98 StringRef Tok;
99 RegOp Reg;
100 ImmOp Imm;
101 };
102
103 BPFOperand(KindTy K) : Kind(K) {}
104
105public:
106 BPFOperand(const BPFOperand &o) : MCParsedAsmOperand() {
107 Kind = o.Kind;
108 StartLoc = o.StartLoc;
109 EndLoc = o.EndLoc;
110
111 switch (Kind) {
112 case Register:
113 Reg = o.Reg;
114 break;
115 case Immediate:
116 Imm = o.Imm;
117 break;
118 case Token:
119 Tok = o.Tok;
120 break;
121 }
122 }
123
124 bool isToken() const override { return Kind == Token; }
125 bool isReg() const override { return Kind == Register; }
126 bool isImm() const override { return Kind == Immediate; }
127 bool isMem() const override { return false; }
128
129 bool isConstantImm() const {
130 return isImm() && isa<MCConstantExpr>(getImm());
131 }
132
133 int64_t getConstantImm() const {
134 const MCExpr *Val = getImm();
135 return static_cast<const MCConstantExpr *>(Val)->getValue();
136 }
137
138 bool isSImm16() const {
139 return (isConstantImm() && isInt<16>(getConstantImm()));
140 }
141
142 bool isSymbolRef() const { return isImm() && isa<MCSymbolRefExpr>(getImm()); }
143
144 bool isBrTarget() const { return isSymbolRef() || isSImm16(); }
145
146 /// getStartLoc - Gets location of the first token of this operand
147 SMLoc getStartLoc() const override { return StartLoc; }
148 /// getEndLoc - Gets location of the last token of this operand
149 SMLoc getEndLoc() const override { return EndLoc; }
150
151 unsigned getReg() const override {
152 assert(Kind == Register && "Invalid type access!");
153 return Reg.RegNum;
154 }
155
156 const MCExpr *getImm() const {
157 assert(Kind == Immediate && "Invalid type access!");
158 return Imm.Val;
159 }
160
161 StringRef getToken() const {
162 assert(Kind == Token && "Invalid type access!");
163 return Tok;
164 }
165
166 void print(raw_ostream &OS) const override {
167 switch (Kind) {
168 case Immediate:
169 OS << *getImm();
170 break;
171 case Register:
172 OS << "<register x";
173 OS << getReg() << ">";
174 break;
175 case Token:
176 OS << "'" << getToken() << "'";
177 break;
178 }
179 }
180
181 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
182 assert(Expr && "Expr shouldn't be null!");
183
184 if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
185 Inst.addOperand(MCOperand::createImm(CE->getValue()));
186 else
188 }
189
190 // Used by the TableGen Code
191 void addRegOperands(MCInst &Inst, unsigned N) const {
192 assert(N == 1 && "Invalid number of operands!");
194 }
195
196 void addImmOperands(MCInst &Inst, unsigned N) const {
197 assert(N == 1 && "Invalid number of operands!");
198 addExpr(Inst, getImm());
199 }
200
201 static std::unique_ptr<BPFOperand> createToken(StringRef Str, SMLoc S) {
202 auto Op = std::make_unique<BPFOperand>(Token);
203 Op->Tok = Str;
204 Op->StartLoc = S;
205 Op->EndLoc = S;
206 return Op;
207 }
208
209 static std::unique_ptr<BPFOperand> createReg(unsigned RegNo, SMLoc S,
210 SMLoc E) {
211 auto Op = std::make_unique<BPFOperand>(Register);
212 Op->Reg.RegNum = RegNo;
213 Op->StartLoc = S;
214 Op->EndLoc = E;
215 return Op;
216 }
217
218 static std::unique_ptr<BPFOperand> createImm(const MCExpr *Val, SMLoc S,
219 SMLoc E) {
220 auto Op = std::make_unique<BPFOperand>(Immediate);
221 Op->Imm.Val = Val;
222 Op->StartLoc = S;
223 Op->EndLoc = E;
224 return Op;
225 }
226
227 // Identifiers that can be used at the start of a statment.
228 static bool isValidIdAtStart(StringRef Name) {
229 return StringSwitch<bool>(Name.lower())
230 .Case("if", true)
231 .Case("call", true)
232 .Case("callx", true)
233 .Case("goto", true)
234 .Case("gotol", true)
235 .Case("*", true)
236 .Case("exit", true)
237 .Case("lock", true)
238 .Case("ld_pseudo", true)
239 .Default(false);
240 }
241
242 // Identifiers that can be used in the middle of a statment.
243 static bool isValidIdInMiddle(StringRef Name) {
244 return StringSwitch<bool>(Name.lower())
245 .Case("u64", true)
246 .Case("u32", true)
247 .Case("u16", true)
248 .Case("u8", true)
249 .Case("s32", true)
250 .Case("s16", true)
251 .Case("s8", true)
252 .Case("be64", true)
253 .Case("be32", true)
254 .Case("be16", true)
255 .Case("le64", true)
256 .Case("le32", true)
257 .Case("le16", true)
258 .Case("bswap16", true)
259 .Case("bswap32", true)
260 .Case("bswap64", true)
261 .Case("goto", true)
262 .Case("gotol", true)
263 .Case("ll", true)
264 .Case("skb", true)
265 .Case("s", true)
266 .Case("atomic_fetch_add", true)
267 .Case("atomic_fetch_and", true)
268 .Case("atomic_fetch_or", true)
269 .Case("atomic_fetch_xor", true)
270 .Case("xchg_64", true)
271 .Case("xchg32_32", true)
272 .Case("cmpxchg_64", true)
273 .Case("cmpxchg32_32", true)
274 .Default(false);
275 }
276};
277} // end anonymous namespace.
278
279#define GET_REGISTER_MATCHER
280#define GET_MATCHER_IMPLEMENTATION
281#include "BPFGenAsmMatcher.inc"
282
283bool BPFAsmParser::PreMatchCheck(OperandVector &Operands) {
284
285 if (Operands.size() == 4) {
286 // check "reg1 = -reg2" and "reg1 = be16/be32/be64/le16/le32/le64 reg2",
287 // reg1 must be the same as reg2
288 BPFOperand &Op0 = (BPFOperand &)*Operands[0];
289 BPFOperand &Op1 = (BPFOperand &)*Operands[1];
290 BPFOperand &Op2 = (BPFOperand &)*Operands[2];
291 BPFOperand &Op3 = (BPFOperand &)*Operands[3];
292 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg()
293 && Op1.getToken() == "="
294 && (Op2.getToken() == "-" || Op2.getToken() == "be16"
295 || Op2.getToken() == "be32" || Op2.getToken() == "be64"
296 || Op2.getToken() == "le16" || Op2.getToken() == "le32"
297 || Op2.getToken() == "le64")
298 && Op0.getReg() != Op3.getReg())
299 return true;
300 }
301
302 return false;
303}
304
305bool BPFAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
308 bool MatchingInlineAsm) {
309 MCInst Inst;
310 SMLoc ErrorLoc;
311
312 if (PreMatchCheck(Operands))
313 return Error(IDLoc, "additional inst constraint not met");
314
315 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
316 default:
317 break;
318 case Match_Success:
319 Inst.setLoc(IDLoc);
320 Out.emitInstruction(Inst, getSTI());
321 return false;
322 case Match_MissingFeature:
323 return Error(IDLoc, "instruction use requires an option to be enabled");
324 case Match_MnemonicFail:
325 return Error(IDLoc, "unrecognized instruction mnemonic");
326 case Match_InvalidOperand:
327 ErrorLoc = IDLoc;
328
329 if (ErrorInfo != ~0U) {
330 if (ErrorInfo >= Operands.size())
331 return Error(ErrorLoc, "too few operands for instruction");
332
333 ErrorLoc = ((BPFOperand &)*Operands[ErrorInfo]).getStartLoc();
334
335 if (ErrorLoc == SMLoc())
336 ErrorLoc = IDLoc;
337 }
338
339 return Error(ErrorLoc, "invalid operand for instruction");
340 case Match_InvalidBrTarget:
341 return Error(Operands[ErrorInfo]->getStartLoc(),
342 "operand is not an identifier or 16-bit signed integer");
343 case Match_InvalidSImm16:
344 return Error(Operands[ErrorInfo]->getStartLoc(),
345 "operand is not a 16-bit signed integer");
346 }
347
348 llvm_unreachable("Unknown match type detected!");
349}
350
351bool BPFAsmParser::parseRegister(MCRegister &Reg, SMLoc &StartLoc,
352 SMLoc &EndLoc) {
353 if (!tryParseRegister(Reg, StartLoc, EndLoc).isSuccess())
354 return Error(StartLoc, "invalid register name");
355 return false;
356}
357
358ParseStatus BPFAsmParser::tryParseRegister(MCRegister &Reg, SMLoc &StartLoc,
359 SMLoc &EndLoc) {
360 const AsmToken &Tok = getParser().getTok();
361 StartLoc = Tok.getLoc();
362 EndLoc = Tok.getEndLoc();
363 Reg = BPF::NoRegister;
364 StringRef Name = getLexer().getTok().getIdentifier();
365
366 if (!MatchRegisterName(Name)) {
367 getParser().Lex(); // Eat identifier token.
369 }
370
372}
373
374ParseStatus BPFAsmParser::parseOperandAsOperator(OperandVector &Operands) {
375 SMLoc S = getLoc();
376
377 if (getLexer().getKind() == AsmToken::Identifier) {
378 StringRef Name = getLexer().getTok().getIdentifier();
379
380 if (BPFOperand::isValidIdInMiddle(Name)) {
381 getLexer().Lex();
382 Operands.push_back(BPFOperand::createToken(Name, S));
384 }
385
387 }
388
389 switch (getLexer().getKind()) {
390 case AsmToken::Minus:
391 case AsmToken::Plus: {
392 if (getLexer().peekTok().is(AsmToken::Integer))
394 [[fallthrough]];
395 }
396
397 case AsmToken::Equal:
399 case AsmToken::Less:
400 case AsmToken::Pipe:
401 case AsmToken::Star:
402 case AsmToken::LParen:
403 case AsmToken::RParen:
404 case AsmToken::LBrac:
405 case AsmToken::RBrac:
406 case AsmToken::Slash:
407 case AsmToken::Amp:
409 case AsmToken::Caret: {
410 StringRef Name = getLexer().getTok().getString();
411 getLexer().Lex();
412 Operands.push_back(BPFOperand::createToken(Name, S));
413
415 }
416
422 case AsmToken::LessLess: {
423 Operands.push_back(BPFOperand::createToken(
424 getLexer().getTok().getString().substr(0, 1), S));
425 Operands.push_back(BPFOperand::createToken(
426 getLexer().getTok().getString().substr(1, 1), S));
427 getLexer().Lex();
428
430 }
431
432 default:
433 break;
434 }
435
437}
438
439ParseStatus BPFAsmParser::parseRegister(OperandVector &Operands) {
440 SMLoc S = getLoc();
442
443 switch (getLexer().getKind()) {
444 default:
447 StringRef Name = getLexer().getTok().getIdentifier();
448 unsigned RegNo = MatchRegisterName(Name);
449
450 if (RegNo == 0)
452
453 getLexer().Lex();
454 Operands.push_back(BPFOperand::createReg(RegNo, S, E));
455 }
457}
458
459ParseStatus BPFAsmParser::parseImmediate(OperandVector &Operands) {
460 switch (getLexer().getKind()) {
461 default:
463 case AsmToken::LParen:
464 case AsmToken::Minus:
465 case AsmToken::Plus:
467 case AsmToken::String:
469 break;
470 }
471
472 const MCExpr *IdVal;
473 SMLoc S = getLoc();
474
475 if (getParser().parseExpression(IdVal))
477
479 Operands.push_back(BPFOperand::createImm(IdVal, S, E));
480
482}
483
484/// ParseInstruction - Parse an BPF instruction which is in BPF verifier
485/// format.
486bool BPFAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
487 SMLoc NameLoc, OperandVector &Operands) {
488 // The first operand could be either register or actually an operator.
489 unsigned RegNo = MatchRegisterName(Name);
490
491 if (RegNo != 0) {
492 SMLoc E = SMLoc::getFromPointer(NameLoc.getPointer() - 1);
493 Operands.push_back(BPFOperand::createReg(RegNo, NameLoc, E));
494 } else if (BPFOperand::isValidIdAtStart (Name))
495 Operands.push_back(BPFOperand::createToken(Name, NameLoc));
496 else
497 return Error(NameLoc, "invalid register/token name");
498
499 while (!getLexer().is(AsmToken::EndOfStatement)) {
500 // Attempt to parse token as operator
501 if (parseOperandAsOperator(Operands).isSuccess())
502 continue;
503
504 // Attempt to parse token as register
505 if (parseRegister(Operands).isSuccess())
506 continue;
507
508 if (getLexer().is(AsmToken::Comma)) {
509 getLexer().Lex();
510 continue;
511 }
512
513 // Attempt to parse token as an immediate
514 if (!parseImmediate(Operands).isSuccess()) {
515 SMLoc Loc = getLexer().getLoc();
516 return Error(Loc, "unexpected token");
517 }
518 }
519
520 if (getLexer().isNot(AsmToken::EndOfStatement)) {
521 SMLoc Loc = getLexer().getLoc();
522
523 getParser().eatToEndOfStatement();
524
525 return Error(Loc, "unexpected token");
526 }
527
528 // Consume the EndOfStatement.
529 getParser().Lex();
530 return false;
531}
532
537}
static MCRegister MatchRegisterName(StringRef Name)
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeBPFAsmParser()
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
std::string Name
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static LVOptions Options
Definition: LVOptions.cpp:25
mir Rename Register Operands
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
This file contains some templates that are useful if you are working with the STL at all.
raw_pwrite_stream & OS
static StringRef substr(StringRef Str, uint64_t Len)
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
bool parseImmediate(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes)
Target independent representation for an assembler token.
Definition: MCAsmMacro.h:21
SMLoc getLoc() const
Definition: MCAsmLexer.cpp:26
SMLoc getEndLoc() const
Definition: MCAsmLexer.cpp:30
This class represents an Operation in the Expression.
Base class for user error types.
Definition: Error.h:352
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
Generic assembler parser interface, for use by target specific assembly parsers.
Definition: MCAsmParser.h:123
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Definition: MCAsmParser.cpp:40
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void setLoc(SMLoc loc)
Definition: MCInst.h:203
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Streaming machine code generation interface.
Definition: MCStreamer.h:212
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
MCTargetAsmParser - Generic interface to target specific assembly parsers.
virtual bool equalIsAsmAssignment()
virtual bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
virtual ParseStatus tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
tryParseRegister - parse one register if possible
virtual bool starIsStartOfStatement()
void setAvailableFeatures(const FeatureBitset &Value)
virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands)=0
ParseInstruction - Parse one assembly instruction.
virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm)=0
MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst ...
Ternary parse status returned by various parse* methods.
static constexpr StatusTy Failure
static constexpr StatusTy Success
static constexpr StatusTy NoMatch
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents a location in source code.
Definition: SMLoc.h:23
static SMLoc getFromPointer(const char *Ptr)
Definition: SMLoc.h:36
constexpr const char * getPointer() const
Definition: SMLoc.h:34
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
StringSwitch & Case(StringLiteral S, T Value)
Definition: StringSwitch.h:69
R Default(T Value)
Definition: StringSwitch.h:182
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ CE
Windows NT (Windows on ARM)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:148
Target & getTheBPFleTarget()
Target & getTheBPFbeTarget()
Target & getTheBPFTarget()
DWARFExpression::Operation Op
#define N
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...