40 bool MatchingInlineAsm)
override;
43 SMLoc &EndLoc)
override;
45 SMLoc &EndLoc)
override;
59#define GET_ASSEMBLER_HEADER
60#include "BPFGenAsmMatcher.inc"
67 enum BPFMatchResultTy {
69#define GET_OPERAND_DIAGNOSTIC_TYPES
70#include "BPFGenAsmMatcher.inc"
71#undef GET_OPERAND_DIAGNOSTIC_TYPES
99 SMLoc StartLoc, EndLoc;
106 BPFOperand(KindTy K) :
Kind(K) {}
111 StartLoc = o.StartLoc;
127 bool isToken()
const override {
return Kind == Token; }
129 bool isImm()
const override {
return Kind == Immediate; }
130 bool isMem()
const override {
return false; }
132 bool isConstantImm()
const {
133 return isImm() && isa<MCConstantExpr>(getImm());
136 int64_t getConstantImm()
const {
137 const MCExpr *Val = getImm();
141 bool isSImm12()
const {
142 return (isConstantImm() && isInt<12>(getConstantImm()));
146 SMLoc getStartLoc()
const override {
return StartLoc; }
148 SMLoc getEndLoc()
const override {
return EndLoc; }
150 unsigned getReg()
const override {
155 const MCExpr *getImm()
const {
156 assert(Kind == Immediate &&
"Invalid type access!");
161 assert(Kind == Token &&
"Invalid type access!");
175 OS <<
"'" << getToken() <<
"'";
181 assert(Expr &&
"Expr shouldn't be null!");
183 if (
auto *CE = dyn_cast<MCConstantExpr>(Expr))
190 void addRegOperands(
MCInst &Inst,
unsigned N)
const {
191 assert(
N == 1 &&
"Invalid number of operands!");
195 void addImmOperands(
MCInst &Inst,
unsigned N)
const {
196 assert(
N == 1 &&
"Invalid number of operands!");
197 addExpr(Inst, getImm());
200 static std::unique_ptr<BPFOperand> createToken(
StringRef Str,
SMLoc S) {
201 auto Op = std::make_unique<BPFOperand>(Token);
208 static std::unique_ptr<BPFOperand> createReg(
unsigned RegNo,
SMLoc S,
210 auto Op = std::make_unique<BPFOperand>(
Register);
211 Op->Reg.RegNum = RegNo;
217 static std::unique_ptr<BPFOperand> createImm(
const MCExpr *Val,
SMLoc S,
219 auto Op = std::make_unique<BPFOperand>(Immediate);
235 .
Case(
"ld_pseudo",
true)
261#define GET_REGISTER_MATCHER
262#define GET_MATCHER_IMPLEMENTATION
263#include "BPFGenAsmMatcher.inc"
270 BPFOperand &Op0 = (BPFOperand &)*
Operands[0];
271 BPFOperand &Op1 = (BPFOperand &)*
Operands[1];
272 BPFOperand &Op2 = (BPFOperand &)*
Operands[2];
273 BPFOperand &Op3 = (BPFOperand &)*
Operands[3];
274 if (Op0.isReg() && Op1.isToken() && Op2.isToken() && Op3.isReg()
275 && Op1.getToken() ==
"="
276 && (Op2.getToken() ==
"-" || Op2.getToken() ==
"be16"
277 || Op2.getToken() ==
"be32" || Op2.getToken() ==
"be64"
278 || Op2.getToken() ==
"le16" || Op2.getToken() ==
"le32"
279 || Op2.getToken() ==
"le64")
280 && Op0.getReg() != Op3.getReg())
287bool BPFAsmParser::MatchAndEmitInstruction(
SMLoc IDLoc,
unsigned &Opcode,
290 bool MatchingInlineAsm) {
295 return Error(IDLoc,
"additional inst constraint not met");
304 case Match_MissingFeature:
305 return Error(IDLoc,
"instruction use requires an option to be enabled");
306 case Match_MnemonicFail:
307 return Error(IDLoc,
"unrecognized instruction mnemonic");
308 case Match_InvalidOperand:
313 return Error(ErrorLoc,
"too few operands for instruction");
317 if (ErrorLoc ==
SMLoc())
321 return Error(ErrorLoc,
"invalid operand for instruction");
330 return Error(StartLoc,
"invalid register name");
337 const AsmToken &Tok = getParser().getTok();
358 if (BPFOperand::isValidIdInMiddle(
Name)) {
367 switch (getLexer().getKind()) {
401 Operands.push_back(BPFOperand::createToken(
402 getLexer().getTok().getString().
substr(0, 1), S));
403 Operands.push_back(BPFOperand::createToken(
404 getLexer().getTok().getString().
substr(1, 1), S));
421 switch (getLexer().getKind()) {
432 Operands.push_back(BPFOperand::createReg(RegNo, S,
E));
438 switch (getLexer().getKind()) {
453 if (getParser().parseExpression(IdVal))
457 Operands.push_back(BPFOperand::createImm(IdVal, S,
E));
471 Operands.push_back(BPFOperand::createReg(RegNo, NameLoc,
E));
472 }
else if (BPFOperand::isValidIdAtStart (
Name))
473 Operands.push_back(BPFOperand::createToken(
Name, NameLoc));
475 return Error(NameLoc,
"invalid register/token name");
488 SMLoc Loc = getLexer().getLoc();
489 return Error(Loc,
"unexpected token");
494 SMLoc Loc = getLexer().getLoc();
496 getParser().eatToEndOfStatement();
498 return Error(Loc,
"unexpected token");
506bool BPFAsmParser::ParseDirective(
AsmToken DirectiveID) {
return true; }
static unsigned MatchRegisterName(StringRef Name)
static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI)
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeBPFAsmParser()
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
mir Rename Register Operands
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isImm(const MachineOperand &MO, MachineRegisterInfo *MRI)
static StringRef substr(StringRef Str, uint64_t Len)
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
bool parseImmediate(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes)
Target independent representation for an assembler token.
Base class for user error types.
Lightweight error class with error context and mandatory checking.
MCAsmParser & getParser()
Generic assembler parser interface, for use by target specific assembly parsers.
const AsmToken & getTok() const
Get the current AsmToken from the stream.
Base class for the full range of assembler expressions which are needed for parsing.
Instances of this class represent a single low-level machine instruction.
void addOperand(const MCOperand Op)
Interface to description of machine instruction set.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
MCParsedAsmOperand - This abstract class represents a source-level assembly instruction operand.
Wrapper class representing physical registers. Should be passed by value.
Streaming machine code generation interface.
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
MCTargetAsmParser - Generic interface to target specific assembly parsers.
virtual bool ParseDirective(AsmToken DirectiveID)=0
ParseDirective - Parse a target specific assembler directive.
virtual bool equalIsAsmAssignment()
@ FIRST_TARGET_MATCH_RESULT_TY
virtual bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
virtual bool starIsStartOfStatement()
void setAvailableFeatures(const FeatureBitset &Value)
virtual bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands)=0
ParseInstruction - Parse one assembly instruction.
virtual bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm)=0
MatchAndEmitInstruction - Recognize a series of operands of a parsed instruction as an actual MCInst ...
virtual OperandMatchResultTy tryParseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc)=0
tryParseRegister - parse one register if possible
Wrapper class representing virtual and physical registers.
Represents a location in source code.
static SMLoc getFromPointer(const char *Ptr)
const char * getPointer() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ CE
Windows NT (Windows on ARM)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
static bool isMem(const MachineInstr &MI, unsigned Op)
Target & getTheBPFleTarget()
Target & getTheBPFbeTarget()
Target & getTheBPFTarget()
RegisterMCAsmParser - Helper template for registering a target specific assembly parser,...