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X86InstrInfo.h
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1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 
17 #include "X86InstrFMA3Info.h"
18 #include "X86RegisterInfo.h"
21 #include <vector>
22 
23 #define GET_INSTRINFO_HEADER
24 #include "X86GenInstrInfo.inc"
25 
26 namespace llvm {
27 class X86Subtarget;
28 
29 namespace X86 {
30 
32  // For instr that was compressed from EVEX to VEX.
34 };
35 
36 /// Return a pair of condition code for the given predicate and whether
37 /// the instruction operands should be swaped to match the condition code.
38 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
39 
40 /// Return a cmov opcode for the given register size in bytes, and operand type.
41 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
42 
43 /// Return the source operand # for condition code by \p MCID. If the
44 /// instruction doesn't have a condition code, return -1.
45 int getCondSrcNoFromDesc(const MCInstrDesc &MCID);
46 
47 /// Return the condition code of the instruction. If the instruction doesn't
48 /// have a condition code, return X86::COND_INVALID.
50 
51 // Turn JCC instruction into condition code.
53 
54 // Turn SETCC instruction into condition code.
56 
57 // Turn CMOV instruction into condition code.
59 
60 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
61 /// e.g. turning COND_E to COND_NE.
63 
64 /// Get the VPCMP immediate for the given condition.
66 
67 /// Get the VPCMP immediate if the opcodes are swapped.
68 unsigned getSwappedVPCMPImm(unsigned Imm);
69 
70 /// Get the VPCOM immediate if the opcodes are swapped.
71 unsigned getSwappedVPCOMImm(unsigned Imm);
72 
73 /// Get the VCMP immediate if the opcodes are swapped.
74 unsigned getSwappedVCMPImm(unsigned Imm);
75 
76 /// Check if the instruction is X87 instruction.
78 } // namespace X86
79 
80 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
81 /// a reference to a stub for a global, not the global itself.
82 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
83  switch (TargetFlag) {
84  case X86II::MO_DLLIMPORT: // dllimport stub.
85  case X86II::MO_GOTPCREL: // rip-relative GOT reference.
86  case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference.
87  case X86II::MO_GOT: // normal GOT reference.
88  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
89  case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
90  case X86II::MO_COFFSTUB: // COFF .refptr stub.
91  return true;
92  default:
93  return false;
94  }
95 }
96 
97 /// isGlobalRelativeToPICBase - Return true if the specified global value
98 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
99 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
100 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
101  switch (TargetFlag) {
102  case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
103  case X86II::MO_GOT: // isPICStyleGOT: other global.
104  case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
105  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
106  case X86II::MO_TLVP: // ??? Pretty sure..
107  return true;
108  default:
109  return false;
110  }
111 }
112 
113 inline static bool isScale(const MachineOperand &MO) {
114  return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
115  MO.getImm() == 4 || MO.getImm() == 8);
116 }
117 
118 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
119  if (MI.getOperand(Op).isFI())
120  return true;
121  return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
122  MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
123  isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
124  MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
125  (MI.getOperand(Op + X86::AddrDisp).isImm() ||
126  MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
127  MI.getOperand(Op + X86::AddrDisp).isCPI() ||
128  MI.getOperand(Op + X86::AddrDisp).isJTI());
129 }
130 
131 inline static bool isMem(const MachineInstr &MI, unsigned Op) {
132  if (MI.getOperand(Op).isFI())
133  return true;
134  return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
135  MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
136 }
137 
138 class X86InstrInfo final : public X86GenInstrInfo {
139  X86Subtarget &Subtarget;
140  const X86RegisterInfo RI;
141 
142  virtual void anchor();
143 
144  bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
145  MachineBasicBlock *&FBB,
147  SmallVectorImpl<MachineInstr *> &CondBranches,
148  bool AllowModify) const;
149 
150 public:
151  explicit X86InstrInfo(X86Subtarget &STI);
152 
153  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
154  /// such, whenever a client has an instance of instruction info, it should
155  /// always be able to get register info as well (through this method).
156  ///
157  const X86RegisterInfo &getRegisterInfo() const { return RI; }
158 
159  /// Returns the stack pointer adjustment that happens inside the frame
160  /// setup..destroy sequence (e.g. by pushes, or inside the callee).
161  int64_t getFrameAdjustment(const MachineInstr &I) const {
162  assert(isFrameInstr(I));
163  if (isFrameSetup(I))
164  return I.getOperand(2).getImm();
165  return I.getOperand(1).getImm();
166  }
167 
168  /// Sets the stack pointer adjustment made inside the frame made up by this
169  /// instruction.
170  void setFrameAdjustment(MachineInstr &I, int64_t V) const {
171  assert(isFrameInstr(I));
172  if (isFrameSetup(I))
173  I.getOperand(2).setImm(V);
174  else
175  I.getOperand(1).setImm(V);
176  }
177 
178  /// getSPAdjust - This returns the stack pointer adjustment made by
179  /// this instruction. For x86, we need to handle more complex call
180  /// sequences involving PUSHes.
181  int getSPAdjust(const MachineInstr &MI) const override;
182 
183  /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
184  /// extension instruction. That is, it's like a copy where it's legal for the
185  /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
186  /// true, then it's expected the pre-extension value is available as a subreg
187  /// of the result register. This also returns the sub-register index in
188  /// SubIdx.
189  bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
190  Register &DstReg, unsigned &SubIdx) const override;
191 
192  /// Returns true if the instruction has no behavior (specified or otherwise)
193  /// that is based on the value of any of its register operands
194  ///
195  /// Instructions are considered data invariant even if they set EFLAGS.
196  ///
197  /// A classical example of something that is inherently not data invariant is
198  /// an indirect jump -- the destination is loaded into icache based on the
199  /// bits set in the jump destination register.
200  ///
201  /// FIXME: This should become part of our instruction tables.
202  static bool isDataInvariant(MachineInstr &MI);
203 
204  /// Returns true if the instruction has no behavior (specified or otherwise)
205  /// that is based on the value loaded from memory or the value of any
206  /// non-address register operands.
207  ///
208  /// For example, if the latency of the instruction is dependent on the
209  /// particular bits set in any of the registers *or* any of the bits loaded
210  /// from memory.
211  ///
212  /// Instructions are considered data invariant even if they set EFLAGS.
213  ///
214  /// A classical example of something that is inherently not data invariant is
215  /// an indirect jump -- the destination is loaded into icache based on the
216  /// bits set in the jump destination register.
217  ///
218  /// FIXME: This should become part of our instruction tables.
219  static bool isDataInvariantLoad(MachineInstr &MI);
220 
221  unsigned isLoadFromStackSlot(const MachineInstr &MI,
222  int &FrameIndex) const override;
223  unsigned isLoadFromStackSlot(const MachineInstr &MI,
224  int &FrameIndex,
225  unsigned &MemBytes) const override;
226  /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
227  /// stack locations as well. This uses a heuristic so it isn't
228  /// reliable for correctness.
229  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
230  int &FrameIndex) const override;
231 
232  unsigned isStoreToStackSlot(const MachineInstr &MI,
233  int &FrameIndex) const override;
234  unsigned isStoreToStackSlot(const MachineInstr &MI,
235  int &FrameIndex,
236  unsigned &MemBytes) const override;
237  /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
238  /// stack locations as well. This uses a heuristic so it isn't
239  /// reliable for correctness.
240  unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
241  int &FrameIndex) const override;
242 
243  bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
245  Register DestReg, unsigned SubIdx,
246  const MachineInstr &Orig,
247  const TargetRegisterInfo &TRI) const override;
248 
249  /// Given an operand within a MachineInstr, insert preceding code to put it
250  /// into the right format for a particular kind of LEA instruction. This may
251  /// involve using an appropriate super-register instead (with an implicit use
252  /// of the original) or creating a new virtual register and inserting COPY
253  /// instructions to get the data into the right class.
254  ///
255  /// Reference parameters are set to indicate how caller should add this
256  /// operand to the LEA instruction.
257  bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
258  unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
259  bool &isKill, MachineOperand &ImplicitOp,
260  LiveVariables *LV, LiveIntervals *LIS) const;
261 
262  /// convertToThreeAddress - This method must be implemented by targets that
263  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
264  /// may be able to convert a two-address instruction into a true
265  /// three-address instruction on demand. This allows the X86 target (for
266  /// example) to convert ADD and SHL instructions into LEA instructions if they
267  /// would require register copies due to two-addressness.
268  ///
269  /// This method returns a null pointer if the transformation cannot be
270  /// performed, otherwise it returns the new instruction.
271  ///
273  LiveIntervals *LIS) const override;
274 
275  /// Returns true iff the routine could find two commutable operands in the
276  /// given machine instruction.
277  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
278  /// input values can be re-defined in this method only if the input values
279  /// are not pre-defined, which is designated by the special value
280  /// 'CommuteAnyOperandIndex' assigned to it.
281  /// If both of indices are pre-defined and refer to some operands, then the
282  /// method simply returns true if the corresponding operands are commutable
283  /// and returns false otherwise.
284  ///
285  /// For example, calling this method this way:
286  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
287  /// findCommutedOpIndices(MI, Op1, Op2);
288  /// can be interpreted as a query asking to find an operand that would be
289  /// commutable with the operand#1.
290  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
291  unsigned &SrcOpIdx2) const override;
292 
293  /// Returns true if we have preference on the operands order in MI, the
294  /// commute decision is returned in Commute.
295  bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override;
296 
297  /// Returns an adjusted FMA opcode that must be used in FMA instruction that
298  /// performs the same computations as the given \p MI but which has the
299  /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
300  /// It may return 0 if it is unsafe to commute the operands.
301  /// Note that a machine instruction (instead of its opcode) is passed as the
302  /// first parameter to make it possible to analyze the instruction's uses and
303  /// commute the first operand of FMA even when it seems unsafe when you look
304  /// at the opcode. For example, it is Ok to commute the first operand of
305  /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
306  ///
307  /// The returned FMA opcode may differ from the opcode in the given \p MI.
308  /// For example, commuting the operands #1 and #3 in the following FMA
309  /// FMA213 #1, #2, #3
310  /// results into instruction with adjusted opcode:
311  /// FMA231 #3, #2, #1
312  unsigned
313  getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
314  unsigned SrcOpIdx2,
315  const X86InstrFMA3Group &FMA3Group) const;
316 
317  // Branch analysis.
318  bool isUnconditionalTailCall(const MachineInstr &MI) const override;
320  const MachineInstr &TailCall) const override;
323  const MachineInstr &TailCall) const override;
324 
326  MachineBasicBlock *&FBB,
328  bool AllowModify) const override;
329 
332  const TargetRegisterInfo *TRI) const override;
333 
335  int64_t &ImmVal) const override;
336 
338  const Register NullValueReg,
339  const TargetRegisterInfo *TRI) const override;
340 
342  const MachineInstr &LdSt,
343  SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
344  bool &OffsetIsScalable, unsigned &Width,
345  const TargetRegisterInfo *TRI) const override;
348  bool AllowModify = false) const override;
349 
351  int *BytesRemoved = nullptr) const override;
354  const DebugLoc &DL,
355  int *BytesAdded = nullptr) const override;
357  Register, Register, Register, int &, int &,
358  int &) const override;
360  const DebugLoc &DL, Register DstReg,
362  Register FalseReg) const override;
364  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
365  bool KillSrc) const override;
368  bool isKill, int FrameIndex,
369  const TargetRegisterClass *RC,
370  const TargetRegisterInfo *TRI) const override;
371 
374  int FrameIndex, const TargetRegisterClass *RC,
375  const TargetRegisterInfo *TRI) const override;
376 
378  unsigned Opc, Register Reg, int FrameIdx,
379  bool isKill = false) const;
380 
381  bool expandPostRAPseudo(MachineInstr &MI) const override;
382 
383  /// Check whether the target can fold a load that feeds a subreg operand
384  /// (or a subreg operand that feeds a store).
385  bool isSubregFoldable() const override { return true; }
386 
387  /// foldMemoryOperand - If this target supports it, fold a load or store of
388  /// the specified stack slot into the specified machine instruction for the
389  /// specified operand(s). If this is possible, the target should perform the
390  /// folding and return true, otherwise it should return false. If it folds
391  /// the instruction, it is likely that the MachineInstruction the iterator
392  /// references has been changed.
393  MachineInstr *
395  ArrayRef<unsigned> Ops,
397  LiveIntervals *LIS = nullptr,
398  VirtRegMap *VRM = nullptr) const override;
399 
400  /// foldMemoryOperand - Same as the previous version except it allows folding
401  /// of any load and store from / to any address, not just from a specific
402  /// stack slot.
405  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
406  LiveIntervals *LIS = nullptr) const override;
407 
408  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
409  /// a store or a load and a store into two or more instruction. If this is
410  /// possible, returns true as well as the new instructions by reference.
411  bool
413  bool UnfoldLoad, bool UnfoldStore,
414  SmallVectorImpl<MachineInstr *> &NewMIs) const override;
415 
417  SmallVectorImpl<SDNode *> &NewNodes) const override;
418 
419  /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
420  /// instruction after load / store are unfolded from an instruction of the
421  /// specified opcode. It returns zero if the specified unfolding is not
422  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
423  /// index of the operand which will hold the register holding the loaded
424  /// value.
425  unsigned
426  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
427  unsigned *LoadRegIndex = nullptr) const override;
428 
429  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
430  /// to determine if two loads are loading from the same base address. It
431  /// should only return true if the base pointers are the same and the
432  /// only differences between the two addresses are the offset. It also returns
433  /// the offsets by reference.
434  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
435  int64_t &Offset2) const override;
436 
437  /// isSchedulingBoundary - Overrides the isSchedulingBoundary from
438  /// Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR
439  /// intructions and prevent it from being re-scheduled.
441  const MachineBasicBlock *MBB,
442  const MachineFunction &MF) const override;
443 
444  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
445  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
446  /// should be scheduled togther. On some targets if two loads are loading from
447  /// addresses in the same cache line, it's better if they are scheduled
448  /// together. This function takes two integers that represent the load offsets
449  /// from the common base address. It returns true if it decides it's desirable
450  /// to schedule the two loads together. "NumLoads" is the number of loads that
451  /// have already been scheduled after Load1.
452  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
453  int64_t Offset2,
454  unsigned NumLoads) const override;
455 
456  MCInst getNop() const override;
457 
458  bool
460 
461  /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
462  /// instruction that defines the specified register class.
463  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
464 
465  /// True if MI has a condition code def, e.g. EFLAGS, that is
466  /// not marked dead.
467  bool hasLiveCondCodeDef(MachineInstr &MI) const;
468 
469  /// getGlobalBaseReg - Return a virtual register initialized with the
470  /// the global base register value. Output instructions required to
471  /// initialize the register in the function entry block, if necessary.
472  ///
473  unsigned getGlobalBaseReg(MachineFunction *MF) const;
474 
475  std::pair<uint16_t, uint16_t>
476  getExecutionDomain(const MachineInstr &MI) const override;
477 
479 
480  void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
481 
482  bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
483 
484  unsigned
485  getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
486  const TargetRegisterInfo *TRI) const override;
487  unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
488  const TargetRegisterInfo *TRI) const override;
489  void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
490  const TargetRegisterInfo *TRI) const override;
491 
493  unsigned OpNum,
496  unsigned Size, Align Alignment,
497  bool AllowCommute) const;
498 
499  bool isHighLatencyDef(int opc) const override;
500 
501  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
502  const MachineRegisterInfo *MRI,
503  const MachineInstr &DefMI, unsigned DefIdx,
504  const MachineInstr &UseMI,
505  unsigned UseIdx) const override;
506 
507  bool useMachineCombiner() const override { return true; }
508 
509  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
510 
511  bool hasReassociableOperands(const MachineInstr &Inst,
512  const MachineBasicBlock *MBB) const override;
513 
514  void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
515  MachineInstr &NewMI1,
516  MachineInstr &NewMI2) const override;
517 
518  /// analyzeCompare - For a comparison instruction, return the source registers
519  /// in SrcReg and SrcReg2 if having two register operands, and the value it
520  /// compares against in CmpValue. Return true if the comparison instruction
521  /// can be analyzed.
522  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
523  Register &SrcReg2, int64_t &CmpMask,
524  int64_t &CmpValue) const override;
525 
526  /// optimizeCompareInstr - Check if there exists an earlier instruction that
527  /// operates on the same source operands and sets flags in the same way as
528  /// Compare; remove Compare if possible.
529  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
530  Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
531  const MachineRegisterInfo *MRI) const override;
532 
533  /// optimizeLoadInstr - Try to remove the load by folding it to a register
534  /// operand at the use. We fold the load instructions if and only if the
535  /// def and use are in the same BB. We only look at one load and see
536  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
537  /// defined by the load we are trying to fold. DefMI returns the machine
538  /// instruction that defines FoldAsLoadDefReg, and the function returns
539  /// the machine instruction generated due to folding.
541  const MachineRegisterInfo *MRI,
542  Register &FoldAsLoadDefReg,
543  MachineInstr *&DefMI) const override;
544 
545  std::pair<unsigned, unsigned>
546  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
547 
550 
552  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
553 
555  bool OutlineFromLinkOnceODRs) const override;
556 
558  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
559 
561  const outliner::OutlinedFunction &OF) const override;
562 
566  outliner::Candidate &C) const override;
567 
568  bool verifyInstruction(const MachineInstr &MI,
569  StringRef &ErrInfo) const override;
570 #define GET_INSTRINFO_HELPER_DECLS
571 #include "X86GenInstrInfo.inc"
572 
573  static bool hasLockPrefix(const MachineInstr &MI) {
574  return MI.getDesc().TSFlags & X86II::LOCK;
575  }
576 
578  Register Reg) const override;
579 
580 protected:
581  /// Commutes the operands in the given instruction by changing the operands
582  /// order and/or changing the instruction's opcode and/or the immediate value
583  /// operand.
584  ///
585  /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
586  /// to be commuted.
587  ///
588  /// Do not call this method for a non-commutable instruction or
589  /// non-commutable operands.
590  /// Even though the instruction is commutable, the method may still
591  /// fail to commute the operands, null pointer is returned in such cases.
593  unsigned CommuteOpIdx1,
594  unsigned CommuteOpIdx2) const override;
595 
596  /// If the specific machine instruction is a instruction that moves/copies
597  /// value from one register to another register return destination and source
598  /// registers as machine operands.
600  isCopyInstrImpl(const MachineInstr &MI) const override;
601 
602 private:
603  /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
604  /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
605  /// super-register and then truncating back down to a 8/16-bit sub-register.
606  MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI,
607  LiveVariables *LV,
608  LiveIntervals *LIS,
609  bool Is8BitOp) const;
610 
611  /// Handles memory folding for special case instructions, for instance those
612  /// requiring custom manipulation of the address.
613  MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
614  unsigned OpNum,
617  unsigned Size, Align Alignment) const;
618 
619  /// isFrameOperand - Return true and the FrameIndex if the specified
620  /// operand and follow operands form a reference to the stack frame.
621  bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
622  int &FrameIndex) const;
623 
624  /// Returns true iff the routine could find two commutable operands in the
625  /// given machine instruction with 3 vector inputs.
626  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
627  /// input values can be re-defined in this method only if the input values
628  /// are not pre-defined, which is designated by the special value
629  /// 'CommuteAnyOperandIndex' assigned to it.
630  /// If both of indices are pre-defined and refer to some operands, then the
631  /// method simply returns true if the corresponding operands are commutable
632  /// and returns false otherwise.
633  ///
634  /// For example, calling this method this way:
635  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
636  /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
637  /// can be interpreted as a query asking to find an operand that would be
638  /// commutable with the operand#1.
639  ///
640  /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
641  bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
642  unsigned &SrcOpIdx1,
643  unsigned &SrcOpIdx2,
644  bool IsIntrinsic = false) const;
645 
646  /// Returns true when instruction \p FlagI produces the same flags as \p OI.
647  /// The caller should pass in the results of calling analyzeCompare on \p OI:
648  /// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue.
649  /// If the flags match \p OI as if it had the input operands swapped then the
650  /// function succeeds and sets \p IsSwapped to true.
651  ///
652  /// Examples of OI, FlagI pairs returning true:
653  /// CMP %1, 42 and CMP %1, 42
654  /// CMP %1, %2 and %3 = SUB %1, %2
655  /// TEST %1, %1 and %2 = SUB %1, 0
656  /// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true
657  bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg,
658  Register SrcReg2, int64_t ImmMask, int64_t ImmValue,
659  const MachineInstr &OI, bool *IsSwapped,
660  int64_t *ImmDelta) const;
661 };
662 
663 } // namespace llvm
664 
665 #endif
X86InstrFMA3Info.h
llvm::X86II::MO_TLVP
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:553
llvm::X86II::MO_DARWIN_NONLAZY
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:542
llvm::X86InstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: X86InstrInfo.cpp:9236
llvm::X86InstrInfo::isDataInvariant
static bool isDataInvariant(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value o...
Definition: X86InstrInfo.cpp:142
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::X86InstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: X86InstrInfo.cpp:3165
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:105
llvm::X86InstrInfo::loadStoreTileReg
void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Opc, Register Reg, int FrameIdx, bool isKill=false) const
Definition: X86InstrInfo.cpp:3864
llvm::MachineInstr::TAsmComments
@ TAsmComments
Definition: MachineInstr.h:79
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::X86::AddrDisp
@ AddrDisp
Definition: X86BaseInfo.h:35
llvm::TargetInstrInfo::MachineBranchPredicate
Represents a predicate at the MachineFunction level.
Definition: TargetInstrInfo.h:649
llvm::X86::AsmComments
AsmComments
Definition: X86InstrInfo.h:31
llvm::X86InstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: X86InstrInfo.cpp:659
llvm::X86InstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: X86InstrInfo.cpp:693
llvm::X86InstrInfo::isHighLatencyDef
bool isHighLatencyDef(int opc) const override
Definition: X86InstrInfo.cpp:8349
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::X86::AddrNumOperands
@ AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
llvm::X86InstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: X86InstrInfo.cpp:9241
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:462
llvm::X86InstrInfo::isAssociativeAndCommutative
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Definition: X86InstrInfo.cpp:8692
llvm::X86InstrInfo::hasReassociableOperands
bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
Definition: X86InstrInfo.cpp:8668
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:237
llvm::X86InstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
Definition: X86InstrInfo.cpp:3945
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:33
llvm::X86::AddrIndexReg
@ AddrIndexReg
Definition: X86BaseInfo.h:34
TargetInstrInfo.h
llvm::X86::getCondSrcNoFromDesc
int getCondSrcNoFromDesc(const MCInstrDesc &MCID)
Return the source operand # for condition code by MCID.
Definition: X86InstrInfo.cpp:2716
llvm::X86InstrInfo::verifyInstruction
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
Definition: X86InstrInfo.cpp:3728
llvm::X86InstrInfo::getExecutionDomainCustom
uint16_t getExecutionDomainCustom(const MachineInstr &MI) const
Definition: X86InstrInfo.cpp:8021
llvm::X86InstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3797
llvm::Optional
Definition: APInt.h:33
llvm::X86InstrInfo::getNop
MCInst getNop() const override
Return the noop instruction to use for a noop.
Definition: X86InstrInfo.cpp:8343
llvm::X86InstrInfo::isDataInvariantLoad
static bool isDataInvariantLoad(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value l...
Definition: X86InstrInfo.cpp:209
llvm::X86::getCondFromBranch
CondCode getCondFromBranch(const MachineInstr &MI)
Definition: X86InstrInfo.cpp:2734
llvm::X86InstrInfo::isStoreToStackSlotPostFE
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
Definition: X86InstrInfo.cpp:709
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::X86InstrInfo::getFMA3OpcodeToCommuteOperands
unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computatio...
Definition: X86InstrInfo.cpp:1813
llvm::X86::CondCode
CondCode
Definition: X86BaseInfo.h:80
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:214
llvm::X86II::MO_GOTOFF
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:434
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::isLeaMem
static bool isLeaMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:118
llvm::X86::getSwappedVPCMPImm
unsigned getSwappedVPCMPImm(unsigned Imm)
Get the VPCMP immediate if the opcodes are swapped.
Definition: X86InstrInfo.cpp:2859
llvm::X86InstrInfo::unfoldMemoryOperand
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
Definition: X86InstrInfo.cpp:6870
llvm::X86II::MO_GOT
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:427
llvm::X86InstrInfo::isFunctionSafeToOutlineFrom
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
Definition: X86InstrInfo.cpp:9586
llvm::X86II::LOCK
@ LOCK
Definition: X86BaseInfo.h:893
llvm::X86::getCondFromCMov
CondCode getCondFromCMov(const MachineInstr &MI)
Definition: X86InstrInfo.cpp:2744
llvm::X86II::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: X86BaseInfo.h:575
llvm::X86::AC_EVEX_2_VEX
@ AC_EVEX_2_VEX
Definition: X86InstrInfo.h:33
llvm::X86InstrInfo::isCoalescableExtInstr
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.
Definition: X86InstrInfo.cpp:94
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::X86InstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: X86InstrInfo.cpp:3362
llvm::X86InstrInfo::getExecutionDomain
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
Definition: X86InstrInfo.cpp:8252
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:546
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::X86InstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: X86InstrInfo.cpp:3325
llvm::X86InstrInfo::setFrameAdjustment
void setFrameAdjustment(MachineInstr &I, int64_t V) const
Sets the stack pointer adjustment made inside the frame made up by this instruction.
Definition: X86InstrInfo.h:170
llvm::X86InstrInfo::setExecutionDomain
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
Definition: X86InstrInfo.cpp:8292
llvm::X86II::MO_GOTPCREL
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:442
llvm::X86::getCondFromSETCC
CondCode getCondFromSETCC(const MachineInstr &MI)
Definition: X86InstrInfo.cpp:2739
X86GenInstrInfo
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::X86::getVPCMPImmForCond
unsigned getVPCMPImmForCond(ISD::CondCode CC)
Get the VPCMP immediate for the given condition.
Definition: X86InstrInfo.cpp:2842
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:710
TBB
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
Definition: RISCVRedundantCopyElimination.cpp:76
llvm::X86InstrInfo::hasLiveCondCodeDef
bool hasLiveCondCodeDef(MachineInstr &MI) const
True if MI has a condition code def, e.g.
Definition: X86InstrInfo.cpp:941
llvm::X86InstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: X86InstrInfo.cpp:3243
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::X86::getSwappedVPCOMImm
unsigned getSwappedVPCOMImm(unsigned Imm)
Get the VPCOM immediate if the opcodes are swapped.
Definition: X86InstrInfo.cpp:2877
llvm::X86::getSwappedVCMPImm
unsigned getSwappedVCMPImm(unsigned Imm)
Get the VCMP immediate if the opcodes are swapped.
Definition: X86InstrInfo.cpp:2895
llvm::X86II::MO_GOTPCREL_NORELAX
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
Definition: X86BaseInfo.h:447
llvm::X86InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3899
llvm::X86InstrInfo::describeLoadedValue
Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Definition: X86InstrInfo.cpp:9047
llvm::X86InstrInfo::preservesZeroValueInReg
bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3769
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::X86InstrFMA3Group
This class is used to group {132, 213, 231} forms of FMA opcodes together.
Definition: X86InstrFMA3Info.h:24
llvm::X86InstrInfo::hasCommutePreference
bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override
Returns true if we have preference on the operands order in MI, the commute decision is returned in C...
Definition: X86InstrInfo.cpp:2681
llvm::X86InstrInfo::breakPartialRegDependency
void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:5791
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::X86InstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Returns true iff the routine could find two commutable operands in the given machine instruction.
Definition: X86InstrInfo.cpp:2437
llvm::X86InstrInfo::setExecutionDomainCustom
bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const
Definition: X86InstrInfo.cpp:8119
llvm::X86InstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: X86InstrInfo.cpp:3266
llvm::X86InstrInfo::isSafeToMoveRegClassDefs
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the sp...
Definition: X86InstrInfo.cpp:7433
llvm::X86InstrInfo::hasLockPrefix
static bool hasLockPrefix(const MachineInstr &MI)
Definition: X86InstrInfo.h:573
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
llvm::X86InstrInfo::isUnconditionalTailCall
bool isUnconditionalTailCall(const MachineInstr &MI) const override
Definition: X86InstrInfo.cpp:2928
llvm::X86II::MO_DARWIN_NONLAZY_PIC_BASE
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:547
llvm::X86InstrInfo::classifyLEAReg
bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, Register &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV, LiveIntervals *LIS) const
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a p...
Definition: X86InstrInfo.cpp:1067
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::isGlobalStubReference
static bool isGlobalStubReference(unsigned char TargetFlag)
isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for ...
Definition: X86InstrInfo.h:82
llvm::X86InstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: X86InstrInfo.cpp:4901
llvm::X86InstrInfo::isCopyInstrImpl
Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: X86InstrInfo.cpp:3547
llvm::X86II::MO_PIC_BASE_OFFSET
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:420
llvm::X86InstrInfo::getOutliningType
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
Definition: X86InstrInfo.cpp:9609
llvm::X86InstrInfo::areLoadsFromSameBasePtr
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
Definition: X86InstrInfo.cpp:7165
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:37
llvm::X86InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: X86InstrInfo.cpp:3461
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::X86InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3923
llvm::X86InstrInfo::analyzeBranchPredicate
bool analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
Definition: X86InstrInfo.cpp:3174
llvm::X86::AddrBaseReg
@ AddrBaseReg
Definition: X86BaseInfo.h:32
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::X86InstrInfo::setSpecialOperandAttr
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
Definition: X86InstrInfo.cpp:9190
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1424
llvm::isScale
static bool isScale(const MachineOperand &MO)
Definition: X86InstrInfo.h:113
llvm::X86InstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo....
Definition: X86InstrInfo.cpp:7411
llvm::X86InstrInfo::replaceBranchWithTailCall
void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
Definition: X86InstrInfo.cpp:2973
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::X86::GetOppositeBranchCondition
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
Definition: X86InstrInfo.cpp:2751
llvm::X86InstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into...
Definition: X86InstrInfo.cpp:6255
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::X86InstrInfo
Definition: X86InstrInfo.h:138
llvm::X86InstrInfo::getAddrModeFromMemoryOp
Optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3702
llvm::X86II::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:537
llvm::X86InstrInfo::getUndefRegClearance
unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register...
Definition: X86InstrInfo.cpp:5781
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::X86InstrInfo::canMakeTailCallConditional
bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
Definition: X86InstrInfo.cpp:2942
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::isGlobalRelativeToPICBase
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-b...
Definition: X86InstrInfo.h:100
llvm::X86InstrInfo::getSPAdjust
int getSPAdjust(const MachineInstr &MI) const override
getSPAdjust - This returns the stack pointer adjustment made by this instruction.
Definition: X86InstrInfo.cpp:399
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::X86InstrInfo::isLoadFromStackSlotPostFE
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
Definition: X86InstrInfo.cpp:674
llvm::X86::getCondFromMI
CondCode getCondFromMI(const MachineInstr &MI)
Return the condition code of the instruction.
Definition: X86InstrInfo.cpp:2725
llvm::X86InstrInfo::getPartialRegUpdateClearance
unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register upd...
Definition: X86InstrInfo.cpp:5411
llvm::X86InstrInfo::getRegisterInfo
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:157
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::X86InstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
Definition: X86InstrInfo.cpp:1982
llvm::X86InstrInfo::X86InstrInfo
X86InstrInfo(X86Subtarget &STI)
Definition: X86InstrInfo.cpp:83
llvm::MipsISD::TailCall
@ TailCall
Definition: MipsISelLowering.h:65
llvm::X86InstrInfo::getConstValDefinedInReg
bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override
Definition: X86InstrInfo.cpp:3757
llvm::X86InstrInfo::isReallyTriviallyReMaterializable
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
Definition: X86InstrInfo.cpp:745
llvm::X86InstrInfo::reMaterialize
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
Definition: X86InstrInfo.cpp:908
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::X86InstrInfo::getFrameAdjustment
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e....
Definition: X86InstrInfo.h:161
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::X86InstrInfo::useMachineCombiner
bool useMachineCombiner() const override
Definition: X86InstrInfo.h:507
llvm::X86InstrInfo::getOutliningCandidateInfo
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
Definition: X86InstrInfo.cpp:9529
llvm::X86::AddrScaleAmt
@ AddrScaleAmt
Definition: X86BaseInfo.h:33
llvm::X86InstrInfo::getOpcodeAfterMemoryUnfold
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store ar...
Definition: X86InstrInfo.cpp:7147
llvm::X86InstrInfo::buildOutlinedFrame
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
Definition: X86InstrInfo.cpp:9668
llvm::X86InstrInfo::isSubregFoldable
bool isSubregFoldable() const override
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: X86InstrInfo.h:385
llvm::X86InstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: X86InstrInfo.cpp:7425
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
ISDOpcodes.h
llvm::X86II::ImmMask
@ ImmMask
Definition: X86BaseInfo.h:844
llvm::X86InstrInfo::hasHighOperandLatency
bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
Definition: X86InstrInfo.cpp:8659
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::X86::getCMovOpcode
unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand=false)
Return a cmov opcode for the given register size in bytes, and operand type.
Definition: X86InstrInfo.cpp:2832
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:322
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
X86RegisterInfo.h
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
X86BaseInfo.h
llvm::X86InstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_AD...
Definition: X86InstrInfo.cpp:1313
llvm::X86::getX86ConditionCode
std::pair< CondCode, bool > getX86ConditionCode(CmpInst::Predicate Predicate)
Return a pair of condition code for the given predicate and whether the instruction operands should b...
Definition: X86InstrInfo.cpp:2794
llvm::X86InstrInfo::getGlobalBaseReg
unsigned getGlobalBaseReg(MachineFunction *MF) const
getGlobalBaseReg - Return a virtual register initialized with the the global base register value.
Definition: X86InstrInfo.cpp:7447
N
#define N
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:106
llvm::X86::AddrSegmentReg
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
llvm::isMem
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:131
llvm::X86::isX87Instruction
bool isX87Instruction(MachineInstr &MI)
Check if the instruction is X87 instruction.
Definition: X86InstrInfo.cpp:2918
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::X86InstrInfo::optimizeLoadInstr
MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use.
Definition: X86InstrInfo.cpp:4657
llvm::LiveVariables
Definition: LiveVariables.h:47
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::X86InstrInfo::shouldScheduleLoadsNear
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
Definition: X86InstrInfo.cpp:7363
llvm::X86InstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source ...
Definition: X86InstrInfo.cpp:4282
llvm::X86InstrInfo::insertOutlinedCall
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
Definition: X86InstrInfo.cpp:9683
X86
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
Definition: README.txt:568
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24