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X86InstrInfo.h
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1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the X86 implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 
17 #include "X86InstrFMA3Info.h"
18 #include "X86RegisterInfo.h"
21 #include <vector>
22 
23 #define GET_INSTRINFO_HEADER
24 #include "X86GenInstrInfo.inc"
25 
26 namespace llvm {
27 class X86Subtarget;
28 
29 namespace X86 {
30 
32  // For instr that was compressed from EVEX to VEX.
34 };
35 
36 /// Return a pair of condition code for the given predicate and whether
37 /// the instruction operands should be swaped to match the condition code.
38 std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
39 
40 /// Return a setcc opcode based on whether it has a memory operand.
41 unsigned getSETOpc(bool HasMemoryOperand = false);
42 
43 /// Return a cmov opcode for the given register size in bytes, and operand type.
44 unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
45 
46 // Turn jCC instruction into condition code.
48 
49 // Turn setCC instruction into condition code.
51 
52 // Turn CMov instruction into condition code.
54 
55 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
56 /// e.g. turning COND_E to COND_NE.
58 
59 /// Get the VPCMP immediate for the given condition.
61 
62 /// Get the VPCMP immediate if the opcodes are swapped.
63 unsigned getSwappedVPCMPImm(unsigned Imm);
64 
65 /// Get the VPCOM immediate if the opcodes are swapped.
66 unsigned getSwappedVPCOMImm(unsigned Imm);
67 
68 /// Get the VCMP immediate if the opcodes are swapped.
69 unsigned getSwappedVCMPImm(unsigned Imm);
70 
71 } // namespace X86
72 
73 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
74 /// a reference to a stub for a global, not the global itself.
75 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
76  switch (TargetFlag) {
77  case X86II::MO_DLLIMPORT: // dllimport stub.
78  case X86II::MO_GOTPCREL: // rip-relative GOT reference.
79  case X86II::MO_GOT: // normal GOT reference.
80  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
81  case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
82  case X86II::MO_COFFSTUB: // COFF .refptr stub.
83  return true;
84  default:
85  return false;
86  }
87 }
88 
89 /// isGlobalRelativeToPICBase - Return true if the specified global value
90 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
91 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
92 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
93  switch (TargetFlag) {
94  case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
95  case X86II::MO_GOT: // isPICStyleGOT: other global.
96  case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
97  case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
98  case X86II::MO_TLVP: // ??? Pretty sure..
99  return true;
100  default:
101  return false;
102  }
103 }
104 
105 inline static bool isScale(const MachineOperand &MO) {
106  return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
107  MO.getImm() == 4 || MO.getImm() == 8);
108 }
109 
110 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
111  if (MI.getOperand(Op).isFI())
112  return true;
113  return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
114  MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
115  isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
116  MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
117  (MI.getOperand(Op + X86::AddrDisp).isImm() ||
118  MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
119  MI.getOperand(Op + X86::AddrDisp).isCPI() ||
120  MI.getOperand(Op + X86::AddrDisp).isJTI());
121 }
122 
123 inline static bool isMem(const MachineInstr &MI, unsigned Op) {
124  if (MI.getOperand(Op).isFI())
125  return true;
126  return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
127  MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
128 }
129 
130 class X86InstrInfo final : public X86GenInstrInfo {
131  X86Subtarget &Subtarget;
132  const X86RegisterInfo RI;
133 
134  virtual void anchor();
135 
136  bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
137  MachineBasicBlock *&FBB,
139  SmallVectorImpl<MachineInstr *> &CondBranches,
140  bool AllowModify) const;
141 
142 public:
143  explicit X86InstrInfo(X86Subtarget &STI);
144 
145  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
146  /// such, whenever a client has an instance of instruction info, it should
147  /// always be able to get register info as well (through this method).
148  ///
149  const X86RegisterInfo &getRegisterInfo() const { return RI; }
150 
151  /// Returns the stack pointer adjustment that happens inside the frame
152  /// setup..destroy sequence (e.g. by pushes, or inside the callee).
153  int64_t getFrameAdjustment(const MachineInstr &I) const {
154  assert(isFrameInstr(I));
155  if (isFrameSetup(I))
156  return I.getOperand(2).getImm();
157  return I.getOperand(1).getImm();
158  }
159 
160  /// Sets the stack pointer adjustment made inside the frame made up by this
161  /// instruction.
162  void setFrameAdjustment(MachineInstr &I, int64_t V) const {
163  assert(isFrameInstr(I));
164  if (isFrameSetup(I))
165  I.getOperand(2).setImm(V);
166  else
167  I.getOperand(1).setImm(V);
168  }
169 
170  /// getSPAdjust - This returns the stack pointer adjustment made by
171  /// this instruction. For x86, we need to handle more complex call
172  /// sequences involving PUSHes.
173  int getSPAdjust(const MachineInstr &MI) const override;
174 
175  /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
176  /// extension instruction. That is, it's like a copy where it's legal for the
177  /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
178  /// true, then it's expected the pre-extension value is available as a subreg
179  /// of the result register. This also returns the sub-register index in
180  /// SubIdx.
181  bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
182  Register &DstReg, unsigned &SubIdx) const override;
183 
184  /// Returns true if the instruction has no behavior (specified or otherwise)
185  /// that is based on the value of any of its register operands
186  ///
187  /// Instructions are considered data invariant even if they set EFLAGS.
188  ///
189  /// A classical example of something that is inherently not data invariant is
190  /// an indirect jump -- the destination is loaded into icache based on the
191  /// bits set in the jump destination register.
192  ///
193  /// FIXME: This should become part of our instruction tables.
194  static bool isDataInvariant(MachineInstr &MI);
195 
196  /// Returns true if the instruction has no behavior (specified or otherwise)
197  /// that is based on the value loaded from memory or the value of any
198  /// non-address register operands.
199  ///
200  /// For example, if the latency of the instruction is dependent on the
201  /// particular bits set in any of the registers *or* any of the bits loaded
202  /// from memory.
203  ///
204  /// Instructions are considered data invariant even if they set EFLAGS.
205  ///
206  /// A classical example of something that is inherently not data invariant is
207  /// an indirect jump -- the destination is loaded into icache based on the
208  /// bits set in the jump destination register.
209  ///
210  /// FIXME: This should become part of our instruction tables.
211  static bool isDataInvariantLoad(MachineInstr &MI);
212 
213  unsigned isLoadFromStackSlot(const MachineInstr &MI,
214  int &FrameIndex) const override;
215  unsigned isLoadFromStackSlot(const MachineInstr &MI,
216  int &FrameIndex,
217  unsigned &MemBytes) const override;
218  /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
219  /// stack locations as well. This uses a heuristic so it isn't
220  /// reliable for correctness.
221  unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
222  int &FrameIndex) const override;
223 
224  unsigned isStoreToStackSlot(const MachineInstr &MI,
225  int &FrameIndex) const override;
226  unsigned isStoreToStackSlot(const MachineInstr &MI,
227  int &FrameIndex,
228  unsigned &MemBytes) const override;
229  /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
230  /// stack locations as well. This uses a heuristic so it isn't
231  /// reliable for correctness.
232  unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
233  int &FrameIndex) const override;
234 
236  AAResults *AA) const override;
238  Register DestReg, unsigned SubIdx,
239  const MachineInstr &Orig,
240  const TargetRegisterInfo &TRI) const override;
241 
242  /// Given an operand within a MachineInstr, insert preceding code to put it
243  /// into the right format for a particular kind of LEA instruction. This may
244  /// involve using an appropriate super-register instead (with an implicit use
245  /// of the original) or creating a new virtual register and inserting COPY
246  /// instructions to get the data into the right class.
247  ///
248  /// Reference parameters are set to indicate how caller should add this
249  /// operand to the LEA instruction.
250  bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
251  unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
252  bool &isKill, MachineOperand &ImplicitOp,
253  LiveVariables *LV) const;
254 
255  /// convertToThreeAddress - This method must be implemented by targets that
256  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
257  /// may be able to convert a two-address instruction into a true
258  /// three-address instruction on demand. This allows the X86 target (for
259  /// example) to convert ADD and SHL instructions into LEA instructions if they
260  /// would require register copies due to two-addressness.
261  ///
262  /// This method returns a null pointer if the transformation cannot be
263  /// performed, otherwise it returns the new instruction.
264  ///
266  LiveVariables *LV) const override;
267 
268  /// Returns true iff the routine could find two commutable operands in the
269  /// given machine instruction.
270  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
271  /// input values can be re-defined in this method only if the input values
272  /// are not pre-defined, which is designated by the special value
273  /// 'CommuteAnyOperandIndex' assigned to it.
274  /// If both of indices are pre-defined and refer to some operands, then the
275  /// method simply returns true if the corresponding operands are commutable
276  /// and returns false otherwise.
277  ///
278  /// For example, calling this method this way:
279  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
280  /// findCommutedOpIndices(MI, Op1, Op2);
281  /// can be interpreted as a query asking to find an operand that would be
282  /// commutable with the operand#1.
283  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
284  unsigned &SrcOpIdx2) const override;
285 
286  /// Returns true if we have preference on the operands order in MI, the
287  /// commute decision is returned in Commute.
288  bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override;
289 
290  /// Returns an adjusted FMA opcode that must be used in FMA instruction that
291  /// performs the same computations as the given \p MI but which has the
292  /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
293  /// It may return 0 if it is unsafe to commute the operands.
294  /// Note that a machine instruction (instead of its opcode) is passed as the
295  /// first parameter to make it possible to analyze the instruction's uses and
296  /// commute the first operand of FMA even when it seems unsafe when you look
297  /// at the opcode. For example, it is Ok to commute the first operand of
298  /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
299  ///
300  /// The returned FMA opcode may differ from the opcode in the given \p MI.
301  /// For example, commuting the operands #1 and #3 in the following FMA
302  /// FMA213 #1, #2, #3
303  /// results into instruction with adjusted opcode:
304  /// FMA231 #3, #2, #1
305  unsigned
306  getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
307  unsigned SrcOpIdx2,
308  const X86InstrFMA3Group &FMA3Group) const;
309 
310  // Branch analysis.
311  bool isUnconditionalTailCall(const MachineInstr &MI) const override;
313  const MachineInstr &TailCall) const override;
316  const MachineInstr &TailCall) const override;
317 
319  MachineBasicBlock *&FBB,
321  bool AllowModify) const override;
322 
325  const TargetRegisterInfo *TRI) const override;
326 
328  int64_t &ImmVal) const override;
329 
331  const Register NullValueReg,
332  const TargetRegisterInfo *TRI) const override;
333 
335  const MachineInstr &LdSt,
337  bool &OffsetIsScalable, unsigned &Width,
338  const TargetRegisterInfo *TRI) const override;
341  bool AllowModify = false) const override;
342 
344  int *BytesRemoved = nullptr) const override;
347  const DebugLoc &DL,
348  int *BytesAdded = nullptr) const override;
350  Register, Register, Register, int &, int &,
351  int &) const override;
353  const DebugLoc &DL, Register DstReg,
355  Register FalseReg) const override;
357  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
358  bool KillSrc) const override;
361  bool isKill, int FrameIndex,
362  const TargetRegisterClass *RC,
363  const TargetRegisterInfo *TRI) const override;
364 
367  int FrameIndex, const TargetRegisterClass *RC,
368  const TargetRegisterInfo *TRI) const override;
369 
370  bool expandPostRAPseudo(MachineInstr &MI) const override;
371 
372  /// Check whether the target can fold a load that feeds a subreg operand
373  /// (or a subreg operand that feeds a store).
374  bool isSubregFoldable() const override { return true; }
375 
376  /// foldMemoryOperand - If this target supports it, fold a load or store of
377  /// the specified stack slot into the specified machine instruction for the
378  /// specified operand(s). If this is possible, the target should perform the
379  /// folding and return true, otherwise it should return false. If it folds
380  /// the instruction, it is likely that the MachineInstruction the iterator
381  /// references has been changed.
382  MachineInstr *
384  ArrayRef<unsigned> Ops,
386  LiveIntervals *LIS = nullptr,
387  VirtRegMap *VRM = nullptr) const override;
388 
389  /// foldMemoryOperand - Same as the previous version except it allows folding
390  /// of any load and store from / to any address, not just from a specific
391  /// stack slot.
394  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
395  LiveIntervals *LIS = nullptr) const override;
396 
397  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
398  /// a store or a load and a store into two or more instruction. If this is
399  /// possible, returns true as well as the new instructions by reference.
400  bool
402  bool UnfoldLoad, bool UnfoldStore,
403  SmallVectorImpl<MachineInstr *> &NewMIs) const override;
404 
406  SmallVectorImpl<SDNode *> &NewNodes) const override;
407 
408  /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
409  /// instruction after load / store are unfolded from an instruction of the
410  /// specified opcode. It returns zero if the specified unfolding is not
411  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
412  /// index of the operand which will hold the register holding the loaded
413  /// value.
414  unsigned
415  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
416  unsigned *LoadRegIndex = nullptr) const override;
417 
418  /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
419  /// to determine if two loads are loading from the same base address. It
420  /// should only return true if the base pointers are the same and the
421  /// only differences between the two addresses are the offset. It also returns
422  /// the offsets by reference.
423  bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
424  int64_t &Offset2) const override;
425 
426  /// isSchedulingBoundary - Overrides the isSchedulingBoundary from
427  /// Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR
428  /// intructions and prevent it from being re-scheduled.
430  const MachineBasicBlock *MBB,
431  const MachineFunction &MF) const override;
432 
433  /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
434  /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
435  /// should be scheduled togther. On some targets if two loads are loading from
436  /// addresses in the same cache line, it's better if they are scheduled
437  /// together. This function takes two integers that represent the load offsets
438  /// from the common base address. It returns true if it decides it's desirable
439  /// to schedule the two loads together. "NumLoads" is the number of loads that
440  /// have already been scheduled after Load1.
441  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
442  int64_t Offset2,
443  unsigned NumLoads) const override;
444 
445  MCInst getNop() const override;
446 
447  bool
449 
450  /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
451  /// instruction that defines the specified register class.
452  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
453 
454  /// True if MI has a condition code def, e.g. EFLAGS, that is
455  /// not marked dead.
456  bool hasLiveCondCodeDef(MachineInstr &MI) const;
457 
458  /// getGlobalBaseReg - Return a virtual register initialized with the
459  /// the global base register value. Output instructions required to
460  /// initialize the register in the function entry block, if necessary.
461  ///
462  unsigned getGlobalBaseReg(MachineFunction *MF) const;
463 
464  std::pair<uint16_t, uint16_t>
465  getExecutionDomain(const MachineInstr &MI) const override;
466 
468 
469  void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
470 
471  bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
472 
473  unsigned
474  getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
475  const TargetRegisterInfo *TRI) const override;
476  unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
477  const TargetRegisterInfo *TRI) const override;
478  void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
479  const TargetRegisterInfo *TRI) const override;
480 
482  unsigned OpNum,
485  unsigned Size, Align Alignment,
486  bool AllowCommute) const;
487 
488  bool isHighLatencyDef(int opc) const override;
489 
490  bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
491  const MachineRegisterInfo *MRI,
492  const MachineInstr &DefMI, unsigned DefIdx,
493  const MachineInstr &UseMI,
494  unsigned UseIdx) const override;
495 
496  bool useMachineCombiner() const override { return true; }
497 
498  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
499 
500  bool hasReassociableOperands(const MachineInstr &Inst,
501  const MachineBasicBlock *MBB) const override;
502 
503  void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
504  MachineInstr &NewMI1,
505  MachineInstr &NewMI2) const override;
506 
507  /// analyzeCompare - For a comparison instruction, return the source registers
508  /// in SrcReg and SrcReg2 if having two register operands, and the value it
509  /// compares against in CmpValue. Return true if the comparison instruction
510  /// can be analyzed.
511  bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
512  Register &SrcReg2, int64_t &CmpMask,
513  int64_t &CmpValue) const override;
514 
515  /// optimizeCompareInstr - Check if there exists an earlier instruction that
516  /// operates on the same source operands and sets flags in the same way as
517  /// Compare; remove Compare if possible.
518  bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
519  Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
520  const MachineRegisterInfo *MRI) const override;
521 
522  /// optimizeLoadInstr - Try to remove the load by folding it to a register
523  /// operand at the use. We fold the load instructions if and only if the
524  /// def and use are in the same BB. We only look at one load and see
525  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
526  /// defined by the load we are trying to fold. DefMI returns the machine
527  /// instruction that defines FoldAsLoadDefReg, and the function returns
528  /// the machine instruction generated due to folding.
530  const MachineRegisterInfo *MRI,
531  Register &FoldAsLoadDefReg,
532  MachineInstr *&DefMI) const override;
533 
534  std::pair<unsigned, unsigned>
535  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
536 
539 
541  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
542 
544  bool OutlineFromLinkOnceODRs) const override;
545 
547  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
548 
550  const outliner::OutlinedFunction &OF) const override;
551 
555  const outliner::Candidate &C) const override;
556 
557 #define GET_INSTRINFO_HELPER_DECLS
558 #include "X86GenInstrInfo.inc"
559 
560  static bool hasLockPrefix(const MachineInstr &MI) {
561  return MI.getDesc().TSFlags & X86II::LOCK;
562  }
563 
565  Register Reg) const override;
566 
567 protected:
568  /// Commutes the operands in the given instruction by changing the operands
569  /// order and/or changing the instruction's opcode and/or the immediate value
570  /// operand.
571  ///
572  /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
573  /// to be commuted.
574  ///
575  /// Do not call this method for a non-commutable instruction or
576  /// non-commutable operands.
577  /// Even though the instruction is commutable, the method may still
578  /// fail to commute the operands, null pointer is returned in such cases.
580  unsigned CommuteOpIdx1,
581  unsigned CommuteOpIdx2) const override;
582 
583  /// If the specific machine instruction is a instruction that moves/copies
584  /// value from one register to another register return destination and source
585  /// registers as machine operands.
587  isCopyInstrImpl(const MachineInstr &MI) const override;
588 
589 private:
590  /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
591  /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
592  /// super-register and then truncating back down to a 8/16-bit sub-register.
593  MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc,
594  MachineInstr &MI,
595  LiveVariables *LV,
596  bool Is8BitOp) const;
597 
598  /// Handles memory folding for special case instructions, for instance those
599  /// requiring custom manipulation of the address.
600  MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
601  unsigned OpNum,
604  unsigned Size, Align Alignment) const;
605 
606  /// isFrameOperand - Return true and the FrameIndex if the specified
607  /// operand and follow operands form a reference to the stack frame.
608  bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
609  int &FrameIndex) const;
610 
611  /// Returns true iff the routine could find two commutable operands in the
612  /// given machine instruction with 3 vector inputs.
613  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
614  /// input values can be re-defined in this method only if the input values
615  /// are not pre-defined, which is designated by the special value
616  /// 'CommuteAnyOperandIndex' assigned to it.
617  /// If both of indices are pre-defined and refer to some operands, then the
618  /// method simply returns true if the corresponding operands are commutable
619  /// and returns false otherwise.
620  ///
621  /// For example, calling this method this way:
622  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
623  /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
624  /// can be interpreted as a query asking to find an operand that would be
625  /// commutable with the operand#1.
626  ///
627  /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
628  bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
629  unsigned &SrcOpIdx1,
630  unsigned &SrcOpIdx2,
631  bool IsIntrinsic = false) const;
632 };
633 
634 } // namespace llvm
635 
636 #endif
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
X86InstrFMA3Info.h
llvm::X86II::MO_TLVP
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:548
llvm::X86II::MO_DARWIN_NONLAZY
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:537
llvm::X86InstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: X86InstrInfo.cpp:8818
llvm::X86InstrInfo::isDataInvariant
static bool isDataInvariant(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value o...
Definition: X86InstrInfo.cpp:138
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::X86InstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: X86InstrInfo.cpp:3232
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::MachineInstr::TAsmComments
@ TAsmComments
Definition: MachineInstr.h:77
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:720
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::TargetInstrInfo::MachineBranchPredicate
Represents a predicate at the MachineFunction level.
Definition: TargetInstrInfo.h:637
llvm::X86::AsmComments
AsmComments
Definition: X86InstrInfo.h:31
llvm::X86::AddrIndexReg
@ AddrIndexReg
Definition: X86BaseInfo.h:34
llvm::X86InstrInfo::isLoadFromStackSlot
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: X86InstrInfo.cpp:883
llvm::X86InstrInfo::isStoreToStackSlot
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
Definition: X86InstrInfo.cpp:917
llvm::X86InstrInfo::isHighLatencyDef
bool isHighLatencyDef(int opc) const override
Definition: X86InstrInfo.cpp:7931
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::X86InstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: X86InstrInfo.cpp:8823
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
llvm::X86InstrInfo::isAssociativeAndCommutative
bool isAssociativeAndCommutative(const MachineInstr &Inst) const override
Definition: X86InstrInfo.cpp:8274
llvm::X86InstrInfo::hasReassociableOperands
bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
Definition: X86InstrInfo.cpp:8250
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::X86InstrInfo::analyzeCompare
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
Definition: X86InstrInfo.cpp:3938
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:34
TargetInstrInfo.h
llvm::X86InstrInfo::getExecutionDomainCustom
uint16_t getExecutionDomainCustom(const MachineInstr &MI) const
Definition: X86InstrInfo.cpp:7603
llvm::X86::AddrDisp
@ AddrDisp
Definition: X86BaseInfo.h:35
llvm::X86InstrInfo::getMemOperandsWithOffsetWidth
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3819
llvm::Optional
Definition: APInt.h:33
llvm::X86InstrInfo::getNop
MCInst getNop() const override
Return the noop instruction to use for a noop.
Definition: X86InstrInfo.cpp:7925
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::X86InstrInfo::isDataInvariantLoad
static bool isDataInvariantLoad(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value l...
Definition: X86InstrInfo.cpp:433
llvm::X86::getCondFromBranch
CondCode getCondFromBranch(const MachineInstr &MI)
Definition: X86InstrInfo.cpp:2759
llvm::X86InstrInfo::isStoreToStackSlotPostFE
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
Definition: X86InstrInfo.cpp:933
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::X86InstrInfo::getFMA3OpcodeToCommuteOperands
unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computatio...
Definition: X86InstrInfo.cpp:1855
llvm::X86::CondCode
CondCode
Definition: X86BaseInfo.h:80
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:164
llvm::X86II::MO_GOTOFF
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:434
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::isLeaMem
static bool isLeaMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:110
llvm::X86::getSwappedVPCMPImm
unsigned getSwappedVPCMPImm(unsigned Imm)
Get the VPCMP immediate if the opcodes are swapped.
Definition: X86InstrInfo.cpp:2904
llvm::X86InstrInfo::unfoldMemoryOperand
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
Definition: X86InstrInfo.cpp:6452
llvm::X86II::MO_GOT
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:427
llvm::X86InstrInfo::isFunctionSafeToOutlineFrom
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
Definition: X86InstrInfo.cpp:9174
llvm::X86::AddrSegmentReg
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
llvm::X86::getCondFromCMov
CondCode getCondFromCMov(const MachineInstr &MI)
Return condition code of a CMov opcode.
Definition: X86InstrInfo.cpp:2779
llvm::X86II::MO_COFFSTUB
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: X86BaseInfo.h:570
llvm::X86::AC_EVEX_2_VEX
@ AC_EVEX_2_VEX
Definition: X86InstrInfo.h:33
llvm::X86InstrInfo::isCoalescableExtInstr
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.
Definition: X86InstrInfo.cpp:90
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::AAResults
Definition: AliasAnalysis.h:508
llvm::X86InstrInfo::insertSelect
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
Definition: X86InstrInfo.cpp:3429
llvm::X86InstrInfo::getExecutionDomain
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
Definition: X86InstrInfo.cpp:7834
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::X86InstrInfo::canInsertSelect
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
Definition: X86InstrInfo.cpp:3392
llvm::X86InstrInfo::setFrameAdjustment
void setFrameAdjustment(MachineInstr &I, int64_t V) const
Sets the stack pointer adjustment made inside the frame made up by this instruction.
Definition: X86InstrInfo.h:162
llvm::X86InstrInfo::setExecutionDomain
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
Definition: X86InstrInfo.cpp:7874
llvm::X86II::MO_GOTPCREL
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:442
llvm::X86::getCondFromSETCC
CondCode getCondFromSETCC(const MachineInstr &MI)
Return condition code of a SETCC opcode.
Definition: X86InstrInfo.cpp:2769
X86GenInstrInfo
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::X86::getVPCMPImmForCond
unsigned getVPCMPImmForCond(ISD::CondCode CC)
Get the VPCMP immediate for the given condition.
Definition: X86InstrInfo.cpp:2887
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:660
llvm::X86InstrInfo::hasLiveCondCodeDef
bool hasLiveCondCodeDef(MachineInstr &MI) const
True if MI has a condition code def, e.g.
Definition: X86InstrInfo.cpp:1164
llvm::X86InstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: X86InstrInfo.cpp:3310
llvm::X86InstrInfo::isReallyTriviallyReMaterializable
bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const override
Definition: X86InstrInfo.cpp:969
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::X86::getSwappedVPCOMImm
unsigned getSwappedVPCOMImm(unsigned Imm)
Get the VPCOM immediate if the opcodes are swapped.
Definition: X86InstrInfo.cpp:2922
llvm::X86::getSwappedVCMPImm
unsigned getSwappedVCMPImm(unsigned Imm)
Get the VCMP immediate if the opcodes are swapped.
Definition: X86InstrInfo.cpp:2940
llvm::X86::AddrNumOperands
@ AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
llvm::X86InstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3876
llvm::X86InstrInfo::describeLoadedValue
Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
Definition: X86InstrInfo.cpp:8629
llvm::X86InstrInfo::preservesZeroValueInReg
bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3791
llvm::X86InstrInfo::insertOutlinedCall
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const override
Definition: X86InstrInfo.cpp:9271
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::X86InstrFMA3Group
This class is used to group {132, 213, 231} forms of FMA opcodes together.
Definition: X86InstrFMA3Info.h:24
llvm::X86InstrInfo::hasCommutePreference
bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override
Returns true if we have preference on the operands order in MI, the commute decision is returned in C...
Definition: X86InstrInfo.cpp:2724
llvm::X86InstrInfo::breakPartialRegDependency
void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:5395
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::X86InstrInfo::findCommutedOpIndices
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Returns true iff the routine could find two commutable operands in the given machine instruction.
Definition: X86InstrInfo.cpp:2480
llvm::X86InstrInfo::setExecutionDomainCustom
bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const
Definition: X86InstrInfo.cpp:7701
llvm::X86::AddrBaseReg
@ AddrBaseReg
Definition: X86BaseInfo.h:32
llvm::X86InstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: X86InstrInfo.cpp:3333
llvm::X86InstrInfo::isSafeToMoveRegClassDefs
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the sp...
Definition: X86InstrInfo.cpp:7015
llvm::X86::AddrScaleAmt
@ AddrScaleAmt
Definition: X86BaseInfo.h:33
llvm::X86InstrInfo::hasLockPrefix
static bool hasLockPrefix(const MachineInstr &MI)
Definition: X86InstrInfo.h:560
llvm::PPC::Predicate
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
llvm::X86InstrInfo::isUnconditionalTailCall
bool isUnconditionalTailCall(const MachineInstr &MI) const override
Definition: X86InstrInfo.cpp:2956
llvm::X86II::MO_DARWIN_NONLAZY_PIC_BASE
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:542
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::isGlobalStubReference
static bool isGlobalStubReference(unsigned char TargetFlag)
isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for ...
Definition: X86InstrInfo.h:75
llvm::X86InstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: X86InstrInfo.cpp:4755
llvm::X86InstrInfo::isCopyInstrImpl
Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: X86InstrInfo.cpp:3614
llvm::X86II::MO_PIC_BASE_OFFSET
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:420
llvm::X86InstrInfo::getOutliningType
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
Definition: X86InstrInfo.cpp:9197
llvm::X86InstrInfo::areLoadsFromSameBasePtr
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
Definition: X86InstrInfo.cpp:6747
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:38
llvm::X86InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: X86InstrInfo.cpp:3528
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::X86InstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3908
llvm::X86InstrInfo::analyzeBranchPredicate
bool analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
Definition: X86InstrInfo.cpp:3241
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::X86InstrInfo::setSpecialOperandAttr
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
Definition: X86InstrInfo.cpp:8772
llvm::ISD::CondCode
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1361
llvm::isScale
static bool isScale(const MachineOperand &MO)
Definition: X86InstrInfo.h:105
llvm::X86InstrInfo::isSchedulingBoundary
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo....
Definition: X86InstrInfo.cpp:6993
llvm::X86InstrInfo::replaceBranchWithTailCall
void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
Definition: X86InstrInfo.cpp:3001
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::X86::GetOppositeBranchCondition
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
Definition: X86InstrInfo.cpp:2791
llvm::X86InstrInfo::foldMemoryOperandImpl
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into...
Definition: X86InstrInfo.cpp:5839
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::X86InstrInfo
Definition: X86InstrInfo.h:130
llvm::X86InstrInfo::getAddrModeFromMemoryOp
Optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
Definition: X86InstrInfo.cpp:3753
llvm::X86II::MO_DLLIMPORT
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:532
llvm::X86InstrInfo::getUndefRegClearance
unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register...
Definition: X86InstrInfo.cpp:5385
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::X86InstrInfo::canMakeTailCallConditional
bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
Definition: X86InstrInfo.cpp:2970
llvm::isGlobalRelativeToPICBase
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-b...
Definition: X86InstrInfo.h:92
llvm::X86InstrInfo::getSPAdjust
int getSPAdjust(const MachineInstr &MI) const override
getSPAdjust - This returns the stack pointer adjustment made by this instruction.
Definition: X86InstrInfo.cpp:623
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::X86InstrInfo::isLoadFromStackSlotPostFE
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
Definition: X86InstrInfo.cpp:898
llvm::X86InstrInfo::getPartialRegUpdateClearance
unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register upd...
Definition: X86InstrInfo.cpp:5015
llvm::X86InstrInfo::getRegisterInfo
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:149
llvm::X86InstrInfo::classifyLEAReg
bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, Register &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV) const
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a p...
Definition: X86InstrInfo.cpp:1195
llvm::X86InstrInfo::commuteInstructionImpl
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
Definition: X86InstrInfo.cpp:2025
llvm::X86InstrInfo::X86InstrInfo
X86InstrInfo(X86Subtarget &STI)
Definition: X86InstrInfo.cpp:79
llvm::MipsISD::TailCall
@ TailCall
Definition: MipsISelLowering.h:65
llvm::X86InstrInfo::getConstValDefinedInReg
bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override
Definition: X86InstrInfo.cpp:3779
llvm::X86InstrInfo::reMaterialize
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
Definition: X86InstrInfo.cpp:1131
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::X86InstrInfo::getFrameAdjustment
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e....
Definition: X86InstrInfo.h:153
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::X86InstrInfo::useMachineCombiner
bool useMachineCombiner() const override
Definition: X86InstrInfo.h:496
llvm::X86InstrInfo::getOutliningCandidateInfo
virtual outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
Definition: X86InstrInfo.cpp:9110
llvm::X86InstrInfo::getOpcodeAfterMemoryUnfold
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store ar...
Definition: X86InstrInfo.cpp:6729
llvm::X86InstrInfo::buildOutlinedFrame
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
Definition: X86InstrInfo.cpp:9256
llvm::X86InstrInfo::isSubregFoldable
bool isSubregFoldable() const override
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: X86InstrInfo.h:374
llvm::X86InstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: X86InstrInfo.cpp:7007
uint16_t
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
ISDOpcodes.h
llvm::X86InstrInfo::hasHighOperandLatency
bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
Definition: X86InstrInfo.cpp:8241
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::X86::getCMovOpcode
unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand=false)
Return a cmov opcode for the given register size in bytes, and operand type.
Definition: X86InstrInfo.cpp:2877
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition: MachineOperand.h:323
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:413
llvm::X86::getSETOpc
unsigned getSETOpc(bool HasMemoryOperand=false)
Return a setcc opcode based on whether it has a memory operand.
Definition: X86InstrInfo.cpp:2872
X86RegisterInfo.h
X86BaseInfo.h
llvm::X86::getX86ConditionCode
std::pair< CondCode, bool > getX86ConditionCode(CmpInst::Predicate Predicate)
Return a pair of condition code for the given predicate and whether the instruction operands should b...
Definition: X86InstrInfo.cpp:2834
llvm::X86InstrInfo::getGlobalBaseReg
unsigned getGlobalBaseReg(MachineFunction *MF) const
getGlobalBaseReg - Return a virtual register initialized with the the global base register value.
Definition: X86InstrInfo.cpp:7029
N
#define N
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::isMem
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:123
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::X86InstrInfo::optimizeLoadInstr
MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use.
Definition: X86InstrInfo.cpp:4511
llvm::LiveVariables
Definition: LiveVariables.h:46
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::X86InstrInfo::shouldScheduleLoadsNear
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
Definition: X86InstrInfo.cpp:6945
llvm::X86InstrInfo::optimizeCompareInstr
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source ...
Definition: X86InstrInfo.cpp:4223
X86
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
Definition: README.txt:568
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::X86InstrInfo::convertToThreeAddress
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV) const override
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_AD...
Definition: X86InstrInfo.cpp:1383
llvm::X86II::LOCK
@ LOCK
Definition: X86BaseInfo.h:888
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24