LLVM 18.0.0git
X86InstrInfo.h
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1//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14#define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15
17#include "X86InstrFMA3Info.h"
18#include "X86RegisterInfo.h"
21#include <vector>
22
23#define GET_INSTRINFO_HEADER
24#include "X86GenInstrInfo.inc"
25
26namespace llvm {
27class X86Subtarget;
28
29namespace X86 {
30
32 // For instr that was compressed from EVEX to VEX.
34};
35
36/// Return a pair of condition code for the given predicate and whether
37/// the instruction operands should be swaped to match the condition code.
38std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
39
40/// Return a cmov opcode for the given register size in bytes, and operand type.
41unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
42
43/// Return the source operand # for condition code by \p MCID. If the
44/// instruction doesn't have a condition code, return -1.
45int getCondSrcNoFromDesc(const MCInstrDesc &MCID);
46
47/// Return the condition code of the instruction. If the instruction doesn't
48/// have a condition code, return X86::COND_INVALID.
50
51// Turn JCC instruction into condition code.
53
54// Turn SETCC instruction into condition code.
56
57// Turn CMOV instruction into condition code.
59
60/// GetOppositeBranchCondition - Return the inverse of the specified cond,
61/// e.g. turning COND_E to COND_NE.
63
64/// Get the VPCMP immediate for the given condition.
66
67/// Get the VPCMP immediate if the opcodes are swapped.
68unsigned getSwappedVPCMPImm(unsigned Imm);
69
70/// Get the VPCOM immediate if the opcodes are swapped.
71unsigned getSwappedVPCOMImm(unsigned Imm);
72
73/// Get the VCMP immediate if the opcodes are swapped.
74unsigned getSwappedVCMPImm(unsigned Imm);
75
76/// Check if the instruction is X87 instruction.
78} // namespace X86
79
80/// isGlobalStubReference - Return true if the specified TargetFlag operand is
81/// a reference to a stub for a global, not the global itself.
82inline static bool isGlobalStubReference(unsigned char TargetFlag) {
83 switch (TargetFlag) {
84 case X86II::MO_DLLIMPORT: // dllimport stub.
85 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
86 case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference.
87 case X86II::MO_GOT: // normal GOT reference.
88 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
89 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
90 case X86II::MO_COFFSTUB: // COFF .refptr stub.
91 return true;
92 default:
93 return false;
94 }
95}
96
97/// isGlobalRelativeToPICBase - Return true if the specified global value
98/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
99/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
100inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
101 switch (TargetFlag) {
102 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
103 case X86II::MO_GOT: // isPICStyleGOT: other global.
104 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
105 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
106 case X86II::MO_TLVP: // ??? Pretty sure..
107 return true;
108 default:
109 return false;
110 }
111}
112
113inline static bool isScale(const MachineOperand &MO) {
114 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
115 MO.getImm() == 4 || MO.getImm() == 8);
116}
117
118inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
119 if (MI.getOperand(Op).isFI())
120 return true;
121 return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
122 MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
123 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
124 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
125 (MI.getOperand(Op + X86::AddrDisp).isImm() ||
126 MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
127 MI.getOperand(Op + X86::AddrDisp).isCPI() ||
128 MI.getOperand(Op + X86::AddrDisp).isJTI());
129}
130
131inline static bool isMem(const MachineInstr &MI, unsigned Op) {
132 if (MI.getOperand(Op).isFI())
133 return true;
134 return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
135 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
136}
137
138class X86InstrInfo final : public X86GenInstrInfo {
139 X86Subtarget &Subtarget;
140 const X86RegisterInfo RI;
141
142 virtual void anchor();
143
144 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
145 MachineBasicBlock *&FBB,
148 bool AllowModify) const;
149
150public:
151 explicit X86InstrInfo(X86Subtarget &STI);
152
153 /// Given a machine instruction descriptor, returns the register
154 /// class constraint for OpNum, or NULL. Returned register class
155 /// may be different from the definition in the TD file, e.g.
156 /// GR*RegClass (definition in TD file)
157 /// ->
158 /// GR*_NOREX2RegClass (Returned register class)
159 const TargetRegisterClass *
160 getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
161 const TargetRegisterInfo *TRI,
162 const MachineFunction &MF) const override;
163
164 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
165 /// such, whenever a client has an instance of instruction info, it should
166 /// always be able to get register info as well (through this method).
167 ///
168 const X86RegisterInfo &getRegisterInfo() const { return RI; }
169
170 /// Returns the stack pointer adjustment that happens inside the frame
171 /// setup..destroy sequence (e.g. by pushes, or inside the callee).
172 int64_t getFrameAdjustment(const MachineInstr &I) const {
173 assert(isFrameInstr(I));
174 if (isFrameSetup(I))
175 return I.getOperand(2).getImm();
176 return I.getOperand(1).getImm();
177 }
178
179 /// Sets the stack pointer adjustment made inside the frame made up by this
180 /// instruction.
181 void setFrameAdjustment(MachineInstr &I, int64_t V) const {
182 assert(isFrameInstr(I));
183 if (isFrameSetup(I))
184 I.getOperand(2).setImm(V);
185 else
186 I.getOperand(1).setImm(V);
187 }
188
189 /// getSPAdjust - This returns the stack pointer adjustment made by
190 /// this instruction. For x86, we need to handle more complex call
191 /// sequences involving PUSHes.
192 int getSPAdjust(const MachineInstr &MI) const override;
193
194 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
195 /// extension instruction. That is, it's like a copy where it's legal for the
196 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
197 /// true, then it's expected the pre-extension value is available as a subreg
198 /// of the result register. This also returns the sub-register index in
199 /// SubIdx.
200 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
201 Register &DstReg, unsigned &SubIdx) const override;
202
203 /// Returns true if the instruction has no behavior (specified or otherwise)
204 /// that is based on the value of any of its register operands
205 ///
206 /// Instructions are considered data invariant even if they set EFLAGS.
207 ///
208 /// A classical example of something that is inherently not data invariant is
209 /// an indirect jump -- the destination is loaded into icache based on the
210 /// bits set in the jump destination register.
211 ///
212 /// FIXME: This should become part of our instruction tables.
213 static bool isDataInvariant(MachineInstr &MI);
214
215 /// Returns true if the instruction has no behavior (specified or otherwise)
216 /// that is based on the value loaded from memory or the value of any
217 /// non-address register operands.
218 ///
219 /// For example, if the latency of the instruction is dependent on the
220 /// particular bits set in any of the registers *or* any of the bits loaded
221 /// from memory.
222 ///
223 /// Instructions are considered data invariant even if they set EFLAGS.
224 ///
225 /// A classical example of something that is inherently not data invariant is
226 /// an indirect jump -- the destination is loaded into icache based on the
227 /// bits set in the jump destination register.
228 ///
229 /// FIXME: This should become part of our instruction tables.
230 static bool isDataInvariantLoad(MachineInstr &MI);
231
232 unsigned isLoadFromStackSlot(const MachineInstr &MI,
233 int &FrameIndex) const override;
234 unsigned isLoadFromStackSlot(const MachineInstr &MI,
235 int &FrameIndex,
236 unsigned &MemBytes) const override;
237 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
238 /// stack locations as well. This uses a heuristic so it isn't
239 /// reliable for correctness.
241 int &FrameIndex) const override;
242
243 unsigned isStoreToStackSlot(const MachineInstr &MI,
244 int &FrameIndex) const override;
245 unsigned isStoreToStackSlot(const MachineInstr &MI,
246 int &FrameIndex,
247 unsigned &MemBytes) const override;
248 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
249 /// stack locations as well. This uses a heuristic so it isn't
250 /// reliable for correctness.
252 int &FrameIndex) const override;
253
254 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
256 Register DestReg, unsigned SubIdx,
257 const MachineInstr &Orig,
258 const TargetRegisterInfo &TRI) const override;
259
260 /// Given an operand within a MachineInstr, insert preceding code to put it
261 /// into the right format for a particular kind of LEA instruction. This may
262 /// involve using an appropriate super-register instead (with an implicit use
263 /// of the original) or creating a new virtual register and inserting COPY
264 /// instructions to get the data into the right class.
265 ///
266 /// Reference parameters are set to indicate how caller should add this
267 /// operand to the LEA instruction.
269 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
270 bool &isKill, MachineOperand &ImplicitOp,
271 LiveVariables *LV, LiveIntervals *LIS) const;
272
273 /// convertToThreeAddress - This method must be implemented by targets that
274 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
275 /// may be able to convert a two-address instruction into a true
276 /// three-address instruction on demand. This allows the X86 target (for
277 /// example) to convert ADD and SHL instructions into LEA instructions if they
278 /// would require register copies due to two-addressness.
279 ///
280 /// This method returns a null pointer if the transformation cannot be
281 /// performed, otherwise it returns the new instruction.
282 ///
284 LiveIntervals *LIS) const override;
285
286 /// Returns true iff the routine could find two commutable operands in the
287 /// given machine instruction.
288 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
289 /// input values can be re-defined in this method only if the input values
290 /// are not pre-defined, which is designated by the special value
291 /// 'CommuteAnyOperandIndex' assigned to it.
292 /// If both of indices are pre-defined and refer to some operands, then the
293 /// method simply returns true if the corresponding operands are commutable
294 /// and returns false otherwise.
295 ///
296 /// For example, calling this method this way:
297 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
298 /// findCommutedOpIndices(MI, Op1, Op2);
299 /// can be interpreted as a query asking to find an operand that would be
300 /// commutable with the operand#1.
301 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
302 unsigned &SrcOpIdx2) const override;
303
304 /// Returns true if we have preference on the operands order in MI, the
305 /// commute decision is returned in Commute.
306 bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override;
307
308 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
309 /// performs the same computations as the given \p MI but which has the
310 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
311 /// It may return 0 if it is unsafe to commute the operands.
312 /// Note that a machine instruction (instead of its opcode) is passed as the
313 /// first parameter to make it possible to analyze the instruction's uses and
314 /// commute the first operand of FMA even when it seems unsafe when you look
315 /// at the opcode. For example, it is Ok to commute the first operand of
316 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
317 ///
318 /// The returned FMA opcode may differ from the opcode in the given \p MI.
319 /// For example, commuting the operands #1 and #3 in the following FMA
320 /// FMA213 #1, #2, #3
321 /// results into instruction with adjusted opcode:
322 /// FMA231 #3, #2, #1
323 unsigned
324 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
325 unsigned SrcOpIdx2,
326 const X86InstrFMA3Group &FMA3Group) const;
327
328 // Branch analysis.
329 bool isUnconditionalTailCall(const MachineInstr &MI) const override;
331 const MachineInstr &TailCall) const override;
334 const MachineInstr &TailCall) const override;
335
337 MachineBasicBlock *&FBB,
339 bool AllowModify) const override;
340
341 int getJumpTableIndex(const MachineInstr &MI) const override;
342
343 std::optional<ExtAddrMode>
345 const TargetRegisterInfo *TRI) const override;
346
348 int64_t &ImmVal) const override;
349
351 const Register NullValueReg,
352 const TargetRegisterInfo *TRI) const override;
353
355 const MachineInstr &LdSt,
357 bool &OffsetIsScalable, unsigned &Width,
358 const TargetRegisterInfo *TRI) const override;
361 bool AllowModify = false) const override;
362
364 int *BytesRemoved = nullptr) const override;
367 const DebugLoc &DL,
368 int *BytesAdded = nullptr) const override;
370 Register, Register, Register, int &, int &,
371 int &) const override;
373 const DebugLoc &DL, Register DstReg,
375 Register FalseReg) const override;
377 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
378 bool KillSrc) const override;
381 bool isKill, int FrameIndex,
382 const TargetRegisterClass *RC,
383 const TargetRegisterInfo *TRI,
384 Register VReg) const override;
385
388 int FrameIndex, const TargetRegisterClass *RC,
389 const TargetRegisterInfo *TRI,
390 Register VReg) const override;
391
393 unsigned Opc, Register Reg, int FrameIdx,
394 bool isKill = false) const;
395
396 bool expandPostRAPseudo(MachineInstr &MI) const override;
397
398 /// Check whether the target can fold a load that feeds a subreg operand
399 /// (or a subreg operand that feeds a store).
400 bool isSubregFoldable() const override { return true; }
401
402 /// foldMemoryOperand - If this target supports it, fold a load or store of
403 /// the specified stack slot into the specified machine instruction for the
404 /// specified operand(s). If this is possible, the target should perform the
405 /// folding and return true, otherwise it should return false. If it folds
406 /// the instruction, it is likely that the MachineInstruction the iterator
407 /// references has been changed.
411 MachineBasicBlock::iterator InsertPt, int FrameIndex,
412 LiveIntervals *LIS = nullptr,
413 VirtRegMap *VRM = nullptr) const override;
414
415 /// foldMemoryOperand - Same as the previous version except it allows folding
416 /// of any load and store from / to any address, not just from a specific
417 /// stack slot.
421 LiveIntervals *LIS = nullptr) const override;
422
423 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
424 /// a store or a load and a store into two or more instruction. If this is
425 /// possible, returns true as well as the new instructions by reference.
426 bool
428 bool UnfoldLoad, bool UnfoldStore,
429 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
430
432 SmallVectorImpl<SDNode *> &NewNodes) const override;
433
434 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
435 /// instruction after load / store are unfolded from an instruction of the
436 /// specified opcode. It returns zero if the specified unfolding is not
437 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
438 /// index of the operand which will hold the register holding the loaded
439 /// value.
440 unsigned
441 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
442 unsigned *LoadRegIndex = nullptr) const override;
443
444 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
445 /// to determine if two loads are loading from the same base address. It
446 /// should only return true if the base pointers are the same and the
447 /// only differences between the two addresses are the offset. It also returns
448 /// the offsets by reference.
449 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
450 int64_t &Offset2) const override;
451
452 /// isSchedulingBoundary - Overrides the isSchedulingBoundary from
453 /// Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR
454 /// intructions and prevent it from being re-scheduled.
456 const MachineBasicBlock *MBB,
457 const MachineFunction &MF) const override;
458
459 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
460 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
461 /// should be scheduled togther. On some targets if two loads are loading from
462 /// addresses in the same cache line, it's better if they are scheduled
463 /// together. This function takes two integers that represent the load offsets
464 /// from the common base address. It returns true if it decides it's desirable
465 /// to schedule the two loads together. "NumLoads" is the number of loads that
466 /// have already been scheduled after Load1.
467 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
468 int64_t Offset2,
469 unsigned NumLoads) const override;
470
472 MachineBasicBlock::iterator MI) const override;
473
474 MCInst getNop() const override;
475
476 bool
478
479 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
480 /// instruction that defines the specified register class.
481 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
482
483 /// True if MI has a condition code def, e.g. EFLAGS, that is
484 /// not marked dead.
486
487 /// getGlobalBaseReg - Return a virtual register initialized with the
488 /// the global base register value. Output instructions required to
489 /// initialize the register in the function entry block, if necessary.
490 ///
491 unsigned getGlobalBaseReg(MachineFunction *MF) const;
492
493 std::pair<uint16_t, uint16_t>
494 getExecutionDomain(const MachineInstr &MI) const override;
495
497
498 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
499
500 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
501
502 unsigned
503 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
504 const TargetRegisterInfo *TRI) const override;
505 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
506 const TargetRegisterInfo *TRI) const override;
507 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
508 const TargetRegisterInfo *TRI) const override;
509
511 unsigned OpNum,
514 unsigned Size, Align Alignment,
515 bool AllowCommute) const;
516
517 bool isHighLatencyDef(int opc) const override;
518
519 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
521 const MachineInstr &DefMI, unsigned DefIdx,
522 const MachineInstr &UseMI,
523 unsigned UseIdx) const override;
524
525 bool useMachineCombiner() const override { return true; }
526
528 bool Invert) const override;
529
530 bool hasReassociableOperands(const MachineInstr &Inst,
531 const MachineBasicBlock *MBB) const override;
532
533 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
534 MachineInstr &NewMI1,
535 MachineInstr &NewMI2) const override;
536
537 /// analyzeCompare - For a comparison instruction, return the source registers
538 /// in SrcReg and SrcReg2 if having two register operands, and the value it
539 /// compares against in CmpValue. Return true if the comparison instruction
540 /// can be analyzed.
541 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
542 Register &SrcReg2, int64_t &CmpMask,
543 int64_t &CmpValue) const override;
544
545 /// optimizeCompareInstr - Check if there exists an earlier instruction that
546 /// operates on the same source operands and sets flags in the same way as
547 /// Compare; remove Compare if possible.
548 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
549 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
550 const MachineRegisterInfo *MRI) const override;
551
552 /// optimizeLoadInstr - Try to remove the load by folding it to a register
553 /// operand at the use. We fold the load instructions if and only if the
554 /// def and use are in the same BB. We only look at one load and see
555 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
556 /// defined by the load we are trying to fold. DefMI returns the machine
557 /// instruction that defines FoldAsLoadDefReg, and the function returns
558 /// the machine instruction generated due to folding.
561 Register &FoldAsLoadDefReg,
562 MachineInstr *&DefMI) const override;
563
565 int64_t ImmVal, MachineRegisterInfo *MRI,
566 bool MakeChange) const;
567
568 /// Reg is known to be defined by a move immediate instruction, try to fold
569 /// the immediate into the use instruction.
571 MachineRegisterInfo *MRI) const override;
572
573 std::pair<unsigned, unsigned>
574 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
575
578
579 std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo(
580 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
581
583 bool OutlineFromLinkOnceODRs) const override;
584
586 getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
587
589 const outliner::OutlinedFunction &OF) const override;
590
594 outliner::Candidate &C) const override;
595
598 bool AllowSideEffects = true) const override;
599
601 StringRef &ErrInfo) const override;
602#define GET_INSTRINFO_HELPER_DECLS
603#include "X86GenInstrInfo.inc"
604
605 static bool hasLockPrefix(const MachineInstr &MI) {
606 return MI.getDesc().TSFlags & X86II::LOCK;
607 }
608
609 std::optional<ParamLoadedValue>
610 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
611
612protected:
613 /// Commutes the operands in the given instruction by changing the operands
614 /// order and/or changing the instruction's opcode and/or the immediate value
615 /// operand.
616 ///
617 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
618 /// to be commuted.
619 ///
620 /// Do not call this method for a non-commutable instruction or
621 /// non-commutable operands.
622 /// Even though the instruction is commutable, the method may still
623 /// fail to commute the operands, null pointer is returned in such cases.
625 unsigned CommuteOpIdx1,
626 unsigned CommuteOpIdx2) const override;
627
628 /// If the specific machine instruction is a instruction that moves/copies
629 /// value from one register to another register return destination and source
630 /// registers as machine operands.
631 std::optional<DestSourcePair>
632 isCopyInstrImpl(const MachineInstr &MI) const override;
633
634 /// Return true when there is potentially a faster code sequence for an
635 /// instruction chain ending in \p Root. All potential patterns are listed in
636 /// the \p Pattern vector. Pattern should be sorted in priority order since
637 /// the pattern evaluator stops checking as soon as it finds a faster
638 /// sequence.
639 bool
642 bool DoRegPressureReduce) const override;
643
644 /// When getMachineCombinerPatterns() finds potential patterns,
645 /// this function generates the instructions that could replace the
646 /// original code sequence.
651 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
652
653 /// When calculate the latency of the root instruction, accumulate the
654 /// latency of the sequence to the root latency.
655 /// \param Root - Instruction that could be combined with one of its operands
656 /// For X86 instruction (vpmaddwd + vpmaddwd) -> vpdpwssd, the vpmaddwd
657 /// is not in the critical path, so the root latency only include vpmaddwd.
659 return false;
660 }
661
663 int FI) const override;
664
665private:
666 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
667 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
668 /// super-register and then truncating back down to a 8/16-bit sub-register.
669 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI,
670 LiveVariables *LV,
671 LiveIntervals *LIS,
672 bool Is8BitOp) const;
673
674 /// Handles memory folding for special case instructions, for instance those
675 /// requiring custom manipulation of the address.
676 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
677 unsigned OpNum,
680 unsigned Size, Align Alignment) const;
681
682 /// isFrameOperand - Return true and the FrameIndex if the specified
683 /// operand and follow operands form a reference to the stack frame.
684 bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
685 int &FrameIndex) const;
686
687 /// Returns true iff the routine could find two commutable operands in the
688 /// given machine instruction with 3 vector inputs.
689 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
690 /// input values can be re-defined in this method only if the input values
691 /// are not pre-defined, which is designated by the special value
692 /// 'CommuteAnyOperandIndex' assigned to it.
693 /// If both of indices are pre-defined and refer to some operands, then the
694 /// method simply returns true if the corresponding operands are commutable
695 /// and returns false otherwise.
696 ///
697 /// For example, calling this method this way:
698 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
699 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
700 /// can be interpreted as a query asking to find an operand that would be
701 /// commutable with the operand#1.
702 ///
703 /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
704 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
705 unsigned &SrcOpIdx1,
706 unsigned &SrcOpIdx2,
707 bool IsIntrinsic = false) const;
708
709 /// Returns true when instruction \p FlagI produces the same flags as \p OI.
710 /// The caller should pass in the results of calling analyzeCompare on \p OI:
711 /// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue.
712 /// If the flags match \p OI as if it had the input operands swapped then the
713 /// function succeeds and sets \p IsSwapped to true.
714 ///
715 /// Examples of OI, FlagI pairs returning true:
716 /// CMP %1, 42 and CMP %1, 42
717 /// CMP %1, %2 and %3 = SUB %1, %2
718 /// TEST %1, %1 and %2 = SUB %1, 0
719 /// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true
720 bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg,
721 Register SrcReg2, int64_t ImmMask, int64_t ImmValue,
722 const MachineInstr &OI, bool *IsSwapped,
723 int64_t *ImmDelta) const;
724};
725
726} // namespace llvm
727
728#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static constexpr uint32_t ImmMask
Definition: aarch32.h:201
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:748
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const override
When calculate the latency of the root instruction, accumulate the latency of the sequence to the roo...
Definition: X86InstrInfo.h:658
void getFrameIndexOperands(SmallVectorImpl< MachineOperand > &Ops, int FI) const override
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source ...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo....
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
unsigned getGlobalBaseReg(MachineFunction *MF) const
getGlobalBaseReg - Return a virtual register initialized with the the global base register value.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store ar...
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Returns true iff the routine could find two commutable operands in the given machine instruction.
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
static bool isDataInvariantLoad(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value l...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:168
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override
Returns true if we have preference on the operands order in MI, the commute decision is returned in C...
bool hasLiveCondCodeDef(MachineInstr &MI) const
True if MI has a condition code def, e.g.
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_AD...
static bool hasLockPrefix(const MachineInstr &MI)
Definition: X86InstrInfo.h:605
bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
Reg is known to be defined by a move immediate instruction, try to fold the immediate into the use in...
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
MCInst getNop() const override
Return the noop instruction to use for a noop.
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into...
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const override
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override
std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
bool isUnconditionalTailCall(const MachineInstr &MI) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
bool useMachineCombiner() const override
Definition: X86InstrInfo.h:525
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const
int getSPAdjust(const MachineInstr &MI) const override
getSPAdjust - This returns the stack pointer adjustment made by this instruction.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
outliner::InstrType getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
int getJumpTableIndex(const MachineInstr &MI) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
void setFrameAdjustment(MachineInstr &I, int64_t V) const
Sets the stack pointer adjustment made inside the frame made up by this instruction.
Definition: X86InstrInfo.h:181
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.
void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Opc, Register Reg, int FrameIdx, bool isKill=false) const
bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, Register &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV, LiveIntervals *LIS) const
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a p...
bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
bool analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
static bool isDataInvariant(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value o...
unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register...
void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
void buildClearRegister(Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const override
bool FoldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, Register Reg, int64_t ImmVal, MachineRegisterInfo *MRI, bool MakeChange) const
Real implementation of FoldImmediate.
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e....
Definition: X86InstrInfo.h:172
bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the sp...
bool isSubregFoldable() const override
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: X86InstrInfo.h:400
uint16_t getExecutionDomainCustom(const MachineInstr &MI) const
bool isHighLatencyDef(int opc) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions ...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computatio...
std::optional< outliner::OutlinedFunction > getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const override
unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register upd...
MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1506
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
Definition: X86BaseInfo.h:405
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:395
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:482
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: X86BaseInfo.h:502
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:478
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:390
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:486
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:474
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:385
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:401
CondCode getCondFromBranch(const MachineInstr &MI)
CondCode getCondFromMI(const MachineInstr &MI)
Return the condition code of the instruction.
unsigned getSwappedVCMPImm(unsigned Imm)
Get the VCMP immediate if the opcodes are swapped.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
unsigned getSwappedVPCOMImm(unsigned Imm)
Get the VPCOM immediate if the opcodes are swapped.
bool isX87Instruction(MachineInstr &MI)
Check if the instruction is X87 instruction.
@ AddrScaleAmt
Definition: X86BaseInfo.h:30
@ AddrSegmentReg
Definition: X86BaseInfo.h:34
@ AddrIndexReg
Definition: X86BaseInfo.h:31
@ AddrNumOperands
Definition: X86BaseInfo.h:36
unsigned getVPCMPImmForCond(ISD::CondCode CC)
Get the VPCMP immediate for the given condition.
std::pair< CondCode, bool > getX86ConditionCode(CmpInst::Predicate Predicate)
Return a pair of condition code for the given predicate and whether the instruction operands should b...
CondCode getCondFromSETCC(const MachineInstr &MI)
unsigned getSwappedVPCMPImm(unsigned Imm)
Get the VPCMP immediate if the opcodes are swapped.
int getCondSrcNoFromDesc(const MCInstrDesc &MCID)
Return the source operand # for condition code by MCID.
unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand=false)
Return a cmov opcode for the given register size in bytes, and operand type.
CondCode getCondFromCMov(const MachineInstr &MI)
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static bool isGlobalStubReference(unsigned char TargetFlag)
isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for ...
Definition: X86InstrInfo.h:82
@ Offset
Definition: DWP.cpp:456
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-b...
Definition: X86InstrInfo.h:100
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:131
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
static bool isScale(const MachineOperand &MO)
Definition: X86InstrInfo.h:113
static bool isLeaMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:118
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Represents a predicate at the MachineFunction level.
This class is used to group {132, 213, 231} forms of FMA opcodes together.
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.