LLVM 19.0.0git
X86InstrInfo.h
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1//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14#define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15
17#include "X86InstrFMA3Info.h"
18#include "X86RegisterInfo.h"
21#include <vector>
22
23#define GET_INSTRINFO_HEADER
24#include "X86GenInstrInfo.inc"
25
26namespace llvm {
27class X86Subtarget;
28
29// X86 MachineCombiner patterns
31 // X86 VNNI
33};
34
35namespace X86 {
36
38 // For instr that was compressed from EVEX to LEGACY.
40 // For instr that was compressed from EVEX to VEX.
42 // For instr that was compressed from EVEX to EVEX.
44};
45
46/// Return a pair of condition code for the given predicate and whether
47/// the instruction operands should be swaped to match the condition code.
48std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
49
50/// Return a cmov opcode for the given register size in bytes, and operand type.
51unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false,
52 bool HasNDD = false);
53
54/// Return the source operand # for condition code by \p MCID. If the
55/// instruction doesn't have a condition code, return -1.
56int getCondSrcNoFromDesc(const MCInstrDesc &MCID);
57
58/// Return the condition code of the instruction. If the instruction doesn't
59/// have a condition code, return X86::COND_INVALID.
61
62// Turn JCC instruction into condition code.
64
65// Turn SETCC instruction into condition code.
67
68// Turn CMOV instruction into condition code.
70
71// Turn CFCMOV instruction into condition code.
73
74/// GetOppositeBranchCondition - Return the inverse of the specified cond,
75/// e.g. turning COND_E to COND_NE.
77
78/// Get the VPCMP immediate for the given condition.
80
81/// Get the VPCMP immediate if the opcodes are swapped.
82unsigned getSwappedVPCMPImm(unsigned Imm);
83
84/// Get the VPCOM immediate if the opcodes are swapped.
85unsigned getSwappedVPCOMImm(unsigned Imm);
86
87/// Get the VCMP immediate if the opcodes are swapped.
88unsigned getSwappedVCMPImm(unsigned Imm);
89
90/// Get the width of the vector register operand.
92
93/// Check if the instruction is X87 instruction.
95
96/// Return the index of the instruction's first address operand, if it has a
97/// memory reference, or -1 if it has none. Unlike X86II::getMemoryOperandNo(),
98/// this also works for both pseudo instructions (e.g., TCRETURNmi) as well as
99/// real instructions (e.g., JMP64m).
101
102/// Find any constant pool entry associated with a specific instruction operand.
103const Constant *getConstantFromPool(const MachineInstr &MI, unsigned OpNo);
104
105} // namespace X86
106
107/// isGlobalStubReference - Return true if the specified TargetFlag operand is
108/// a reference to a stub for a global, not the global itself.
109inline static bool isGlobalStubReference(unsigned char TargetFlag) {
110 switch (TargetFlag) {
111 case X86II::MO_DLLIMPORT: // dllimport stub.
112 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
113 case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference.
114 case X86II::MO_GOT: // normal GOT reference.
115 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
116 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
117 case X86II::MO_COFFSTUB: // COFF .refptr stub.
118 return true;
119 default:
120 return false;
121 }
122}
123
124/// isGlobalRelativeToPICBase - Return true if the specified global value
125/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
126/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
127inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
128 switch (TargetFlag) {
129 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
130 case X86II::MO_GOT: // isPICStyleGOT: other global.
131 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
132 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
133 case X86II::MO_TLVP: // ??? Pretty sure..
134 return true;
135 default:
136 return false;
137 }
138}
139
140inline static bool isScale(const MachineOperand &MO) {
141 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
142 MO.getImm() == 4 || MO.getImm() == 8);
143}
144
145inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
146 if (MI.getOperand(Op).isFI())
147 return true;
148 return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
149 MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
150 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
151 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
152 (MI.getOperand(Op + X86::AddrDisp).isImm() ||
153 MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
154 MI.getOperand(Op + X86::AddrDisp).isCPI() ||
155 MI.getOperand(Op + X86::AddrDisp).isJTI());
156}
157
158inline static bool isMem(const MachineInstr &MI, unsigned Op) {
159 if (MI.getOperand(Op).isFI())
160 return true;
161 return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
162 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
163}
164
165class X86InstrInfo final : public X86GenInstrInfo {
166 X86Subtarget &Subtarget;
167 const X86RegisterInfo RI;
168
169 virtual void anchor();
170
171 bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
172 MachineBasicBlock *&FBB,
175 bool AllowModify) const;
176
177 bool foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, Register Reg,
178 int64_t ImmVal, MachineRegisterInfo *MRI,
179 bool MakeChange) const;
180
181public:
182 explicit X86InstrInfo(X86Subtarget &STI);
183
184 /// Given a machine instruction descriptor, returns the register
185 /// class constraint for OpNum, or NULL. Returned register class
186 /// may be different from the definition in the TD file, e.g.
187 /// GR*RegClass (definition in TD file)
188 /// ->
189 /// GR*_NOREX2RegClass (Returned register class)
190 const TargetRegisterClass *
191 getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
192 const TargetRegisterInfo *TRI,
193 const MachineFunction &MF) const override;
194
195 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
196 /// such, whenever a client has an instance of instruction info, it should
197 /// always be able to get register info as well (through this method).
198 ///
199 const X86RegisterInfo &getRegisterInfo() const { return RI; }
200
201 /// Returns the stack pointer adjustment that happens inside the frame
202 /// setup..destroy sequence (e.g. by pushes, or inside the callee).
203 int64_t getFrameAdjustment(const MachineInstr &I) const {
204 assert(isFrameInstr(I));
205 if (isFrameSetup(I))
206 return I.getOperand(2).getImm();
207 return I.getOperand(1).getImm();
208 }
209
210 /// Sets the stack pointer adjustment made inside the frame made up by this
211 /// instruction.
212 void setFrameAdjustment(MachineInstr &I, int64_t V) const {
213 assert(isFrameInstr(I));
214 if (isFrameSetup(I))
215 I.getOperand(2).setImm(V);
216 else
217 I.getOperand(1).setImm(V);
218 }
219
220 /// getSPAdjust - This returns the stack pointer adjustment made by
221 /// this instruction. For x86, we need to handle more complex call
222 /// sequences involving PUSHes.
223 int getSPAdjust(const MachineInstr &MI) const override;
224
225 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
226 /// extension instruction. That is, it's like a copy where it's legal for the
227 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
228 /// true, then it's expected the pre-extension value is available as a subreg
229 /// of the result register. This also returns the sub-register index in
230 /// SubIdx.
231 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
232 Register &DstReg, unsigned &SubIdx) const override;
233
234 /// Returns true if the instruction has no behavior (specified or otherwise)
235 /// that is based on the value of any of its register operands
236 ///
237 /// Instructions are considered data invariant even if they set EFLAGS.
238 ///
239 /// A classical example of something that is inherently not data invariant is
240 /// an indirect jump -- the destination is loaded into icache based on the
241 /// bits set in the jump destination register.
242 ///
243 /// FIXME: This should become part of our instruction tables.
244 static bool isDataInvariant(MachineInstr &MI);
245
246 /// Returns true if the instruction has no behavior (specified or otherwise)
247 /// that is based on the value loaded from memory or the value of any
248 /// non-address register operands.
249 ///
250 /// For example, if the latency of the instruction is dependent on the
251 /// particular bits set in any of the registers *or* any of the bits loaded
252 /// from memory.
253 ///
254 /// Instructions are considered data invariant even if they set EFLAGS.
255 ///
256 /// A classical example of something that is inherently not data invariant is
257 /// an indirect jump -- the destination is loaded into icache based on the
258 /// bits set in the jump destination register.
259 ///
260 /// FIXME: This should become part of our instruction tables.
261 static bool isDataInvariantLoad(MachineInstr &MI);
262
264 int &FrameIndex) const override;
266 int &FrameIndex,
267 unsigned &MemBytes) const override;
268 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
269 /// stack locations as well. This uses a heuristic so it isn't
270 /// reliable for correctness.
272 int &FrameIndex) const override;
273
275 int &FrameIndex) const override;
277 int &FrameIndex,
278 unsigned &MemBytes) const override;
279 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
280 /// stack locations as well. This uses a heuristic so it isn't
281 /// reliable for correctness.
283 int &FrameIndex) const override;
284
285 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
287 Register DestReg, unsigned SubIdx,
288 const MachineInstr &Orig,
289 const TargetRegisterInfo &TRI) const override;
290
291 /// Given an operand within a MachineInstr, insert preceding code to put it
292 /// into the right format for a particular kind of LEA instruction. This may
293 /// involve using an appropriate super-register instead (with an implicit use
294 /// of the original) or creating a new virtual register and inserting COPY
295 /// instructions to get the data into the right class.
296 ///
297 /// Reference parameters are set to indicate how caller should add this
298 /// operand to the LEA instruction.
300 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
301 bool &isKill, MachineOperand &ImplicitOp,
302 LiveVariables *LV, LiveIntervals *LIS) const;
303
304 /// convertToThreeAddress - This method must be implemented by targets that
305 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
306 /// may be able to convert a two-address instruction into a true
307 /// three-address instruction on demand. This allows the X86 target (for
308 /// example) to convert ADD and SHL instructions into LEA instructions if they
309 /// would require register copies due to two-addressness.
310 ///
311 /// This method returns a null pointer if the transformation cannot be
312 /// performed, otherwise it returns the new instruction.
313 ///
315 LiveIntervals *LIS) const override;
316
317 /// Returns true iff the routine could find two commutable operands in the
318 /// given machine instruction.
319 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
320 /// input values can be re-defined in this method only if the input values
321 /// are not pre-defined, which is designated by the special value
322 /// 'CommuteAnyOperandIndex' assigned to it.
323 /// If both of indices are pre-defined and refer to some operands, then the
324 /// method simply returns true if the corresponding operands are commutable
325 /// and returns false otherwise.
326 ///
327 /// For example, calling this method this way:
328 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
329 /// findCommutedOpIndices(MI, Op1, Op2);
330 /// can be interpreted as a query asking to find an operand that would be
331 /// commutable with the operand#1.
332 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
333 unsigned &SrcOpIdx2) const override;
334
335 /// Returns true if we have preference on the operands order in MI, the
336 /// commute decision is returned in Commute.
337 bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override;
338
339 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
340 /// performs the same computations as the given \p MI but which has the
341 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
342 /// It may return 0 if it is unsafe to commute the operands.
343 /// Note that a machine instruction (instead of its opcode) is passed as the
344 /// first parameter to make it possible to analyze the instruction's uses and
345 /// commute the first operand of FMA even when it seems unsafe when you look
346 /// at the opcode. For example, it is Ok to commute the first operand of
347 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
348 ///
349 /// The returned FMA opcode may differ from the opcode in the given \p MI.
350 /// For example, commuting the operands #1 and #3 in the following FMA
351 /// FMA213 #1, #2, #3
352 /// results into instruction with adjusted opcode:
353 /// FMA231 #3, #2, #1
354 unsigned
355 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
356 unsigned SrcOpIdx2,
357 const X86InstrFMA3Group &FMA3Group) const;
358
359 // Branch analysis.
360 bool isUnconditionalTailCall(const MachineInstr &MI) const override;
362 const MachineInstr &TailCall) const override;
365 const MachineInstr &TailCall) const override;
366
368 MachineBasicBlock *&FBB,
370 bool AllowModify) const override;
371
372 int getJumpTableIndex(const MachineInstr &MI) const override;
373
374 std::optional<ExtAddrMode>
376 const TargetRegisterInfo *TRI) const override;
377
379 int64_t &ImmVal) const override;
380
382 const Register NullValueReg,
383 const TargetRegisterInfo *TRI) const override;
384
386 const MachineInstr &LdSt,
388 bool &OffsetIsScalable, LocationSize &Width,
389 const TargetRegisterInfo *TRI) const override;
392 bool AllowModify = false) const override;
393
395 int *BytesRemoved = nullptr) const override;
398 const DebugLoc &DL,
399 int *BytesAdded = nullptr) const override;
401 Register, Register, Register, int &, int &,
402 int &) const override;
404 const DebugLoc &DL, Register DstReg,
406 Register FalseReg) const override;
408 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
409 bool KillSrc) const override;
412 bool isKill, int FrameIndex,
413 const TargetRegisterClass *RC,
414 const TargetRegisterInfo *TRI,
415 Register VReg) const override;
416
419 int FrameIndex, const TargetRegisterClass *RC,
420 const TargetRegisterInfo *TRI,
421 Register VReg) const override;
422
424 unsigned Opc, Register Reg, int FrameIdx,
425 bool isKill = false) const;
426
427 bool expandPostRAPseudo(MachineInstr &MI) const override;
428
429 /// Check whether the target can fold a load that feeds a subreg operand
430 /// (or a subreg operand that feeds a store).
431 bool isSubregFoldable() const override { return true; }
432
433 /// Fold a load or store of the specified stack slot into the specified
434 /// machine instruction for the specified operand(s). If folding happens, it
435 /// is likely that the referenced instruction has been changed.
436 ///
437 /// \returns true on success.
441 MachineBasicBlock::iterator InsertPt, int FrameIndex,
442 LiveIntervals *LIS = nullptr,
443 VirtRegMap *VRM = nullptr) const override;
444
445 /// Same as the previous version except it allows folding of any load and
446 /// store from / to any address, not just from a specific stack slot.
450 LiveIntervals *LIS = nullptr) const override;
451
452 bool
454 bool UnfoldLoad, bool UnfoldStore,
455 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
456
458 SmallVectorImpl<SDNode *> &NewNodes) const override;
459
460 unsigned
461 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
462 unsigned *LoadRegIndex = nullptr) const override;
463
464 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
465 int64_t &Offset2) const override;
466
467 /// Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to
468 /// make it capable of identifying ENDBR intructions and prevent it from being
469 /// re-scheduled.
471 const MachineBasicBlock *MBB,
472 const MachineFunction &MF) const override;
473
474 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
475 /// with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On
476 /// some targets if two loads are loading from addresses in the same cache
477 /// line, it's better if they are scheduled together. This function takes two
478 /// integers that represent the load offsets from the common base address. It
479 /// returns true if it decides it's desirable to schedule the two loads
480 /// together. "NumLoads" is the number of loads that have already been
481 /// scheduled after Load1.
482 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
483 int64_t Offset2,
484 unsigned NumLoads) const override;
485
487 MachineBasicBlock::iterator MI) const override;
488
489 MCInst getNop() const override;
490
491 bool
493
494 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
495
496 /// True if MI has a condition code def, e.g. EFLAGS, that is
497 /// not marked dead.
499
500 /// getGlobalBaseReg - Return a virtual register initialized with the
501 /// the global base register value. Output instructions required to
502 /// initialize the register in the function entry block, if necessary.
503 ///
504 unsigned getGlobalBaseReg(MachineFunction *MF) const;
505
506 std::pair<uint16_t, uint16_t>
507 getExecutionDomain(const MachineInstr &MI) const override;
508
510
511 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
512
513 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
514
515 unsigned
516 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
517 const TargetRegisterInfo *TRI) const override;
518 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
519 const TargetRegisterInfo *TRI) const override;
520 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
521 const TargetRegisterInfo *TRI) const override;
522
524 unsigned OpNum,
527 unsigned Size, Align Alignment,
528 bool AllowCommute) const;
529
530 bool isHighLatencyDef(int opc) const override;
531
532 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
534 const MachineInstr &DefMI, unsigned DefIdx,
535 const MachineInstr &UseMI,
536 unsigned UseIdx) const override;
537
538 bool useMachineCombiner() const override { return true; }
539
541 bool Invert) const override;
542
543 bool hasReassociableOperands(const MachineInstr &Inst,
544 const MachineBasicBlock *MBB) const override;
545
546 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
547 MachineInstr &NewMI1,
548 MachineInstr &NewMI2) const override;
549
550 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
551 Register &SrcReg2, int64_t &CmpMask,
552 int64_t &CmpValue) const override;
553
554 /// Check if there exists an earlier instruction that operates on the same
555 /// source operands and sets eflags in the same way as CMP and remove CMP if
556 /// possible.
557 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
558 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
559 const MachineRegisterInfo *MRI) const override;
560
563 Register &FoldAsLoadDefReg,
564 MachineInstr *&DefMI) const override;
565
567 MachineRegisterInfo *MRI) const override;
568
569 std::pair<unsigned, unsigned>
570 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
571
574
575 std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo(
576 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
577
579 bool OutlineFromLinkOnceODRs) const override;
580
582 getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
583
585 const outliner::OutlinedFunction &OF) const override;
586
590 outliner::Candidate &C) const override;
591
594 bool AllowSideEffects = true) const override;
595
597 StringRef &ErrInfo) const override;
598#define GET_INSTRINFO_HELPER_DECLS
599#include "X86GenInstrInfo.inc"
600
601 static bool hasLockPrefix(const MachineInstr &MI) {
602 return MI.getDesc().TSFlags & X86II::LOCK;
603 }
604
605 std::optional<ParamLoadedValue>
606 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
607
608protected:
610 unsigned CommuteOpIdx1,
611 unsigned CommuteOpIdx2) const override;
612
613 std::optional<DestSourcePair>
614 isCopyInstrImpl(const MachineInstr &MI) const override;
615
618 bool DoRegPressureReduce) const override;
619
620 /// When getMachineCombinerPatterns() finds potential patterns,
621 /// this function generates the instructions that could replace the
622 /// original code sequence.
624 MachineInstr &Root, unsigned Pattern,
627 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
628
629 /// When calculate the latency of the root instruction, accumulate the
630 /// latency of the sequence to the root latency.
631 /// \param Root - Instruction that could be combined with one of its operands
632 /// For X86 instruction (vpmaddwd + vpmaddwd) -> vpdpwssd, the vpmaddwd
633 /// is not in the critical path, so the root latency only include vpmaddwd.
635 return false;
636 }
637
639 int FI) const override;
640
641private:
642 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
643 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
644 /// super-register and then truncating back down to a 8/16-bit sub-register.
645 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI,
646 LiveVariables *LV,
647 LiveIntervals *LIS,
648 bool Is8BitOp) const;
649
650 /// Handles memory folding for special case instructions, for instance those
651 /// requiring custom manipulation of the address.
652 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
653 unsigned OpNum,
656 unsigned Size, Align Alignment) const;
657
658 MachineInstr *foldMemoryBroadcast(MachineFunction &MF, MachineInstr &MI,
659 unsigned OpNum,
662 unsigned BitsSize, bool AllowCommute) const;
663
664 /// isFrameOperand - Return true and the FrameIndex if the specified
665 /// operand and follow operands form a reference to the stack frame.
666 bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
667 int &FrameIndex) const;
668
669 /// Returns true iff the routine could find two commutable operands in the
670 /// given machine instruction with 3 vector inputs.
671 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
672 /// input values can be re-defined in this method only if the input values
673 /// are not pre-defined, which is designated by the special value
674 /// 'CommuteAnyOperandIndex' assigned to it.
675 /// If both of indices are pre-defined and refer to some operands, then the
676 /// method simply returns true if the corresponding operands are commutable
677 /// and returns false otherwise.
678 ///
679 /// For example, calling this method this way:
680 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
681 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
682 /// can be interpreted as a query asking to find an operand that would be
683 /// commutable with the operand#1.
684 ///
685 /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
686 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
687 unsigned &SrcOpIdx1,
688 unsigned &SrcOpIdx2,
689 bool IsIntrinsic = false) const;
690
691 /// Returns true when instruction \p FlagI produces the same flags as \p OI.
692 /// The caller should pass in the results of calling analyzeCompare on \p OI:
693 /// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue.
694 /// If the flags match \p OI as if it had the input operands swapped then the
695 /// function succeeds and sets \p IsSwapped to true.
696 ///
697 /// Examples of OI, FlagI pairs returning true:
698 /// CMP %1, 42 and CMP %1, 42
699 /// CMP %1, %2 and %3 = SUB %1, %2
700 /// TEST %1, %1 and %2 = SUB %1, 0
701 /// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true
702 bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg,
703 Register SrcReg2, int64_t ImmMask, int64_t ImmValue,
704 const MachineInstr &OI, bool *IsSwapped,
705 int64_t *ImmDelta) const;
706
707 /// Commute operands of \p MI for memory fold.
708 ///
709 /// \param Idx1 the index of operand to be commuted.
710 ///
711 /// \returns the index of operand that is commuted with \p Idx1. If the method
712 /// fails to commute the operands, it will return \p Idx1.
713 unsigned commuteOperandsForFold(MachineInstr &MI, unsigned Idx1) const;
714};
715} // namespace llvm
716
717#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:993
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const override
When calculate the latency of the root instruction, accumulate the latency of the sequence to the roo...
Definition: X86InstrInfo.h:634
void getFrameIndexOperands(SmallVectorImpl< MachineOperand > &Ops, int FI) const override
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
Check if there exists an earlier instruction that operates on the same source operands and sets eflag...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to make it capable of identifying...
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
unsigned getGlobalBaseReg(MachineFunction *MF) const
getGlobalBaseReg - Return a virtual register initialized with the the global base register value.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Returns true iff the routine could find two commutable operands in the given machine instruction.
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
static bool isDataInvariantLoad(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value l...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:199
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override
Returns true if we have preference on the operands order in MI, the commute decision is returned in C...
bool hasLiveCondCodeDef(MachineInstr &MI) const
True if MI has a condition code def, e.g.
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_AD...
static bool hasLockPrefix(const MachineInstr &MI)
Definition: X86InstrInfo.h:601
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
MCInst getNop() const override
Return the noop instruction to use for a noop.
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
Fold a load or store of the specified stack slot into the specified machine instruction for the speci...
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const override
When getMachineCombinerPatterns() finds potential patterns, this function generates the instructions ...
bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override
std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
Register isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
bool isUnconditionalTailCall(const MachineInstr &MI) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Register isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
bool useMachineCombiner() const override
Definition: X86InstrInfo.h:538
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const
int getSPAdjust(const MachineInstr &MI) const override
getSPAdjust - This returns the stack pointer adjustment made by this instruction.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
outliner::InstrType getOutliningTypeImpl(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
int getJumpTableIndex(const MachineInstr &MI) const override
void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
void setFrameAdjustment(MachineInstr &I, int64_t V) const
Sets the stack pointer adjustment made inside the frame made up by this instruction.
Definition: X86InstrInfo.h:212
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.
void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Opc, Register Reg, int FrameIdx, bool isKill=false) const
bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, Register &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV, LiveIntervals *LIS) const
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a p...
bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
bool analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
static bool isDataInvariant(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value o...
unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register...
void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
void buildClearRegister(Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const override
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e....
Definition: X86InstrInfo.h:203
bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
bool isSubregFoldable() const override
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: X86InstrInfo.h:431
uint16_t getExecutionDomainCustom(const MachineInstr &MI) const
bool isHighLatencyDef(int opc) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const override
foldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immedia...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computatio...
std::optional< outliner::OutlinedFunction > getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const override
unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register upd...
MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
Try to remove the load by folding it to a register operand at the use.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1523
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
Definition: X86BaseInfo.h:405
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:395
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:482
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: X86BaseInfo.h:502
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:478
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:390
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:486
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:474
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:385
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:401
CondCode getCondFromBranch(const MachineInstr &MI)
CondCode getCondFromCFCMov(const MachineInstr &MI)
CondCode getCondFromMI(const MachineInstr &MI)
Return the condition code of the instruction.
int getFirstAddrOperandIdx(const MachineInstr &MI)
Return the index of the instruction's first address operand, if it has a memory reference,...
unsigned getSwappedVCMPImm(unsigned Imm)
Get the VCMP immediate if the opcodes are swapped.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
@ AddrScaleAmt
Definition: X86BaseInfo.h:30
@ AddrSegmentReg
Definition: X86BaseInfo.h:34
@ AddrIndexReg
Definition: X86BaseInfo.h:31
@ AddrNumOperands
Definition: X86BaseInfo.h:36
unsigned getSwappedVPCOMImm(unsigned Imm)
Get the VPCOM immediate if the opcodes are swapped.
bool isX87Instruction(MachineInstr &MI)
Check if the instruction is X87 instruction.
unsigned getVPCMPImmForCond(ISD::CondCode CC)
Get the VPCMP immediate for the given condition.
std::pair< CondCode, bool > getX86ConditionCode(CmpInst::Predicate Predicate)
Return a pair of condition code for the given predicate and whether the instruction operands should b...
CondCode getCondFromSETCC(const MachineInstr &MI)
unsigned getSwappedVPCMPImm(unsigned Imm)
Get the VPCMP immediate if the opcodes are swapped.
int getCondSrcNoFromDesc(const MCInstrDesc &MCID)
Return the source operand # for condition code by MCID.
const Constant * getConstantFromPool(const MachineInstr &MI, unsigned OpNo)
Find any constant pool entry associated with a specific instruction operand.
@ AC_EVEX_2_EVEX
Definition: X86InstrInfo.h:43
@ AC_EVEX_2_LEGACY
Definition: X86InstrInfo.h:39
unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand=false, bool HasNDD=false)
Return a cmov opcode for the given register size in bytes, and operand type.
unsigned getVectorRegisterWidth(const MCOperandInfo &Info)
Get the width of the vector register operand.
CondCode getCondFromCMov(const MachineInstr &MI)
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static bool isGlobalStubReference(unsigned char TargetFlag)
isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for ...
Definition: X86InstrInfo.h:109
@ Offset
Definition: DWP.cpp:456
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-b...
Definition: X86InstrInfo.h:127
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:158
static bool isScale(const MachineOperand &MO)
Definition: X86InstrInfo.h:140
static bool isLeaMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:145
X86MachineCombinerPattern
Definition: X86InstrInfo.h:30
@ DPWSSD
Definition: X86InstrInfo.h:32
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Represents a predicate at the MachineFunction level.
This class is used to group {132, 213, 231} forms of FMA opcodes together.
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.