LLVM 17.0.0git
X86InstrInfo.h
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1//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the X86 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14#define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15
17#include "X86InstrFMA3Info.h"
18#include "X86RegisterInfo.h"
21#include <vector>
22
23#define GET_INSTRINFO_HEADER
24#include "X86GenInstrInfo.inc"
25
26namespace llvm {
27class X86Subtarget;
28
29namespace X86 {
30
32 // For instr that was compressed from EVEX to VEX.
34};
35
36/// Return a pair of condition code for the given predicate and whether
37/// the instruction operands should be swaped to match the condition code.
38std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
39
40/// Return a cmov opcode for the given register size in bytes, and operand type.
41unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false);
42
43/// Return the source operand # for condition code by \p MCID. If the
44/// instruction doesn't have a condition code, return -1.
45int getCondSrcNoFromDesc(const MCInstrDesc &MCID);
46
47/// Return the condition code of the instruction. If the instruction doesn't
48/// have a condition code, return X86::COND_INVALID.
50
51// Turn JCC instruction into condition code.
53
54// Turn SETCC instruction into condition code.
56
57// Turn CMOV instruction into condition code.
59
60/// GetOppositeBranchCondition - Return the inverse of the specified cond,
61/// e.g. turning COND_E to COND_NE.
63
64/// Get the VPCMP immediate for the given condition.
66
67/// Get the VPCMP immediate if the opcodes are swapped.
68unsigned getSwappedVPCMPImm(unsigned Imm);
69
70/// Get the VPCOM immediate if the opcodes are swapped.
71unsigned getSwappedVPCOMImm(unsigned Imm);
72
73/// Get the VCMP immediate if the opcodes are swapped.
74unsigned getSwappedVCMPImm(unsigned Imm);
75
76/// Check if the instruction is X87 instruction.
78} // namespace X86
79
80/// isGlobalStubReference - Return true if the specified TargetFlag operand is
81/// a reference to a stub for a global, not the global itself.
82inline static bool isGlobalStubReference(unsigned char TargetFlag) {
83 switch (TargetFlag) {
84 case X86II::MO_DLLIMPORT: // dllimport stub.
85 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
86 case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference.
87 case X86II::MO_GOT: // normal GOT reference.
88 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
89 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
90 case X86II::MO_COFFSTUB: // COFF .refptr stub.
91 return true;
92 default:
93 return false;
94 }
95}
96
97/// isGlobalRelativeToPICBase - Return true if the specified global value
98/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
99/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
100inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
101 switch (TargetFlag) {
102 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
103 case X86II::MO_GOT: // isPICStyleGOT: other global.
104 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
105 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
106 case X86II::MO_TLVP: // ??? Pretty sure..
107 return true;
108 default:
109 return false;
110 }
111}
112
113inline static bool isScale(const MachineOperand &MO) {
114 return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
115 MO.getImm() == 4 || MO.getImm() == 8);
116}
117
118inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
119 if (MI.getOperand(Op).isFI())
120 return true;
121 return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
122 MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
123 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
124 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
125 (MI.getOperand(Op + X86::AddrDisp).isImm() ||
126 MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
127 MI.getOperand(Op + X86::AddrDisp).isCPI() ||
128 MI.getOperand(Op + X86::AddrDisp).isJTI());
129}
130
131inline static bool isMem(const MachineInstr &MI, unsigned Op) {
132 if (MI.getOperand(Op).isFI())
133 return true;
134 return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
135 MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
136}
137
138class X86InstrInfo final : public X86GenInstrInfo {
139 X86Subtarget &Subtarget;
140 const X86RegisterInfo RI;
141
142 virtual void anchor();
143
144 bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
145 MachineBasicBlock *&FBB,
148 bool AllowModify) const;
149
150public:
151 explicit X86InstrInfo(X86Subtarget &STI);
152
153 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
154 /// such, whenever a client has an instance of instruction info, it should
155 /// always be able to get register info as well (through this method).
156 ///
157 const X86RegisterInfo &getRegisterInfo() const { return RI; }
158
159 /// Returns the stack pointer adjustment that happens inside the frame
160 /// setup..destroy sequence (e.g. by pushes, or inside the callee).
161 int64_t getFrameAdjustment(const MachineInstr &I) const {
162 assert(isFrameInstr(I));
163 if (isFrameSetup(I))
164 return I.getOperand(2).getImm();
165 return I.getOperand(1).getImm();
166 }
167
168 /// Sets the stack pointer adjustment made inside the frame made up by this
169 /// instruction.
170 void setFrameAdjustment(MachineInstr &I, int64_t V) const {
171 assert(isFrameInstr(I));
172 if (isFrameSetup(I))
173 I.getOperand(2).setImm(V);
174 else
175 I.getOperand(1).setImm(V);
176 }
177
178 /// getSPAdjust - This returns the stack pointer adjustment made by
179 /// this instruction. For x86, we need to handle more complex call
180 /// sequences involving PUSHes.
181 int getSPAdjust(const MachineInstr &MI) const override;
182
183 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
184 /// extension instruction. That is, it's like a copy where it's legal for the
185 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
186 /// true, then it's expected the pre-extension value is available as a subreg
187 /// of the result register. This also returns the sub-register index in
188 /// SubIdx.
189 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
190 Register &DstReg, unsigned &SubIdx) const override;
191
192 /// Returns true if the instruction has no behavior (specified or otherwise)
193 /// that is based on the value of any of its register operands
194 ///
195 /// Instructions are considered data invariant even if they set EFLAGS.
196 ///
197 /// A classical example of something that is inherently not data invariant is
198 /// an indirect jump -- the destination is loaded into icache based on the
199 /// bits set in the jump destination register.
200 ///
201 /// FIXME: This should become part of our instruction tables.
202 static bool isDataInvariant(MachineInstr &MI);
203
204 /// Returns true if the instruction has no behavior (specified or otherwise)
205 /// that is based on the value loaded from memory or the value of any
206 /// non-address register operands.
207 ///
208 /// For example, if the latency of the instruction is dependent on the
209 /// particular bits set in any of the registers *or* any of the bits loaded
210 /// from memory.
211 ///
212 /// Instructions are considered data invariant even if they set EFLAGS.
213 ///
214 /// A classical example of something that is inherently not data invariant is
215 /// an indirect jump -- the destination is loaded into icache based on the
216 /// bits set in the jump destination register.
217 ///
218 /// FIXME: This should become part of our instruction tables.
219 static bool isDataInvariantLoad(MachineInstr &MI);
220
221 unsigned isLoadFromStackSlot(const MachineInstr &MI,
222 int &FrameIndex) const override;
223 unsigned isLoadFromStackSlot(const MachineInstr &MI,
224 int &FrameIndex,
225 unsigned &MemBytes) const override;
226 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
227 /// stack locations as well. This uses a heuristic so it isn't
228 /// reliable for correctness.
230 int &FrameIndex) const override;
231
232 unsigned isStoreToStackSlot(const MachineInstr &MI,
233 int &FrameIndex) const override;
234 unsigned isStoreToStackSlot(const MachineInstr &MI,
235 int &FrameIndex,
236 unsigned &MemBytes) const override;
237 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
238 /// stack locations as well. This uses a heuristic so it isn't
239 /// reliable for correctness.
241 int &FrameIndex) const override;
242
243 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
245 Register DestReg, unsigned SubIdx,
246 const MachineInstr &Orig,
247 const TargetRegisterInfo &TRI) const override;
248
249 /// Given an operand within a MachineInstr, insert preceding code to put it
250 /// into the right format for a particular kind of LEA instruction. This may
251 /// involve using an appropriate super-register instead (with an implicit use
252 /// of the original) or creating a new virtual register and inserting COPY
253 /// instructions to get the data into the right class.
254 ///
255 /// Reference parameters are set to indicate how caller should add this
256 /// operand to the LEA instruction.
258 unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
259 bool &isKill, MachineOperand &ImplicitOp,
260 LiveVariables *LV, LiveIntervals *LIS) const;
261
262 /// convertToThreeAddress - This method must be implemented by targets that
263 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
264 /// may be able to convert a two-address instruction into a true
265 /// three-address instruction on demand. This allows the X86 target (for
266 /// example) to convert ADD and SHL instructions into LEA instructions if they
267 /// would require register copies due to two-addressness.
268 ///
269 /// This method returns a null pointer if the transformation cannot be
270 /// performed, otherwise it returns the new instruction.
271 ///
273 LiveIntervals *LIS) const override;
274
275 /// Returns true iff the routine could find two commutable operands in the
276 /// given machine instruction.
277 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
278 /// input values can be re-defined in this method only if the input values
279 /// are not pre-defined, which is designated by the special value
280 /// 'CommuteAnyOperandIndex' assigned to it.
281 /// If both of indices are pre-defined and refer to some operands, then the
282 /// method simply returns true if the corresponding operands are commutable
283 /// and returns false otherwise.
284 ///
285 /// For example, calling this method this way:
286 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
287 /// findCommutedOpIndices(MI, Op1, Op2);
288 /// can be interpreted as a query asking to find an operand that would be
289 /// commutable with the operand#1.
290 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
291 unsigned &SrcOpIdx2) const override;
292
293 /// Returns true if we have preference on the operands order in MI, the
294 /// commute decision is returned in Commute.
295 bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override;
296
297 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
298 /// performs the same computations as the given \p MI but which has the
299 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
300 /// It may return 0 if it is unsafe to commute the operands.
301 /// Note that a machine instruction (instead of its opcode) is passed as the
302 /// first parameter to make it possible to analyze the instruction's uses and
303 /// commute the first operand of FMA even when it seems unsafe when you look
304 /// at the opcode. For example, it is Ok to commute the first operand of
305 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
306 ///
307 /// The returned FMA opcode may differ from the opcode in the given \p MI.
308 /// For example, commuting the operands #1 and #3 in the following FMA
309 /// FMA213 #1, #2, #3
310 /// results into instruction with adjusted opcode:
311 /// FMA231 #3, #2, #1
312 unsigned
313 getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
314 unsigned SrcOpIdx2,
315 const X86InstrFMA3Group &FMA3Group) const;
316
317 // Branch analysis.
318 bool isUnconditionalTailCall(const MachineInstr &MI) const override;
320 const MachineInstr &TailCall) const override;
323 const MachineInstr &TailCall) const override;
324
326 MachineBasicBlock *&FBB,
328 bool AllowModify) const override;
329
330 std::optional<ExtAddrMode>
332 const TargetRegisterInfo *TRI) const override;
333
335 int64_t &ImmVal) const override;
336
338 const Register NullValueReg,
339 const TargetRegisterInfo *TRI) const override;
340
342 const MachineInstr &LdSt,
344 bool &OffsetIsScalable, unsigned &Width,
345 const TargetRegisterInfo *TRI) const override;
348 bool AllowModify = false) const override;
349
351 int *BytesRemoved = nullptr) const override;
354 const DebugLoc &DL,
355 int *BytesAdded = nullptr) const override;
357 Register, Register, Register, int &, int &,
358 int &) const override;
360 const DebugLoc &DL, Register DstReg,
362 Register FalseReg) const override;
364 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
365 bool KillSrc) const override;
368 bool isKill, int FrameIndex,
369 const TargetRegisterClass *RC,
370 const TargetRegisterInfo *TRI,
371 Register VReg) const override;
372
375 int FrameIndex, const TargetRegisterClass *RC,
376 const TargetRegisterInfo *TRI,
377 Register VReg) const override;
378
380 unsigned Opc, Register Reg, int FrameIdx,
381 bool isKill = false) const;
382
383 bool expandPostRAPseudo(MachineInstr &MI) const override;
384
385 /// Check whether the target can fold a load that feeds a subreg operand
386 /// (or a subreg operand that feeds a store).
387 bool isSubregFoldable() const override { return true; }
388
389 /// foldMemoryOperand - If this target supports it, fold a load or store of
390 /// the specified stack slot into the specified machine instruction for the
391 /// specified operand(s). If this is possible, the target should perform the
392 /// folding and return true, otherwise it should return false. If it folds
393 /// the instruction, it is likely that the MachineInstruction the iterator
394 /// references has been changed.
398 MachineBasicBlock::iterator InsertPt, int FrameIndex,
399 LiveIntervals *LIS = nullptr,
400 VirtRegMap *VRM = nullptr) const override;
401
402 /// foldMemoryOperand - Same as the previous version except it allows folding
403 /// of any load and store from / to any address, not just from a specific
404 /// stack slot.
408 LiveIntervals *LIS = nullptr) const override;
409
410 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
411 /// a store or a load and a store into two or more instruction. If this is
412 /// possible, returns true as well as the new instructions by reference.
413 bool
415 bool UnfoldLoad, bool UnfoldStore,
416 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
417
419 SmallVectorImpl<SDNode *> &NewNodes) const override;
420
421 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
422 /// instruction after load / store are unfolded from an instruction of the
423 /// specified opcode. It returns zero if the specified unfolding is not
424 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
425 /// index of the operand which will hold the register holding the loaded
426 /// value.
427 unsigned
428 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
429 unsigned *LoadRegIndex = nullptr) const override;
430
431 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
432 /// to determine if two loads are loading from the same base address. It
433 /// should only return true if the base pointers are the same and the
434 /// only differences between the two addresses are the offset. It also returns
435 /// the offsets by reference.
436 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
437 int64_t &Offset2) const override;
438
439 /// isSchedulingBoundary - Overrides the isSchedulingBoundary from
440 /// Codegen/TargetInstrInfo.cpp to make it capable of identifying ENDBR
441 /// intructions and prevent it from being re-scheduled.
443 const MachineBasicBlock *MBB,
444 const MachineFunction &MF) const override;
445
446 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
447 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
448 /// should be scheduled togther. On some targets if two loads are loading from
449 /// addresses in the same cache line, it's better if they are scheduled
450 /// together. This function takes two integers that represent the load offsets
451 /// from the common base address. It returns true if it decides it's desirable
452 /// to schedule the two loads together. "NumLoads" is the number of loads that
453 /// have already been scheduled after Load1.
454 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
455 int64_t Offset2,
456 unsigned NumLoads) const override;
457
458 MCInst getNop() const override;
459
460 bool
462
463 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
464 /// instruction that defines the specified register class.
465 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
466
467 /// True if MI has a condition code def, e.g. EFLAGS, that is
468 /// not marked dead.
470
471 /// getGlobalBaseReg - Return a virtual register initialized with the
472 /// the global base register value. Output instructions required to
473 /// initialize the register in the function entry block, if necessary.
474 ///
475 unsigned getGlobalBaseReg(MachineFunction *MF) const;
476
477 std::pair<uint16_t, uint16_t>
478 getExecutionDomain(const MachineInstr &MI) const override;
479
481
482 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
483
484 bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
485
486 unsigned
487 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
488 const TargetRegisterInfo *TRI) const override;
489 unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
490 const TargetRegisterInfo *TRI) const override;
491 void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
492 const TargetRegisterInfo *TRI) const override;
493
495 unsigned OpNum,
498 unsigned Size, Align Alignment,
499 bool AllowCommute) const;
500
501 bool isHighLatencyDef(int opc) const override;
502
503 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
505 const MachineInstr &DefMI, unsigned DefIdx,
506 const MachineInstr &UseMI,
507 unsigned UseIdx) const override;
508
509 bool useMachineCombiner() const override { return true; }
510
512 bool Invert) const override;
513
514 bool hasReassociableOperands(const MachineInstr &Inst,
515 const MachineBasicBlock *MBB) const override;
516
517 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
518 MachineInstr &NewMI1,
519 MachineInstr &NewMI2) const override;
520
521 /// analyzeCompare - For a comparison instruction, return the source registers
522 /// in SrcReg and SrcReg2 if having two register operands, and the value it
523 /// compares against in CmpValue. Return true if the comparison instruction
524 /// can be analyzed.
525 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
526 Register &SrcReg2, int64_t &CmpMask,
527 int64_t &CmpValue) const override;
528
529 /// optimizeCompareInstr - Check if there exists an earlier instruction that
530 /// operates on the same source operands and sets flags in the same way as
531 /// Compare; remove Compare if possible.
532 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
533 Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
534 const MachineRegisterInfo *MRI) const override;
535
536 /// optimizeLoadInstr - Try to remove the load by folding it to a register
537 /// operand at the use. We fold the load instructions if and only if the
538 /// def and use are in the same BB. We only look at one load and see
539 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
540 /// defined by the load we are trying to fold. DefMI returns the machine
541 /// instruction that defines FoldAsLoadDefReg, and the function returns
542 /// the machine instruction generated due to folding.
545 Register &FoldAsLoadDefReg,
546 MachineInstr *&DefMI) const override;
547
548 std::pair<unsigned, unsigned>
549 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
550
553
555 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
556
558 bool OutlineFromLinkOnceODRs) const override;
559
561 getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
562
564 const outliner::OutlinedFunction &OF) const override;
565
569 outliner::Candidate &C) const override;
570
572 StringRef &ErrInfo) const override;
573#define GET_INSTRINFO_HELPER_DECLS
574#include "X86GenInstrInfo.inc"
575
576 static bool hasLockPrefix(const MachineInstr &MI) {
577 return MI.getDesc().TSFlags & X86II::LOCK;
578 }
579
580 std::optional<ParamLoadedValue>
581 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
582
583protected:
584 /// Commutes the operands in the given instruction by changing the operands
585 /// order and/or changing the instruction's opcode and/or the immediate value
586 /// operand.
587 ///
588 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
589 /// to be commuted.
590 ///
591 /// Do not call this method for a non-commutable instruction or
592 /// non-commutable operands.
593 /// Even though the instruction is commutable, the method may still
594 /// fail to commute the operands, null pointer is returned in such cases.
596 unsigned CommuteOpIdx1,
597 unsigned CommuteOpIdx2) const override;
598
599 /// If the specific machine instruction is a instruction that moves/copies
600 /// value from one register to another register return destination and source
601 /// registers as machine operands.
602 std::optional<DestSourcePair>
603 isCopyInstrImpl(const MachineInstr &MI) const override;
604
605private:
606 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
607 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
608 /// super-register and then truncating back down to a 8/16-bit sub-register.
609 MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI,
610 LiveVariables *LV,
611 LiveIntervals *LIS,
612 bool Is8BitOp) const;
613
614 /// Handles memory folding for special case instructions, for instance those
615 /// requiring custom manipulation of the address.
616 MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
617 unsigned OpNum,
620 unsigned Size, Align Alignment) const;
621
622 /// isFrameOperand - Return true and the FrameIndex if the specified
623 /// operand and follow operands form a reference to the stack frame.
624 bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
625 int &FrameIndex) const;
626
627 /// Returns true iff the routine could find two commutable operands in the
628 /// given machine instruction with 3 vector inputs.
629 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
630 /// input values can be re-defined in this method only if the input values
631 /// are not pre-defined, which is designated by the special value
632 /// 'CommuteAnyOperandIndex' assigned to it.
633 /// If both of indices are pre-defined and refer to some operands, then the
634 /// method simply returns true if the corresponding operands are commutable
635 /// and returns false otherwise.
636 ///
637 /// For example, calling this method this way:
638 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
639 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
640 /// can be interpreted as a query asking to find an operand that would be
641 /// commutable with the operand#1.
642 ///
643 /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
644 bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
645 unsigned &SrcOpIdx1,
646 unsigned &SrcOpIdx2,
647 bool IsIntrinsic = false) const;
648
649 /// Returns true when instruction \p FlagI produces the same flags as \p OI.
650 /// The caller should pass in the results of calling analyzeCompare on \p OI:
651 /// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue.
652 /// If the flags match \p OI as if it had the input operands swapped then the
653 /// function succeeds and sets \p IsSwapped to true.
654 ///
655 /// Examples of OI, FlagI pairs returning true:
656 /// CMP %1, 42 and CMP %1, 42
657 /// CMP %1, %2 and %3 = SUB %1, %2
658 /// TEST %1, %1 and %2 = SUB %1, 0
659 /// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true
660 bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg,
661 Register SrcReg2, int64_t ImmMask, int64_t ImmValue,
662 const MachineInstr &OI, bool *IsSwapped,
663 int64_t *ImmDelta) const;
664};
665
666} // namespace llvm
667
668#endif
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
SmallVector< MachineOperand, 4 > Cond
uint64_t Size
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
unsigned Reg
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:718
A debug info location.
Definition: DebugLoc.h:33
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:577
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override
optimizeCompareInstr - Check if there exists an earlier instruction that operates on the same source ...
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
isSchedulingBoundary - Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo....
MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const override
unsigned getGlobalBaseReg(MachineFunction *MF) const
getGlobalBaseReg - Return a virtual register initialized with the the global base register value.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool canInsertSelect(const MachineBasicBlock &, ArrayRef< MachineOperand > Cond, Register, Register, Register, int &, int &, int &) const override
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store ar...
bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
Returns true iff the routine could find two commutable operands in the given machine instruction.
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are lo...
unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
static bool isDataInvariantLoad(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value l...
MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned CommuteOpIdx1, unsigned CommuteOpIdx2) const override
Commutes the operands in the given instruction by changing the operands order and/or changing the ins...
bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
const X86RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
Definition: X86InstrInfo.h:157
bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override
bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override
Returns true if we have preference on the operands order in MI, the commute decision is returned in C...
bool hasLiveCondCodeDef(MachineInstr &MI) const
True if MI has a condition code def, e.g.
std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const override
bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const override
bool getMemOperandsWithOffsetWidth(const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const override
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const override
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override
MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_AD...
static bool hasLockPrefix(const MachineInstr &MI)
Definition: X86InstrInfo.h:576
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override
bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert) const override
MCInst getNop() const override
Return the noop instruction to use for a noop.
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction w...
bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
foldMemoryOperand - If this target supports it, fold a load or store of the specified stack slot into...
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if h...
bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const override
std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const override
bool isUnconditionalTailCall(const MachineInstr &MI) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override
bool useMachineCombiner() const override
Definition: X86InstrInfo.h:509
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const
int getSPAdjust(const MachineInstr &MI) const override
getSPAdjust - This returns the stack pointer adjustment made by this instruction.
bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const override
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const override
This is an architecture-specific helper function of reassociateOps.
void setFrameAdjustment(MachineInstr &I, int64_t V) const
Sets the stack pointer adjustment made inside the frame made up by this instruction.
Definition: X86InstrInfo.h:170
std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const override
bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction.
void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Opc, Register Reg, int FrameIdx, bool isKill=false) const
bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, Register &NewSrc, bool &isKill, MachineOperand &ImplicitOp, LiveVariables *LV, LiveIntervals *LIS) const
Given an operand within a MachineInstr, insert preceding code to put it into the right format for a p...
bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
bool analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify=false) const override
static bool isDataInvariant(MachineInstr &MI)
Returns true if the instruction has no behavior (specified or otherwise) that is based on the value o...
unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before certain undef register...
void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const override
int64_t getFrameAdjustment(const MachineInstr &I) const
Returns the stack pointer adjustment that happens inside the frame setup..destroy sequence (e....
Definition: X86InstrInfo.h:161
bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const override
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override
isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the sp...
bool isSubregFoldable() const override
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: X86InstrInfo.h:387
outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override
uint16_t getExecutionDomainCustom(const MachineInstr &MI) const
bool isHighLatencyDef(int opc) const override
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
unsigned getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2, const X86InstrFMA3Group &FMA3Group) const
Returns an adjusted FMA opcode that must be used in FMA instruction that performs the same computatio...
bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const override
unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override
Inform the BreakFalseDeps pass how many idle instructions we would like before a partial register upd...
MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const override
optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use.
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1428
@ MO_GOTPCREL_NORELAX
MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL relocations are guaranteed to...
Definition: X86BaseInfo.h:447
@ MO_GOTOFF
MO_GOTOFF - On a symbol operand this indicates that the immediate is the offset to the location of th...
Definition: X86BaseInfo.h:434
@ MO_DARWIN_NONLAZY_PIC_BASE
MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates that the reference is actually...
Definition: X86BaseInfo.h:547
@ MO_COFFSTUB
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "....
Definition: X86BaseInfo.h:575
@ MO_DARWIN_NONLAZY
MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the reference is actually to the "...
Definition: X86BaseInfo.h:542
@ MO_GOT
MO_GOT - On a symbol operand this indicates that the immediate is the offset to the GOT entry for the...
Definition: X86BaseInfo.h:427
@ MO_TLVP
MO_TLVP - On a symbol operand this indicates that the immediate is some TLS offset.
Definition: X86BaseInfo.h:553
@ MO_DLLIMPORT
MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the reference is actually to the "__imp...
Definition: X86BaseInfo.h:537
@ MO_PIC_BASE_OFFSET
MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the immediate should get the value of th...
Definition: X86BaseInfo.h:420
@ MO_GOTPCREL
MO_GOTPCREL - On a symbol operand this indicates that the immediate is offset to the GOT entry for th...
Definition: X86BaseInfo.h:442
CondCode getCondFromBranch(const MachineInstr &MI)
CondCode getCondFromMI(const MachineInstr &MI)
Return the condition code of the instruction.
unsigned getSwappedVCMPImm(unsigned Imm)
Get the VCMP immediate if the opcodes are swapped.
CondCode GetOppositeBranchCondition(CondCode CC)
GetOppositeBranchCondition - Return the inverse of the specified cond, e.g.
unsigned getSwappedVPCOMImm(unsigned Imm)
Get the VPCOM immediate if the opcodes are swapped.
bool isX87Instruction(MachineInstr &MI)
Check if the instruction is X87 instruction.
unsigned getVPCMPImmForCond(ISD::CondCode CC)
Get the VPCMP immediate for the given condition.
std::pair< CondCode, bool > getX86ConditionCode(CmpInst::Predicate Predicate)
Return a pair of condition code for the given predicate and whether the instruction operands should b...
CondCode getCondFromSETCC(const MachineInstr &MI)
unsigned getSwappedVPCMPImm(unsigned Imm)
Get the VPCMP immediate if the opcodes are swapped.
int getCondSrcNoFromDesc(const MCInstrDesc &MCID)
Return the source operand # for condition code by MCID.
unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand=false)
Return a cmov opcode for the given register size in bytes, and operand type.
@ AddrScaleAmt
Definition: X86BaseInfo.h:33
@ AddrSegmentReg
AddrSegmentReg - The operand # of the segment in the memory operand.
Definition: X86BaseInfo.h:38
@ AddrIndexReg
Definition: X86BaseInfo.h:34
@ AddrNumOperands
AddrNumOperands - Total number of operands in a memory reference.
Definition: X86BaseInfo.h:41
CondCode getCondFromCMov(const MachineInstr &MI)
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static bool isGlobalStubReference(unsigned char TargetFlag)
isGlobalStubReference - Return true if the specified TargetFlag operand is a reference to a stub for ...
Definition: X86InstrInfo.h:82
@ Offset
Definition: DWP.cpp:406
static bool isGlobalRelativeToPICBase(unsigned char TargetFlag)
isGlobalRelativeToPICBase - Return true if the specified global value reference is relative to a 32-b...
Definition: X86InstrInfo.h:100
static bool isMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:131
static bool isScale(const MachineOperand &MO)
Definition: X86InstrInfo.h:113
static bool isLeaMem(const MachineInstr &MI, unsigned Op)
Definition: X86InstrInfo.h:118
#define N
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Represents a predicate at the MachineFunction level.
This class is used to group {132, 213, 231} forms of FMA opcodes together.
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.