13#ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
14#define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
27class MachineRegisterInfo;
38 bool IsHazardRecognizerMode;
44 std::list<MachineInstr*> EmittedInstrs;
50 bool RunLdsBranchVmemWARHazardFixup;
77 int getWaitStatesSince(
IsHazardFn IsHazard,
int Limit);
78 int getWaitStatesSinceDef(
unsigned Reg,
IsHazardFn IsHazardDef,
int Limit);
79 int getWaitStatesSinceSetReg(
IsHazardFn IsHazard,
int Limit);
147 void Reset()
override;
unsigned const MachineRegisterInfo * MRI
This file implements the BitVector class.
void EmitNoop() override
EmitNoop - This callback is invoked when a noop was added to the instruction stream.
void Reset() override
Reset - This callback is invoked when a new block of instructions is about to be schedule.
unsigned PreEmitNoops(MachineInstr *) override
This overload will be used when the hazard recognizer is being used by a non-scheduling pass,...
void EmitInstruction(SUnit *SU) override
EmitInstruction - This callback is invoked when an instruction is emitted, to advance the hazard stat...
function_ref< bool(const MachineInstr &)> IsHazardFn
void AdvanceCycle() override
AdvanceCycle - This callback is invoked whenever the next top-down instruction to be scheduled cannot...
unsigned PreEmitNoopsCommon(MachineInstr *)
bool ShouldPreferAnother(SUnit *SU) override
ShouldPreferAnother - This callback may be invoked if getHazardType returns NoHazard.
HazardType getHazardType(SUnit *SU, int Stalls) override
getHazardType - Return the hazard type of emitting this node.
void RecedeCycle() override
RecedeCycle - This callback is invoked whenever the next bottom-up instruction to be scheduled cannot...
bool atIssueLimit() const override
atIssueLimit - Return true if no more instructions may be issued in this cycle.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Scheduling unit. This is a node in the scheduling DAG.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Provide an instruction scheduling machine model to CodeGen passes.
An efficient, type-erasing, non-owning reference to a callable.
This is an optimization pass for GlobalISel generic memory operations.