LLVM 19.0.0git
LiveIntervalCalc.cpp
Go to the documentation of this file.
1//===- LiveIntervalCalc.cpp - Calculate live interval --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implementation of the LiveIntervalCalc class.
10//
11//===----------------------------------------------------------------------===//
12
21#include "llvm/MC/LaneBitmask.h"
23#include <cassert>
24
25using namespace llvm;
26
27#define DEBUG_TYPE "regalloc"
28
29// Reserve an address that indicates a value that is known to be "undef".
30static VNInfo UndefVNI(0xbad, SlotIndex());
31
32static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc,
33 LiveRange &LR, const MachineOperand &MO) {
34 const MachineInstr &MI = *MO.getParent();
35 SlotIndex DefIdx =
37
38 // Create the def in LR. This may find an existing def.
39 LR.createDeadDef(DefIdx, Alloc);
40}
41
42void LiveIntervalCalc::calculate(LiveInterval &LI, bool TrackSubRegs) {
44 SlotIndexes *Indexes = getIndexes();
46
47 assert(MRI && Indexes && "call reset() first");
48
49 // Step 1: Create minimal live segments for every definition of Reg.
50 // Visit all def operands. If the same instruction has multiple defs of Reg,
51 // createDeadDef() will deduplicate.
52 const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
53 Register Reg = LI.reg();
54 for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
55 if (!MO.isDef() && !MO.readsReg())
56 continue;
57
58 unsigned SubReg = MO.getSubReg();
59 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) {
60 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
61 : MRI->getMaxLaneMaskForVReg(Reg);
62 // If this is the first time we see a subregister def, initialize
63 // subranges by creating a copy of the main range.
64 if (!LI.hasSubRanges() && !LI.empty()) {
65 LaneBitmask ClassMask = MRI->getMaxLaneMaskForVReg(Reg);
66 LI.createSubRangeFrom(*Alloc, ClassMask, LI);
67 }
68
70 *Alloc, SubMask,
71 [&MO, Indexes, Alloc](LiveInterval::SubRange &SR) {
72 if (MO.isDef())
73 createDeadDef(*Indexes, *Alloc, SR, MO);
74 },
75 *Indexes, TRI);
76 }
77
78 // Create the def in the main liverange. We do not have to do this if
79 // subranges are tracked as we recreate the main range later in this case.
80 if (MO.isDef() && !LI.hasSubRanges())
81 createDeadDef(*Indexes, *Alloc, LI, MO);
82 }
83
84 // We may have created empty live ranges for partially undefined uses, we
85 // can't keep them because we won't find defs in them later.
87
90 // Step 2: Extend live segments to all uses, constructing SSA form as
91 // necessary.
92 if (LI.hasSubRanges()) {
93 for (LiveInterval::SubRange &S : LI.subranges()) {
94 LiveIntervalCalc SubLIC;
95 SubLIC.reset(MF, Indexes, DomTree, Alloc);
96 SubLIC.extendToUses(S, Reg, S.LaneMask, &LI);
97 }
98 LI.clear();
100 } else {
102 extendToUses(LI, Reg, LaneBitmask::getAll());
103 }
104}
105
107 // First create dead defs at all defs found in subranges.
108 LiveRange &MainRange = LI;
109 assert(MainRange.segments.empty() && MainRange.valnos.empty() &&
110 "Expect empty main liverange");
111
112 VNInfo::Allocator *Alloc = getVNAlloc();
113 for (const LiveInterval::SubRange &SR : LI.subranges()) {
114 for (const VNInfo *VNI : SR.valnos) {
115 if (!VNI->isUnused() && !VNI->isPHIDef())
116 MainRange.createDeadDef(VNI->def, *Alloc);
117 }
118 }
120 extendToUses(MainRange, LI.reg(), LaneBitmask::getAll(), &LI);
121}
122
125 SlotIndexes *Indexes = getIndexes();
126 VNInfo::Allocator *Alloc = getVNAlloc();
127 assert(MRI && Indexes && "call reset() first");
128
129 // Visit all def operands. If the same instruction has multiple defs of Reg,
130 // LR.createDeadDef() will deduplicate.
131 for (MachineOperand &MO : MRI->def_operands(Reg))
132 createDeadDef(*Indexes, *Alloc, LR, MO);
133}
134
135void LiveIntervalCalc::extendToUses(LiveRange &LR, Register Reg,
136 LaneBitmask Mask, LiveInterval *LI) {
138 SlotIndexes *Indexes = getIndexes();
140 if (LI != nullptr)
141 LI->computeSubRangeUndefs(Undefs, Mask, *MRI, *Indexes);
142
143 // Visit all operands that read Reg. This may include partial defs.
144 bool IsSubRange = !Mask.all();
145 const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
146 for (MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
147 // Clear all kill flags. They will be reinserted after register allocation
148 // by LiveIntervals::addKillFlags().
149 if (MO.isUse())
150 MO.setIsKill(false);
151 // MO::readsReg returns "true" for subregister defs. This is for keeping
152 // liveness of the entire register (i.e. for the main range of the live
153 // interval). For subranges, definitions of non-overlapping subregisters
154 // do not count as uses.
155 if (!MO.readsReg() || (IsSubRange && MO.isDef()))
156 continue;
157
158 unsigned SubReg = MO.getSubReg();
159 if (SubReg != 0) {
160 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg);
161 if (MO.isDef())
162 SLM = ~SLM;
163 // Ignore uses not reading the current (sub)range.
164 if ((SLM & Mask).none())
165 continue;
166 }
167
168 // Determine the actual place of the use.
169 const MachineInstr *MI = MO.getParent();
170 unsigned OpNo = (&MO - &MI->getOperand(0));
171 SlotIndex UseIdx;
172 if (MI->isPHI()) {
173 assert(!MO.isDef() && "Cannot handle PHI def of partial register.");
174 // The actual place where a phi operand is used is the end of the pred
175 // MBB. PHI operands are paired: (Reg, PredMBB).
176 UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo + 1).getMBB());
177 } else {
178 // Check for early-clobber redefs.
179 bool isEarlyClobber = false;
180 unsigned DefIdx;
181 if (MO.isDef())
182 isEarlyClobber = MO.isEarlyClobber();
183 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
184 // FIXME: This would be a lot easier if tied early-clobber uses also
185 // had an early-clobber flag.
186 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
187 }
188 UseIdx = Indexes->getInstructionIndex(*MI).getRegSlot(isEarlyClobber);
189 }
190
191 // MI is reading Reg. We may have visited MI before if it happens to be
192 // reading Reg multiple times. That is OK, extend() is idempotent.
193 extend(LR, UseIdx, Reg, Undefs);
194 }
195}
unsigned SubReg
unsigned const MachineRegisterInfo * MRI
IRTranslator LLVM IR MI
A common definition of LaneBitmask for use in TableGen and CodeGen.
static VNInfo UndefVNI(0xbad, SlotIndex())
static void createDeadDef(SlotIndexes &Indexes, VNInfo::Allocator &Alloc, LiveRange &LR, const MachineOperand &MO)
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
void createDeadDefs(LiveRange &LR, Register Reg)
createDeadDefs - Create a dead def in LI for every def operand of Reg.
void calculate(LiveInterval &LI, bool TrackSubRegs)
Calculates liveness for the register specified in live interval LI.
void constructMainRangeFromSubranges(LiveInterval &LI)
For live interval LI with correct SubRanges construct matching information for the main live range.
A live range for subregisters.
Definition: LiveInterval.h:694
LiveInterval - This class represents the liveness of a register, or stack slot.
Definition: LiveInterval.h:687
void removeEmptySubRanges()
Removes all subranges without any segments (subranges without segments are not considered valid and s...
Register reg() const
Definition: LiveInterval.h:718
bool hasSubRanges() const
Returns true if subregister liveness information is available.
Definition: LiveInterval.h:810
SubRange * createSubRangeFrom(BumpPtrAllocator &Allocator, LaneBitmask LaneMask, const LiveRange &CopyFrom)
Like createSubRange() but the new range is filled with a copy of the liveness information in CopyFrom...
Definition: LiveInterval.h:801
iterator_range< subrange_iterator > subranges()
Definition: LiveInterval.h:782
void refineSubRanges(BumpPtrAllocator &Allocator, LaneBitmask LaneMask, std::function< void(LiveInterval::SubRange &)> Apply, const SlotIndexes &Indexes, const TargetRegisterInfo &TRI, unsigned ComposeSubRegIdx=0)
Refines the subranges to support LaneMask.
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
SlotIndexes * getIndexes()
MachineDominatorTree * getDomTree()
void resetLiveOutMap()
Reset Map and Seen fields.
VNInfo::Allocator * getVNAlloc()
void reset(const MachineFunction *mf, SlotIndexes *SI, MachineDominatorTree *MDT, VNInfo::Allocator *VNIA)
reset - Prepare caches for a new set of non-overlapping live ranges.
const MachineFunction * getMachineFunction()
Some getters to expose in a read-only way some private fields to subclasses.
const MachineRegisterInfo * getRegInfo() const
void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg, ArrayRef< SlotIndex > Undefs)
Extend the live range of LR to reach Use.
This class represents the liveness of a register, stack slot, etc.
Definition: LiveInterval.h:157
VNInfo * createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc)
createDeadDef - Make sure the range has a value defined at Def.
bool empty() const
Definition: LiveInterval.h:382
Segments segments
Definition: LiveInterval.h:203
VNInfoList valnos
Definition: LiveInterval.h:204
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
bool isEarlyClobber() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
SlotIndex - An opaque wrapper around machine indexes.
Definition: SlotIndexes.h:68
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
Definition: SlotIndexes.h:240
SlotIndexes pass.
Definition: SlotIndexes.h:300
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
Definition: SlotIndexes.h:462
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
Definition: SlotIndexes.h:371
bool empty() const
Definition: SmallVector.h:94
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
VNInfo - Value Number Information.
Definition: LiveInterval.h:53
bool isUnused() const
Returns true if this value is unused.
Definition: LiveInterval.h:81
SlotIndex def
The index of the defining instruction.
Definition: LiveInterval.h:61
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
Definition: LiveInterval.h:78
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
static constexpr LaneBitmask getAll()
Definition: LaneBitmask.h:82