22#define DEBUG_TYPE "loongarch-isel"
23#define PASS_NAME "LoongArch DAG->DAG Pattern Instruction Selection"
31 if (Node->isMachineOpcode()) {
39 unsigned Opcode = Node->getOpcode();
40 MVT GRLenVT = Subtarget->getGRLenVT();
42 MVT VT = Node->getSimpleValueType(0);
48 int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();
49 if (Imm == 0 && VT == GRLenVT) {
50 SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
DL,
51 LoongArch::R0, GRLenVT);
52 ReplaceNode(Node, New.getNode());
56 SDValue SrcReg = CurDAG->getRegister(LoongArch::R0, GRLenVT);
59 SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm,
DL, GRLenVT);
60 if (Inst.Opc == LoongArch::LU12I_W)
61 Result = CurDAG->getMachineNode(LoongArch::LU12I_W,
DL, GRLenVT, SDImm);
63 Result = CurDAG->getMachineNode(Inst.Opc,
DL, GRLenVT, SrcReg, SDImm);
67 ReplaceNode(Node, Result);
71 SDValue Imm = CurDAG->getTargetConstant(0,
DL, GRLenVT);
72 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
73 SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
75 Subtarget->is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
76 ReplaceNode(Node, CurDAG->getMachineNode(ADDIOp,
DL, VT, TFI, Imm));
81 ReplaceUses(
SDValue(Node, 0), Node->getOperand(0));
82 CurDAG->RemoveDeadNode(Node);
95 std::vector<SDValue> &OutOps) {
99 switch (ConstraintID) {
134 OutOps.push_back(
Base);
142 if (
auto *FIN = dyn_cast<FrameIndexSDNode>(
Addr))
154 MVT VT =
Addr.getSimpleValueType();
156 if (!isa<ConstantSDNode>(
Addr))
161 int64_t CVal = cast<ConstantSDNode>(
Addr)->getSExtValue();
162 if (!isInt<12>(CVal))
171 if (isa<FrameIndexSDNode>(
Addr))
182 if (
N.getOpcode() ==
ISD::AND && isa<ConstantSDNode>(
N.getOperand(1))) {
183 const APInt &AndMask =
N->getConstantOperandAPInt(1);
191 ShAmt =
N.getOperand(0);
199 ShAmt =
N.getOperand(0);
206 assert(isa<ConstantSDNode>(
N.getOperand(1)) &&
"Illegal msb operand!");
207 assert(isa<ConstantSDNode>(
N.getOperand(2)) &&
"Illegal lsb operand!");
208 uint64_t msb =
N.getConstantOperandVal(1), lsb =
N.getConstantOperandVal(2);
209 if (lsb == 0 &&
Log2_32(ShiftWidth) <= msb + 1) {
210 ShAmt =
N.getOperand(0);
214 isa<ConstantSDNode>(
N.getOperand(0))) {
215 uint64_t Imm =
N.getConstantOperandVal(0);
218 if (Imm != 0 && Imm % ShiftWidth == 0) {
220 EVT VT =
N.getValueType();
223 unsigned NegOpc = VT == MVT::i64 ? LoongArch::SUB_D : LoongArch::SUB_W;
237 cast<VTSDNode>(
N.getOperand(1))->getVT() == MVT::i32) {
238 Val =
N.getOperand(0);
242 N.getConstantOperandVal(1) < UINT64_C(0X1F) &&
243 N.getConstantOperandVal(2) == UINT64_C(0)) {
247 MVT VT =
N.getSimpleValueType();
258 auto *
C = dyn_cast<ConstantSDNode>(
N.getOperand(1));
259 if (
C &&
C->getZExtValue() == UINT64_C(0xFFFFFFFF)) {
260 Val =
N.getOperand(0);
264 MVT VT =
N.getSimpleValueType();
275 unsigned MinSizeInBits)
const {
284 APInt SplatValue, SplatUndef;
285 unsigned SplatBitSize;
288 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
289 MinSizeInBits,
false))
297template <
unsigned ImmBitSize,
bool IsSigned>
300 EVT EltTy =
N->getValueType(0).getVectorElementType();
303 N =
N->getOperand(0);
312 if (!IsSigned && ImmValue.
isIntN(ImmBitSize)) {
325 EVT EltTy =
N->getValueType(0).getVectorElementType();
328 N =
N->getOperand(0);
332 int32_t
Log2 = (~ImmValue).exactLogBase2();
346 EVT EltTy =
N->getValueType(0).getVectorElementType();
349 N =
N->getOperand(0);
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu AMDGPU Register Bank Select
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Class for arbitrary precision integers.
uint64_t getZExtValue() const
Get zero extended value.
unsigned getBitWidth() const
Return the number of bits in the APInt.
int32_t exactLogBase2() const
bool isSignedIntN(unsigned N) const
Check if this APInt has an N-bits signed integer value.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
bool isIntN(unsigned N) const
Check if this APInt has an N-bits unsigned integer value.
int64_t getSExtValue() const
Get sign extended value.
A "pseudo-class" with methods for operating on BUILD_VECTORs.
uint64_t getZExtValue() const
int64_t getSExtValue() const
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
bool selectNonFIBaseAddr(SDValue Addr, SDValue &Base)
bool selectSExti32(SDValue N, SDValue &Val)
bool SelectInlineAsmMemoryOperand(const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode,...
bool selectVSplatUimmPow2(SDValue N, SDValue &SplatImm) const
bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt)
bool selectZExti32(SDValue N, SDValue &Val)
bool SelectAddrConstant(SDValue Addr, SDValue &Base, SDValue &Offset)
bool selectVSplat(SDNode *N, APInt &Imm, unsigned MinSizeInBits) const
bool selectVSplatImm(SDValue N, SDValue &SplatVal)
bool selectVSplatUimmInvPow2(SDValue N, SDValue &SplatImm) const
bool SelectBaseAddr(SDValue Addr, SDValue &Base)
bool is128BitVector() const
Return true if this is a 128-bit vector type.
bool is512BitVector() const
Return true if this is a 512-bit vector type.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
An SDNode that represents everything that will be needed to construct a MachineInstr.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getTargetFrameIndex(int FI, EVT VT)
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side,...
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ C
The default llvm calling convention, compatible with C.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ AND
Bitwise operators - logical and, logical or, logical xor.
InstSeq generateInstSeq(int64_t Val)
This is an optimization pass for GlobalISel generic memory operations.
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
FunctionPass * createLoongArchISelDag(LoongArchTargetMachine &TM)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
DWARFExpression::Operation Op
unsigned Log2(Align A)
Returns the log2 of the alignment.
This struct is a compact representation of a valid (non-zero power of two) alignment.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.