LLVM  17.0.0git
LoongArchISelLowering.h
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1 //=- LoongArchISelLowering.h - LoongArch DAG Lowering Interface -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that LoongArch uses to lower LLVM code into
10 // a selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H
15 #define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H
16 
17 #include "LoongArch.h"
21 
22 namespace llvm {
23 class LoongArchSubtarget;
24 struct LoongArchRegisterInfo;
25 namespace LoongArchISD {
26 enum NodeType : unsigned {
28 
29  // TODO: add more LoongArchISDs
31  RET,
33 
34  // 32-bit shifts, directly matching the semantics of the named LoongArch
35  // instructions.
39 
42 
43  // FPR<->GPR transfer operations
48 
50 
51  // Bit counting operations
54 
57 
58  // Byte-swapping and bit-reversal
63 
64  // Intrinsic operations start ============================================
71 
72  // CRC check operations
81 
85 
86  // IOCSR access operations
95 
96  // Read CPU configuration information operation
98  // Intrinsic operations end =============================================
99 };
100 } // end namespace LoongArchISD
101 
103  const LoongArchSubtarget &Subtarget;
104 
105 public:
106  explicit LoongArchTargetLowering(const TargetMachine &TM,
107  const LoongArchSubtarget &STI);
108 
109  const LoongArchSubtarget &getSubtarget() const { return Subtarget; }
110 
111  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
112 
113  // Provide custom lowering hooks for some operations.
114  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
116  SelectionDAG &DAG) const override;
117 
118  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
119 
120  // This method returns the name of a target specific DAG node.
121  const char *getTargetNodeName(unsigned Opcode) const override;
122 
123  // Lower incoming arguments, copy physregs into vregs.
125  bool IsVarArg,
127  const SDLoc &DL, SelectionDAG &DAG,
128  SmallVectorImpl<SDValue> &InVals) const override;
130  bool IsVarArg,
132  LLVMContext &Context) const override;
133  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
135  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
136  SelectionDAG &DAG) const override;
138  SmallVectorImpl<SDValue> &InVals) const override;
139  bool isCheapToSpeculateCttz(Type *Ty) const override;
140  bool isCheapToSpeculateCtlz(Type *Ty) const override;
141  bool hasAndNot(SDValue Y) const override;
143  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
144 
146  Value *AlignedAddr, Value *Incr,
147  Value *Mask, Value *ShiftAmt,
148  AtomicOrdering Ord) const override;
149 
151  EVT VT) const override;
155  AtomicCmpXchgInst *CI,
156  Value *AlignedAddr, Value *CmpVal,
157  Value *NewVal, Value *Mask,
158  AtomicOrdering Ord) const override;
159 
160  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
161  MachineFunction &MF,
162  unsigned Intrinsic) const override;
163 
165  EVT VT) const override;
166 
167  Register
168  getExceptionPointerRegister(const Constant *PersonalityFn) const override;
169 
170  Register
171  getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
172 
174  return ISD::SIGN_EXTEND;
175  }
176 
177  Register getRegisterByName(const char *RegName, LLT VT,
178  const MachineFunction &MF) const override;
179  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
180 
182  SDValue C) const override;
183 
184 private:
185  /// Target-specific function used to lower LoongArch calling conventions.
186  typedef bool LoongArchCCAssignFn(const DataLayout &DL, LoongArchABI::ABI ABI,
187  unsigned ValNo, MVT ValVT,
188  CCValAssign::LocInfo LocInfo,
189  ISD::ArgFlagsTy ArgFlags, CCState &State,
190  bool IsFixed, bool IsReg, Type *OrigTy);
191 
192  void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
193  const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
194  LoongArchCCAssignFn Fn) const;
195  void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
197  bool IsRet, CallLoweringInfo *CLI,
198  LoongArchCCAssignFn Fn) const;
199 
200  template <class NodeTy>
201  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
202  SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
203  unsigned Opc) const;
204  SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
205  unsigned Opc) const;
206  SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
207  SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
208  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
209  SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
210  SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
211  SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
212 
214  EmitInstrWithCustomInserter(MachineInstr &MI,
215  MachineBasicBlock *BB) const override;
216  SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
217  SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
218  SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
219  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
220  SDValue lowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
221  SDValue lowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
222  SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
223  SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
224  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
225  SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
226  SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
227  SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
228  SDValue lowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) const;
229 
230  bool isFPImmLegal(const APFloat &Imm, EVT VT,
231  bool ForCodeSize) const override;
232 
233  bool shouldInsertFencesForAtomic(const Instruction *I) const override;
234 
235  ConstraintType getConstraintType(StringRef Constraint) const override;
236 
237  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
238 
239  std::pair<unsigned, const TargetRegisterClass *>
240  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
241  StringRef Constraint, MVT VT) const override;
242 
243  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
244  std::vector<SDValue> &Ops,
245  SelectionDAG &DAG) const override;
246 
247  bool isEligibleForTailCallOptimization(
248  CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
249  const SmallVectorImpl<CCValAssign> &ArgLocs) const;
250 };
251 
252 } // end namespace llvm
253 
254 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H
llvm::LoongArchTargetLowering::LowerOperation
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
Definition: LoongArchISelLowering.cpp:215
llvm::LoongArchISD::SRA_W
@ SRA_W
Definition: LoongArchISelLowering.h:37
ABI
Generic address nodes are lowered to some combination of target independent and machine specific ABI
Definition: Relocation.txt:34
llvm::LoongArchISD::CRC_W_D_W
@ CRC_W_D_W
Definition: LoongArchISelLowering.h:76
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:109
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::LoongArchTargetLowering::getTargetNodeName
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
Definition: LoongArchISelLowering.cpp:1767
llvm::LoongArchISD::CSRWR
@ CSRWR
Definition: LoongArchISelLowering.h:83
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1106
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:114
llvm::LoongArchISD::CSRRD
@ CSRRD
Definition: LoongArchISelLowering.h:82
llvm::TargetLowering::ConstraintType
ConstraintType
Definition: TargetLowering.h:4592
llvm::CCState
CCState - This class holds information needed while lowering arguments and return values.
Definition: CallingConvLower.h:168
llvm::LoongArchISD::SYSCALL
@ SYSCALL
Definition: LoongArchISelLowering.h:70
llvm::LoongArchTargetLowering::mayBeEmittedAsTailCall
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
Definition: LoongArchISelLowering.cpp:2329
llvm::LoongArchISD::MOVGR2FR_W_LA64
@ MOVGR2FR_W_LA64
Definition: LoongArchISelLowering.h:44
llvm::LoongArchTargetLowering::emitMaskedAtomicRMWIntrinsic
Value * emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override
Perform a masked atomicrmw using a target-specific intrinsic.
Definition: LoongArchISelLowering.cpp:2842
llvm::LoongArchTargetLowering::isCheapToSpeculateCtlz
bool isCheapToSpeculateCtlz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Definition: LoongArchISelLowering.cpp:2692
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:463
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
llvm::LoongArchISD::BITREV_W
@ BITREV_W
Definition: LoongArchISelLowering.h:62
llvm::LoongArchISD::CACOP_D
@ CACOP_D
Definition: LoongArchISelLowering.h:66
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::LoongArchISD::FIRST_NUMBER
@ FIRST_NUMBER
Definition: LoongArchISelLowering.h:27
llvm::LoongArchTargetLowering::getRegisterByName
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Definition: LoongArchISelLowering.cpp:3075
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:769
llvm::LoongArchISD::SLL_W
@ SLL_W
Definition: LoongArchISelLowering.h:36
llvm::LoongArchISD::CRCC_W_D_W
@ CRCC_W_D_W
Definition: LoongArchISelLowering.h:80
llvm::LoongArchTargetLowering::LoongArchTargetLowering
LoongArchTargetLowering(const TargetMachine &TM, const LoongArchSubtarget &STI)
Definition: LoongArchISelLowering.cpp:42
llvm::LoongArchISD::CACOP_W
@ CACOP_W
Definition: LoongArchISelLowering.h:67
llvm::LoongArchTargetLowering::getExceptionPointerRegister
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
Definition: LoongArchISelLowering.cpp:2903
llvm::LoongArchISD::CRC_W_H_W
@ CRC_W_H_W
Definition: LoongArchISelLowering.h:74
SelectionDAG.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::LoongArchTargetLowering::shouldExpandAtomicCmpXchgInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
Definition: LoongArchISelLowering.cpp:2814
llvm::LoongArchTargetLowering::getExceptionSelectorRegister
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
Definition: LoongArchISelLowering.cpp:2908
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TargetLowering.h
llvm::LoongArchTargetLowering::hasAndNot
bool hasAndNot(SDValue Y) const override
Return true if the target has a bitwise and-not operation: X = ~A & B This can be used to simplify se...
Definition: LoongArchISelLowering.cpp:2722
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
llvm::LoongArchISD::CRC_W_B_W
@ CRC_W_B_W
Definition: LoongArchISelLowering.h:73
llvm::LoongArchISD::CPUCFG
@ CPUCFG
Definition: LoongArchISelLowering.h:97
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:34
llvm::LoongArchISD::REVB_2H
@ REVB_2H
Definition: LoongArchISelLowering.h:59
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3510
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::LoongArchTargetLowering::ReplaceNodeResults
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Definition: LoongArchISelLowering.cpp:1025
llvm::LoongArchTargetLowering::isCheapToSpeculateCttz
bool isCheapToSpeculateCttz(Type *Ty) const override
Return true if it is cheap to speculate a call to intrinsic cttz.
Definition: LoongArchISelLowering.cpp:2688
llvm::LoongArchTargetLowering::decomposeMulByConstant
bool decomposeMulByConstant(LLVMContext &Context, EVT VT, SDValue C) const override
Return true if it is profitable to transform an integer multiplication-by-constant into simpler opera...
Definition: LoongArchISelLowering.cpp:3092
llvm::ISD::NodeType
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
llvm::Instruction
Definition: Instruction.h:41
llvm::LoongArchISD::IOCSRWR_H
@ IOCSRWR_H
Definition: LoongArchISelLowering.h:92
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::LoongArchISD::FTINT
@ FTINT
Definition: LoongArchISelLowering.h:49
llvm::LoongArchISD::MOVFCSR2GR
@ MOVFCSR2GR
Definition: LoongArchISelLowering.h:46
llvm::LoongArchTargetLowering::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
Definition: LoongArchISelLowering.cpp:2727
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::LoongArchISD::MOVGR2FCSR
@ MOVGR2FCSR
Definition: LoongArchISelLowering.h:47
llvm::LoongArchTargetLowering::LowerCall
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
Definition: LoongArchISelLowering.cpp:2383
llvm::LoongArchTargetLowering::LowerReturn
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
Definition: LoongArchISelLowering.cpp:2636
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::APFloat
Definition: APFloat.h:722
llvm::LoongArchISD::IOCSRWR_D
@ IOCSRWR_D
Definition: LoongArchISelLowering.h:94
llvm::CCValAssign::LocInfo
LocInfo
Definition: CallingConvLower.h:33
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::LoongArchISD::CRCC_W_H_W
@ CRCC_W_H_W
Definition: LoongArchISelLowering.h:78
llvm::LoongArchSubtarget
Definition: LoongArchSubtarget.h:32
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::LoongArchTargetLowering::LowerFormalArguments
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
Definition: LoongArchISelLowering.cpp:2199
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::LoongArchISD::ROTR_W
@ ROTR_W
Definition: LoongArchISelLowering.h:41
llvm::LoongArchISD::ROTL_W
@ ROTL_W
Definition: LoongArchISelLowering.h:40
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:4170
llvm::LoongArchABI::ABI
ABI
Definition: LoongArchBaseInfo.h:47
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
llvm::LoongArchTargetLowering::getSetCCResultType
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
Return the ValueType of the result of SETCC operations.
Definition: LoongArchISelLowering.cpp:2714
llvm::LoongArchTargetLowering::PerformDAGCombine
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
Definition: LoongArchISelLowering.cpp:1663
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::LoongArchISD::CALL
@ CALL
Definition: LoongArchISelLowering.h:30
llvm::LoongArchTargetLowering
Definition: LoongArchISelLowering.h:102
llvm::LoongArchTargetLowering::emitMaskedAtomicCmpXchgIntrinsic
Value * emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const override
Perform a masked cmpxchg using a target-specific intrinsic.
Definition: LoongArchISelLowering.cpp:2822
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:651
llvm::MachineFunction
Definition: MachineFunction.h:258
llvm::LoongArchISD::IBAR
@ IBAR
Definition: LoongArchISelLowering.h:69
LoongArch.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::LoongArchISD::CRCC_W_W_W
@ CRCC_W_W_W
Definition: LoongArchISelLowering.h:79
llvm::LoongArchISD::DBAR
@ DBAR
Definition: LoongArchISelLowering.h:68
llvm::ISD::ArgFlagsTy
Definition: TargetCallingConv.h:27
llvm::IRBuilderBase
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::ISD::BUILTIN_OP_END
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1311
llvm::LoongArchTargetLowering::shouldExpandAtomicRMWInIR
TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
Definition: LoongArchISelLowering.cpp:2751
llvm::LoongArchISD::RET
@ RET
Definition: LoongArchISelLowering.h:31
llvm::AtomicRMWInst
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:718
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::LoongArchTargetLowering::isOffsetFoldingLegal
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
Definition: LoongArchISelLowering.cpp:206
llvm::GlobalAddressSDNode
Definition: SelectionDAGNodes.h:1763
llvm::LoongArchISD::NodeType
NodeType
Definition: LoongArchISelLowering.h:26
llvm::TargetLoweringBase::AtomicExpansionKind
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
Definition: TargetLowering.h:250
CallingConvLower.h
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:354
llvm::LoongArchISD::BSTRPICK
@ BSTRPICK
Definition: LoongArchISelLowering.h:56
llvm::LoongArchISD::CTZ_W
@ CTZ_W
Definition: LoongArchISelLowering.h:53
llvm::LoongArchISD::IOCSRWR_B
@ IOCSRWR_B
Definition: LoongArchISelLowering.h:91
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:145
llvm::LoongArchISD::TAIL
@ TAIL
Definition: LoongArchISelLowering.h:32
llvm::LoongArchISD::SRL_W
@ SRL_W
Definition: LoongArchISelLowering.h:38
llvm::LoongArchISD::BREAK
@ BREAK
Definition: LoongArchISelLowering.h:65
llvm::LoongArchTargetLowering::getSubtarget
const LoongArchSubtarget & getSubtarget() const
Definition: LoongArchISelLowering.h:109
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::LoongArchISD::IOCSRRD_B
@ IOCSRRD_B
Definition: LoongArchISelLowering.h:87
llvm::LoongArchISD::IOCSRRD_W
@ IOCSRRD_W
Definition: LoongArchISelLowering.h:88
llvm::LoongArchISD::CSRXCHG
@ CSRXCHG
Definition: LoongArchISelLowering.h:84
N
#define N
llvm::LoongArchISD::BSTRINS
@ BSTRINS
Definition: LoongArchISelLowering.h:55
llvm::LoongArchISD::CRC_W_W_W
@ CRC_W_W_W
Definition: LoongArchISelLowering.h:75
llvm::LoongArchTargetLowering::getExtendForAtomicOps
ISD::NodeType getExtendForAtomicOps() const override
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
Definition: LoongArchISelLowering.h:173
llvm::LoongArchISD::IOCSRRD_H
@ IOCSRRD_H
Definition: LoongArchISelLowering.h:89
llvm::LoongArchISD::IOCSRRD_D
@ IOCSRRD_D
Definition: LoongArchISelLowering.h:90
llvm::MipsISD::Ins
@ Ins
Definition: MipsISelLowering.h:160
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
RegName
#define RegName(no)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::CallInst
This class represents a function call, abstracting a target machine's calling convention.
Definition: Instructions.h:1485
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::LoongArchISD::CRCC_W_B_W
@ CRCC_W_B_W
Definition: LoongArchISelLowering.h:77
llvm::LoongArchISD::REVB_2W
@ REVB_2W
Definition: LoongArchISelLowering.h:60
llvm::ISD::SIGN_EXTEND
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:760
llvm::LoongArchISD::BITREV_4B
@ BITREV_4B
Definition: LoongArchISelLowering.h:61
llvm::LoongArchISD::IOCSRWR_W
@ IOCSRWR_W
Definition: LoongArchISelLowering.h:93
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AtomicCmpXchgInst
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:513
llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
Definition: LoongArchISelLowering.cpp:2885
llvm::LoongArchISD::MOVFR2GR_S_LA64
@ MOVFR2GR_S_LA64
Definition: LoongArchISelLowering.h:45
llvm::LoongArchTargetLowering::CanLowerReturn
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
Definition: LoongArchISelLowering.cpp:2619
llvm::LLT
Definition: LowLevelTypeImpl.h:39
llvm::LoongArchISD::CLZ_W
@ CLZ_W
Definition: LoongArchISelLowering.h:52