LLVM  17.0.0git
M68kTargetMachine.cpp
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1 //===-- M68kTargetMachine.cpp - M68k Target Machine -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file contains implementation for M68k target machine.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "M68kTargetMachine.h"
15 #include "M68k.h"
16 #include "M68kMachineFunction.h"
17 #include "M68kSubtarget.h"
18 #include "M68kTargetObjectFile.h"
24 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/InitializePasses.h"
28 #include "llvm/MC/TargetRegistry.h"
29 #include "llvm/PassRegistry.h"
30 #include <memory>
31 #include <optional>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "m68k"
36 
39  auto *PR = PassRegistry::getPassRegistry();
42 }
43 
44 namespace {
45 
46 std::string computeDataLayout(const Triple &TT, StringRef CPU,
47  const TargetOptions &Options) {
48  std::string Ret = "";
49  // M68k is Big Endian
50  Ret += "E";
51 
52  // FIXME how to wire it with the used object format?
53  Ret += "-m:e";
54 
55  // M68k pointers are always 32 bit wide even for 16-bit CPUs.
56  // The ABI only specifies 16-bit alignment.
57  // On at least the 68020+ with a 32-bit bus, there is a performance benefit
58  // to having 32-bit alignment.
59  Ret += "-p:32:16:32";
60 
61  // Bytes do not require special alignment, words are word aligned and
62  // long words are word aligned at minimum.
63  Ret += "-i8:8:8-i16:16:16-i32:16:32";
64 
65  // FIXME no floats at the moment
66 
67  // The registers can hold 8, 16, 32 bits
68  Ret += "-n8:16:32";
69 
70  Ret += "-a:0:16-S16";
71 
72  return Ret;
73 }
74 
76  std::optional<Reloc::Model> RM) {
77  // If not defined we default to static
78  if (!RM.has_value())
79  return Reloc::Static;
80 
81  return *RM;
82 }
83 
84 CodeModel::Model getEffectiveCodeModel(std::optional<CodeModel::Model> CM,
85  bool JIT) {
86  if (!CM) {
87  return CodeModel::Small;
88  } else if (CM == CodeModel::Large) {
89  llvm_unreachable("Large code model is not supported");
90  } else if (CM == CodeModel::Kernel) {
91  llvm_unreachable("Kernel code model is not implemented yet");
92  }
93  return CM.value();
94 }
95 } // end anonymous namespace
96 
98  StringRef CPU, StringRef FS,
99  const TargetOptions &Options,
100  std::optional<Reloc::Model> RM,
101  std::optional<CodeModel::Model> CM,
102  CodeGenOpt::Level OL, bool JIT)
103  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS,
105  ::getEffectiveCodeModel(CM, JIT), OL),
106  TLOF(std::make_unique<M68kELFTargetObjectFile>()),
107  Subtarget(TT, CPU, FS, *this) {
108  initAsmInfo();
109 }
110 
112 
113 const M68kSubtarget *
115  Attribute CPUAttr = F.getFnAttribute("target-cpu");
116  Attribute FSAttr = F.getFnAttribute("target-features");
117 
118  auto CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
119  auto FS = FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
120 
121  auto &I = SubtargetMap[CPU + FS];
122  if (!I) {
123  // This needs to be done before we create a new subtarget since any
124  // creation will depend on the TM and the code generation flags on the
125  // function that reside in TargetOptions.
127  I = std::make_unique<M68kSubtarget>(TargetTriple, CPU, FS, *this);
128  }
129  return I.get();
130 }
131 
134  const TargetSubtargetInfo *STI) const {
135  return M68kMachineFunctionInfo::create<M68kMachineFunctionInfo>(Allocator, F,
136  STI);
137 }
138 
139 //===----------------------------------------------------------------------===//
140 // Pass Pipeline Configuration
141 //===----------------------------------------------------------------------===//
142 
143 namespace {
144 class M68kPassConfig : public TargetPassConfig {
145 public:
146  M68kPassConfig(M68kTargetMachine &TM, PassManagerBase &PM)
147  : TargetPassConfig(TM, PM) {}
148 
149  M68kTargetMachine &getM68kTargetMachine() const {
150  return getTM<M68kTargetMachine>();
151  }
152 
153  const M68kSubtarget &getM68kSubtarget() const {
154  return *getM68kTargetMachine().getSubtargetImpl();
155  }
156  void addIRPasses() override;
157  bool addIRTranslator() override;
158  bool addLegalizeMachineIR() override;
159  bool addRegBankSelect() override;
160  bool addGlobalInstructionSelect() override;
161  bool addInstSelector() override;
162  void addPreSched2() override;
163  void addPreEmitPass() override;
164 };
165 } // namespace
166 
168  return new M68kPassConfig(*this, PM);
169 }
170 
171 void M68kPassConfig::addIRPasses() {
172  addPass(createAtomicExpandPass());
174 }
175 
176 bool M68kPassConfig::addInstSelector() {
177  // Install an instruction selector.
178  addPass(createM68kISelDag(getM68kTargetMachine()));
179  addPass(createM68kGlobalBaseRegPass());
180  return false;
181 }
182 
183 bool M68kPassConfig::addIRTranslator() {
184  addPass(new IRTranslator());
185  return false;
186 }
187 
188 bool M68kPassConfig::addLegalizeMachineIR() {
189  addPass(new Legalizer());
190  return false;
191 }
192 
193 bool M68kPassConfig::addRegBankSelect() {
194  addPass(new RegBankSelect());
195  return false;
196 }
197 
198 bool M68kPassConfig::addGlobalInstructionSelect() {
199  addPass(new InstructionSelect());
200  return false;
201 }
202 
203 void M68kPassConfig::addPreSched2() { addPass(createM68kExpandPseudoPass()); }
204 
205 void M68kPassConfig::addPreEmitPass() {
206  addPass(createM68kCollapseMOVEMPass());
207 }
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::M68kTargetMachine
Definition: M68kTargetMachine.h:31
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:185
llvm::TargetMachine::STI
std::unique_ptr< const MCSubtargetInfo > STI
Definition: TargetMachine.h:109
M68kTargetMachine.h
llvm::TargetOptions
Definition: TargetOptions.h:124
T
llvm::Function
Definition: Function.h:59
llvm::Attribute
Definition: Attributes.h:67
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::getTheM68kTarget
Target & getTheM68kTarget()
Definition: M68kTargetInfo.cpp:18
llvm::X86AS::FS
@ FS
Definition: X86.h:201
InstructionSelect.h
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
llvm::initializeM68kDAGToDAGISelPass
void initializeM68kDAGToDAGISelPass(PassRegistry &)
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:31
LegacyPassManager.h
PassRegistry.h
F
#define F(x, y, z)
Definition: MD5.cpp:55
M68kTargetObjectFile.h
M68k.h
llvm::Reloc::Model
Model
Definition: CodeGen.h:25
llvm::M68kTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: M68kTargetMachine.cpp:167
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::Legalizer
Definition: Legalizer.h:36
llvm::createM68kCollapseMOVEMPass
FunctionPass * createM68kCollapseMOVEMPass()
Finds sequential MOVEM instruction and collapse them into a single one.
Definition: M68kCollapseMOVEMPass.cpp:305
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:31
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1354
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:99
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:312
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
llvm::M68kSubtarget
Definition: M68kSubtarget.h:44
llvm::CodeModel::Model
Model
Definition: CodeGen.h:31
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::M68kTargetMachine::getSubtargetImpl
const M68kSubtarget * getSubtargetImpl() const
Definition: M68kTargetMachine.h:46
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:97
llvm::M68kTargetMachine::M68kTargetMachine
M68kTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: M68kTargetMachine.cpp:97
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:510
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
llvm::M68kTargetMachine::createMachineFunctionInfo
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
Definition: M68kTargetMachine.cpp:132
llvm::BumpPtrAllocatorImpl
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:63
computeDataLayout
static std::string computeDataLayout(const Triple &TT, const MCTargetOptions &Options, bool LittleEndian)
Definition: AArch64TargetMachine.cpp:256
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::M68kELFTargetObjectFile
Definition: M68kTargetObjectFile.h:21
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:839
TargetPassConfig.h
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:43
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:499
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:25
IRTranslator.h
llvm::createM68kISelDag
FunctionPass * createM68kISelDag(M68kTargetMachine &TM)
This pass converts a legalized DAG into a M68k-specific DAG, ready for instruction scheduling.
Definition: M68kISelDAGToDAG.cpp:355
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:62
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
std
Definition: BitVector.h:851
M68kTargetInfo.h
RegBankSelect.h
M68kMachineFunction.h
LLVMInitializeM68kTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kTarget()
Definition: M68kTargetMachine.cpp:37
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:417
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:31
Legalizer.h
llvm::createM68kExpandPseudoPass
FunctionPass * createM68kExpandPseudoPass()
Return a Machine IR pass that expands M68k-specific pseudo instructions into a sequence of actual ins...
Definition: M68kExpandPseudo.cpp:318
Allocator
Basic Register Allocator
Definition: RegAllocBasic.cpp:143
M68kSubtarget.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::IRTranslator
Definition: IRTranslator.h:64
llvm::StringRef::str
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:222
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::CodeGenOpt::Level
Level
Code generation optimization level.
Definition: CodeGen.h:57
TargetRegistry.h
llvm::MachineFunctionInfo
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
Definition: MachineFunction.h:95
InitializePasses.h
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:98
llvm::createM68kGlobalBaseRegPass
FunctionPass * createM68kGlobalBaseRegPass()
This pass initializes a global base register for PIC on M68k.
Definition: M68kInstrInfo.cpp:857
llvm::M68kTargetMachine::~M68kTargetMachine
~M68kTargetMachine() override
Definition: M68kTargetMachine.cpp:111