LLVM  13.0.0git
AArch64TargetMachine.cpp
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1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Triple.h"
32 #include "llvm/CodeGen/Passes.h"
34 #include "llvm/IR/Attributes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/InitializePasses.h"
37 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/Pass.h"
40 #include "llvm/Support/CodeGen.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include <memory>
48 #include <string>
49 
50 using namespace llvm;
51 
52 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
53  cl::desc("Enable the CCMP formation pass"),
54  cl::init(true), cl::Hidden);
55 
56 static cl::opt<bool>
57  EnableCondBrTuning("aarch64-enable-cond-br-tune",
58  cl::desc("Enable the conditional branch tuning pass"),
59  cl::init(true), cl::Hidden);
60 
61 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
62  cl::desc("Enable the machine combiner pass"),
63  cl::init(true), cl::Hidden);
64 
65 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
66  cl::desc("Suppress STP for AArch64"),
67  cl::init(true), cl::Hidden);
68 
70  "aarch64-enable-simd-scalar",
71  cl::desc("Enable use of AdvSIMD scalar integer instructions"),
72  cl::init(false), cl::Hidden);
73 
74 static cl::opt<bool>
75  EnablePromoteConstant("aarch64-enable-promote-const",
76  cl::desc("Enable the promote constant pass"),
77  cl::init(true), cl::Hidden);
78 
80  "aarch64-enable-collect-loh",
81  cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
82  cl::init(true), cl::Hidden);
83 
84 static cl::opt<bool>
85  EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
86  cl::desc("Enable the pass that removes dead"
87  " definitons and replaces stores to"
88  " them with stores to the zero"
89  " register"),
90  cl::init(true));
91 
93  "aarch64-enable-copyelim",
94  cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
95  cl::Hidden);
96 
97 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
98  cl::desc("Enable the load/store pair"
99  " optimization pass"),
100  cl::init(true), cl::Hidden);
101 
103  "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
104  cl::desc("Run SimplifyCFG after expanding atomic operations"
105  " to make use of cmpxchg flow-based information"),
106  cl::init(true));
107 
108 static cl::opt<bool>
109 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
110  cl::desc("Run early if-conversion"),
111  cl::init(true));
112 
113 static cl::opt<bool>
114  EnableCondOpt("aarch64-enable-condopt",
115  cl::desc("Enable the condition optimizer pass"),
116  cl::init(true), cl::Hidden);
117 
118 static cl::opt<bool>
119 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
120  cl::desc("Work around Cortex-A53 erratum 835769"),
121  cl::init(false));
122 
123 static cl::opt<bool>
124  EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
125  cl::desc("Enable optimizations on complex GEPs"),
126  cl::init(false));
127 
128 static cl::opt<bool>
129  BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
130  cl::desc("Relax out of range conditional branches"));
131 
133  "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
134  cl::desc("Use smallest entry possible for jump tables"));
135 
136 // FIXME: Unify control over GlobalMerge.
138  EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
139  cl::desc("Enable the global merge pass"));
140 
141 static cl::opt<bool>
142  EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
143  cl::desc("Enable the loop data prefetch pass"),
144  cl::init(true));
145 
147  "aarch64-enable-global-isel-at-O", cl::Hidden,
148  cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
149  cl::init(0));
150 
151 static cl::opt<bool>
152  EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
153  cl::desc("Enable SVE intrinsic opts"),
154  cl::init(true));
155 
156 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
157  cl::init(true), cl::Hidden);
158 
159 static cl::opt<bool>
160  EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
161  cl::desc("Enable the AAcrh64 branch target pass"),
162  cl::init(true));
163 
165 
167  // Register the target.
173  auto PR = PassRegistry::getPassRegistry();
204 }
205 
206 //===----------------------------------------------------------------------===//
207 // AArch64 Lowering public interface.
208 //===----------------------------------------------------------------------===//
209 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
210  if (TT.isOSBinFormatMachO())
211  return std::make_unique<AArch64_MachoTargetObjectFile>();
212  if (TT.isOSBinFormatCOFF())
213  return std::make_unique<AArch64_COFFTargetObjectFile>();
214 
215  return std::make_unique<AArch64_ELFTargetObjectFile>();
216 }
217 
218 // Helper function to build a DataLayout string
219 static std::string computeDataLayout(const Triple &TT,
220  const MCTargetOptions &Options,
221  bool LittleEndian) {
222  if (TT.isOSBinFormatMachO()) {
223  if (TT.getArch() == Triple::aarch64_32)
224  return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
225  return "e-m:o-i64:64-i128:128-n32:64-S128";
226  }
227  if (TT.isOSBinFormatCOFF())
228  return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
229  std::string Endian = LittleEndian ? "e" : "E";
230  std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
231  return Endian + "-m:e" + Ptr32 +
232  "-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
233 }
234 
235 static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {
236  if (CPU.empty() && TT.isArm64e())
237  return "apple-a12";
238  return CPU;
239 }
240 
243  // AArch64 Darwin and Windows are always PIC.
244  if (TT.isOSDarwin() || TT.isOSWindows())
245  return Reloc::PIC_;
246  // On ELF platforms the default static relocation model has a smart enough
247  // linker to cope with referencing external symbols defined in a shared
248  // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
249  if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
250  return Reloc::Static;
251  return *RM;
252 }
253 
254 static CodeModel::Model
256  bool JIT) {
257  if (CM) {
258  if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
259  *CM != CodeModel::Large) {
261  "Only small, tiny and large code models are allowed on AArch64");
262  } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
263  report_fatal_error("tiny code model is only supported on ELF");
264  return *CM;
265  }
266  // The default MCJIT memory managers make no guarantees about where they can
267  // find an executable page; JITed code needs to be able to refer to globals
268  // no matter how far away they are.
269  // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
270  // since with large code model LLVM generating 4 MOV instructions, and
271  // Windows doesn't support relocating these long branch (4 MOVs).
272  if (JIT && !TT.isOSWindows())
273  return CodeModel::Large;
274  return CodeModel::Small;
275 }
276 
277 /// Create an AArch64 architecture model.
278 ///
280  StringRef CPU, StringRef FS,
281  const TargetOptions &Options,
284  CodeGenOpt::Level OL, bool JIT,
285  bool LittleEndian)
287  computeDataLayout(TT, Options.MCOptions, LittleEndian),
288  TT, computeDefaultCPU(TT, CPU), FS, Options,
290  getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
291  TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
292  initAsmInfo();
293 
294  if (TT.isOSBinFormatMachO()) {
295  this->Options.TrapUnreachable = true;
296  this->Options.NoTrapAfterNoreturn = true;
297  }
298 
299  if (getMCAsmInfo()->usesWindowsCFI()) {
300  // Unwinding can get confused if the last instruction in an
301  // exception-handling region (function, funclet, try block, etc.)
302  // is a call.
303  //
304  // FIXME: We could elide the trap if the next instruction would be in
305  // the same region anyway.
306  this->Options.TrapUnreachable = true;
307  }
308 
309  if (this->Options.TLSSize == 0) // default
310  this->Options.TLSSize = 24;
311  if ((getCodeModel() == CodeModel::Small ||
313  this->Options.TLSSize > 32)
314  // for the small (and kernel) code model, the maximum TLS size is 4GiB
315  this->Options.TLSSize = 32;
316  else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
317  // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
318  this->Options.TLSSize = 24;
319 
320  // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
321  // MachO/CodeModel::Large, which GlobalISel does not support.
322  if (getOptLevel() <= EnableGlobalISelAtO &&
323  TT.getArch() != Triple::aarch64_32 &&
324  TT.getEnvironment() != Triple::GNUILP32 &&
325  !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
326  setGlobalISel(true);
328  }
329 
330  // AArch64 supports the MachineOutliner.
331  setMachineOutliner(true);
332 
333  // AArch64 supports default outlining behaviour.
335 
336  // AArch64 supports the debug entry values.
338 }
339 
341 
342 const AArch64Subtarget *
344  Attribute CPUAttr = F.getFnAttribute("target-cpu");
345  Attribute FSAttr = F.getFnAttribute("target-features");
346 
347  std::string CPU =
348  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
349  std::string FS =
350  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
351 
352  auto &I = SubtargetMap[CPU + FS];
353  if (!I) {
354  // This needs to be done before we create a new subtarget since any
355  // creation will depend on the TM and the code generation flags on the
356  // function that reside in TargetOptions.
358  I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
359  isLittle);
360  }
361  return I.get();
362 }
363 
364 void AArch64leTargetMachine::anchor() { }
365 
367  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
370  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
371 
372 void AArch64beTargetMachine::anchor() { }
373 
375  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
378  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
379 
380 namespace {
381 
382 /// AArch64 Code Generator Pass Configuration Options.
383 class AArch64PassConfig : public TargetPassConfig {
384 public:
385  AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
386  : TargetPassConfig(TM, PM) {
387  if (TM.getOptLevel() != CodeGenOpt::None)
388  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
389  }
390 
391  AArch64TargetMachine &getAArch64TargetMachine() const {
392  return getTM<AArch64TargetMachine>();
393  }
394 
396  createMachineScheduler(MachineSchedContext *C) const override {
397  const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
399  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
400  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
401  if (ST.hasFusion())
402  DAG->addMutation(createAArch64MacroFusionDAGMutation());
403  return DAG;
404  }
405 
407  createPostMachineScheduler(MachineSchedContext *C) const override {
408  const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
409  if (ST.hasFusion()) {
410  // Run the Macro Fusion after RA again since literals are expanded from
411  // pseudos then (v. addPreSched2()).
414  return DAG;
415  }
416 
417  return nullptr;
418  }
419 
420  void addIRPasses() override;
421  bool addPreISel() override;
422  bool addInstSelector() override;
423  bool addIRTranslator() override;
424  void addPreLegalizeMachineIR() override;
425  bool addLegalizeMachineIR() override;
426  void addPreRegBankSelect() override;
427  bool addRegBankSelect() override;
428  void addPreGlobalInstructionSelect() override;
429  bool addGlobalInstructionSelect() override;
430  bool addILPOpts() override;
431  void addPreRegAlloc() override;
432  void addPostRegAlloc() override;
433  void addPreSched2() override;
434  void addPreEmitPass() override;
435  void addPreEmitPass2() override;
436 
437  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
438 };
439 
440 } // end anonymous namespace
441 
444  return TargetTransformInfo(AArch64TTIImpl(this, F));
445 }
446 
448  return new AArch64PassConfig(*this, PM);
449 }
450 
451 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
452  return getStandardCSEConfigForOpt(TM->getOptLevel());
453 }
454 
455 void AArch64PassConfig::addIRPasses() {
456  // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
457  // ourselves.
458  addPass(createAtomicExpandPass());
459 
460  // Expand any SVE vector library calls that we can't code generate directly.
461  if (EnableSVEIntrinsicOpts && TM->getOptLevel() == CodeGenOpt::Aggressive)
462  addPass(createSVEIntrinsicOptsPass());
463 
464  // Cmpxchg instructions are often used with a subsequent comparison to
465  // determine whether it succeeded. We can exploit existing control-flow in
466  // ldrex/strex loops to simplify this, but it needs tidying up.
467  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
469  .forwardSwitchCondToPhi(true)
470  .convertSwitchToLookupTable(true)
471  .needCanonicalLoops(false)
472  .hoistCommonInsts(true)
473  .sinkCommonInsts(true)));
474 
475  // Run LoopDataPrefetch
476  //
477  // Run this before LSR to remove the multiplies involved in computing the
478  // pointer values N iterations ahead.
479  if (TM->getOptLevel() != CodeGenOpt::None) {
481  addPass(createLoopDataPrefetchPass());
484  }
485 
487 
489  /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
490 
491  // Match interleaved memory accesses to ldN/stN intrinsics.
492  if (TM->getOptLevel() != CodeGenOpt::None) {
494  addPass(createInterleavedAccessPass());
495  }
496 
497  if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
498  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
499  // and lower a GEP with multiple indices to either arithmetic operations or
500  // multiple GEPs with single index.
502  // Call EarlyCSE pass to find and remove subexpressions in the lowered
503  // result.
504  addPass(createEarlyCSEPass());
505  // Do loop invariant code motion in case part of the lowered result is
506  // invariant.
507  addPass(createLICMPass());
508  }
509 
510  // Add Control Flow Guard checks.
511  if (TM->getTargetTriple().isOSWindows())
512  addPass(createCFGuardCheckPass());
513 }
514 
515 // Pass Pipeline Configuration
516 bool AArch64PassConfig::addPreISel() {
517  // Run promote constant before global merge, so that the promoted constants
518  // get a chance to be merged
519  if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
521  // FIXME: On AArch64, this depends on the type.
522  // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
523  // and the offset has to be a multiple of the related size in bytes.
524  if ((TM->getOptLevel() != CodeGenOpt::None &&
527  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
529 
530  // Merging of extern globals is enabled by default on non-Mach-O as we
531  // expect it to be generally either beneficial or harmless. On Mach-O it
532  // is disabled as we emit the .subsections_via_symbols directive which
533  // means that merging extern globals is not safe.
534  bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
535 
536  // FIXME: extern global merging is only enabled when we optimise for size
537  // because there are some regressions with it also enabled for performance.
538  if (!OnlyOptimizeForSize)
539  MergeExternalByDefault = false;
540 
541  addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
542  MergeExternalByDefault));
543  }
544 
545  return false;
546 }
547 
548 bool AArch64PassConfig::addInstSelector() {
549  addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
550 
551  // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
552  // references to _TLS_MODULE_BASE_ as possible.
553  if (TM->getTargetTriple().isOSBinFormatELF() &&
554  getOptLevel() != CodeGenOpt::None)
556 
557  return false;
558 }
559 
560 bool AArch64PassConfig::addIRTranslator() {
561  addPass(new IRTranslator(getOptLevel()));
562  return false;
563 }
564 
565 void AArch64PassConfig::addPreLegalizeMachineIR() {
566  if (getOptLevel() == CodeGenOpt::None)
568  else
570 }
571 
572 bool AArch64PassConfig::addLegalizeMachineIR() {
573  addPass(new Legalizer());
574  return false;
575 }
576 
577 void AArch64PassConfig::addPreRegBankSelect() {
578  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
579  if (!IsOptNone)
580  addPass(createAArch64PostLegalizerCombiner(IsOptNone));
582 }
583 
584 bool AArch64PassConfig::addRegBankSelect() {
585  addPass(new RegBankSelect());
586  return false;
587 }
588 
589 void AArch64PassConfig::addPreGlobalInstructionSelect() {
590  addPass(new Localizer());
591 }
592 
593 bool AArch64PassConfig::addGlobalInstructionSelect() {
594  addPass(new InstructionSelect(getOptLevel()));
595  if (getOptLevel() != CodeGenOpt::None)
597  return false;
598 }
599 
600 bool AArch64PassConfig::addILPOpts() {
601  if (EnableCondOpt)
603  if (EnableCCMP)
605  if (EnableMCR)
606  addPass(&MachineCombinerID);
607  if (EnableCondBrTuning)
608  addPass(createAArch64CondBrTuning());
610  addPass(&EarlyIfConverterID);
614  if (TM->getOptLevel() != CodeGenOpt::None)
616  return true;
617 }
618 
619 void AArch64PassConfig::addPreRegAlloc() {
620  // Change dead register definitions to refer to the zero register.
621  if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
623 
624  // Use AdvSIMD scalar instructions whenever profitable.
625  if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
626  addPass(createAArch64AdvSIMDScalar());
627  // The AdvSIMD pass may produce copies that can be rewritten to
628  // be register coalescer friendly.
629  addPass(&PeepholeOptimizerID);
630  }
631 }
632 
633 void AArch64PassConfig::addPostRegAlloc() {
634  // Remove redundant copy instructions.
635  if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
637 
638  if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
639  // Improve performance for some FP/SIMD code for A57.
641 }
642 
643 void AArch64PassConfig::addPreSched2() {
644  // Lower homogeneous frame instructions
647  // Expand some pseudo instructions to allow proper scheduling.
649  // Use load/store pair instructions when possible.
650  if (TM->getOptLevel() != CodeGenOpt::None) {
651  if (EnableLoadStoreOpt)
653  }
654 
655  // The AArch64SpeculationHardeningPass destroys dominator tree and natural
656  // loop info, which is needed for the FalkorHWPFFixPass and also later on.
657  // Therefore, run the AArch64SpeculationHardeningPass before the
658  // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
659  // info.
661 
662  addPass(createAArch64IndirectThunks());
664 
665  if (TM->getOptLevel() != CodeGenOpt::None) {
667  addPass(createFalkorHWPFFixPass());
668  }
669 }
670 
671 void AArch64PassConfig::addPreEmitPass() {
672  // Machine Block Placement might have created new opportunities when run
673  // at O3, where the Tail Duplication Threshold is set to 4 instructions.
674  // Run the load/store optimizer once more.
675  if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
677 
678  if (EnableA53Fix835769)
679  addPass(createAArch64A53Fix835769());
680 
683 
684  // Relax conditional branch instructions if they're otherwise out of
685  // range of their destination.
686  if (BranchRelaxation)
687  addPass(&BranchRelaxationPassID);
688 
689  if (TM->getTargetTriple().isOSWindows()) {
690  // Identify valid longjmp targets for Windows Control Flow Guard.
691  addPass(createCFGuardLongjmpPass());
692  // Identify valid eh continuation targets for Windows EHCont Guard.
694  }
695 
696  if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
698 
699  if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
700  TM->getTargetTriple().isOSBinFormatMachO())
701  addPass(createAArch64CollectLOHPass());
702 }
703 
704 void AArch64PassConfig::addPreEmitPass2() {
705  // SVE bundles move prefixes with destructive operations. BLR_RVMARKER pseudo
706  // instructions are lowered to bundles as well.
707  addPass(createUnpackMachineBundles(nullptr));
708 }
709 
712  return new yaml::AArch64FunctionInfo();
713 }
714 
717  const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
718  return new yaml::AArch64FunctionInfo(*MFI);
719 }
720 
723  SMDiagnostic &Error, SMRange &SourceRange) const {
724  const auto &YamlMFI =
725  reinterpret_cast<const yaml::AArch64FunctionInfo &>(MFI);
726  MachineFunction &MF = PFS.MF;
727  MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
728  return false;
729 }
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Definition: AArch64TargetMachine.cpp:235
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Definition: AArch64TargetMachine.cpp:209
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void initializeAArch64StackTaggingPass(PassRegistry &)
llvm::createSeparateConstOffsetFromGEPPass
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Definition: SeparateConstOffsetFromGEP.cpp:499
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
AArch64.h
llvm::Triple::GNUILP32
@ GNUILP32
Definition: Triple.h:213
llvm::createAArch64PromoteConstantPass
ModulePass * createAArch64PromoteConstantPass()
Definition: AArch64PromoteConstant.cpp:235
MCTargetOptions.h
llvm::PeepholeOptimizerID
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
Definition: PeepholeOptimizer.cpp:443
llvm::initializeAArch64BranchTargetsPass
void initializeAArch64BranchTargetsPass(PassRegistry &)
llvm::TargetOptions
Definition: TargetOptions.h:113
Scalar.h
llvm::initializeAArch64O0PreLegalizerCombinerPass
void initializeAArch64O0PreLegalizerCombinerPass(PassRegistry &)
llvm::Function
Definition: Function.h:61
llvm::Attribute
Definition: Attributes.h:52
Pass.h
llvm::yaml::MachineFunctionInfo
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Definition: MIRYamlMapping.h:671
EnableGlobalISelAtO
static cl::opt< int > EnableGlobalISelAtO("aarch64-enable-global-isel-at-O", cl::Hidden, cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"), cl::init(0))
CSEConfigBase.h
llvm::createAArch64SpeculationHardeningPass
FunctionPass * createAArch64SpeculationHardeningPass()
Returns an instance of the pseudo instruction expansion pass.
Definition: AArch64SpeculationHardening.cpp:700
llvm::createCFGSimplificationPass
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
Definition: SimplifyCFGPass.cpp:384
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:125
EnableRedundantCopyElimination
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:181
EnableCompressJumpTables
static cl::opt< bool > EnableCompressJumpTables("aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true), cl::desc("Use smallest entry possible for jump tables"))
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:167
llvm::initializeAArch64DeadRegisterDefinitionsPass
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
llvm::createAArch64CondBrTuning
FunctionPass * createAArch64CondBrTuning()
Definition: AArch64CondBrTuning.cpp:328
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
llvm::AArch64beTargetMachine::AArch64beTargetMachine
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AArch64TargetMachine.cpp:374
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::createEarlyCSEPass
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1719
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::createAArch64DeadRegisterDefinitions
FunctionPass * createAArch64DeadRegisterDefinitions()
Definition: AArch64DeadRegisterDefinitionsPass.cpp:201
llvm::createAArch64BranchTargetsPass
FunctionPass * createAArch64BranchTargetsPass()
EnableAdvSIMDScalar
static cl::opt< bool > EnableAdvSIMDScalar("aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden)
EnableHomogeneousPrologEpilog
cl::opt< bool > EnableHomogeneousPrologEpilog
llvm::TargetMachine::setSupportsDefaultOutlining
void setSupportsDefaultOutlining(bool Enable)
Definition: TargetMachine.h:250
llvm::AArch64TargetMachine::convertFuncInfoToYAML
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
Definition: AArch64TargetMachine.cpp:716
llvm::initializeAArch64CompressJumpTablesPass
void initializeAArch64CompressJumpTablesPass(PassRegistry &)
llvm::TargetOptions::TrapUnreachable
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Definition: TargetOptions.h:255
llvm::initializeAArch64A53Fix835769Pass
void initializeAArch64A53Fix835769Pass(PassRegistry &)
InstructionSelect.h
EnableBranchTargets
static cl::opt< bool > EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden, cl::desc("Enable the AAcrh64 branch target pass"), cl::init(true))
llvm::createSVEIntrinsicOptsPass
ModulePass * createSVEIntrinsicOptsPass()
Definition: SVEIntrinsicOpts.cpp:89
llvm::Optional< Reloc::Model >
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
llvm::createAArch64A57FPLoadBalancing
FunctionPass * createAArch64A57FPLoadBalancing()
Definition: AArch64A57FPLoadBalancing.cpp:721
llvm::createAArch64PostSelectOptimize
FunctionPass * createAArch64PostSelectOptimize()
Definition: AArch64PostSelectOptimize.cpp:195
llvm::initializeAArch64LowerHomogeneousPrologEpilogPass
void initializeAArch64LowerHomogeneousPrologEpilogPass(PassRegistry &)
llvm::initializeAArch64SIMDInstrOptPass
void initializeAArch64SIMDInstrOptPass(PassRegistry &)
llvm::createAArch64PreLegalizerCombiner
FunctionPass * createAArch64PreLegalizerCombiner()
Definition: AArch64PreLegalizerCombiner.cpp:367
STLExtras.h
llvm::initializeAArch64PromoteConstantPass
void initializeAArch64PromoteConstantPass(PassRegistry &)
llvm::createAArch64SIMDInstrOptPass
FunctionPass * createAArch64SIMDInstrOptPass()
Returns an instance of the high cost ASIMD instruction replacement optimization pass.
Definition: AArch64SIMDInstrOpt.cpp:741
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:28
llvm::Triple::aarch64_32
@ aarch64_32
Definition: Triple.h:54
llvm::createAArch64LoadStoreOptimizationPass
FunctionPass * createAArch64LoadStoreOptimizationPass()
createAArch64LoadStoreOptimizationPass - returns an instance of the load / store optimization pass.
Definition: AArch64LoadStoreOptimizer.cpp:2305
LLVMInitializeAArch64Target
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target()
Definition: AArch64TargetMachine.cpp:166
llvm::AArch64TargetMachine::SubtargetMap
StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap
Definition: AArch64TargetMachine.h:28
llvm::initializeFalkorHWPFFixPass
void initializeFalkorHWPFFixPass(PassRegistry &)
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::createAArch64A53Fix835769
FunctionPass * createAArch64A53Fix835769()
Definition: AArch64A53Fix835769.cpp:242
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
BranchRelaxation
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
CommandLine.h
llvm::createAArch64PostLegalizerLowering
FunctionPass * createAArch64PostLegalizerLowering()
Definition: AArch64PostLegalizerLowering.cpp:1063
AArch64TargetMachine.h
EnableA53Fix835769
static cl::opt< bool > EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden, cl::desc("Work around Cortex-A53 erratum 835769"), cl::init(false))
llvm::createEHContGuardCatchretPass
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::createAArch64CompressJumpTablesPass
FunctionPass * createAArch64CompressJumpTablesPass()
Definition: AArch64CompressJumpTables.cpp:186
llvm::TargetMachine::setMachineOutliner
void setMachineOutliner(bool Enable)
Definition: TargetMachine.h:247
llvm::initializeAArch64ExpandPseudoPass
void initializeAArch64ExpandPseudoPass(PassRegistry &)
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:674
llvm::initializeAArch64StorePairSuppressPass
void initializeAArch64StorePairSuppressPass(PassRegistry &)
llvm::Legalizer
Definition: Legalizer.h:31
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
EnableFalkorHWPFFix
static cl::opt< bool > EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix", cl::init(true), cl::Hidden)
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:251
llvm::createAArch64StorePairSuppressPass
FunctionPass * createAArch64StorePairSuppressPass()
false
Definition: StackSlotColoring.cpp:142
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:784
llvm::createGenericSchedPostRA
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Definition: MachineScheduler.cpp:3638
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
EnableAtomicTidy
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:31
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1199
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:318
AArch64TargetObjectFile.h
llvm::AArch64TargetMachine
Definition: AArch64TargetMachine.h:25
llvm::report_fatal_error
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createAArch64ISelDag
FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOpt::Level OptLevel)
createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG,...
Definition: AArch64ISelDAGToDAG.cpp:4870
EnableCollectLOH
static cl::opt< bool > EnableCollectLOH("aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden)
llvm::initializeAArch64SLSHardeningPass
void initializeAArch64SLSHardeningPass(PassRegistry &)
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:98
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
llvm::createAArch64IndirectThunks
FunctionPass * createAArch64IndirectThunks()
Definition: AArch64SLSHardening.cpp:434
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
AArch64MacroFusion.h
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
llvm::AArch64TargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: AArch64TargetMachine.cpp:443
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::cl::opt< bool >
llvm::createFalkorHWPFFixPass
FunctionPass * createFalkorHWPFFixPass()
Definition: AArch64FalkorHWPFFix.cpp:839
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
getEffectiveAArch64CodeModel
static CodeModel::Model getEffectiveAArch64CodeModel(const Triple &TT, Optional< CodeModel::Model > CM, bool JIT)
Definition: AArch64TargetMachine.cpp:255
llvm::cl::BOU_UNSET
@ BOU_UNSET
Definition: CommandLine.h:625
llvm::initializeAArch64ConditionalComparesPass
void initializeAArch64ConditionalComparesPass(PassRegistry &)
llvm::initializeAArch64SpeculationHardeningPass
void initializeAArch64SpeculationHardeningPass(PassRegistry &)
llvm::AArch64TTIImpl
Definition: AArch64TargetTransformInfo.h:41
llvm::initializeAArch64PostSelectOptimizePass
void initializeAArch64PostSelectOptimizePass(PassRegistry &)
CFGuard.h
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3485
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:525
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
EnableGlobalMerge
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
llvm::createAArch64ExpandPseudoPass
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
Definition: AArch64ExpandPseudoInsts.cpp:1203
llvm::createAArch64RedundantCopyEliminationPass
FunctionPass * createAArch64RedundantCopyEliminationPass()
Definition: AArch64RedundantCopyElimination.cpp:495
llvm::initializeAArch64CollectLOHPass
void initializeAArch64CollectLOHPass(PassRegistry &)
llvm::initializeAArch64PostLegalizerLoweringPass
void initializeAArch64PostLegalizerLoweringPass(PassRegistry &)
computeDataLayout
static std::string computeDataLayout(const Triple &TT, const MCTargetOptions &Options, bool LittleEndian)
Definition: AArch64TargetMachine.cpp:219
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:120
EnableMCR
static cl::opt< bool > EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
llvm::AArch64FunctionInfo
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Definition: AArch64MachineFunctionInfo.h:37
llvm::TargetOptions::NoTrapAfterNoreturn
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
Definition: TargetOptions.h:259
llvm::initializeAArch64AdvSIMDScalarPass
void initializeAArch64AdvSIMDScalarPass(PassRegistry &)
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:810
llvm::createUnpackMachineBundles
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
Definition: MachineInstrBundle.cpp:80
EnableEarlyIfConversion
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
EnableCondBrTuning
static cl::opt< bool > EnableCondBrTuning("aarch64-enable-cond-br-tune", cl::desc("Enable the conditional branch tuning pass"), cl::init(true), cl::Hidden)
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
TargetPassConfig.h
Localizer.h
llvm::initializeAArch64PreLegalizerCombinerPass
void initializeAArch64PreLegalizerCombinerPass(PassRegistry &)
llvm::createAArch64PostLegalizerCombiner
FunctionPass * createAArch64PostLegalizerCombiner(bool IsOptNone)
Definition: AArch64PostLegalizerCombiner.cpp:387
llvm::TargetOptions::TLSSize
unsigned TLSSize
Bit size of immediate TLS offsets (0 == use the default).
Definition: TargetOptions.h:262
llvm::createCFGuardCheckPass
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:294
llvm::initializeLDTLSCleanupPass
void initializeLDTLSCleanupPass(PassRegistry &)
EnableLoadStoreOpt
static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden)
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:266
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::Reloc::DynamicNoPIC
@ DynamicNoPIC
Definition: CodeGen.h:22
llvm::MachineFunction
Definition: MachineFunction.h:230
Triple.h
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:469
EnableGEPOpt
static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:202
llvm::initializeAArch64StackTaggingPreRAPass
void initializeAArch64StackTaggingPreRAPass(PassRegistry &)
llvm::initializeAArch64PostLegalizerCombinerPass
void initializeAArch64PostLegalizerCombinerPass(PassRegistry &)
MCAsmInfo.h
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
llvm::createAArch64SLSHardeningPass
FunctionPass * createAArch64SLSHardeningPass()
Definition: AArch64SLSHardening.cpp:394
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::createAArch64StackTaggingPreRAPass
FunctionPass * createAArch64StackTaggingPreRAPass()
Definition: AArch64StackTaggingPreRA.cpp:100
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:74
IRTranslator.h
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:39
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
EnableSVEIntrinsicOpts
static cl::opt< bool > EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden, cl::desc("Enable SVE intrinsic opts"), cl::init(true))
AArch64TargetTransformInfo.h
llvm::createInterleavedAccessPass
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
Definition: InterleavedAccessPass.cpp:145
llvm::AArch64TargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: AArch64TargetMachine.cpp:721
Attributes.h
llvm::PerFunctionMIParsingState
Definition: MIParser.h:160
llvm::initializeAArch64RedundantCopyEliminationPass
void initializeAArch64RedundantCopyEliminationPass(PassRegistry &)
llvm::initializeFalkorMarkStridedAccessesLegacyPass
void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry &)
llvm::initializeAArch64LoadStoreOptPass
void initializeAArch64LoadStoreOptPass(PassRegistry &)
llvm::TargetMachine::setGlobalISelAbort
void setGlobalISelAbort(GlobalISelAbortMode Mode)
Definition: TargetMachine.h:244
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:157
llvm::createLoadClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1573
RegBankSelect.h
llvm::createAArch64MacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAArch64MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAArch64MacroFusionDAGMutation()); to AArch64PassConf...
Definition: AArch64MacroFusion.cpp:413
EnableCondOpt
static cl::opt< bool > EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)
Function.h
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
llvm::createAArch64CollectLOHPass
FunctionPass * createAArch64CollectLOHPass()
Definition: AArch64CollectLOH.cpp:597
llvm::createAArch64O0PreLegalizerCombiner
FunctionPass * createAArch64O0PreLegalizerCombiner()
Definition: AArch64O0PreLegalizerCombiner.cpp:168
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.cpp:74
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:385
AArch64MCTargetDesc.h
llvm::initializeSVEIntrinsicOptsPass
void initializeSVEIntrinsicOptsPass(PassRegistry &)
llvm::TargetMachine::setGlobalISel
void setGlobalISel(bool Enable)
Definition: TargetMachine.h:243
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:162
llvm::AArch64TargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: AArch64TargetMachine.cpp:447
llvm::createGlobalMergePass
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
Definition: GlobalMerge.cpp:680
llvm::BranchRelaxationPassID
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Definition: BranchRelaxation.cpp:119
EnableLoopDataPrefetch
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
CodeGen.h
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
EnableCCMP
static cl::opt< bool > EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)
llvm::cl::BOU_TRUE
@ BOU_TRUE
Definition: CommandLine.h:625
Legalizer.h
llvm::SimplifyCFGOptions
Definition: SimplifyCFGOptions.h:23
llvm::createLICMPass
Pass * createLICMPass()
Definition: LICM.cpp:309
MachineScheduler.h
AArch64Subtarget.h
EnableDeadRegisterElimination
static cl::opt< bool > EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to the zero" " register"), cl::init(true))
llvm::createAArch64AdvSIMDScalar
FunctionPass * createAArch64AdvSIMDScalar()
Definition: AArch64AdvSIMDScalarPass.cpp:410
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:199
llvm::createAArch64StackTaggingPass
FunctionPass * createAArch64StackTaggingPass(bool IsOptNone)
Definition: AArch64StackTagging.cpp:353
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
llvm::createAArch64ConditionOptimizerPass
FunctionPass * createAArch64ConditionOptimizerPass()
Definition: AArch64ConditionOptimizer.cpp:133
llvm::MachineCombinerID
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
Definition: MachineCombiner.cpp:130
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::createStoreClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1580
llvm::IRTranslator
Definition: IRTranslator.h:62
llvm::GlobalISelAbortMode::Disable
@ Disable
EnablePromoteConstant
static cl::opt< bool > EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden)
llvm::AArch64TargetMachine::AArch64TargetMachine
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT, bool IsLittleEndian)
Create an AArch64 architecture model.
Definition: AArch64TargetMachine.cpp:279
llvm::initializeAArch64ConditionOptimizerPass
void initializeAArch64ConditionOptimizerPass(PassRegistry &)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::createInterleavedLoadCombinePass
FunctionPass * createInterleavedLoadCombinePass()
InterleavedLoadCombines Pass - This pass identifies interleaved loads and combines them into wide loa...
Definition: InterleavedLoadCombinePass.cpp:1363
llvm::TargetMachine::setSupportsDebugEntryValues
void setSupportsDebugEntryValues(bool Enable)
Definition: TargetMachine.h:253
llvm::createAArch64CleanupLocalDynamicTLSPass
FunctionPass * createAArch64CleanupLocalDynamicTLSPass()
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:241
llvm::cl::desc
Definition: CommandLine.h:414
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:385
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::createAArch64ConditionalCompares
FunctionPass * createAArch64ConditionalCompares()
Definition: AArch64ConditionalCompares.cpp:805
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1799
llvm::createFalkorMarkStridedAccessesPass
FunctionPass * createFalkorMarkStridedAccessesPass()
Definition: AArch64FalkorHWPFFix.cpp:116
TargetRegistry.h
llvm::AArch64TargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: AArch64TargetMachine.cpp:711
InitializePasses.h
llvm::AArch64leTargetMachine::AArch64leTargetMachine
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AArch64TargetMachine.cpp:366
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:97
llvm::yaml::AArch64FunctionInfo
Definition: AArch64MachineFunctionInfo.h:420
llvm::createLoopDataPrefetchPass
FunctionPass * createLoopDataPrefetchPass()
Definition: LoopDataPrefetch.cpp:151
MIParser.h
AArch64TargetInfo.h
llvm::createCFGuardLongjmpPass
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
llvm::AArch64TargetMachine::~AArch64TargetMachine
~AArch64TargetMachine() override
llvm::Localizer
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:40
llvm::AArch64TargetMachine::getSubtargetImpl
const AArch64Subtarget * getSubtargetImpl() const =delete