LLVM  14.0.0git
AArch64TargetMachine.cpp
Go to the documentation of this file.
1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Triple.h"
33 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/InitializePasses.h"
38 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/TargetRegistry.h"
41 #include "llvm/Pass.h"
42 #include "llvm/Support/CodeGen.h"
47 #include "llvm/Transforms/Scalar.h"
48 #include <memory>
49 #include <string>
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
54  cl::desc("Enable the CCMP formation pass"),
55  cl::init(true), cl::Hidden);
56 
57 static cl::opt<bool>
58  EnableCondBrTuning("aarch64-enable-cond-br-tune",
59  cl::desc("Enable the conditional branch tuning pass"),
60  cl::init(true), cl::Hidden);
61 
62 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
63  cl::desc("Enable the machine combiner pass"),
64  cl::init(true), cl::Hidden);
65 
66 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
67  cl::desc("Suppress STP for AArch64"),
68  cl::init(true), cl::Hidden);
69 
71  "aarch64-enable-simd-scalar",
72  cl::desc("Enable use of AdvSIMD scalar integer instructions"),
73  cl::init(false), cl::Hidden);
74 
75 static cl::opt<bool>
76  EnablePromoteConstant("aarch64-enable-promote-const",
77  cl::desc("Enable the promote constant pass"),
78  cl::init(true), cl::Hidden);
79 
81  "aarch64-enable-collect-loh",
82  cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
83  cl::init(true), cl::Hidden);
84 
85 static cl::opt<bool>
86  EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
87  cl::desc("Enable the pass that removes dead"
88  " definitons and replaces stores to"
89  " them with stores to the zero"
90  " register"),
91  cl::init(true));
92 
94  "aarch64-enable-copyelim",
95  cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
96  cl::Hidden);
97 
98 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
99  cl::desc("Enable the load/store pair"
100  " optimization pass"),
101  cl::init(true), cl::Hidden);
102 
104  "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
105  cl::desc("Run SimplifyCFG after expanding atomic operations"
106  " to make use of cmpxchg flow-based information"),
107  cl::init(true));
108 
109 static cl::opt<bool>
110 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
111  cl::desc("Run early if-conversion"),
112  cl::init(true));
113 
114 static cl::opt<bool>
115  EnableCondOpt("aarch64-enable-condopt",
116  cl::desc("Enable the condition optimizer pass"),
117  cl::init(true), cl::Hidden);
118 
119 static cl::opt<bool>
120  EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
121  cl::desc("Enable optimizations on complex GEPs"),
122  cl::init(false));
123 
124 static cl::opt<bool>
125  BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
126  cl::desc("Relax out of range conditional branches"));
127 
129  "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
130  cl::desc("Use smallest entry possible for jump tables"));
131 
132 // FIXME: Unify control over GlobalMerge.
134  EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
135  cl::desc("Enable the global merge pass"));
136 
137 static cl::opt<bool>
138  EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
139  cl::desc("Enable the loop data prefetch pass"),
140  cl::init(true));
141 
143  "aarch64-enable-global-isel-at-O", cl::Hidden,
144  cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
145  cl::init(0));
146 
147 static cl::opt<bool>
148  EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden,
149  cl::desc("Enable SVE intrinsic opts"),
150  cl::init(true));
151 
152 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
153  cl::init(true), cl::Hidden);
154 
155 static cl::opt<bool>
156  EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
157  cl::desc("Enable the AArch64 branch target pass"),
158  cl::init(true));
159 
161  "aarch64-sve-vector-bits-max",
162  cl::desc("Assume SVE vector registers are at most this big, "
163  "with zero meaning no maximum size is assumed."),
164  cl::init(0), cl::Hidden);
165 
167  "aarch64-sve-vector-bits-min",
168  cl::desc("Assume SVE vector registers are at least this big, "
169  "with zero meaning no minimum size is assumed."),
170  cl::init(0), cl::Hidden);
171 
173 
175  "aarch64-enable-gisel-ldst-prelegal",
176  cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"),
177  cl::init(true), cl::Hidden);
178 
180  "aarch64-enable-gisel-ldst-postlegal",
181  cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"),
182  cl::init(false), cl::Hidden);
183 
185  // Register the target.
191  auto PR = PassRegistry::getPassRegistry();
223 }
224 
225 //===----------------------------------------------------------------------===//
226 // AArch64 Lowering public interface.
227 //===----------------------------------------------------------------------===//
228 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
229  if (TT.isOSBinFormatMachO())
230  return std::make_unique<AArch64_MachoTargetObjectFile>();
231  if (TT.isOSBinFormatCOFF())
232  return std::make_unique<AArch64_COFFTargetObjectFile>();
233 
234  return std::make_unique<AArch64_ELFTargetObjectFile>();
235 }
236 
237 // Helper function to build a DataLayout string
238 static std::string computeDataLayout(const Triple &TT,
239  const MCTargetOptions &Options,
240  bool LittleEndian) {
241  if (TT.isOSBinFormatMachO()) {
242  if (TT.getArch() == Triple::aarch64_32)
243  return "e-m:o-p:32:32-i64:64-i128:128-n32:64-S128";
244  return "e-m:o-i64:64-i128:128-n32:64-S128";
245  }
246  if (TT.isOSBinFormatCOFF())
247  return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
248  std::string Endian = LittleEndian ? "e" : "E";
249  std::string Ptr32 = TT.getEnvironment() == Triple::GNUILP32 ? "-p:32:32" : "";
250  return Endian + "-m:e" + Ptr32 +
251  "-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
252 }
253 
254 static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU) {
255  if (CPU.empty() && TT.isArm64e())
256  return "apple-a12";
257  return CPU;
258 }
259 
262  // AArch64 Darwin and Windows are always PIC.
263  if (TT.isOSDarwin() || TT.isOSWindows())
264  return Reloc::PIC_;
265  // On ELF platforms the default static relocation model has a smart enough
266  // linker to cope with referencing external symbols defined in a shared
267  // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
268  if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
269  return Reloc::Static;
270  return *RM;
271 }
272 
273 static CodeModel::Model
275  bool JIT) {
276  if (CM) {
277  if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
278  *CM != CodeModel::Large) {
280  "Only small, tiny and large code models are allowed on AArch64");
281  } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
282  report_fatal_error("tiny code model is only supported on ELF");
283  return *CM;
284  }
285  // The default MCJIT memory managers make no guarantees about where they can
286  // find an executable page; JITed code needs to be able to refer to globals
287  // no matter how far away they are.
288  // We should set the CodeModel::Small for Windows ARM64 in JIT mode,
289  // since with large code model LLVM generating 4 MOV instructions, and
290  // Windows doesn't support relocating these long branch (4 MOVs).
291  if (JIT && !TT.isOSWindows())
292  return CodeModel::Large;
293  return CodeModel::Small;
294 }
295 
296 /// Create an AArch64 architecture model.
297 ///
299  StringRef CPU, StringRef FS,
300  const TargetOptions &Options,
303  CodeGenOpt::Level OL, bool JIT,
304  bool LittleEndian)
306  computeDataLayout(TT, Options.MCOptions, LittleEndian),
307  TT, computeDefaultCPU(TT, CPU), FS, Options,
309  getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
310  TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
311  initAsmInfo();
312 
313  if (TT.isOSBinFormatMachO()) {
314  this->Options.TrapUnreachable = true;
315  this->Options.NoTrapAfterNoreturn = true;
316  }
317 
318  if (getMCAsmInfo()->usesWindowsCFI()) {
319  // Unwinding can get confused if the last instruction in an
320  // exception-handling region (function, funclet, try block, etc.)
321  // is a call.
322  //
323  // FIXME: We could elide the trap if the next instruction would be in
324  // the same region anyway.
325  this->Options.TrapUnreachable = true;
326  }
327 
328  if (this->Options.TLSSize == 0) // default
329  this->Options.TLSSize = 24;
330  if ((getCodeModel() == CodeModel::Small ||
332  this->Options.TLSSize > 32)
333  // for the small (and kernel) code model, the maximum TLS size is 4GiB
334  this->Options.TLSSize = 32;
335  else if (getCodeModel() == CodeModel::Tiny && this->Options.TLSSize > 24)
336  // for the tiny code model, the maximum TLS size is 1MiB (< 16MiB)
337  this->Options.TLSSize = 24;
338 
339  // Enable GlobalISel at or below EnableGlobalISelAt0, unless this is
340  // MachO/CodeModel::Large, which GlobalISel does not support.
341  if (getOptLevel() <= EnableGlobalISelAtO &&
342  TT.getArch() != Triple::aarch64_32 &&
343  TT.getEnvironment() != Triple::GNUILP32 &&
344  !(getCodeModel() == CodeModel::Large && TT.isOSBinFormatMachO())) {
345  setGlobalISel(true);
347  }
348 
349  // AArch64 supports the MachineOutliner.
350  setMachineOutliner(true);
351 
352  // AArch64 supports default outlining behaviour.
354 
355  // AArch64 supports the debug entry values.
357 }
358 
360 
361 const AArch64Subtarget *
363  Attribute CPUAttr = F.getFnAttribute("target-cpu");
364  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
365  Attribute FSAttr = F.getFnAttribute("target-features");
366 
367  std::string CPU =
368  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
369  std::string TuneCPU =
370  TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
371  std::string FS =
372  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
373 
375 
376  unsigned MinSVEVectorSize = 0;
377  unsigned MaxSVEVectorSize = 0;
378  Attribute VScaleRangeAttr = F.getFnAttribute(Attribute::VScaleRange);
379  if (VScaleRangeAttr.isValid()) {
380  Optional<unsigned> VScaleMax = VScaleRangeAttr.getVScaleRangeMax();
381  MinSVEVectorSize = VScaleRangeAttr.getVScaleRangeMin() * 128;
382  MaxSVEVectorSize = VScaleMax ? VScaleMax.getValue() * 128 : 0;
383  } else {
384  MinSVEVectorSize = SVEVectorBitsMinOpt;
385  MaxSVEVectorSize = SVEVectorBitsMaxOpt;
386  }
387 
388  assert(MinSVEVectorSize % 128 == 0 &&
389  "SVE requires vector length in multiples of 128!");
390  assert(MaxSVEVectorSize % 128 == 0 &&
391  "SVE requires vector length in multiples of 128!");
392  assert((MaxSVEVectorSize >= MinSVEVectorSize || MaxSVEVectorSize == 0) &&
393  "Minimum SVE vector size should not be larger than its maximum!");
394 
395  // Sanitize user input in case of no asserts
396  if (MaxSVEVectorSize == 0)
397  MinSVEVectorSize = (MinSVEVectorSize / 128) * 128;
398  else {
399  MinSVEVectorSize =
400  (std::min(MinSVEVectorSize, MaxSVEVectorSize) / 128) * 128;
401  MaxSVEVectorSize =
402  (std::max(MinSVEVectorSize, MaxSVEVectorSize) / 128) * 128;
403  }
404 
405  Key += "SVEMin";
406  Key += std::to_string(MinSVEVectorSize);
407  Key += "SVEMax";
408  Key += std::to_string(MaxSVEVectorSize);
409  Key += CPU;
410  Key += TuneCPU;
411  Key += FS;
412 
413  auto &I = SubtargetMap[Key];
414  if (!I) {
415  // This needs to be done before we create a new subtarget since any
416  // creation will depend on the TM and the code generation flags on the
417  // function that reside in TargetOptions.
419  I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, TuneCPU, FS,
420  *this, isLittle, MinSVEVectorSize,
421  MaxSVEVectorSize);
422  }
423  return I.get();
424 }
425 
426 void AArch64leTargetMachine::anchor() { }
427 
429  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
432  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
433 
434 void AArch64beTargetMachine::anchor() { }
435 
437  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
440  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
441 
442 namespace {
443 
444 /// AArch64 Code Generator Pass Configuration Options.
445 class AArch64PassConfig : public TargetPassConfig {
446 public:
447  AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
448  : TargetPassConfig(TM, PM) {
449  if (TM.getOptLevel() != CodeGenOpt::None)
450  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
451  }
452 
453  AArch64TargetMachine &getAArch64TargetMachine() const {
454  return getTM<AArch64TargetMachine>();
455  }
456 
458  createMachineScheduler(MachineSchedContext *C) const override {
459  const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
461  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
462  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
463  if (ST.hasFusion())
464  DAG->addMutation(createAArch64MacroFusionDAGMutation());
465  return DAG;
466  }
467 
469  createPostMachineScheduler(MachineSchedContext *C) const override {
470  const AArch64Subtarget &ST = C->MF->getSubtarget<AArch64Subtarget>();
471  if (ST.hasFusion()) {
472  // Run the Macro Fusion after RA again since literals are expanded from
473  // pseudos then (v. addPreSched2()).
476  return DAG;
477  }
478 
479  return nullptr;
480  }
481 
482  void addIRPasses() override;
483  bool addPreISel() override;
484  void addCodeGenPrepare() override;
485  bool addInstSelector() override;
486  bool addIRTranslator() override;
487  void addPreLegalizeMachineIR() override;
488  bool addLegalizeMachineIR() override;
489  void addPreRegBankSelect() override;
490  bool addRegBankSelect() override;
491  void addPreGlobalInstructionSelect() override;
492  bool addGlobalInstructionSelect() override;
493  void addMachineSSAOptimization() override;
494  bool addILPOpts() override;
495  void addPreRegAlloc() override;
496  void addPostRegAlloc() override;
497  void addPreSched2() override;
498  void addPreEmitPass() override;
499  void addPreEmitPass2() override;
500 
501  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
502 };
503 
504 } // end anonymous namespace
505 
508  return TargetTransformInfo(AArch64TTIImpl(this, F));
509 }
510 
512  return new AArch64PassConfig(*this, PM);
513 }
514 
515 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
516  return getStandardCSEConfigForOpt(TM->getOptLevel());
517 }
518 
519 void AArch64PassConfig::addIRPasses() {
520  // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
521  // ourselves.
522  addPass(createAtomicExpandPass());
523 
524  // Expand any SVE vector library calls that we can't code generate directly.
525  if (EnableSVEIntrinsicOpts && TM->getOptLevel() == CodeGenOpt::Aggressive)
526  addPass(createSVEIntrinsicOptsPass());
527 
528  // Cmpxchg instructions are often used with a subsequent comparison to
529  // determine whether it succeeded. We can exploit existing control-flow in
530  // ldrex/strex loops to simplify this, but it needs tidying up.
531  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
533  .forwardSwitchCondToPhi(true)
534  .convertSwitchToLookupTable(true)
535  .needCanonicalLoops(false)
536  .hoistCommonInsts(true)
537  .sinkCommonInsts(true)));
538 
539  // Run LoopDataPrefetch
540  //
541  // Run this before LSR to remove the multiplies involved in computing the
542  // pointer values N iterations ahead.
543  if (TM->getOptLevel() != CodeGenOpt::None) {
545  addPass(createLoopDataPrefetchPass());
548  }
549 
551 
553  /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None));
554 
555  // Match interleaved memory accesses to ldN/stN intrinsics.
556  if (TM->getOptLevel() != CodeGenOpt::None) {
558  addPass(createInterleavedAccessPass());
559  }
560 
561  if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
562  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
563  // and lower a GEP with multiple indices to either arithmetic operations or
564  // multiple GEPs with single index.
566  // Call EarlyCSE pass to find and remove subexpressions in the lowered
567  // result.
568  addPass(createEarlyCSEPass());
569  // Do loop invariant code motion in case part of the lowered result is
570  // invariant.
571  addPass(createLICMPass());
572  }
573 
574  // Add Control Flow Guard checks.
575  if (TM->getTargetTriple().isOSWindows())
576  addPass(createCFGuardCheckPass());
577 }
578 
579 // Pass Pipeline Configuration
580 bool AArch64PassConfig::addPreISel() {
581  // Run promote constant before global merge, so that the promoted constants
582  // get a chance to be merged
583  if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
585  // FIXME: On AArch64, this depends on the type.
586  // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
587  // and the offset has to be a multiple of the related size in bytes.
588  if ((TM->getOptLevel() != CodeGenOpt::None &&
591  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
593 
594  // Merging of extern globals is enabled by default on non-Mach-O as we
595  // expect it to be generally either beneficial or harmless. On Mach-O it
596  // is disabled as we emit the .subsections_via_symbols directive which
597  // means that merging extern globals is not safe.
598  bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
599 
600  // FIXME: extern global merging is only enabled when we optimise for size
601  // because there are some regressions with it also enabled for performance.
602  if (!OnlyOptimizeForSize)
603  MergeExternalByDefault = false;
604 
605  addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
606  MergeExternalByDefault));
607  }
608 
609  return false;
610 }
611 
612 void AArch64PassConfig::addCodeGenPrepare() {
613  if (getOptLevel() != CodeGenOpt::None)
614  addPass(createTypePromotionPass());
616 }
617 
618 bool AArch64PassConfig::addInstSelector() {
619  addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
620 
621  // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
622  // references to _TLS_MODULE_BASE_ as possible.
623  if (TM->getTargetTriple().isOSBinFormatELF() &&
624  getOptLevel() != CodeGenOpt::None)
626 
627  return false;
628 }
629 
630 bool AArch64PassConfig::addIRTranslator() {
631  addPass(new IRTranslator(getOptLevel()));
632  return false;
633 }
634 
635 void AArch64PassConfig::addPreLegalizeMachineIR() {
636  if (getOptLevel() == CodeGenOpt::None)
638  else {
641  addPass(new LoadStoreOpt());
642  }
643 }
644 
645 bool AArch64PassConfig::addLegalizeMachineIR() {
646  addPass(new Legalizer());
647  return false;
648 }
649 
650 void AArch64PassConfig::addPreRegBankSelect() {
651  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
652  if (!IsOptNone) {
653  addPass(createAArch64PostLegalizerCombiner(IsOptNone));
655  addPass(new LoadStoreOpt());
656  }
658 }
659 
660 bool AArch64PassConfig::addRegBankSelect() {
661  addPass(new RegBankSelect());
662  return false;
663 }
664 
665 void AArch64PassConfig::addPreGlobalInstructionSelect() {
666  addPass(new Localizer());
667 }
668 
669 bool AArch64PassConfig::addGlobalInstructionSelect() {
670  addPass(new InstructionSelect(getOptLevel()));
671  if (getOptLevel() != CodeGenOpt::None)
673  return false;
674 }
675 
676 void AArch64PassConfig::addMachineSSAOptimization() {
677  // Run default MachineSSAOptimization first.
679 
680  if (TM->getOptLevel() != CodeGenOpt::None)
682 }
683 
684 bool AArch64PassConfig::addILPOpts() {
685  if (EnableCondOpt)
687  if (EnableCCMP)
689  if (EnableMCR)
690  addPass(&MachineCombinerID);
691  if (EnableCondBrTuning)
692  addPass(createAArch64CondBrTuning());
694  addPass(&EarlyIfConverterID);
698  if (TM->getOptLevel() != CodeGenOpt::None)
700  return true;
701 }
702 
703 void AArch64PassConfig::addPreRegAlloc() {
704  // Change dead register definitions to refer to the zero register.
705  if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
707 
708  // Use AdvSIMD scalar instructions whenever profitable.
709  if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
710  addPass(createAArch64AdvSIMDScalar());
711  // The AdvSIMD pass may produce copies that can be rewritten to
712  // be register coalescer friendly.
713  addPass(&PeepholeOptimizerID);
714  }
715 }
716 
717 void AArch64PassConfig::addPostRegAlloc() {
718  // Remove redundant copy instructions.
719  if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
721 
722  if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
723  // Improve performance for some FP/SIMD code for A57.
725 }
726 
727 void AArch64PassConfig::addPreSched2() {
728  // Lower homogeneous frame instructions
731  // Expand some pseudo instructions to allow proper scheduling.
733  // Use load/store pair instructions when possible.
734  if (TM->getOptLevel() != CodeGenOpt::None) {
735  if (EnableLoadStoreOpt)
737  }
738 
739  // The AArch64SpeculationHardeningPass destroys dominator tree and natural
740  // loop info, which is needed for the FalkorHWPFFixPass and also later on.
741  // Therefore, run the AArch64SpeculationHardeningPass before the
742  // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
743  // info.
745 
746  addPass(createAArch64IndirectThunks());
748 
749  if (TM->getOptLevel() != CodeGenOpt::None) {
751  addPass(createFalkorHWPFFixPass());
752  }
753 }
754 
755 void AArch64PassConfig::addPreEmitPass() {
756  // Machine Block Placement might have created new opportunities when run
757  // at O3, where the Tail Duplication Threshold is set to 4 instructions.
758  // Run the load/store optimizer once more.
759  if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
761 
762  addPass(createAArch64A53Fix835769());
763 
766 
767  // Relax conditional branch instructions if they're otherwise out of
768  // range of their destination.
769  if (BranchRelaxation)
770  addPass(&BranchRelaxationPassID);
771 
772  if (TM->getTargetTriple().isOSWindows()) {
773  // Identify valid longjmp targets for Windows Control Flow Guard.
774  addPass(createCFGuardLongjmpPass());
775  // Identify valid eh continuation targets for Windows EHCont Guard.
777  }
778 
779  if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
781 
782  if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
783  TM->getTargetTriple().isOSBinFormatMachO())
784  addPass(createAArch64CollectLOHPass());
785 }
786 
787 void AArch64PassConfig::addPreEmitPass2() {
788  // SVE bundles move prefixes with destructive operations. BLR_RVMARKER pseudo
789  // instructions are lowered to bundles as well.
790  addPass(createUnpackMachineBundles(nullptr));
791 }
792 
795  return new yaml::AArch64FunctionInfo();
796 }
797 
800  const auto *MFI = MF.getInfo<AArch64FunctionInfo>();
801  return new yaml::AArch64FunctionInfo(*MFI);
802 }
803 
806  SMDiagnostic &Error, SMRange &SourceRange) const {
807  const auto &YamlMFI =
808  reinterpret_cast<const yaml::AArch64FunctionInfo &>(MFI);
809  MachineFunction &MF = PFS.MF;
810  MF.getInfo<AArch64FunctionInfo>()->initializeBaseYamlFields(YamlMFI);
811  return false;
812 }
llvm::initializeAArch64A57FPLoadBalancingPass
void initializeAArch64A57FPLoadBalancingPass(PassRegistry &)
computeDefaultCPU
static StringRef computeDefaultCPU(const Triple &TT, StringRef CPU)
Definition: AArch64TargetMachine.cpp:254
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: AArch64TargetMachine.cpp:228
llvm::TargetMachine::getOptLevel
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
Definition: TargetMachine.cpp:188
EnableBranchTargets
static cl::opt< bool > EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden, cl::desc("Enable the AArch64 branch target pass"), cl::init(true))
EnableStPairSuppress
static cl::opt< bool > EnableStPairSuppress("aarch64-enable-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden)
llvm::createAArch64LowerHomogeneousPrologEpilogPass
ModulePass * createAArch64LowerHomogeneousPrologEpilogPass()
Definition: AArch64LowerHomogeneousPrologEpilog.cpp:612
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
AArch64MachineFunctionInfo.h
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:168
llvm::initializeAArch64StackTaggingPass
void initializeAArch64StackTaggingPass(PassRegistry &)
llvm::createSeparateConstOffsetFromGEPPass
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Definition: SeparateConstOffsetFromGEP.cpp:499
AArch64.h
llvm::Triple::GNUILP32
@ GNUILP32
Definition: Triple.h:219
llvm::createAArch64PromoteConstantPass
ModulePass * createAArch64PromoteConstantPass()
Definition: AArch64PromoteConstant.cpp:235
MCTargetOptions.h
llvm::PeepholeOptimizerID
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
Definition: PeepholeOptimizer.cpp:443
llvm::initializeAArch64BranchTargetsPass
void initializeAArch64BranchTargetsPass(PassRegistry &)
llvm::TargetOptions
Definition: TargetOptions.h:124
Scalar.h
T
llvm::initializeAArch64O0PreLegalizerCombinerPass
void initializeAArch64O0PreLegalizerCombinerPass(PassRegistry &)
llvm::Function
Definition: Function.h:62
llvm::Attribute
Definition: Attributes.h:52
Pass.h
llvm::yaml::MachineFunctionInfo
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
Definition: MIRYamlMapping.h:673
EnableGlobalISelAtO
static cl::opt< int > EnableGlobalISelAtO("aarch64-enable-global-isel-at-O", cl::Hidden, cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"), cl::init(0))
CSEConfigBase.h
llvm::createAArch64SpeculationHardeningPass
FunctionPass * createAArch64SpeculationHardeningPass()
Returns an instance of the pseudo instruction expansion pass.
Definition: AArch64SpeculationHardening.cpp:700
llvm::createCFGSimplificationPass
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
Definition: SimplifyCFGPass.cpp:426
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
EnableRedundantCopyElimination
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
llvm::RISCVFenceField::W
@ W
Definition: RISCVBaseInfo.h:208
EnableCompressJumpTables
static cl::opt< bool > EnableCompressJumpTables("aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true), cl::desc("Use smallest entry possible for jump tables"))
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::initializeAArch64DeadRegisterDefinitionsPass
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
llvm::createAArch64CondBrTuning
FunctionPass * createAArch64CondBrTuning()
Definition: AArch64CondBrTuning.cpp:322
llvm::getTheAArch64_32Target
Target & getTheAArch64_32Target()
Definition: AArch64TargetInfo.cpp:21
llvm::AArch64beTargetMachine::AArch64beTargetMachine
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AArch64TargetMachine.cpp:436
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::createEarlyCSEPass
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1746
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::createAArch64DeadRegisterDefinitions
FunctionPass * createAArch64DeadRegisterDefinitions()
Definition: AArch64DeadRegisterDefinitionsPass.cpp:201
llvm::createAArch64BranchTargetsPass
FunctionPass * createAArch64BranchTargetsPass()
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1886
EnableAdvSIMDScalar
static cl::opt< bool > EnableAdvSIMDScalar("aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden)
EnableHomogeneousPrologEpilog
cl::opt< bool > EnableHomogeneousPrologEpilog
llvm::TargetMachine::setSupportsDefaultOutlining
void setSupportsDefaultOutlining(bool Enable)
Definition: TargetMachine.h:256
llvm::AArch64TargetMachine::convertFuncInfoToYAML
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
Definition: AArch64TargetMachine.cpp:799
llvm::initializeAArch64CompressJumpTablesPass
void initializeAArch64CompressJumpTablesPass(PassRegistry &)
llvm::TargetOptions::TrapUnreachable
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Definition: TargetOptions.h:274
llvm::initializeAArch64A53Fix835769Pass
void initializeAArch64A53Fix835769Pass(PassRegistry &)
InstructionSelect.h
llvm::createSVEIntrinsicOptsPass
ModulePass * createSVEIntrinsicOptsPass()
Definition: SVEIntrinsicOpts.cpp:79
llvm::Optional< Reloc::Model >
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
llvm::createAArch64A57FPLoadBalancing
FunctionPass * createAArch64A57FPLoadBalancing()
Definition: AArch64A57FPLoadBalancing.cpp:721
llvm::createAArch64PostSelectOptimize
FunctionPass * createAArch64PostSelectOptimize()
Definition: AArch64PostSelectOptimize.cpp:195
llvm::initializeAArch64LowerHomogeneousPrologEpilogPass
void initializeAArch64LowerHomogeneousPrologEpilogPass(PassRegistry &)
llvm::initializeAArch64SIMDInstrOptPass
void initializeAArch64SIMDInstrOptPass(PassRegistry &)
llvm::createAArch64PreLegalizerCombiner
FunctionPass * createAArch64PreLegalizerCombiner()
Definition: AArch64PreLegalizerCombiner.cpp:486
STLExtras.h
llvm::initializeAArch64PromoteConstantPass
void initializeAArch64PromoteConstantPass(PassRegistry &)
llvm::createAArch64SIMDInstrOptPass
FunctionPass * createAArch64SIMDInstrOptPass()
Returns an instance of the high cost ASIMD instruction replacement optimization pass.
Definition: AArch64SIMDInstrOpt.cpp:738
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:28
llvm::Triple::aarch64_32
@ aarch64_32
Definition: Triple.h:53
llvm::createAArch64LoadStoreOptimizationPass
FunctionPass * createAArch64LoadStoreOptimizationPass()
createAArch64LoadStoreOptimizationPass - returns an instance of the load / store optimization pass.
Definition: AArch64LoadStoreOptimizer.cpp:2305
LLVMInitializeAArch64Target
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target()
Definition: AArch64TargetMachine.cpp:184
llvm::AArch64TargetMachine::SubtargetMap
StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap
Definition: AArch64TargetMachine.h:26
llvm::initializeFalkorHWPFFixPass
void initializeFalkorHWPFFixPass(PassRegistry &)
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::createAArch64A53Fix835769
FunctionPass * createAArch64A53Fix835769()
Definition: AArch64A53Fix835769.cpp:248
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
BranchRelaxation
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
CommandLine.h
llvm::createAArch64PostLegalizerLowering
FunctionPass * createAArch64PostLegalizerLowering()
Definition: AArch64PostLegalizerLowering.cpp:1067
AArch64TargetMachine.h
llvm::createEHContGuardCatchretPass
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::createAArch64CompressJumpTablesPass
FunctionPass * createAArch64CompressJumpTablesPass()
Definition: AArch64CompressJumpTables.cpp:186
llvm::TargetMachine::setMachineOutliner
void setMachineOutliner(bool Enable)
Definition: TargetMachine.h:253
llvm::initializeAArch64ExpandPseudoPass
void initializeAArch64ExpandPseudoPass(PassRegistry &)
llvm::getTheAArch64leTarget
Target & getTheAArch64leTarget()
Definition: AArch64TargetInfo.cpp:13
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:739
llvm::initializeAArch64StorePairSuppressPass
void initializeAArch64StorePairSuppressPass(PassRegistry &)
llvm::Legalizer
Definition: Legalizer.h:30
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
EnableFalkorHWPFFix
static cl::opt< bool > EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix", cl::init(true), cl::Hidden)
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::SMDiagnostic
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:251
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:481
llvm::createAArch64StorePairSuppressPass
FunctionPass * createAArch64StorePairSuppressPass()
false
Definition: StackSlotColoring.cpp:142
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:784
llvm::createGenericSchedPostRA
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Definition: MachineScheduler.cpp:3649
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
EnableAtomicTidy
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::Attribute::getVScaleRangeMin
unsigned getVScaleRangeMin() const
Returns the minimum value for the vscale_range attribute.
Definition: Attributes.cpp:360
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:31
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1275
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:323
AArch64TargetObjectFile.h
llvm::AArch64TargetMachine
Definition: AArch64TargetMachine.h:23
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::createAArch64ISelDag
FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOpt::Level OptLevel)
createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG,...
Definition: AArch64ISelDAGToDAG.cpp:4968
EnableCollectLOH
static cl::opt< bool > EnableCollectLOH("aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden)
llvm::LoadStoreOpt
Definition: LoadStoreOpt.h:61
llvm::initializeAArch64SLSHardeningPass
void initializeAArch64SLSHardeningPass(PassRegistry &)
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:101
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:244
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
llvm::createAArch64IndirectThunks
FunctionPass * createAArch64IndirectThunks()
Definition: AArch64SLSHardening.cpp:434
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
AArch64MacroFusion.h
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
llvm::AArch64TargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: AArch64TargetMachine.cpp:507
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::cl::opt< bool >
llvm::createFalkorHWPFFixPass
FunctionPass * createFalkorHWPFFixPass()
Definition: AArch64FalkorHWPFFix.cpp:839
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:99
getEffectiveAArch64CodeModel
static CodeModel::Model getEffectiveAArch64CodeModel(const Triple &TT, Optional< CodeModel::Model > CM, bool JIT)
Definition: AArch64TargetMachine.cpp:274
llvm::cl::BOU_UNSET
@ BOU_UNSET
Definition: CommandLine.h:623
llvm::initializeAArch64ConditionalComparesPass
void initializeAArch64ConditionalComparesPass(PassRegistry &)
llvm::initializeAArch64SpeculationHardeningPass
void initializeAArch64SpeculationHardeningPass(PassRegistry &)
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:152
llvm::AArch64TTIImpl
Definition: AArch64TargetTransformInfo.h:41
llvm::Attribute::getVScaleRangeMax
Optional< unsigned > getVScaleRangeMax() const
Returns the maximum value for the vscale_range attribute or None when unknown.
Definition: Attributes.cpp:366
EnableGISelLoadStoreOptPostLegal
static cl::opt< bool > EnableGISelLoadStoreOptPostLegal("aarch64-enable-gisel-ldst-postlegal", cl::desc("Enable GlobalISel's post-legalizer load/store optimization pass"), cl::init(false), cl::Hidden)
llvm::initializeAArch64PostSelectOptimizePass
void initializeAArch64PostSelectOptimizePass(PassRegistry &)
CFGuard.h
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3492
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:136
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
EnableGlobalMerge
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
llvm::createAArch64ExpandPseudoPass
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
Definition: AArch64ExpandPseudoInsts.cpp:1263
llvm::createAArch64RedundantCopyEliminationPass
FunctionPass * createAArch64RedundantCopyEliminationPass()
Definition: AArch64RedundantCopyElimination.cpp:495
llvm::initializeAArch64CollectLOHPass
void initializeAArch64CollectLOHPass(PassRegistry &)
llvm::initializeAArch64PostLegalizerLoweringPass
void initializeAArch64PostLegalizerLoweringPass(PassRegistry &)
LoadStoreOpt.h
computeDataLayout
static std::string computeDataLayout(const Triple &TT, const MCTargetOptions &Options, bool LittleEndian)
Definition: AArch64TargetMachine.cpp:238
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:125
EnableMCR
static cl::opt< bool > EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
llvm::AArch64FunctionInfo
AArch64FunctionInfo - This class is derived from MachineFunctionInfo and contains private AArch64-spe...
Definition: AArch64MachineFunctionInfo.h:37
llvm::TargetOptions::NoTrapAfterNoreturn
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
Definition: TargetOptions.h:278
llvm::initializeAArch64AdvSIMDScalarPass
void initializeAArch64AdvSIMDScalarPass(PassRegistry &)
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:844
llvm::createUnpackMachineBundles
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
Definition: MachineInstrBundle.cpp:80
EnableEarlyIfConversion
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
EnableCondBrTuning
static cl::opt< bool > EnableCondBrTuning("aarch64-enable-cond-br-tune", cl::desc("Enable the conditional branch tuning pass"), cl::init(true), cl::Hidden)
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
TargetPassConfig.h
Localizer.h
llvm::createAArch64MIPeepholeOptPass
FunctionPass * createAArch64MIPeepholeOptPass()
Definition: AArch64MIPeepholeOpt.cpp:429
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:973
llvm::initializeAArch64PreLegalizerCombinerPass
void initializeAArch64PreLegalizerCombinerPass(PassRegistry &)
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::createTypePromotionPass
FunctionPass * createTypePromotionPass()
Create IR Type Promotion pass.
Definition: TypePromotion.cpp:959
llvm::createAArch64PostLegalizerCombiner
FunctionPass * createAArch64PostLegalizerCombiner(bool IsOptNone)
Definition: AArch64PostLegalizerCombiner.cpp:446
llvm::TargetOptions::TLSSize
unsigned TLSSize
Bit size of immediate TLS offsets (0 == use the default).
Definition: TargetOptions.h:281
llvm::createCFGuardCheckPass
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:300
llvm::initializeLDTLSCleanupPass
void initializeLDTLSCleanupPass(PassRegistry &)
EnableLoadStoreOpt
static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden)
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::MCTargetOptions
Definition: MCTargetOptions.h:36
llvm::Reloc::DynamicNoPIC
@ DynamicNoPIC
Definition: CodeGen.h:22
llvm::MachineFunction
Definition: MachineFunction.h:241
Triple.h
llvm::getTheARM64_32Target
Target & getTheARM64_32Target()
Definition: AArch64TargetInfo.cpp:29
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:480
EnableGEPOpt
static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))
llvm::TargetMachine::getMCAsmInfo
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
Definition: TargetMachine.h:208
llvm::initializeAArch64StackTaggingPreRAPass
void initializeAArch64StackTaggingPreRAPass(PassRegistry &)
llvm::initializeAArch64PostLegalizerCombinerPass
void initializeAArch64PostLegalizerCombinerPass(PassRegistry &)
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
llvm::createAArch64SLSHardeningPass
FunctionPass * createAArch64SLSHardeningPass()
Definition: AArch64SLSHardening.cpp:394
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::createAArch64StackTaggingPreRAPass
FunctionPass * createAArch64StackTaggingPreRAPass()
Definition: AArch64StackTaggingPreRA.cpp:99
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:74
IRTranslator.h
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
EnableSVEIntrinsicOpts
static cl::opt< bool > EnableSVEIntrinsicOpts("aarch64-enable-sve-intrinsic-opts", cl::Hidden, cl::desc("Enable SVE intrinsic opts"), cl::init(true))
AArch64TargetTransformInfo.h
llvm::createInterleavedAccessPass
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
Definition: InterleavedAccessPass.cpp:145
llvm::AArch64TargetMachine::parseMachineFunctionInfo
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
Definition: AArch64TargetMachine.cpp:804
Attributes.h
llvm::PerFunctionMIParsingState
Definition: MIParser.h:162
llvm::initializeAArch64MIPeepholeOptPass
void initializeAArch64MIPeepholeOptPass(PassRegistry &)
llvm::initializeAArch64RedundantCopyEliminationPass
void initializeAArch64RedundantCopyEliminationPass(PassRegistry &)
llvm::initializeFalkorMarkStridedAccessesLegacyPass
void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry &)
llvm::initializeAArch64LoadStoreOptPass
void initializeAArch64LoadStoreOptPass(PassRegistry &)
llvm::TargetMachine::setGlobalISelAbort
void setGlobalISelAbort(GlobalISelAbortMode Mode)
Definition: TargetMachine.h:250
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1277
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:156
llvm::createLoadClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1576
RegBankSelect.h
llvm::createAArch64MacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createAArch64MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAArch64MacroFusionDAGMutation()); to AArch64PassConf...
Definition: AArch64MacroFusion.cpp:413
EnableCondOpt
static cl::opt< bool > EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)
Function.h
llvm::getTheAArch64beTarget
Target & getTheAArch64beTarget()
Definition: AArch64TargetInfo.cpp:17
llvm::createAArch64CollectLOHPass
FunctionPass * createAArch64CollectLOHPass()
Definition: AArch64CollectLOH.cpp:597
llvm::createAArch64O0PreLegalizerCombiner
FunctionPass * createAArch64O0PreLegalizerCombiner()
Definition: AArch64O0PreLegalizerCombiner.cpp:170
llvm::TargetMachine::getCodeModel
CodeModel::Model getCodeModel() const
Returns the code model.
Definition: TargetMachine.cpp:74
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:406
AArch64MCTargetDesc.h
llvm::initializeSVEIntrinsicOptsPass
void initializeSVEIntrinsicOptsPass(PassRegistry &)
llvm::TargetMachine::setGlobalISel
void setGlobalISel(bool Enable)
Definition: TargetMachine.h:249
llvm::PerFunctionMIParsingState::MF
MachineFunction & MF
Definition: MIParser.h:164
llvm::AArch64TargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: AArch64TargetMachine.cpp:511
llvm::createGlobalMergePass
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
Definition: GlobalMerge.cpp:678
llvm::BranchRelaxationPassID
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
Definition: BranchRelaxation.cpp:119
EnableLoopDataPrefetch
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
CodeGen.h
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
EnableCCMP
static cl::opt< bool > EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)
llvm::cl::BOU_TRUE
@ BOU_TRUE
Definition: CommandLine.h:623
Legalizer.h
llvm::SimplifyCFGOptions
Definition: SimplifyCFGOptions.h:23
llvm::createLICMPass
Pass * createLICMPass()
Definition: LICM.cpp:322
MachineScheduler.h
AArch64Subtarget.h
EnableDeadRegisterElimination
static cl::opt< bool > EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to the zero" " register"), cl::init(true))
llvm::createAArch64AdvSIMDScalar
FunctionPass * createAArch64AdvSIMDScalar()
Definition: AArch64AdvSIMDScalarPass.cpp:409
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:199
SVEVectorBitsMinOpt
static cl::opt< unsigned > SVEVectorBitsMinOpt("aarch64-sve-vector-bits-min", cl::desc("Assume SVE vector registers are at least this big, " "with zero meaning no minimum size is assumed."), cl::init(0), cl::Hidden)
llvm::createAArch64StackTaggingPass
FunctionPass * createAArch64StackTaggingPass(bool IsOptNone)
Definition: AArch64StackTagging.cpp:353
llvm::SMRange
Represents a range in source code.
Definition: SMLoc.h:48
llvm::getTheARM64Target
Target & getTheARM64Target()
Definition: AArch64TargetInfo.cpp:25
llvm::createAArch64ConditionOptimizerPass
FunctionPass * createAArch64ConditionOptimizerPass()
Definition: AArch64ConditionOptimizer.cpp:133
llvm::to_string
std::string to_string(const T &Value)
Definition: ScopedPrinter.h:87
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
llvm::MachineCombinerID
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
Definition: MachineCombiner.cpp:130
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::createStoreClusterDAGMutation
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1583
llvm::IRTranslator
Definition: IRTranslator.h:63
llvm::GlobalISelAbortMode::Disable
@ Disable
EnablePromoteConstant
static cl::opt< bool > EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden)
llvm::AArch64TargetMachine::AArch64TargetMachine
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT, bool IsLittleEndian)
Create an AArch64 architecture model.
Definition: AArch64TargetMachine.cpp:298
llvm::initializeAArch64ConditionOptimizerPass
void initializeAArch64ConditionOptimizerPass(PassRegistry &)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::createInterleavedLoadCombinePass
FunctionPass * createInterleavedLoadCombinePass()
InterleavedLoadCombines Pass - This pass identifies interleaved loads and combines them into wide loa...
Definition: InterleavedLoadCombinePass.cpp:1363
llvm::TargetMachine::setSupportsDebugEntryValues
void setSupportsDebugEntryValues(bool Enable)
Definition: TargetMachine.h:259
llvm::createAArch64CleanupLocalDynamicTLSPass
FunctionPass * createAArch64CleanupLocalDynamicTLSPass()
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:245
llvm::cl::desc
Definition: CommandLine.h:412
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:390
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::AArch64Subtarget
Definition: AArch64Subtarget.h:38
llvm::createAArch64ConditionalCompares
FunctionPass * createAArch64ConditionalCompares()
Definition: AArch64ConditionalCompares.cpp:805
llvm::createFalkorMarkStridedAccessesPass
FunctionPass * createFalkorMarkStridedAccessesPass()
Definition: AArch64FalkorHWPFFix.cpp:116
TargetRegistry.h
llvm::AArch64TargetMachine::createDefaultFuncInfoYAML
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
Definition: AArch64TargetMachine.cpp:794
InitializePasses.h
SVEVectorBitsMaxOpt
static cl::opt< unsigned > SVEVectorBitsMaxOpt("aarch64-sve-vector-bits-max", cl::desc("Assume SVE vector registers are at most this big, " "with zero meaning no maximum size is assumed."), cl::init(0), cl::Hidden)
llvm::AArch64leTargetMachine::AArch64leTargetMachine
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: AArch64TargetMachine.cpp:428
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:100
llvm::Optional::getValue
constexpr const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:282
llvm::yaml::AArch64FunctionInfo
Definition: AArch64MachineFunctionInfo.h:420
EnableGISelLoadStoreOptPreLegal
static cl::opt< bool > EnableGISelLoadStoreOptPreLegal("aarch64-enable-gisel-ldst-prelegal", cl::desc("Enable GlobalISel's pre-legalizer load/store optimization pass"), cl::init(true), cl::Hidden)
llvm::createLoopDataPrefetchPass
FunctionPass * createLoopDataPrefetchPass()
Definition: LoopDataPrefetch.cpp:155
MIParser.h
AArch64TargetInfo.h
llvm::createCFGuardLongjmpPass
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
llvm::AArch64TargetMachine::~AArch64TargetMachine
~AArch64TargetMachine() override
llvm::Localizer
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:40
llvm::AArch64TargetMachine::getSubtargetImpl
const AArch64Subtarget * getSubtargetImpl() const =delete