LLVM  13.0.0git
M68kInstrInfo.cpp
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1 //===-- M68kInstrInfo.cpp - M68k Instruction Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file contains the M68k declaration of the TargetInstrInfo class.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "M68kInstrInfo.h"
15 
16 #include "M68kInstrBuilder.h"
17 #include "M68kMachineFunction.h"
18 #include "M68kTargetMachine.h"
20 
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/ScopeExit.h"
29 
30 #include <functional>
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "M68k-instr-info"
35 
36 #define GET_INSTRINFO_CTOR_DTOR
37 #include "M68kGenInstrInfo.inc"
38 
39 // Pin the vtable to this file.
40 void M68kInstrInfo::anchor() {}
41 
43  : M68kGenInstrInfo(M68k::ADJCALLSTACKDOWN, M68k::ADJCALLSTACKUP, 0,
44  M68k::RET),
45  Subtarget(STI), RI(STI) {}
46 
47 static M68k::CondCode getCondFromBranchOpc(unsigned BrOpc) {
48  switch (BrOpc) {
49  default:
50  return M68k::COND_INVALID;
51  case M68k::Beq8:
52  return M68k::COND_EQ;
53  case M68k::Bne8:
54  return M68k::COND_NE;
55  case M68k::Blt8:
56  return M68k::COND_LT;
57  case M68k::Ble8:
58  return M68k::COND_LE;
59  case M68k::Bgt8:
60  return M68k::COND_GT;
61  case M68k::Bge8:
62  return M68k::COND_GE;
63  case M68k::Bcs8:
64  return M68k::COND_CS;
65  case M68k::Bls8:
66  return M68k::COND_LS;
67  case M68k::Bhi8:
68  return M68k::COND_HI;
69  case M68k::Bcc8:
70  return M68k::COND_CC;
71  case M68k::Bmi8:
72  return M68k::COND_MI;
73  case M68k::Bpl8:
74  return M68k::COND_PL;
75  case M68k::Bvs8:
76  return M68k::COND_VS;
77  case M68k::Bvc8:
78  return M68k::COND_VC;
79  }
80 }
81 
83  MachineBasicBlock *&TBB,
84  MachineBasicBlock *&FBB,
86  bool AllowModify) const {
87 
88  auto UncondBranch =
89  std::pair<MachineBasicBlock::reverse_iterator, MachineBasicBlock *>{
90  MBB.rend(), nullptr};
91 
92  // Erase any instructions if allowed at the end of the scope.
93  std::vector<std::reference_wrapper<llvm::MachineInstr>> EraseList;
94  auto FinalizeOnReturn = llvm::make_scope_exit([&EraseList] {
95  std::for_each(EraseList.begin(), EraseList.end(),
96  [](auto &ref) { ref.get().eraseFromParent(); });
97  });
98 
99  // Start from the bottom of the block and work up, examining the
100  // terminator instructions.
101  for (auto iter = MBB.rbegin(); iter != MBB.rend(); iter = std::next(iter)) {
102 
103  unsigned Opcode = iter->getOpcode();
104 
105  if (iter->isDebugInstr())
106  continue;
107 
108  // Working from the bottom, when we see a non-terminator instruction, we're
109  // done.
110  if (!isUnpredicatedTerminator(*iter))
111  break;
112 
113  // A terminator that isn't a branch can't easily be handled by this
114  // analysis.
115  if (!iter->isBranch())
116  return true;
117 
118  // Handle unconditional branches.
119  if (Opcode == M68k::BRA8 || Opcode == M68k::BRA16) {
120  if (!iter->getOperand(0).isMBB())
121  return true;
122  UncondBranch = {iter, iter->getOperand(0).getMBB()};
123 
124  // TBB is used to indicate the unconditional destination.
125  TBB = UncondBranch.second;
126 
127  if (!AllowModify)
128  continue;
129 
130  // If the block has any instructions after a JMP, erase them.
131  EraseList.insert(EraseList.begin(), MBB.rbegin(), iter);
132 
133  Cond.clear();
134  FBB = nullptr;
135 
136  // Erase the JMP if it's equivalent to a fall-through.
137  if (MBB.isLayoutSuccessor(UncondBranch.second)) {
138  TBB = nullptr;
139  EraseList.push_back(*iter);
140  UncondBranch = {MBB.rend(), nullptr};
141  }
142 
143  continue;
144  }
145 
146  // Handle conditional branches.
147  auto BranchCode = M68k::GetCondFromBranchOpc(Opcode);
148 
149  // Can't handle indirect branch.
150  if (BranchCode == M68k::COND_INVALID)
151  return true;
152 
153  // In practice we should never have an undef CCR operand, if we do
154  // abort here as we are not prepared to preserve the flag.
155  // ??? Is this required?
156  // if (iter->getOperand(1).isUndef())
157  // return true;
158 
159  // Working from the bottom, handle the first conditional branch.
160  if (Cond.empty()) {
161  if (!iter->getOperand(0).isMBB())
162  return true;
163  MachineBasicBlock *CondBranchTarget = iter->getOperand(0).getMBB();
164 
165  // If we see something like this:
166  //
167  // bcc l1
168  // bra l2
169  // ...
170  // l1:
171  // ...
172  // l2:
173  if (UncondBranch.first != MBB.rend()) {
174 
175  assert(std::next(UncondBranch.first) == iter && "Wrong block layout.");
176 
177  // And we are allowed to modify the block and the target block of the
178  // conditional branch is the direct successor of this block:
179  //
180  // bcc l1
181  // bra l2
182  // l1:
183  // ...
184  // l2:
185  //
186  // we change it to this if allowed:
187  //
188  // bncc l2
189  // l1:
190  // ...
191  // l2:
192  //
193  // Which is a bit more efficient.
194  if (AllowModify && MBB.isLayoutSuccessor(CondBranchTarget)) {
195 
196  BranchCode = GetOppositeBranchCondition(BranchCode);
197  unsigned BNCC = GetCondBranchFromCond(BranchCode);
198 
199  BuildMI(MBB, *UncondBranch.first, MBB.rfindDebugLoc(iter), get(BNCC))
200  .addMBB(UncondBranch.second);
201 
202  EraseList.push_back(*iter);
203  EraseList.push_back(*UncondBranch.first);
204 
205  TBB = UncondBranch.second;
206  FBB = nullptr;
207  Cond.push_back(MachineOperand::CreateImm(BranchCode));
208 
209  // Otherwise preserve TBB, FBB and Cond as requested
210  } else {
211  TBB = CondBranchTarget;
212  FBB = UncondBranch.second;
213  Cond.push_back(MachineOperand::CreateImm(BranchCode));
214  }
215 
216  UncondBranch = {MBB.rend(), nullptr};
217  continue;
218  }
219 
220  TBB = CondBranchTarget;
221  FBB = nullptr;
222  Cond.push_back(MachineOperand::CreateImm(BranchCode));
223 
224  continue;
225  }
226 
227  // Handle subsequent conditional branches. Only handle the case where all
228  // conditional branches branch to the same destination and their condition
229  // opcodes fit one of the special multi-branch idioms.
230  assert(Cond.size() == 1);
231  assert(TBB);
232 
233  // If the conditions are the same, we can leave them alone.
234  auto OldBranchCode = static_cast<M68k::CondCode>(Cond[0].getImm());
235  if (!iter->getOperand(0).isMBB())
236  return true;
237  auto NewTBB = iter->getOperand(0).getMBB();
238  if (OldBranchCode == BranchCode && TBB == NewTBB)
239  continue;
240 
241  // If they differ we cannot do much here.
242  return true;
243  }
244 
245  return false;
246 }
247 
249  MachineBasicBlock *&TBB,
250  MachineBasicBlock *&FBB,
252  bool AllowModify) const {
253  return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, AllowModify);
254 }
255 
257  int *BytesRemoved) const {
258  assert(!BytesRemoved && "code size not handled");
259 
261  unsigned Count = 0;
262 
263  while (I != MBB.begin()) {
264  --I;
265  if (I->isDebugValue())
266  continue;
267  if (I->getOpcode() != M68k::BRA8 &&
268  getCondFromBranchOpc(I->getOpcode()) == M68k::COND_INVALID)
269  break;
270  // Remove the branch.
271  I->eraseFromParent();
272  I = MBB.end();
273  ++Count;
274  }
275 
276  return Count;
277 }
278 
281  ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
282  // Shouldn't be a fall through.
283  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
284  assert((Cond.size() == 1 || Cond.size() == 0) &&
285  "M68k branch conditions have one component!");
286  assert(!BytesAdded && "code size not handled");
287 
288  if (Cond.empty()) {
289  // Unconditional branch?
290  assert(!FBB && "Unconditional branch with multiple successors!");
291  BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(TBB);
292  return 1;
293  }
294 
295  // If FBB is null, it is implied to be a fall-through block.
296  bool FallThru = FBB == nullptr;
297 
298  // Conditional branch.
299  unsigned Count = 0;
300  M68k::CondCode CC = (M68k::CondCode)Cond[0].getImm();
301  unsigned Opc = GetCondBranchFromCond(CC);
302  BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
303  ++Count;
304  if (!FallThru) {
305  // Two-way Conditional branch. Insert the second branch.
306  BuildMI(&MBB, DL, get(M68k::BRA8)).addMBB(FBB);
307  ++Count;
308  }
309  return Count;
310 }
311 
314  unsigned Reg, MVT From, MVT To) const {
315  if (From == MVT::i8) {
316  unsigned R = Reg;
317  // EXT16 requires i16 register
318  if (To == MVT::i32) {
319  R = RI.getSubReg(Reg, M68k::MxSubRegIndex16Lo);
320  assert(R && "No viable SUB register available");
321  }
322  BuildMI(MBB, I, DL, get(M68k::EXT16), R).addReg(R);
323  }
324 
325  if (To == MVT::i32)
326  BuildMI(MBB, I, DL, get(M68k::EXT32), Reg).addReg(Reg);
327 }
328 
331  unsigned Reg, MVT From, MVT To) const {
332 
333  unsigned Mask, And;
334  if (From == MVT::i8)
335  Mask = 0xFF;
336  else
337  Mask = 0xFFFF;
338 
339  if (To == MVT::i16)
340  And = M68k::AND16di;
341  else // i32
342  And = M68k::AND32di;
343 
344  // TODO use xor r,r to decrease size
346 }
347 
349  MVT MVTSrc) const {
350  unsigned Move = MVTDst == MVT::i16 ? M68k::MOV16rr : M68k::MOV32rr;
351  unsigned Dst = MIB->getOperand(0).getReg();
352  unsigned Src = MIB->getOperand(1).getReg();
353 
354  assert(Dst != Src && "You cannot use the same Regs with MOVX_RR");
355 
356  const auto &TRI = getRegisterInfo();
357 
358  const auto *RCDst = TRI.getMaximalPhysRegClass(Dst, MVTDst);
359  const auto *RCSrc = TRI.getMaximalPhysRegClass(Src, MVTSrc);
360 
361  assert(RCDst && RCSrc && "Wrong use of MOVX_RR");
362  assert(RCDst != RCSrc && "You cannot use the same Reg Classes with MOVX_RR");
363 
364  // We need to find the super source register that matches the size of Dst
365  unsigned SSrc = RI.getMatchingMegaReg(Src, RCDst);
366  assert(SSrc && "No viable MEGA register available");
367 
368  DebugLoc DL = MIB->getDebugLoc();
369 
370  // If it happens to that super source register is the destination register
371  // we do nothing
372  if (Dst == SSrc) {
373  LLVM_DEBUG(dbgs() << "Remove " << *MIB.getInstr() << '\n');
374  MIB->eraseFromParent();
375  } else { // otherwise we need to MOV
376  LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to MOV\n");
377  MIB->setDesc(get(Move));
378  MIB->getOperand(1).setReg(SSrc);
379  }
380 
381  return true;
382 }
383 
384 /// Expand SExt MOVE pseudos into a MOV and a EXT if the operands are two
385 /// different registers or just EXT if it is the same register
387  MVT MVTDst, MVT MVTSrc) const {
388  LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to ");
389 
390  unsigned Move;
391 
392  if (MVTDst == MVT::i16)
393  Move = M68k::MOV16rr;
394  else // i32
395  Move = M68k::MOV32rr;
396 
397  unsigned Dst = MIB->getOperand(0).getReg();
398  unsigned Src = MIB->getOperand(1).getReg();
399 
400  assert(Dst != Src && "You cannot use the same Regs with MOVSX_RR");
401 
402  const auto &TRI = getRegisterInfo();
403 
404  const auto *RCDst = TRI.getMaximalPhysRegClass(Dst, MVTDst);
405  const auto *RCSrc = TRI.getMaximalPhysRegClass(Src, MVTSrc);
406 
407  assert(RCDst && RCSrc && "Wrong use of MOVSX_RR");
408  assert(RCDst != RCSrc && "You cannot use the same Reg Classes with MOVSX_RR");
409 
410  // We need to find the super source register that matches the size of Dst
411  unsigned SSrc = RI.getMatchingMegaReg(Src, RCDst);
412  assert(SSrc && "No viable MEGA register available");
413 
414  MachineBasicBlock &MBB = *MIB->getParent();
415  DebugLoc DL = MIB->getDebugLoc();
416 
417  if (Dst != SSrc) {
418  LLVM_DEBUG(dbgs() << "Move and " << '\n');
419  BuildMI(MBB, MIB.getInstr(), DL, get(Move), Dst).addReg(SSrc);
420  }
421 
422  if (IsSigned) {
423  LLVM_DEBUG(dbgs() << "Sign Extend" << '\n');
424  AddSExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst);
425  } else {
426  LLVM_DEBUG(dbgs() << "Zero Extend" << '\n');
427  AddZExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst);
428  }
429 
430  MIB->eraseFromParent();
431 
432  return true;
433 }
434 
436  const MCInstrDesc &Desc, MVT MVTDst,
437  MVT MVTSrc) const {
438  LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to LOAD and ");
439 
440  unsigned Dst = MIB->getOperand(0).getReg();
441 
442  // We need the subreg of Dst to make instruction verifier happy because the
443  // real machine instruction consumes and produces values of the same size and
444  // the registers the will be used here fall into different classes and this
445  // makes IV cry. We could of course use bigger operation but this will put
446  // some pressure on cache and memory so no.
447  unsigned SubDst =
448  RI.getSubReg(Dst, MVTSrc == MVT::i8 ? M68k::MxSubRegIndex8Lo
449  : M68k::MxSubRegIndex16Lo);
450  assert(SubDst && "No viable SUB register available");
451 
452  // Make this a plain move
453  MIB->setDesc(Desc);
454  MIB->getOperand(0).setReg(SubDst);
455 
457  I++;
458  MachineBasicBlock &MBB = *MIB->getParent();
459  DebugLoc DL = MIB->getDebugLoc();
460 
461  if (IsSigned) {
462  LLVM_DEBUG(dbgs() << "Sign Extend" << '\n');
463  AddSExt(MBB, I, DL, Dst, MVTSrc, MVTDst);
464  } else {
465  LLVM_DEBUG(dbgs() << "Zero Extend" << '\n');
466  AddZExt(MBB, I, DL, Dst, MVTSrc, MVTDst);
467  }
468 
469  return true;
470 }
471 
473  const MCInstrDesc &Desc, bool IsPush) const {
475  I++;
476  MachineBasicBlock &MBB = *MIB->getParent();
477  MachineOperand MO = MIB->getOperand(0);
478  DebugLoc DL = MIB->getDebugLoc();
479  if (IsPush)
480  BuildMI(MBB, I, DL, Desc).addReg(RI.getStackRegister()).add(MO);
481  else
482  BuildMI(MBB, I, DL, Desc, MO.getReg()).addReg(RI.getStackRegister());
483 
484  MIB->eraseFromParent();
485  return true;
486 }
487 
488 bool M68kInstrInfo::ExpandCCR(MachineInstrBuilder &MIB, bool IsToCCR) const {
489 
490  // Replace the pseudo instruction with the real one
491  if (IsToCCR)
492  MIB->setDesc(get(M68k::MOV16cd));
493  else
494  // FIXME M68010 or later is required
495  MIB->setDesc(get(M68k::MOV16dc));
496 
497  // Promote used register to the next class
498  auto &Opd = MIB->getOperand(1);
499  Opd.setReg(getRegisterInfo().getMatchingSuperReg(
500  Opd.getReg(), M68k::MxSubRegIndex8Lo, &M68k::DR16RegClass));
501 
502  return true;
503 }
504 
506  const MCInstrDesc &Desc, bool IsRM) const {
507  int Reg = 0, Offset = 0, Base = 0;
508  auto XR32 = RI.getRegClass(M68k::XR32RegClassID);
509  auto DL = MIB->getDebugLoc();
510  auto MI = MIB.getInstr();
511  auto &MBB = *MIB->getParent();
512 
513  if (IsRM) {
514  Reg = MIB->getOperand(0).getReg();
515  Offset = MIB->getOperand(1).getImm();
516  Base = MIB->getOperand(2).getReg();
517  } else {
518  Offset = MIB->getOperand(0).getImm();
519  Base = MIB->getOperand(1).getReg();
520  Reg = MIB->getOperand(2).getReg();
521  }
522 
523  // If the register is not in XR32 then it is smaller than 32 bit, we
524  // implicitly promote it to 32
525  if (!XR32->contains(Reg)) {
526  Reg = RI.getMatchingMegaReg(Reg, XR32);
527  assert(Reg && "Has not meaningful MEGA register");
528  }
529 
530  unsigned Mask = 1 << RI.getSpillRegisterOrder(Reg);
531  if (IsRM) {
532  BuildMI(MBB, MI, DL, Desc)
533  .addImm(Mask)
534  .addImm(Offset)
535  .addReg(Base)
537  .copyImplicitOps(*MIB);
538  } else {
539  BuildMI(MBB, MI, DL, Desc)
540  .addImm(Offset)
541  .addReg(Base)
542  .addImm(Mask)
544  .copyImplicitOps(*MIB);
545  }
546 
547  MIB->eraseFromParent();
548 
549  return true;
550 }
551 
552 /// Expand a single-def pseudo instruction to a two-addr
553 /// instruction with two undef reads of the register being defined.
554 /// This is used for mapping:
555 /// %d0 = SETCS_C32d
556 /// to:
557 /// %d0 = SUBX32dd %d0<undef>, %d0<undef>
558 ///
560  const MCInstrDesc &Desc) {
561  assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
562  unsigned Reg = MIB->getOperand(0).getReg();
563  MIB->setDesc(Desc);
564 
565  // MachineInstr::addOperand() will insert explicit operands before any
566  // implicit operands.
568  // But we don't trust that.
569  assert(MIB->getOperand(1).getReg() == Reg &&
570  MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
571  return true;
572 }
573 
575  MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
576  switch (MI.getOpcode()) {
577  case M68k::PUSH8d:
578  return ExpandPUSH_POP(MIB, get(M68k::MOV8ed), true);
579  case M68k::PUSH16d:
580  return ExpandPUSH_POP(MIB, get(M68k::MOV16er), true);
581  case M68k::PUSH32r:
582  return ExpandPUSH_POP(MIB, get(M68k::MOV32er), true);
583 
584  case M68k::POP8d:
585  return ExpandPUSH_POP(MIB, get(M68k::MOV8do), false);
586  case M68k::POP16d:
587  return ExpandPUSH_POP(MIB, get(M68k::MOV16ro), false);
588  case M68k::POP32r:
589  return ExpandPUSH_POP(MIB, get(M68k::MOV32ro), false);
590 
591  case M68k::SETCS_C8d:
592  return Expand2AddrUndef(MIB, get(M68k::SUBX8dd));
593  case M68k::SETCS_C16d:
594  return Expand2AddrUndef(MIB, get(M68k::SUBX16dd));
595  case M68k::SETCS_C32d:
596  return Expand2AddrUndef(MIB, get(M68k::SUBX32dd));
597  }
598  return false;
599 }
600 
602  const MachineOperand &MO) const {
603  assert(MO.isReg());
604  const auto *MI = MO.getParent();
605  const uint8_t *Beads = M68k::getMCInstrBeads(MI->getOpcode());
606  assert(*Beads);
607 
608  // Only addressing mode k has (non-pc) register with PCRel
609  // So we're looking for EA Beads equal to
610  // `3Bits<011>_1Bit<1>_2Bits<11>`
611  // FIXME: There is an important caveat and two assumptions
612  // here: The caveat is that EA encoding always sit on the LSB.
613  // Where the assumptions are that if there are more than one
614  // operands, the EA encoding for the source operand always sit
615  // on the LSB. At the same time, k addressing mode can not be used
616  // on destination operand.
617  // The last assumption is kinda dirty so we need to find a way around
618  // it
619  const uint8_t EncEAk[3] = {0b011, 0b1, 0b11};
620  for (const uint8_t Pat : EncEAk) {
621  uint8_t Bead = *(Beads++);
622  if (!Bead)
623  return false;
624 
625  switch (Bead & 0xF) {
626  default:
627  return false;
628  case M68kBeads::Bits1:
629  case M68kBeads::Bits2:
630  case M68kBeads::Bits3: {
631  uint8_t Val = (Bead & 0xF0) >> 4;
632  if (Val != Pat)
633  return false;
634  }
635  }
636  }
637  return true;
638 }
639 
642  const DebugLoc &DL, MCRegister DstReg,
643  MCRegister SrcReg, bool KillSrc) const {
644  unsigned Opc = 0;
645 
646  // First deal with the normal symmetric copies.
647  if (M68k::XR32RegClass.contains(DstReg, SrcReg))
648  Opc = M68k::MOV32rr;
649  else if (M68k::XR16RegClass.contains(DstReg, SrcReg))
650  Opc = M68k::MOV16rr;
651  else if (M68k::DR8RegClass.contains(DstReg, SrcReg))
652  Opc = M68k::MOV8dd;
653 
654  if (Opc) {
655  BuildMI(MBB, MI, DL, get(Opc), DstReg)
656  .addReg(SrcReg, getKillRegState(KillSrc));
657  return;
658  }
659 
660  // Now deal with asymmetrically sized copies. The cases that follow are upcast
661  // moves.
662  //
663  // NOTE
664  // These moves are not aware of type nature of these values and thus
665  // won't do any SExt or ZExt and upper bits will basically contain garbage.
667  if (M68k::DR8RegClass.contains(SrcReg)) {
668  if (M68k::XR16RegClass.contains(DstReg))
669  Opc = M68k::MOVXd16d8;
670  else if (M68k::XR32RegClass.contains(DstReg))
671  Opc = M68k::MOVXd32d8;
672  } else if (M68k::XR16RegClass.contains(SrcReg) &&
673  M68k::XR32RegClass.contains(DstReg))
674  Opc = M68k::MOVXd32d16;
675 
676  if (Opc) {
677  BuildMI(MBB, MI, DL, get(Opc), DstReg)
678  .addReg(SrcReg, getKillRegState(KillSrc));
679  return;
680  }
681 
682  bool FromCCR = SrcReg == M68k::CCR;
683  bool FromSR = SrcReg == M68k::SR;
684  bool ToCCR = DstReg == M68k::CCR;
685  bool ToSR = DstReg == M68k::SR;
686 
687  if (FromCCR) {
688  assert(M68k::DR8RegClass.contains(DstReg) &&
689  "Need DR8 register to copy CCR");
690  Opc = M68k::MOV8dc;
691  } else if (ToCCR) {
692  assert(M68k::DR8RegClass.contains(SrcReg) &&
693  "Need DR8 register to copy CCR");
694  Opc = M68k::MOV8cd;
695  } else if (FromSR || ToSR)
696  llvm_unreachable("Cannot emit SR copy instruction");
697 
698  if (Opc) {
699  BuildMI(MBB, MI, DL, get(Opc), DstReg)
700  .addReg(SrcReg, getKillRegState(KillSrc));
701  return;
702  }
703 
704  LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to "
705  << RI.getName(DstReg) << '\n');
706  llvm_unreachable("Cannot emit physreg copy instruction");
707 }
708 
709 namespace {
710 unsigned getLoadStoreRegOpcode(unsigned Reg, const TargetRegisterClass *RC,
711  const TargetRegisterInfo *TRI,
712  const M68kSubtarget &STI, bool load) {
713  switch (TRI->getRegSizeInBits(*RC)) {
714  default:
715  llvm_unreachable("Unknown spill size");
716  case 8:
717  if (M68k::DR8RegClass.hasSubClassEq(RC))
718  return load ? M68k::MOVM8mp_P : M68k::MOVM8pm_P;
719  if (M68k::CCRCRegClass.hasSubClassEq(RC))
720  return load ? M68k::MOV16cp : M68k::MOV16pc;
721 
722  llvm_unreachable("Unknown 1-byte regclass");
723  case 16:
724  assert(M68k::XR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
725  return load ? M68k::MOVM16mp_P : M68k::MOVM16pm_P;
726  case 32:
727  assert(M68k::XR32RegClass.hasSubClassEq(RC) && "Unknown 4-byte regclass");
728  return load ? M68k::MOVM32mp_P : M68k::MOVM32pm_P;
729  }
730 }
731 
732 unsigned getStoreRegOpcode(unsigned SrcReg, const TargetRegisterClass *RC,
733  const TargetRegisterInfo *TRI,
734  const M68kSubtarget &STI) {
735  return getLoadStoreRegOpcode(SrcReg, RC, TRI, STI, false);
736 }
737 
738 unsigned getLoadRegOpcode(unsigned DstReg, const TargetRegisterClass *RC,
739  const TargetRegisterInfo *TRI,
740  const M68kSubtarget &STI) {
741  return getLoadStoreRegOpcode(DstReg, RC, TRI, STI, true);
742 }
743 } // end anonymous namespace
744 
746  unsigned SubIdx, unsigned &Size,
747  unsigned &Offset,
748  const MachineFunction &MF) const {
749  // The slot size must be the maximum size so we can easily use MOVEM.L
750  Size = 4;
751  Offset = 0;
752  return true;
753 }
754 
757  Register SrcReg, bool IsKill,
758  int FrameIndex,
759  const TargetRegisterClass *RC,
760  const TargetRegisterInfo *TRI) const {
761  const MachineFunction &MF = *MBB.getParent();
763  "Stack slot too small for store");
764  unsigned Opc = getStoreRegOpcode(SrcReg, RC, TRI, Subtarget);
766  // (0,FrameIndex) <- $reg
768  .addReg(SrcReg, getKillRegState(IsKill));
769 }
770 
773  Register DstReg, int FrameIndex,
774  const TargetRegisterClass *RC,
775  const TargetRegisterInfo *TRI) const {
776  const MachineFunction &MF = *MBB.getParent();
778  "Stack slot too small for store");
779  unsigned Opc = getLoadRegOpcode(DstReg, RC, TRI, Subtarget);
782 }
783 
784 /// Return a virtual register initialized with the the global base register
785 /// value. Output instructions required to initialize the register in the
786 /// function entry block, if necessary.
787 ///
788 /// TODO Move this function to M68kMachineFunctionInfo.
791  unsigned GlobalBaseReg = MxFI->getGlobalBaseReg();
792  if (GlobalBaseReg != 0)
793  return GlobalBaseReg;
794 
795  // Create the register. The code to initialize it is inserted later,
796  // by the CGBR pass (below).
797  //
798  // NOTE
799  // Normally M68k uses A5 register as global base pointer but this will
800  // create unnecessary spill if we use less then 4 registers in code; since A5
801  // is callee-save anyway we could try to allocate caller-save first and if
802  // lucky get one, otherwise it does not really matter which callee-save to
803  // use.
804  MachineRegisterInfo &RegInfo = MF->getRegInfo();
805  GlobalBaseReg = RegInfo.createVirtualRegister(&M68k::AR32_NOSPRegClass);
807  return GlobalBaseReg;
808 }
809 
810 std::pair<unsigned, unsigned>
812  return std::make_pair(TF, 0u);
813 }
814 
817  using namespace M68kII;
818  static const std::pair<unsigned, const char *> TargetFlags[] = {
819  {MO_ABSOLUTE_ADDRESS, "m68k-absolute"},
820  {MO_PC_RELATIVE_ADDRESS, "m68k-pcrel"},
821  {MO_GOT, "m68k-got"},
822  {MO_GOTOFF, "m68k-gotoff"},
823  {MO_GOTPCREL, "m68k-gotpcrel"},
824  {MO_PLT, "m68k-plt"}};
825  return makeArrayRef(TargetFlags);
826 }
827 
828 namespace {
829 /// Create Global Base Reg pass. This initializes the PIC global base register
830 struct CGBR : public MachineFunctionPass {
831  static char ID;
832  CGBR() : MachineFunctionPass(ID) {}
833 
834  bool runOnMachineFunction(MachineFunction &MF) override {
835  const M68kSubtarget &STI = MF.getSubtarget<M68kSubtarget>();
837 
838  unsigned GlobalBaseReg = MxFI->getGlobalBaseReg();
839 
840  // If we didn't need a GlobalBaseReg, don't insert code.
841  if (GlobalBaseReg == 0)
842  return false;
843 
844  // Insert the set of GlobalBaseReg into the first MBB of the function
845  MachineBasicBlock &FirstMBB = MF.front();
847  DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
848  const M68kInstrInfo *TII = STI.getInstrInfo();
849 
850  // Generate lea (__GLOBAL_OFFSET_TABLE_,%PC), %A5
851  BuildMI(FirstMBB, MBBI, DL, TII->get(M68k::LEA32q), GlobalBaseReg)
852  .addExternalSymbol("_GLOBAL_OFFSET_TABLE_", M68kII::MO_GOTPCREL);
853 
854  return true;
855  }
856 
857  StringRef getPassName() const override {
858  return "M68k PIC Global Base Reg Initialization";
859  }
860 
861  void getAnalysisUsage(AnalysisUsage &AU) const override {
862  AU.setPreservesCFG();
864  }
865 };
866 } // namespace
867 
868 char CGBR::ID = 0;
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:100
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
Definition: AllocatorList.h:23
llvm::MachineInstrBuilder::copyImplicitOps
const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const
Copy all the implicit operands from OtherMI onto this one.
Definition: MachineInstrBuilder.h:315
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::M68kInstrInfo::Subtarget
const M68kSubtarget & Subtarget
Definition: M68kInstrInfo.h:241
Expand2AddrUndef
static bool Expand2AddrUndef(MachineInstrBuilder &MIB, const MCInstrDesc &Desc)
Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register...
Definition: M68kInstrInfo.cpp:559
M68kTargetMachine.h
llvm::M68k::CondCode
CondCode
Definition: M68kInstrInfo.h:34
llvm::M68kInstrInfo::AddZExt
void AddZExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned Reg, MVT From, MVT To) const
Add appropriate ZExt nodes.
Definition: M68kInstrInfo.cpp:329
llvm::M68kBeads::Bits2
@ Bits2
Definition: M68kBaseInfo.h:55
llvm::M68kInstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: M68kInstrInfo.cpp:279
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
contains
return AArch64::GPR64RegClass contains(Reg)
llvm::M68k::COND_PL
@ COND_PL
Definition: M68kInstrInfo.h:45
llvm::M68kInstrInfo::storeRegToStackSlot
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: M68kInstrInfo.cpp:755
llvm::M68kRegisterInfo::getSpillRegisterOrder
int getSpillRegisterOrder(unsigned Reg) const
Return spill order index of a register, if there is none then trap.
Definition: M68kRegisterInfo.cpp:115
llvm::M68k::COND_GT
@ COND_GT
Definition: M68kInstrInfo.h:49
ErrorHandling.h
llvm::M68kInstrInfo::ExpandMOVX_RR
bool ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst, MVT MVTSrc) const
Move across register classes without extension.
Definition: M68kInstrInfo.cpp:348
llvm::M68k::COND_NE
@ COND_NE
Definition: M68kInstrInfo.h:41
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::M68kInstrInfo::ExpandMOVEM
bool ExpandMOVEM(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, bool IsRM) const
Expand all MOVEM pseudos into real MOVEMs.
Definition: M68kInstrInfo.cpp:505
llvm::M68kInstrInfo::ExpandMOVSZX_RR
bool ExpandMOVSZX_RR(MachineInstrBuilder &MIB, bool IsSigned, MVT MVTDst, MVT MVTSrc) const
Move from register and extend.
Definition: M68kInstrInfo.cpp:386
llvm::M68kRegisterInfo::getStackRegister
unsigned getStackRegister() const
Definition: M68kRegisterInfo.h:100
llvm::MachineBasicBlock::findDebugLoc
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
Definition: MachineBasicBlock.cpp:1398
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:231
llvm::M68kInstrInfo::ExpandMOVSZX_RM
bool ExpandMOVSZX_RM(MachineInstrBuilder &MIB, bool IsSigned, const MCInstrDesc &Desc, MVT MVTDst, MVT MVTSrc) const
Move from memory and extend.
Definition: M68kInstrInfo.cpp:435
llvm::M68kII::MO_PLT
@ MO_PLT
On a symbol operand this indicates that the immediate is offset to the PLT entry of symbol name from ...
Definition: M68kBaseInfo.h:114
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::M68kInstrInfo::RI
const M68kRegisterInfo RI
Definition: M68kInstrInfo.h:242
llvm::M68k::COND_VS
@ COND_VS
Definition: M68kInstrInfo.h:44
llvm::M68kBeads::Bits3
@ Bits3
Definition: M68kBaseInfo.h:56
STLExtras.h
M68kInstrBuilder.h
llvm::M68kII::MO_PC_RELATIVE_ADDRESS
@ MO_PC_RELATIVE_ADDRESS
On a symbol operand this indicates that the immediate is the pc-relative address of the symbol.
Definition: M68kBaseInfo.h:90
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:122
MachineRegisterInfo.h
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
M68kInstrInfo.h
llvm::M68kRegisterInfo::getMatchingMegaReg
unsigned getMatchingMegaReg(unsigned Reg, const TargetRegisterClass *RC) const
Return a mega-register of the specified register Reg so its sub-register of index SubIdx is Reg,...
Definition: M68kRegisterInfo.cpp:75
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
llvm::MachineBasicBlock::push_back
void push_back(MachineInstr *MI)
Definition: MachineBasicBlock.h:756
llvm::MachineFunction::front
const MachineBasicBlock & front() const
Definition: MachineFunction.h:752
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:568
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::M68kSubtarget::getInstrInfo
const M68kInstrInfo * getInstrInfo() const override
Definition: M68kSubtarget.h:137
GetCondBranchFromCond
static unsigned GetCondBranchFromCond(XCore::CondCode CC)
GetCondBranchFromCond - Return the Branch instruction opcode that matches the cc.
Definition: XCoreInstrInfo.cpp:146
llvm::PPCISD::GlobalBaseReg
@ GlobalBaseReg
The result of the mflr at function entry, used for PIC code.
Definition: PPCISelLowering.h:156
llvm::M68kII::MO_GOTOFF
@ MO_GOTOFF
On a symbol operand this indicates that the immediate is the offset to the location of the symbol nam...
Definition: M68kBaseInfo.h:102
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:773
llvm::MachineOperand::getImm
int64_t getImm() const
Definition: MachineOperand.h:537
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition: MachineFunction.h:656
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:488
llvm::M68k::COND_GE
@ COND_GE
Definition: M68kInstrInfo.h:47
llvm::M68kInstrInfo::decomposeMachineOperandsTargetFlags
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned TF) const override
Definition: M68kInstrInfo.cpp:811
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
M68kGenInstrInfo
LiveVariables.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::make_scope_exit
LLVM_NODISCARD detail::scope_exit< typename std::decay< Callable >::type > make_scope_exit(Callable &&F)
Definition: ScopeExit.h:58
llvm::M68kInstrInfo::isPCRelRegisterOperandLegal
bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const override
Definition: M68kInstrInfo.cpp:601
llvm::MachineBasicBlock::rend
reverse_iterator rend()
Definition: MachineBasicBlock.h:278
llvm::M68k::addFrameReference
static const MachineInstrBuilder & addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset=0)
addFrameReference - This function is used to add a reference to the base of an abstract object on the...
Definition: M68kInstrBuilder.h:59
llvm::MachineOperand::getParent
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Definition: MachineOperand.h:238
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:184
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::M68k::GetCondFromBranchOpc
static M68k::CondCode GetCondFromBranchOpc(unsigned Opcode)
Definition: M68kInstrInfo.h:132
M68kMCCodeEmitter.h
llvm::M68kSubtarget
Definition: M68kSubtarget.h:40
llvm::M68k::getMCInstrBeads
const uint8_t * getMCInstrBeads(unsigned)
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:558
llvm::MachineInstr::getDebugLoc
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:418
llvm::M68kInstrInfo::ExpandPUSH_POP
bool ExpandPUSH_POP(MachineInstrBuilder &MIB, const MCInstrDesc &Desc, bool IsPush) const
Push/Pop to/from stack.
Definition: M68kInstrInfo.cpp:472
llvm::M68k::COND_HI
@ COND_HI
Definition: M68kInstrInfo.h:37
llvm::M68kMachineFunctionInfo::setGlobalBaseReg
void setGlobalBaseReg(unsigned Reg)
Definition: M68kMachineFunction.h:90
llvm::MachineOperand::isReg
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:321
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::MachineFrameInfo::getObjectSize
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
Definition: MachineFrameInfo.h:451
llvm::for_each
UnaryFunction for_each(R &&Range, UnaryFunction F)
Provide wrappers to std::for_each which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1475
llvm::M68kInstrInfo::getStackSlotRange
bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const override
Definition: M68kInstrInfo.cpp:745
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::M68k::COND_INVALID
@ COND_INVALID
Definition: M68kInstrInfo.h:52
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:41
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::M68k::COND_LT
@ COND_LT
Definition: M68kInstrInfo.h:48
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:574
load
LLVM currently emits rax rax movq rax rax ret It could narrow the loads and stores to emit rax rax movq rax rax ret The trouble is that there is a TokenFactor between the store and the load
Definition: README.txt:1531
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::M68k::COND_CC
@ COND_CC
Definition: M68kInstrInfo.h:39
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:30
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::M68k::COND_VC
@ COND_VC
Definition: M68kInstrInfo.h:43
b1
int b1
Definition: README.txt:84
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::M68kInstrInfo::getGlobalBaseReg
unsigned getGlobalBaseReg(MachineFunction *MF) const
Return a virtual register initialized with the the global base register value.
Definition: M68kInstrInfo.cpp:789
llvm::M68kInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: M68kInstrInfo.cpp:640
llvm::M68kInstrInfo::AnalyzeBranchImpl
bool AnalyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
Definition: M68kInstrInfo.cpp:82
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::M68kII::MO_ABSOLUTE_ADDRESS
@ MO_ABSOLUTE_ADDRESS
On a symbol operand this indicates that the immediate is the absolute address of the symbol.
Definition: M68kBaseInfo.h:86
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:167
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineBasicBlock::rbegin
reverse_iterator rbegin()
Definition: MachineBasicBlock.h:272
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
GetOppositeBranchCondition
static ARCCC::CondCode GetOppositeBranchCondition(ARCCC::CondCode CC)
Return the inverse of passed condition, i.e. turning COND_E to COND_NE.
Definition: ARCInstrInfo.cpp:102
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::M68kMachineFunctionInfo
Definition: M68kMachineFunction.h:23
llvm::MachineBasicBlock::rfindDebugLoc
DebugLoc rfindDebugLoc(reverse_instr_iterator MBBI)
Has exact same behavior as findDebugLoc (it also searches from the first to the last MI of this MBB) ...
Definition: MachineBasicBlock.cpp:1406
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::MachineInstrBuilder::getInstr
MachineInstr * getInstr() const
If conversion operators fail, use this method to get the MachineInstr explicitly.
Definition: MachineInstrBuilder.h:89
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::M68kInstrInfo
Definition: M68kInstrInfo.h:237
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:73
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::M68k::COND_LS
@ COND_LS
Definition: M68kInstrInfo.h:38
llvm::M68kInstrInfo::ExpandCCR
bool ExpandCCR(MachineInstrBuilder &MIB, bool IsToCCR) const
Moves to/from CCR.
Definition: M68kInstrInfo.cpp:488
llvm::TargetRegisterInfo::getRegSizeInBits
unsigned getRegSizeInBits(const TargetRegisterClass &RC) const
Return the size in bits of a register from class RC.
Definition: TargetRegisterInfo.h:274
llvm::M68kInstrInfo::loadRegFromStackSlot
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Definition: M68kInstrInfo.cpp:771
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::M68kInstrInfo::M68kInstrInfo
M68kInstrInfo(const M68kSubtarget &STI)
Definition: M68kInstrInfo.cpp:42
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1337
llvm::ARCISD::RET
@ RET
Definition: ARCISelLowering.h:52
llvm::M68kBeads::Bits1
@ Bits1
Definition: M68kBaseInfo.h:54
llvm::M68kInstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: M68kInstrInfo.cpp:248
M68kMachineFunction.h
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:43
llvm::M68k::COND_MI
@ COND_MI
Definition: M68kInstrInfo.h:46
llvm::MachineBasicBlock::isLayoutSuccessor
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
Definition: MachineBasicBlock.cpp:937
getStoreRegOpcode
static unsigned getStoreRegOpcode(Register SrcReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)
Definition: X86InstrInfo.cpp:3779
getLoadStoreRegOpcode
static unsigned getLoadStoreRegOpcode(Register Reg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI, bool load)
Definition: X86InstrInfo.cpp:3534
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:474
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::M68kInstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: M68kInstrInfo.cpp:256
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::M68kInstrInfo::getRegisterInfo
const M68kRegisterInfo & getRegisterInfo() const
TargetInstrInfo is a superset of MRegister info.
Definition: M68kInstrInfo.h:252
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::MachineOperand::setReg
void setReg(Register Reg)
Change the register this operand corresponds to.
Definition: MachineOperand.cpp:55
llvm::M68k::COND_EQ
@ COND_EQ
Definition: M68kInstrInfo.h:42
llvm::M68kMachineFunctionInfo::getGlobalBaseReg
unsigned getGlobalBaseReg() const
Definition: M68kMachineFunction.h:89
getCondFromBranchOpc
static M68k::CondCode getCondFromBranchOpc(unsigned BrOpc)
Definition: M68kInstrInfo.cpp:47
ScopeExit.h
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::M68kII::MO_GOTPCREL
@ MO_GOTPCREL
On a symbol operand this indicates that the immediate is offset to the GOT entry for the symbol name ...
Definition: M68kBaseInfo.h:108
getLoadRegOpcode
static unsigned getLoadRegOpcode(Register DestReg, const TargetRegisterClass *RC, bool IsStackAligned, const X86Subtarget &STI)
Definition: X86InstrInfo.cpp:3786
llvm::MachineInstr::setDesc
void setDesc(const MCInstrDesc &tid)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
Definition: MachineInstr.h:1731
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:42
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
From
BlockVerifier::State From
Definition: BlockVerifier.cpp:55
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::M68kInstrInfo::getSerializableDirectMachineOperandTargetFlags
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const override
Definition: M68kInstrInfo.cpp:816
llvm::M68kInstrInfo::AddSExt
void AddSExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned Reg, MVT From, MVT To) const
Add appropriate SExt nodes.
Definition: M68kInstrInfo.cpp:312
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:677
llvm::MachineInstrBundleIterator< MachineInstr >
TargetRegistry.h
llvm::M68kInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: M68kInstrInfo.cpp:574
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
llvm::AArch64II::MO_GOT
@ MO_GOT
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
Definition: AArch64BaseInfo.h:632
llvm::createM68kGlobalBaseRegPass
FunctionPass * createM68kGlobalBaseRegPass()
This pass initializes a global base register for PIC on M68k.
Definition: M68kInstrInfo.cpp:869
llvm::M68k::COND_CS
@ COND_CS
Definition: M68kInstrInfo.h:40
llvm::M68k::COND_LE
@ COND_LE
Definition: M68kInstrInfo.h:50
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:22
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
LivePhysRegs.h