LLVM  16.0.0git
MipsTargetMachine.cpp
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1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Mips target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MipsTargetMachine.h"
16 #include "Mips.h"
17 #include "Mips16ISelDAGToDAG.h"
18 #include "MipsSEISelDAGToDAG.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetObjectFile.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
33 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/InitializePasses.h"
38 #include "llvm/MC/TargetRegistry.h"
39 #include "llvm/Support/CodeGen.h"
40 #include "llvm/Support/Debug.h"
43 #include <optional>
44 #include <string>
45 
46 using namespace llvm;
47 
48 #define DEBUG_TYPE "mips"
49 
50 static cl::opt<bool>
51  EnableMulMulFix("mfix4300", cl::init(false),
52  cl::desc("Enable the VR4300 mulmul bug fix."), cl::Hidden);
53 
55  // Register the target.
60 
69 }
70 
71 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
72  const TargetOptions &Options,
73  bool isLittle) {
74  std::string Ret;
76 
77  // There are both little and big endian mips.
78  if (isLittle)
79  Ret += "e";
80  else
81  Ret += "E";
82 
83  if (ABI.IsO32())
84  Ret += "-m:m";
85  else
86  Ret += "-m:e";
87 
88  // Pointers are 32 bit on some ABIs.
89  if (!ABI.IsN64())
90  Ret += "-p:32:32";
91 
92  // 8 and 16 bit integers only need to have natural alignment, but try to
93  // align them to 32 bits. 64 bit integers have natural alignment.
94  Ret += "-i8:8:32-i16:16:32-i64:64";
95 
96  // 32 bit registers are always available and the stack is at least 64 bit
97  // aligned. On N64 64 bit registers are also available and the stack is
98  // 128 bit aligned.
99  if (ABI.IsN64() || ABI.IsN32())
100  Ret += "-n32:64-S128";
101  else
102  Ret += "-n32-S64";
103 
104  return Ret;
105 }
106 
108  std::optional<Reloc::Model> RM) {
109  if (!RM || JIT)
110  return Reloc::Static;
111  return *RM;
112 }
113 
114 // On function prologue, the stack is created by decrementing
115 // its pointer. Once decremented, all references are done with positive
116 // offset from the stack/frame pointer, using StackGrowsUp enables
117 // an easier handling.
118 // Using CodeModel::Large enables different CALL behavior.
120  StringRef CPU, StringRef FS,
121  const TargetOptions &Options,
122  std::optional<Reloc::Model> RM,
123  std::optional<CodeModel::Model> CM,
124  CodeGenOpt::Level OL, bool JIT,
125  bool isLittle)
126  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
129  isLittle(isLittle), TLOF(std::make_unique<MipsTargetObjectFile>()),
130  ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
131  Subtarget(nullptr),
132  DefaultSubtarget(TT, CPU, FS, isLittle, *this, std::nullopt),
133  NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
134  isLittle, *this, std::nullopt),
135  Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
136  isLittle, *this, std::nullopt) {
137  Subtarget = &DefaultSubtarget;
138  initAsmInfo();
139 
140  // Mips supports the debug entry values.
142 }
143 
145 
146 void MipsebTargetMachine::anchor() {}
147 
149  StringRef CPU, StringRef FS,
150  const TargetOptions &Options,
151  std::optional<Reloc::Model> RM,
152  std::optional<CodeModel::Model> CM,
153  CodeGenOpt::Level OL, bool JIT)
154  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
155 
156 void MipselTargetMachine::anchor() {}
157 
159  StringRef CPU, StringRef FS,
160  const TargetOptions &Options,
161  std::optional<Reloc::Model> RM,
162  std::optional<CodeModel::Model> CM,
163  CodeGenOpt::Level OL, bool JIT)
164  : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
165 
166 const MipsSubtarget *
168  Attribute CPUAttr = F.getFnAttribute("target-cpu");
169  Attribute FSAttr = F.getFnAttribute("target-features");
170 
171  std::string CPU =
172  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
173  std::string FS =
174  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
175  bool hasMips16Attr = F.getFnAttribute("mips16").isValid();
176  bool hasNoMips16Attr = F.getFnAttribute("nomips16").isValid();
177 
178  bool HasMicroMipsAttr = F.getFnAttribute("micromips").isValid();
179  bool HasNoMicroMipsAttr = F.getFnAttribute("nomicromips").isValid();
180 
181  // FIXME: This is related to the code below to reset the target options,
182  // we need to know whether or not the soft float flag is set on the
183  // function, so we can enable it as a subtarget feature.
184  bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
185 
186  if (hasMips16Attr)
187  FS += FS.empty() ? "+mips16" : ",+mips16";
188  else if (hasNoMips16Attr)
189  FS += FS.empty() ? "-mips16" : ",-mips16";
190  if (HasMicroMipsAttr)
191  FS += FS.empty() ? "+micromips" : ",+micromips";
192  else if (HasNoMicroMipsAttr)
193  FS += FS.empty() ? "-micromips" : ",-micromips";
194  if (softFloat)
195  FS += FS.empty() ? "+soft-float" : ",+soft-float";
196 
197  auto &I = SubtargetMap[CPU + FS];
198  if (!I) {
199  // This needs to be done before we create a new subtarget since any
200  // creation will depend on the TM and the code generation flags on the
201  // function that reside in TargetOptions.
203  I = std::make_unique<MipsSubtarget>(
204  TargetTriple, CPU, FS, isLittle, *this,
205  MaybeAlign(F.getParent()->getOverrideStackAlignment()));
206  }
207  return I.get();
208 }
209 
211  LLVM_DEBUG(dbgs() << "resetSubtarget\n");
212 
213  Subtarget = &MF->getSubtarget<MipsSubtarget>();
214 }
215 
216 namespace {
217 
218 /// Mips Code Generator Pass Configuration Options.
219 class MipsPassConfig : public TargetPassConfig {
220 public:
221  MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM)
222  : TargetPassConfig(TM, PM) {
223  // The current implementation of long branch pass requires a scratch
224  // register ($at) to be available before branch instructions. Tail merging
225  // can break this requirement, so disable it when long branch pass is
226  // enabled.
227  EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
228  }
229 
230  MipsTargetMachine &getMipsTargetMachine() const {
231  return getTM<MipsTargetMachine>();
232  }
233 
234  const MipsSubtarget &getMipsSubtarget() const {
235  return *getMipsTargetMachine().getSubtargetImpl();
236  }
237 
238  void addIRPasses() override;
239  bool addInstSelector() override;
240  void addPreEmitPass() override;
241  void addPreRegAlloc() override;
242  bool addIRTranslator() override;
243  void addPreLegalizeMachineIR() override;
244  bool addLegalizeMachineIR() override;
245  void addPreRegBankSelect() override;
246  bool addRegBankSelect() override;
247  bool addGlobalInstructionSelect() override;
248 
249  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
250 };
251 
252 } // end anonymous namespace
253 
255  return new MipsPassConfig(*this, PM);
256 }
257 
258 std::unique_ptr<CSEConfigBase> MipsPassConfig::getCSEConfig() const {
259  return getStandardCSEConfigForOpt(TM->getOptLevel());
260 }
261 
262 void MipsPassConfig::addIRPasses() {
264  addPass(createAtomicExpandPass());
265  if (getMipsSubtarget().os16())
266  addPass(createMipsOs16Pass());
267  if (getMipsSubtarget().inMips16HardFloat())
268  addPass(createMips16HardFloatPass());
269 }
270 // Install an instruction selector pass using
271 // the ISelDag to gen Mips code.
272 bool MipsPassConfig::addInstSelector() {
273  addPass(createMipsModuleISelDagPass());
274  addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
275  addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
276  return false;
277 }
278 
279 void MipsPassConfig::addPreRegAlloc() {
281 }
282 
285  if (Subtarget->allowMixed16_32()) {
286  LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n");
287  // FIXME: This is no longer necessary as the TTI returned is per-function.
288  return TargetTransformInfo(F.getParent()->getDataLayout());
289  }
290 
291  LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n");
292  return TargetTransformInfo(MipsTTIImpl(this, F));
293 }
294 
295 // Implemented by targets that want to run passes immediately before
296 // machine code is emitted.
297 void MipsPassConfig::addPreEmitPass() {
298  // Expand pseudo instructions that are sensitive to register allocation.
299  addPass(createMipsExpandPseudoPass());
300 
301  // The microMIPS size reduction pass performs instruction reselection for
302  // instructions which can be remapped to a 16 bit instruction.
304 
305  // This pass inserts a nop instruction between two back-to-back multiplication
306  // instructions when the "mfix4300" flag is passed.
307  if (EnableMulMulFix)
308  addPass(createMipsMulMulBugPass());
309 
310  // The delay slot filler pass can potientially create forbidden slot hazards
311  // for MIPSR6 and therefore it should go before MipsBranchExpansion pass.
313 
314  // This pass expands branches and takes care about the forbidden slot hazards.
315  // Expanding branches may potentially create forbidden slot hazards for
316  // MIPSR6, and fixing such hazard may potentially break a branch by extending
317  // its offset out of range. That's why this pass combine these two tasks, and
318  // runs them alternately until one of them finishes without any changes. Only
319  // then we can be sure that all branches are expanded properly and no hazards
320  // exists.
321  // Any new pass should go before this pass.
322  addPass(createMipsBranchExpansion());
323 
324  addPass(createMipsConstantIslandPass());
325 }
326 
327 bool MipsPassConfig::addIRTranslator() {
328  addPass(new IRTranslator(getOptLevel()));
329  return false;
330 }
331 
332 void MipsPassConfig::addPreLegalizeMachineIR() {
334 }
335 
336 bool MipsPassConfig::addLegalizeMachineIR() {
337  addPass(new Legalizer());
338  return false;
339 }
340 
341 void MipsPassConfig::addPreRegBankSelect() {
342  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
343  addPass(createMipsPostLegalizeCombiner(IsOptNone));
344 }
345 
346 bool MipsPassConfig::addRegBankSelect() {
347  addPass(new RegBankSelect());
348  return false;
349 }
350 
351 bool MipsPassConfig::addGlobalInstructionSelect() {
352  addPass(new InstructionSelect(getOptLevel()));
353  return false;
354 }
Mips16ISelDAGToDAG.h
llvm::createMipsExpandPseudoPass
FunctionPass * createMipsExpandPseudoPass()
createMipsExpandPseudoPass - returns an instance of the pseudo instruction expansion pass.
Definition: MipsExpandPseudo.cpp:910
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Definition: Relocation.txt:34
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Definition: MipsTargetMachine.h:27
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This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
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bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:185
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Definition: MipsTargetMachine.cpp:54
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Definition: TargetOptions.h:124
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Definition: MipsABIInfo.h:22
T
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Definition: Function.h:60
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Definition: Attributes.h:67
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Definition: MipsOs16.cpp:160
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Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
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bool allowMixed16_32() const
Definition: MipsSubtarget.h:350
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Definition: TargetTransformInfo.h:173
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Definition: Triple.h:44
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@ Hidden
Definition: CommandLine.h:139
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Definition: BasicAliasAnalysis.cpp:1794
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Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
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Definition: raw_ostream.cpp:891
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@ Ret
Definition: MipsISelLowering.h:119
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Definition: Mips16HardFloat.cpp:531
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Definition: MipsTargetTransformInfo.h:18
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const MipsSubtarget * getSubtargetImpl() const
Definition: MipsTargetMachine.h:49
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Definition: Debug.h:101
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Definition: MD5.cpp:55
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Definition: CodeGen.h:22
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Definition: Debug.cpp:163
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Definition: MipsPostLegalizerCombiner.cpp:145
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Definition: MSP430Attributes.h:37
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Definition: PassRegistry.cpp:24
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Definition: Legalizer.h:36
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Definition: MipsOptimizePICCall.cpp:318
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Definition: MipsABIInfo.cpp:58
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FunctionPass * createMipsPreLegalizeCombiner()
Definition: MipsPreLegalizerCombiner.cpp:116
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Definition: StackSlotColoring.cpp:141
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Definition: Alignment.h:117
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@ Small
Definition: CodeGen.h:28
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FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
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This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
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Definition: MipsModuleISelDAGToDAG.cpp:55
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RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1354
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Definition: PassRegistry.h:38
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Definition: PassBuilderBindings.cpp:48
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Definition: TargetMachine.h:97
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Return the attribute's value as a string.
Definition: Attributes.cpp:312
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Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
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Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
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Definition: ARMTargetMachine.cpp:122
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getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:660
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static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
Definition: MipsTargetMachine.cpp:71
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Definition: TargetMachine.h:95
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Definition: MipsSEISelDAGToDAG.cpp:1446
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@ JIT
Definition: ExecutionEngine.h:524
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#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
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#define I(x, y, z)
Definition: MD5.cpp:58
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virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:854
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@ FS
Definition: X86.h:200
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Definition: MipsTargetInfo.cpp:13
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Returns an instance of the MicroMips size reduction pass.
Definition: MicroMipsSizeReduction.cpp:795
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Reset the subtarget for the Mips target.
Definition: MipsTargetMachine.cpp:210
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Definition: MachineFunction.h:257
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Definition: CodeGen.h:53
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Definition: AArch64ISelLowering.h:493
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StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
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Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
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@ Static
Definition: CodeGen.h:22
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std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:75
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Target & getTheMips64elTarget()
Definition: MipsTargetInfo.cpp:25
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Definition: MipsTargetInfo.cpp:21
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Definition: CodeGen.h:52
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Definition: MipsSubtarget.h:39
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Definition: LLVMTargetMachine.cpp:40
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Definition: MipsTargetMachine.cpp:119
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Definition: MipsTargetObjectFile.h:16
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Definition: BitVector.h:851
MipsABIInfo.h
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This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:408
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FunctionPass * createMipsDelaySlotFillerPass()
createMipsDelaySlotFillerPass - Returns a pass that fills in delay slots in Mips MachineFunctions
Definition: MipsDelaySlotFiller.cpp:966
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TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: MipsTargetMachine.cpp:284
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~MipsTargetMachine() override
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TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: MipsTargetMachine.cpp:254
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Definition: LegacyPassManager.h:39
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Definition: IRTranslator.h:64
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std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:221
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const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
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This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
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void setSupportsDebugEntryValues(bool Enable)
Definition: TargetMachine.h:258
BasicTTIImpl.h
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Definition: CommandLine.h:412
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MachineFunction.h
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Definition: MipsTargetMachine.cpp:148
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InitializePasses.h
MipsSEISelDAGToDAG.h
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Definition: TargetMachine.h:96
Debug.h
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FunctionPass * createMipsConstantIslandPass()
Returns a pass that converts branches to long branches.
Definition: MipsConstantIslandPass.cpp:1671
llvm::MipselTargetMachine::MipselTargetMachine
MipselTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: MipsTargetMachine.cpp:158
llvm::createMipsMulMulBugPass
FunctionPass * createMipsMulMulBugPass()
Definition: MipsMulMulBugPass.cpp:136
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FunctionPass * createMips16ISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel)
Definition: Mips16ISelDAGToDAG.cpp:222
llvm::initializeMipsPostLegalizerCombinerPass
void initializeMipsPostLegalizerCombinerPass(PassRegistry &)
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Target & getTheMipselTarget()
Definition: MipsTargetInfo.cpp:17