LLVM  14.0.0git
ARMTargetMachine.cpp
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1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "ARMTargetMachine.h"
13 #include "ARM.h"
14 #include "ARMMacroFusion.h"
15 #include "ARMSubtarget.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/Triple.h"
36 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/TargetRegistry.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
50 #include "llvm/Transforms/IPO.h"
51 #include "llvm/Transforms/Scalar.h"
52 #include <cassert>
53 #include <memory>
54 #include <string>
55 
56 using namespace llvm;
57 
58 static cl::opt<bool>
59 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
60  cl::desc("Inhibit optimization of S->D register accesses on A15"),
61  cl::init(false));
62 
63 static cl::opt<bool>
64 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
65  cl::desc("Run SimplifyCFG after expanding atomic operations"
66  " to make use of cmpxchg flow-based information"),
67  cl::init(true));
68 
69 static cl::opt<bool>
70 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
71  cl::desc("Enable ARM load/store optimization pass"),
72  cl::init(true));
73 
74 // FIXME: Unify control over GlobalMerge.
76 EnableGlobalMerge("arm-global-merge", cl::Hidden,
77  cl::desc("Enable the global merge pass"));
78 
79 namespace llvm {
81 }
82 
84  // Register the target.
89 
107 }
108 
109 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
110  if (TT.isOSBinFormatMachO())
111  return std::make_unique<TargetLoweringObjectFileMachO>();
112  if (TT.isOSWindows())
113  return std::make_unique<TargetLoweringObjectFileCOFF>();
114  return std::make_unique<ARMElfTargetObjectFile>();
115 }
116 
119  const TargetOptions &Options) {
120  StringRef ABIName = Options.MCOptions.getABIName();
121 
122  if (ABIName.empty())
123  ABIName = ARM::computeDefaultTargetABI(TT, CPU);
124 
125  if (ABIName == "aapcs16")
127  else if (ABIName.startswith("aapcs"))
129  else if (ABIName.startswith("apcs"))
131 
132  llvm_unreachable("Unhandled/unknown ABI Name!");
134 }
135 
136 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
137  const TargetOptions &Options,
138  bool isLittle) {
139  auto ABI = computeTargetABI(TT, CPU, Options);
140  std::string Ret;
141 
142  if (isLittle)
143  // Little endian.
144  Ret += "e";
145  else
146  // Big endian.
147  Ret += "E";
148 
150 
151  // Pointers are 32 bits and aligned to 32 bits.
152  Ret += "-p:32:32";
153 
154  // Function pointers are aligned to 8 bits (because the LSB stores the
155  // ARM/Thumb state).
156  Ret += "-Fi8";
157 
158  // ABIs other than APCS have 64 bit integers with natural alignment.
160  Ret += "-i64:64";
161 
162  // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
163  // bits, others to 64 bits. We always try to align to 64 bits.
165  Ret += "-f64:32:64";
166 
167  // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
168  // to 64. We always ty to give them natural alignment.
170  Ret += "-v64:32:64-v128:32:128";
172  Ret += "-v128:64:128";
173 
174  // Try to align aggregates to 32 bits (the default is 64 bits, which has no
175  // particular hardware support on 32-bit ARM).
176  Ret += "-a:0:32";
177 
178  // Integer registers are 32 bits.
179  Ret += "-n32";
180 
181  // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
182  // aligned everywhere else.
183  if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
184  Ret += "-S128";
186  Ret += "-S64";
187  else
188  Ret += "-S32";
189 
190  return Ret;
191 }
192 
195  if (!RM.hasValue())
196  // Default relocation model on Darwin is PIC.
197  return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
198 
199  if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
200  assert(TT.isOSBinFormatELF() &&
201  "ROPI/RWPI currently only supported for ELF");
202 
203  // DynamicNoPIC is only used on darwin.
204  if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
205  return Reloc::Static;
206 
207  return *RM;
208 }
209 
210 /// Create an ARM architecture model.
211 ///
213  StringRef CPU, StringRef FS,
214  const TargetOptions &Options,
217  CodeGenOpt::Level OL, bool isLittle)
218  : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
219  CPU, FS, Options, getEffectiveRelocModel(TT, RM),
221  TargetABI(computeTargetABI(TT, CPU, Options)),
222  TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
223 
224  // Default to triple-appropriate float ABI
226  if (isTargetHardFloat())
227  this->Options.FloatABIType = FloatABI::Hard;
228  else
229  this->Options.FloatABIType = FloatABI::Soft;
230  }
231 
232  // Default to triple-appropriate EABI
235  // musl is compatible with glibc with regard to EABI version
241  this->Options.EABIVersion = EABI::GNU;
242  else
243  this->Options.EABIVersion = EABI::EABI5;
244  }
245 
246  if (TT.isOSBinFormatMachO()) {
247  this->Options.TrapUnreachable = true;
248  this->Options.NoTrapAfterNoreturn = true;
249  }
250 
251  // ARM supports the debug entry values.
253 
254  initAsmInfo();
255 
256  // ARM supports the MachineOutliner.
257  setMachineOutliner(true);
259 }
260 
262 
263 const ARMSubtarget *
265  Attribute CPUAttr = F.getFnAttribute("target-cpu");
266  Attribute FSAttr = F.getFnAttribute("target-features");
267 
268  std::string CPU =
269  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
270  std::string FS =
271  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
272 
273  // FIXME: This is related to the code below to reset the target options,
274  // we need to know whether or not the soft float flag is set on the
275  // function before we can generate a subtarget. We also need to use
276  // it as a key for the subtarget since that can be the only difference
277  // between two functions.
278  bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
279  // If the soft float attribute is set on the function turn on the soft float
280  // subtarget feature.
281  if (SoftFloat)
282  FS += FS.empty() ? "+soft-float" : ",+soft-float";
283 
284  // Use the optminsize to identify the subtarget, but don't use it in the
285  // feature string.
286  std::string Key = CPU + FS;
287  if (F.hasMinSize())
288  Key += "+minsize";
289 
290  auto &I = SubtargetMap[Key];
291  if (!I) {
292  // This needs to be done before we create a new subtarget since any
293  // creation will depend on the TM and the code generation flags on the
294  // function that reside in TargetOptions.
296  I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
297  F.hasMinSize());
298 
299  if (!I->isThumb() && !I->hasARMOps())
300  F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
301  "instructions, but the target does not support ARM mode execution.");
302  }
303 
304  return I.get();
305 }
306 
309  return TargetTransformInfo(ARMTTIImpl(this, F));
310 }
311 
313  StringRef CPU, StringRef FS,
314  const TargetOptions &Options,
317  CodeGenOpt::Level OL, bool JIT)
318  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
319 
321  StringRef CPU, StringRef FS,
322  const TargetOptions &Options,
325  CodeGenOpt::Level OL, bool JIT)
326  : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
327 
328 namespace {
329 
330 /// ARM Code Generator Pass Configuration Options.
331 class ARMPassConfig : public TargetPassConfig {
332 public:
333  ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
334  : TargetPassConfig(TM, PM) {}
335 
336  ARMBaseTargetMachine &getARMTargetMachine() const {
337  return getTM<ARMBaseTargetMachine>();
338  }
339 
341  createMachineScheduler(MachineSchedContext *C) const override {
343  // add DAG Mutations here.
344  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
345  if (ST.hasFusion())
347  return DAG;
348  }
349 
351  createPostMachineScheduler(MachineSchedContext *C) const override {
353  // add DAG Mutations here.
354  const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
355  if (ST.hasFusion())
357  return DAG;
358  }
359 
360  void addIRPasses() override;
361  void addCodeGenPrepare() override;
362  bool addPreISel() override;
363  bool addInstSelector() override;
364  bool addIRTranslator() override;
365  bool addLegalizeMachineIR() override;
366  bool addRegBankSelect() override;
367  bool addGlobalInstructionSelect() override;
368  void addPreRegAlloc() override;
369  void addPreSched2() override;
370  void addPreEmitPass() override;
371  void addPreEmitPass2() override;
372 
373  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
374 };
375 
376 class ARMExecutionDomainFix : public ExecutionDomainFix {
377 public:
378  static char ID;
379  ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
380  StringRef getPassName() const override {
381  return "ARM Execution Domain Fix";
382  }
383 };
385 
386 } // end anonymous namespace
387 
388 INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
389  "ARM Execution Domain Fix", false, false)
391 INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
392  "ARM Execution Domain Fix", false, false)
393 
395  return new ARMPassConfig(*this, PM);
396 }
397 
398 std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
399  return getStandardCSEConfigForOpt(TM->getOptLevel());
400 }
401 
402 void ARMPassConfig::addIRPasses() {
403  if (TM->Options.ThreadModel == ThreadModel::Single)
404  addPass(createLowerAtomicPass());
405  else
406  addPass(createAtomicExpandPass());
407 
408  // Cmpxchg instructions are often used with a subsequent comparison to
409  // determine whether it succeeded. We can exploit existing control-flow in
410  // ldrex/strex loops to simplify this, but it needs tidying up.
411  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
413  SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
414  [this](const Function &F) {
415  const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
416  return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
417  }));
418 
421 
423 
424  // Run the parallel DSP pass.
425  if (getOptLevel() == CodeGenOpt::Aggressive)
426  addPass(createARMParallelDSPPass());
427 
428  // Match interleaved memory accesses to ldN/stN intrinsics.
429  if (TM->getOptLevel() != CodeGenOpt::None)
430  addPass(createInterleavedAccessPass());
431 
432  // Add Control Flow Guard checks.
433  if (TM->getTargetTriple().isOSWindows())
434  addPass(createCFGuardCheckPass());
435 }
436 
437 void ARMPassConfig::addCodeGenPrepare() {
438  if (getOptLevel() != CodeGenOpt::None)
439  addPass(createTypePromotionPass());
441 }
442 
443 bool ARMPassConfig::addPreISel() {
444  if ((TM->getOptLevel() != CodeGenOpt::None &&
447  // FIXME: This is using the thumb1 only constant value for
448  // maximal global offset for merging globals. We may want
449  // to look into using the old value for non-thumb1 code of
450  // 4095 based on the TargetMachine, but this starts to become
451  // tricky when doing code gen per function.
452  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
454  // Merging of extern globals is enabled by default on non-Mach-O as we
455  // expect it to be generally either beneficial or harmless. On Mach-O it
456  // is disabled as we emit the .subsections_via_symbols directive which
457  // means that merging extern globals is not safe.
458  bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
459  addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
460  MergeExternalByDefault));
461  }
462 
463  if (TM->getOptLevel() != CodeGenOpt::None) {
464  addPass(createHardwareLoopsPass());
465  addPass(createMVETailPredicationPass());
466  // FIXME: IR passes can delete address-taken basic blocks, deleting
467  // corresponding blockaddresses. ARMConstantPoolConstant holds references to
468  // address-taken basic blocks which can be invalidated if the function
469  // containing the blockaddress has already been codegen'd and the basic
470  // block is removed. Work around this by forcing all IR passes to run before
471  // any ISel takes place. We should have a more principled way of handling
472  // this. See D99707 for more details.
473  addPass(createBarrierNoopPass());
474  }
475 
476  return false;
477 }
478 
479 bool ARMPassConfig::addInstSelector() {
480  addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
481  return false;
482 }
483 
484 bool ARMPassConfig::addIRTranslator() {
485  addPass(new IRTranslator(getOptLevel()));
486  return false;
487 }
488 
489 bool ARMPassConfig::addLegalizeMachineIR() {
490  addPass(new Legalizer());
491  return false;
492 }
493 
494 bool ARMPassConfig::addRegBankSelect() {
495  addPass(new RegBankSelect());
496  return false;
497 }
498 
499 bool ARMPassConfig::addGlobalInstructionSelect() {
500  addPass(new InstructionSelect(getOptLevel()));
501  return false;
502 }
503 
504 void ARMPassConfig::addPreRegAlloc() {
505  if (getOptLevel() != CodeGenOpt::None) {
507 
508  addPass(createMLxExpansionPass());
509 
511  addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
512 
514  addPass(createA15SDOptimizerPass());
515  }
516 }
517 
518 void ARMPassConfig::addPreSched2() {
519  if (getOptLevel() != CodeGenOpt::None) {
522 
523  addPass(new ARMExecutionDomainFix());
524  addPass(createBreakFalseDeps());
525  }
526 
527  // Expand some pseudo instructions into multiple instructions to allow
528  // proper scheduling.
529  addPass(createARMExpandPseudoPass());
530 
531  if (getOptLevel() != CodeGenOpt::None) {
532  // When optimising for size, always run the Thumb2SizeReduction pass before
533  // IfConversion. Otherwise, check whether IT blocks are restricted
534  // (e.g. in v8, IfConversion depends on Thumb instruction widths)
535  addPass(createThumb2SizeReductionPass([this](const Function &F) {
536  return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
537  this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
538  }));
539 
540  addPass(createIfConverter([](const MachineFunction &MF) {
541  return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
542  }));
543  }
544  addPass(createThumb2ITBlockPass());
545 
546  // Add both scheduling passes to give the subtarget an opportunity to pick
547  // between them.
548  if (getOptLevel() != CodeGenOpt::None) {
549  addPass(&PostMachineSchedulerID);
550  addPass(&PostRASchedulerID);
551  }
552 
553  addPass(createMVEVPTBlockPass());
554  addPass(createARMIndirectThunks());
555  addPass(createARMSLSHardeningPass());
556 }
557 
558 void ARMPassConfig::addPreEmitPass() {
560 
561  // Constant island pass work on unbundled instructions.
562  addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
563  return MF.getSubtarget<ARMSubtarget>().isThumb2();
564  }));
565 
566  // Don't optimize barriers or block placement at -O0.
567  if (getOptLevel() != CodeGenOpt::None) {
568  addPass(createARMBlockPlacementPass());
570  }
571 }
572 
573 void ARMPassConfig::addPreEmitPass2() {
574  addPass(createARMConstantIslandPass());
576 
577  if (TM->getTargetTriple().isOSWindows()) {
578  // Identify valid longjmp targets for Windows Control Flow Guard.
579  addPass(createCFGuardLongjmpPass());
580  // Identify valid eh continuation targets for Windows EHCont Guard.
582  }
583 }
ARMSubtarget.h
llvm::initializeARMBlockPlacementPass
void initializeARMBlockPlacementPass(PassRegistry &)
llvm::initializeARMExpandPseudoPass
void initializeARMExpandPseudoPass(PassRegistry &)
llvm::ARMBaseTargetMachine::ARM_ABI_APCS
@ ARM_ABI_APCS
Definition: ARMTargetMachine.h:31
ABI
Generic address nodes are lowered to some combination of target independent and machine specific ABI
Definition: Relocation.txt:34
llvm::StringRef::startswith
LLVM_NODISCARD bool startswith(StringRef Prefix) const
Check if this string starts with the given Prefix.
Definition: StringRef.h:285
EnableAtomicTidy
static cl::opt< bool > EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
llvm::ARMBaseTargetMachine
Definition: ARMTargetMachine.h:27
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:167
ARMTargetInfo.h
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:152
Optional.h
llvm::EABI::GNU
@ GNU
llvm::initializeThumb2SizeReducePass
void initializeThumb2SizeReducePass(PassRegistry &)
llvm::ReachingDefAnalysis
This class provides the reaching def analysis.
Definition: ReachingDefAnalysis.h:69
ARMMCTargetDesc.h
CallLowering.h
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::getTheARMBETarget
Target & getTheARMBETarget()
Definition: ARMTargetInfo.cpp:17
llvm::ARMSubtarget
Definition: ARMSubtarget.h:46
Scalar.h
T
llvm::Function
Definition: Function.h:62
llvm::Attribute
Definition: Attributes.h:51
llvm::createARMLowOverheadLoopsPass
FunctionPass * createARMLowOverheadLoopsPass()
Definition: ARMLowOverheadLoops.cpp:1883
StringRef.h
llvm::createARMConstantIslandPass
FunctionPass * createARMConstantIslandPass()
createARMConstantIslandPass - returns an instance of the constpool island pass.
Definition: ARMConstantIslandPass.cpp:2490
Fix
arm execution domain ARM Execution Domain Fix
Definition: ARMTargetMachine.cpp:392
fix
arm execution domain fix
Definition: ARMTargetMachine.cpp:391
Pass.h
llvm::createCFGSimplificationPass
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
Definition: SimplifyCFGPass.cpp:418
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::initializeARMLowOverheadLoopsPass
void initializeARMLowOverheadLoopsPass(PassRegistry &)
llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS
@ ARM_ABI_AAPCS
Definition: ARMTargetMachine.h:32
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:169
llvm::Triple::MuslEABIHF
@ MuslEABIHF
Definition: Triple.h:225
RegisterBankInfo.h
llvm::EABI::Default
@ Default
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::TargetOptions::EABIVersion
EABI EABIVersion
EABIVersion - This flag specifies the EABI version.
Definition: TargetOptions.h:384
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void setSupportsDefaultOutlining(bool Enable)
Definition: TargetMachine.h:256
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::DataLayout::getManglingComponent
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:153
llvm::createMLxExpansionPass
FunctionPass * createMLxExpansionPass()
Definition: MLxExpansionPass.cpp:390
llvm::TargetOptions::TrapUnreachable
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Definition: TargetOptions.h:274
ARMMacroFusion.h
InstructionSelect.h
llvm::Reloc::ROPI_RWPI
@ ROPI_RWPI
Definition: CodeGen.h:22
EnableGlobalMerge
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("arm-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
llvm::createMVEVPTBlockPass
FunctionPass * createMVEVPTBlockPass()
createMVEVPTBlock - Returns an instance of the MVE VPT block insertion pass.
Definition: MVEVPTBlockPass.cpp:337
llvm::Optional< Reloc::Model >
llvm::createBarrierNoopPass
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
Definition: BarrierNoopPass.cpp:43
llvm::FloatABI::Hard
@ Hard
Definition: TargetOptions.h:31
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
llvm::ExecutionDomainFix
Definition: ExecutionDomainFix.h:116
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::ARMBaseTargetMachine::ARM_ABI_AAPCS16
@ ARM_ABI_AAPCS16
Definition: ARMTargetMachine.h:33
STLExtras.h
TargetParser.h
llvm::WinEH::EncodingType::ARM
@ ARM
Windows AXP64.
LegalizerInfo.h
llvm::ARMBETargetMachine::ARMBETargetMachine
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: ARMTargetMachine.cpp:320
llvm::Triple::GNUEABI
@ GNUEABI
Definition: Triple.h:215
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::ARMBaseTargetMachine::getSubtargetImpl
const ARMSubtarget * getSubtargetImpl() const =delete
llvm::ARMTTIImpl
Definition: ARMTargetTransformInfo.h:56
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Model
Definition: CodeGen.h:22
llvm::getTheARMLETarget
Target & getTheARMLETarget()
Definition: ARMTargetInfo.cpp:13
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~ARMBaseTargetMachine() override
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Definition: MSP430Attributes.h:37
llvm::createEHContGuardCatchretPass
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
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bool isTargetHardFloat() const
Definition: ARMTargetMachine.h:64
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Target & getTheThumbLETarget()
Definition: ARMTargetInfo.cpp:21
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void setMachineOutliner(bool Enable)
Definition: TargetMachine.h:253
llvm::Triple::isOSDarwin
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS or watchOS).
Definition: Triple.h:487
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Definition: Legalizer.h:31
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
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static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
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void initializeARMSLSHardeningPass(PassRegistry &)
Domain
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Definition: CorrelatedValuePropagation.cpp:703
llvm::initializeARMConstantIslandsPass
void initializeARMConstantIslandsPass(PassRegistry &)
llvm::createA15SDOptimizerPass
FunctionPass * createA15SDOptimizerPass()
Definition: A15SDOptimizer.cpp:684
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:481
llvm::initializeARMParallelDSPPass
void initializeARMParallelDSPPass(PassRegistry &)
llvm::initializeARMPreAllocLoadStoreOptPass
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &)
false
Definition: StackSlotColoring.cpp:142
llvm::FloatABI::Default
@ Default
Definition: TargetOptions.h:29
llvm::initializeARMExecutionDomainFixPass
void initializeARMExecutionDomainFixPass(PassRegistry &)
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::createGenericSchedPostRA
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Definition: MachineScheduler.cpp:3646
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:31
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1275
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:318
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::createARMBlockPlacementPass
FunctionPass * createARMBlockPlacementPass()
Definition: ARMBlockPlacement.cpp:56
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::Triple::MuslEABI
@ MuslEABI
Definition: Triple.h:224
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:101
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:244
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:301
llvm::TargetOptions::FloatABIType
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line.
Definition: TargetOptions.h:359
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
InstructionSelector.h
computeTargetABI
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
Definition: ARMTargetMachine.cpp:118
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:634
llvm::cl::opt< bool >
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:99
llvm::cl::BOU_UNSET
@ BOU_UNSET
Definition: CommandLine.h:623
llvm::EABI::Unknown
@ Unknown
LLVMInitializeARMTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget()
Definition: ARMTargetMachine.cpp:83
CFGuard.h
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3489
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
ARMTargetObjectFile.h
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
IPO.h
llvm::createMVETPAndVPTOptimisationsPass
FunctionPass * createMVETPAndVPTOptimisationsPass()
createMVETPAndVPTOptimisationsPass
Definition: MVETPAndVPTOptimisationsPass.cpp:1078
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:120
llvm::createLowerAtomicPass
Pass * createLowerAtomicPass()
llvm::TargetOptions::NoTrapAfterNoreturn
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
Definition: TargetOptions.h:278
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::createARMExpandPseudoPass
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass.
Definition: ARMExpandPseudoInsts.cpp:3127
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:844
llvm::createUnpackMachineBundles
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
Definition: MachineInstrBundle.cpp:80
llvm::createMVEGatherScatterLoweringPass
Pass * createMVEGatherScatterLoweringPass()
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
TargetPassConfig.h
llvm::initializeARMLoadStoreOptPass
void initializeARMLoadStoreOptPass(PassRegistry &)
llvm::TargetMachine::Options
TargetOptions Options
Definition: TargetMachine.h:121
llvm::TargetPassConfig::addCodeGenPrepare
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
Definition: TargetPassConfig.cpp:973
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::createTypePromotionPass
FunctionPass * createTypePromotionPass()
Create IR Type Promotion pass.
Definition: TypePromotion.cpp:959
llvm::createCFGuardCheckPass
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:294
llvm::Reloc::ROPI
@ ROPI
Definition: CodeGen.h:22
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:266
ARM.h
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::Reloc::DynamicNoPIC
@ DynamicNoPIC
Definition: CodeGen.h:22
llvm::MachineFunction
Definition: MachineFunction.h:234
EnableARMLoadStoreOpt
static cl::opt< bool > EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden, cl::desc("Enable ARM load/store optimization pass"), cl::init(true))
Triple.h
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::initializeMVETailPredicationPass
void initializeMVETailPredicationPass(PassRegistry &)
TargetOptions.h
llvm::Reloc::RWPI
@ RWPI
Definition: CodeGen.h:22
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:478
llvm::createARMSLSHardeningPass
FunctionPass * createARMSLSHardeningPass()
Definition: ARMSLSHardening.cpp:361
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::createHardwareLoopsPass
FunctionPass * createHardwareLoopsPass()
Create Hardware Loop pass.
Definition: HardwareLoops.cpp:546
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:74
llvm::createMVELaneInterleavingPass
Pass * createMVELaneInterleavingPass()
llvm::initializeMVEGatherScatterLoweringPass
void initializeMVEGatherScatterLoweringPass(PassRegistry &)
IRTranslator.h
llvm::createARMParallelDSPPass
Pass * createARMParallelDSPPass()
Definition: ARMParallelDSP.cpp:804
llvm::createThumb2SizeReductionPass
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
Definition: Thumb2SizeReduction.cpp:1158
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:498
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
llvm::createARMISelDag
FunctionPass * createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel)
createARMISelDag - This pass converts a legalized DAG into a ARM-specific DAG, ready for instruction ...
Definition: ARMISelDAGToDAG.cpp:5918
llvm::createARMIndirectThunks
FunctionPass * createARMIndirectThunks()
Definition: ARMSLSHardening.cpp:407
llvm::EABI::EABI5
@ EABI5
llvm::Triple::isOSWindows
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:550
llvm::createInterleavedAccessPass
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
Definition: InterleavedAccessPass.cpp:145
Attributes.h
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: ARMTargetMachine.cpp:109
llvm::createBreakFalseDeps
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
Definition: BreakFalseDeps.cpp:105
llvm::ARMBaseTargetMachine::ARMBaseTargetMachine
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool isLittle)
Create an ARM architecture model.
Definition: ARMTargetMachine.cpp:212
computeDataLayout
static std::string computeDataLayout(const Triple &TT, StringRef CPU, const TargetOptions &Options, bool isLittle)
Definition: ARMTargetMachine.cpp:136
RegBankSelect.h
Function.h
llvm::createThumb2ITBlockPass
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
Definition: Thumb2ITBlockPass.cpp:310
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:406
llvm::ThreadModel::Single
@ Single
Definition: TargetOptions.h:57
llvm::ARMBaseTargetMachine::ARMABI
ARMABI
Definition: ARMTargetMachine.h:29
llvm::createIfConverter
FunctionPass * createIfConverter(std::function< bool(const MachineFunction &)> Ftor)
Definition: IfConversion.cpp:2366
llvm::initializeMVELaneInterleavingPass
void initializeMVELaneInterleavingPass(PassRegistry &)
llvm::createMVETailPredicationPass
Pass * createMVETailPredicationPass()
Definition: MVETailPredication.cpp:430
llvm::createGlobalMergePass
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
Definition: GlobalMerge.cpp:678
CodeGen.h
ExecutionDomainFix.h
llvm::ARMLETargetMachine::ARMLETargetMachine
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: ARMTargetMachine.cpp:312
llvm::cl::BOU_TRUE
@ BOU_TRUE
Definition: CommandLine.h:623
Legalizer.h
llvm::SimplifyCFGOptions
Definition: SimplifyCFGOptions.h:23
MachineScheduler.h
llvm::initializeMVEVPTBlockPass
void initializeMVEVPTBlockPass(PassRegistry &)
llvm::Registry
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:44
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:199
llvm::ARMBaseTargetMachine::ARM_ABI_UNKNOWN
@ ARM_ABI_UNKNOWN
Definition: ARMTargetMachine.h:30
llvm::ARM::computeDefaultTargetABI
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
Definition: ARMTargetParser.cpp:600
llvm::ARMBaseTargetMachine::SubtargetMap
StringMap< std::unique_ptr< ARMSubtarget > > SubtargetMap
Definition: ARMTargetMachine.h:39
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
ARMTargetTransformInfo.h
llvm::ARMSubtarget::restrictIT
bool restrictIT() const
Definition: ARMSubtarget.h:853
llvm::FloatABI::Soft
@ Soft
Definition: TargetOptions.h:30
llvm::IRTranslator
Definition: IRTranslator.h:63
llvm::Triple::getEnvironment
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:329
DisableA15SDOptimization
static cl::opt< bool > DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, cl::desc("Inhibit optimization of S->D register accesses on A15"), cl::init(false))
llvm::ARMBaseTargetMachine::isLittle
bool isLittle
Definition: ARMTargetMachine.h:38
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::Triple::GNUEABIHF
@ GNUEABIHF
Definition: Triple.h:216
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::TargetMachine::setSupportsDebugEntryValues
void setSupportsDebugEntryValues(bool Enable)
Definition: TargetMachine.h:259
llvm::getTheThumbBETarget
Target & getTheThumbBETarget()
Definition: ARMTargetInfo.cpp:25
llvm::createARMOptimizeBarriersPass
FunctionPass * createARMOptimizeBarriersPass()
createARMOptimizeBarriersPass - Returns an instance of the remove double barriers pass.
Definition: ARMOptimizeBarriersPass.cpp:104
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:241
llvm::initializeMVETPAndVPTOptimisationsPass
void initializeMVETPAndVPTOptimisationsPass(PassRegistry &)
llvm::cl::desc
Definition: CommandLine.h:412
llvm::ARMBaseTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: ARMTargetMachine.cpp:308
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:385
execution
speculative execution
Definition: SpeculativeExecution.cpp:135
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
ARMTargetMachine.h
llvm::createARMLoadStoreOptimizationPass
FunctionPass * createARMLoadStoreOptimizationPass(bool PreAlloc=false)
Returns an instance of the load / store optimization pass.
Definition: ARMLoadStoreOptimizer.cpp:3016
MachineFunction.h
llvm::createARMMacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createARMMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createARMMacroFusionDAGMutation()); to ARMPassConfig::crea...
Definition: ARMMacroFusion.cpp:65
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1883
TargetRegistry.h
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:100
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix", "ARM Execution Domain Fix", false, false) INITIALIZE_PASS_END(ARMExecutionDomainFix
llvm::createCFGuardLongjmpPass
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38