LLVM 17.0.0git
ARMTargetMachine.cpp
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1//===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "ARMTargetMachine.h"
13#include "ARM.h"
15#include "ARMMacroFusion.h"
16#include "ARMSubtarget.h"
17#include "ARMTargetObjectFile.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/ADT/StringRef.h"
23#include "llvm/ADT/Triple.h"
36#include "llvm/CodeGen/Passes.h"
39#include "llvm/IR/Attributes.h"
40#include "llvm/IR/DataLayout.h"
41#include "llvm/IR/Function.h"
43#include "llvm/Pass.h"
52#include "llvm/Transforms/IPO.h"
54#include <cassert>
55#include <memory>
56#include <optional>
57#include <string>
58
59using namespace llvm;
60
61static cl::opt<bool>
62DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
63 cl::desc("Inhibit optimization of S->D register accesses on A15"),
64 cl::init(false));
65
66static cl::opt<bool>
67EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
68 cl::desc("Run SimplifyCFG after expanding atomic operations"
69 " to make use of cmpxchg flow-based information"),
70 cl::init(true));
71
72static cl::opt<bool>
73EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
74 cl::desc("Enable ARM load/store optimization pass"),
75 cl::init(true));
76
77// FIXME: Unify control over GlobalMerge.
79EnableGlobalMerge("arm-global-merge", cl::Hidden,
80 cl::desc("Enable the global merge pass"));
81
82namespace llvm {
84}
85
87 // Register the target.
92
113}
114
115static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
116 if (TT.isOSBinFormatMachO())
117 return std::make_unique<TargetLoweringObjectFileMachO>();
118 if (TT.isOSWindows())
119 return std::make_unique<TargetLoweringObjectFileCOFF>();
120 return std::make_unique<ARMElfTargetObjectFile>();
121}
122
125 const TargetOptions &Options) {
126 StringRef ABIName = Options.MCOptions.getABIName();
127
128 if (ABIName.empty())
129 ABIName = ARM::computeDefaultTargetABI(TT, CPU);
130
131 if (ABIName == "aapcs16")
133 else if (ABIName.startswith("aapcs"))
135 else if (ABIName.startswith("apcs"))
137
138 llvm_unreachable("Unhandled/unknown ABI Name!");
140}
141
142static std::string computeDataLayout(const Triple &TT, StringRef CPU,
143 const TargetOptions &Options,
144 bool isLittle) {
145 auto ABI = computeTargetABI(TT, CPU, Options);
146 std::string Ret;
147
148 if (isLittle)
149 // Little endian.
150 Ret += "e";
151 else
152 // Big endian.
153 Ret += "E";
154
156
157 // Pointers are 32 bits and aligned to 32 bits.
158 Ret += "-p:32:32";
159
160 // Function pointers are aligned to 8 bits (because the LSB stores the
161 // ARM/Thumb state).
162 Ret += "-Fi8";
163
164 // ABIs other than APCS have 64 bit integers with natural alignment.
166 Ret += "-i64:64";
167
168 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
169 // bits, others to 64 bits. We always try to align to 64 bits.
171 Ret += "-f64:32:64";
172
173 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
174 // to 64. We always ty to give them natural alignment.
176 Ret += "-v64:32:64-v128:32:128";
178 Ret += "-v128:64:128";
179
180 // Try to align aggregates to 32 bits (the default is 64 bits, which has no
181 // particular hardware support on 32-bit ARM).
182 Ret += "-a:0:32";
183
184 // Integer registers are 32 bits.
185 Ret += "-n32";
186
187 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
188 // aligned everywhere else.
189 if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
190 Ret += "-S128";
192 Ret += "-S64";
193 else
194 Ret += "-S32";
195
196 return Ret;
197}
198
200 std::optional<Reloc::Model> RM) {
201 if (!RM)
202 // Default relocation model on Darwin is PIC.
203 return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
204
205 if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
206 assert(TT.isOSBinFormatELF() &&
207 "ROPI/RWPI currently only supported for ELF");
208
209 // DynamicNoPIC is only used on darwin.
210 if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
211 return Reloc::Static;
212
213 return *RM;
214}
215
216/// Create an ARM architecture model.
217///
219 StringRef CPU, StringRef FS,
220 const TargetOptions &Options,
221 std::optional<Reloc::Model> RM,
222 std::optional<CodeModel::Model> CM,
223 CodeGenOpt::Level OL, bool isLittle)
224 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
225 CPU, FS, Options, getEffectiveRelocModel(TT, RM),
226 getEffectiveCodeModel(CM, CodeModel::Small), OL),
227 TargetABI(computeTargetABI(TT, CPU, Options)),
228 TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
229
230 // Default to triple-appropriate float ABI
232 if (isTargetHardFloat())
233 this->Options.FloatABIType = FloatABI::Hard;
234 else
235 this->Options.FloatABIType = FloatABI::Soft;
236 }
237
238 // Default to triple-appropriate EABI
241 // musl is compatible with glibc with regard to EABI version
247 this->Options.EABIVersion = EABI::GNU;
248 else
249 this->Options.EABIVersion = EABI::EABI5;
250 }
251
252 if (TT.isOSBinFormatMachO()) {
253 this->Options.TrapUnreachable = true;
254 this->Options.NoTrapAfterNoreturn = true;
255 }
256
257 // ARM supports the debug entry values.
259
260 initAsmInfo();
261
262 // ARM supports the MachineOutliner.
263 setMachineOutliner(true);
265}
266
268
270 BumpPtrAllocator &Allocator, const Function &F,
271 const TargetSubtargetInfo *STI) const {
272 return ARMFunctionInfo::create<ARMFunctionInfo>(
273 Allocator, F, static_cast<const ARMSubtarget *>(STI));
274}
275
276const ARMSubtarget *
278 Attribute CPUAttr = F.getFnAttribute("target-cpu");
279 Attribute FSAttr = F.getFnAttribute("target-features");
280
281 std::string CPU =
282 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
283 std::string FS =
284 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
285
286 // FIXME: This is related to the code below to reset the target options,
287 // we need to know whether or not the soft float flag is set on the
288 // function before we can generate a subtarget. We also need to use
289 // it as a key for the subtarget since that can be the only difference
290 // between two functions.
291 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
292 // If the soft float attribute is set on the function turn on the soft float
293 // subtarget feature.
294 if (SoftFloat)
295 FS += FS.empty() ? "+soft-float" : ",+soft-float";
296
297 // Use the optminsize to identify the subtarget, but don't use it in the
298 // feature string.
299 std::string Key = CPU + FS;
300 if (F.hasMinSize())
301 Key += "+minsize";
302
303 auto &I = SubtargetMap[Key];
304 if (!I) {
305 // This needs to be done before we create a new subtarget since any
306 // creation will depend on the TM and the code generation flags on the
307 // function that reside in TargetOptions.
309 I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle,
310 F.hasMinSize());
311
312 if (!I->isThumb() && !I->hasARMOps())
313 F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
314 "instructions, but the target does not support ARM mode execution.");
315 }
316
317 return I.get();
318}
319
322 return TargetTransformInfo(ARMTTIImpl(this, F));
323}
324
326 StringRef CPU, StringRef FS,
327 const TargetOptions &Options,
328 std::optional<Reloc::Model> RM,
329 std::optional<CodeModel::Model> CM,
330 CodeGenOpt::Level OL, bool JIT)
331 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
332
334 StringRef CPU, StringRef FS,
335 const TargetOptions &Options,
336 std::optional<Reloc::Model> RM,
337 std::optional<CodeModel::Model> CM,
338 CodeGenOpt::Level OL, bool JIT)
339 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
340
341namespace {
342
343/// ARM Code Generator Pass Configuration Options.
344class ARMPassConfig : public TargetPassConfig {
345public:
346 ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
347 : TargetPassConfig(TM, PM) {}
348
349 ARMBaseTargetMachine &getARMTargetMachine() const {
350 return getTM<ARMBaseTargetMachine>();
351 }
352
354 createMachineScheduler(MachineSchedContext *C) const override {
356 // add DAG Mutations here.
357 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
358 if (ST.hasFusion())
360 return DAG;
361 }
362
364 createPostMachineScheduler(MachineSchedContext *C) const override {
366 // add DAG Mutations here.
367 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
368 if (ST.hasFusion())
370 return DAG;
371 }
372
373 void addIRPasses() override;
374 void addCodeGenPrepare() override;
375 bool addPreISel() override;
376 bool addInstSelector() override;
377 bool addIRTranslator() override;
378 bool addLegalizeMachineIR() override;
379 bool addRegBankSelect() override;
380 bool addGlobalInstructionSelect() override;
381 void addPreRegAlloc() override;
382 void addPreSched2() override;
383 void addPreEmitPass() override;
384 void addPreEmitPass2() override;
385
386 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
387};
388
389class ARMExecutionDomainFix : public ExecutionDomainFix {
390public:
391 static char ID;
392 ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
393 StringRef getPassName() const override {
394 return "ARM Execution Domain Fix";
395 }
396};
397char ARMExecutionDomainFix::ID;
398
399} // end anonymous namespace
400
401INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
402 "ARM Execution Domain Fix", false, false)
404INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
405 "ARM Execution Domain Fix", false, false)
406
408 return new ARMPassConfig(*this, PM);
409}
410
411std::unique_ptr<CSEConfigBase> ARMPassConfig::getCSEConfig() const {
412 return getStandardCSEConfigForOpt(TM->getOptLevel());
413}
414
415void ARMPassConfig::addIRPasses() {
416 if (TM->Options.ThreadModel == ThreadModel::Single)
417 addPass(createLowerAtomicPass());
418 else
419 addPass(createAtomicExpandPass());
420
421 // Cmpxchg instructions are often used with a subsequent comparison to
422 // determine whether it succeeded. We can exploit existing control-flow in
423 // ldrex/strex loops to simplify this, but it needs tidying up.
424 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
426 SimplifyCFGOptions().hoistCommonInsts(true).sinkCommonInsts(true),
427 [this](const Function &F) {
428 const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
429 return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
430 }));
431
434
436
437 // Run the parallel DSP pass.
438 if (getOptLevel() == CodeGenOpt::Aggressive)
439 addPass(createARMParallelDSPPass());
440
441 // Match complex arithmetic patterns
442 if (TM->getOptLevel() >= CodeGenOpt::Default)
444
445 // Match interleaved memory accesses to ldN/stN intrinsics.
446 if (TM->getOptLevel() != CodeGenOpt::None)
448
449 // Add Control Flow Guard checks.
450 if (TM->getTargetTriple().isOSWindows())
451 addPass(createCFGuardCheckPass());
452
453 if (TM->Options.JMCInstrument)
454 addPass(createJMCInstrumenterPass());
455}
456
457void ARMPassConfig::addCodeGenPrepare() {
458 if (getOptLevel() != CodeGenOpt::None)
461}
462
463bool ARMPassConfig::addPreISel() {
464 if ((TM->getOptLevel() != CodeGenOpt::None &&
467 // FIXME: This is using the thumb1 only constant value for
468 // maximal global offset for merging globals. We may want
469 // to look into using the old value for non-thumb1 code of
470 // 4095 based on the TargetMachine, but this starts to become
471 // tricky when doing code gen per function.
472 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
474 // Merging of extern globals is enabled by default on non-Mach-O as we
475 // expect it to be generally either beneficial or harmless. On Mach-O it
476 // is disabled as we emit the .subsections_via_symbols directive which
477 // means that merging extern globals is not safe.
478 bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
479 addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
480 MergeExternalByDefault));
481 }
482
483 if (TM->getOptLevel() != CodeGenOpt::None) {
484 addPass(createHardwareLoopsPass());
486 // FIXME: IR passes can delete address-taken basic blocks, deleting
487 // corresponding blockaddresses. ARMConstantPoolConstant holds references to
488 // address-taken basic blocks which can be invalidated if the function
489 // containing the blockaddress has already been codegen'd and the basic
490 // block is removed. Work around this by forcing all IR passes to run before
491 // any ISel takes place. We should have a more principled way of handling
492 // this. See D99707 for more details.
493 addPass(createBarrierNoopPass());
494 }
495
496 return false;
497}
498
499bool ARMPassConfig::addInstSelector() {
500 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
501 return false;
502}
503
504bool ARMPassConfig::addIRTranslator() {
505 addPass(new IRTranslator(getOptLevel()));
506 return false;
507}
508
509bool ARMPassConfig::addLegalizeMachineIR() {
510 addPass(new Legalizer());
511 return false;
512}
513
514bool ARMPassConfig::addRegBankSelect() {
515 addPass(new RegBankSelect());
516 return false;
517}
518
519bool ARMPassConfig::addGlobalInstructionSelect() {
520 addPass(new InstructionSelect(getOptLevel()));
521 return false;
522}
523
524void ARMPassConfig::addPreRegAlloc() {
525 if (getOptLevel() != CodeGenOpt::None) {
526 if (getOptLevel() == CodeGenOpt::Aggressive)
527 addPass(&MachinePipelinerID);
528
530
531 addPass(createMLxExpansionPass());
532
534 addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
535
537 addPass(createA15SDOptimizerPass());
538 }
539}
540
541void ARMPassConfig::addPreSched2() {
542 if (getOptLevel() != CodeGenOpt::None) {
545
546 addPass(new ARMExecutionDomainFix());
547 addPass(createBreakFalseDeps());
548 }
549
550 // Expand some pseudo instructions into multiple instructions to allow
551 // proper scheduling.
552 addPass(createARMExpandPseudoPass());
553
554 if (getOptLevel() != CodeGenOpt::None) {
555 // When optimising for size, always run the Thumb2SizeReduction pass before
556 // IfConversion. Otherwise, check whether IT blocks are restricted
557 // (e.g. in v8, IfConversion depends on Thumb instruction widths)
558 addPass(createThumb2SizeReductionPass([this](const Function &F) {
559 return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() ||
560 this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
561 }));
562
563 addPass(createIfConverter([](const MachineFunction &MF) {
564 return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
565 }));
566 }
567 addPass(createThumb2ITBlockPass());
568
569 // Add both scheduling passes to give the subtarget an opportunity to pick
570 // between them.
571 if (getOptLevel() != CodeGenOpt::None) {
572 addPass(&PostMachineSchedulerID);
573 addPass(&PostRASchedulerID);
574 }
575
576 addPass(createMVEVPTBlockPass());
577 addPass(createARMIndirectThunks());
578 addPass(createARMSLSHardeningPass());
579}
580
581void ARMPassConfig::addPreEmitPass() {
583
584 // Constant island pass work on unbundled instructions.
585 addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
586 return MF.getSubtarget<ARMSubtarget>().isThumb2();
587 }));
588
589 // Don't optimize barriers or block placement at -O0.
590 if (getOptLevel() != CodeGenOpt::None) {
593 }
594}
595
596void ARMPassConfig::addPreEmitPass2() {
597 // Inserts fixup instructions before unsafe AES operations. Instructions may
598 // be inserted at the start of blocks and at within blocks so this pass has to
599 // come before those below.
601 // Inserts BTIs at the start of functions and indirectly-called basic blocks,
602 // so passes cannot add to the start of basic blocks once this has run.
604 // Inserts Constant Islands. Block sizes cannot be increased after this point,
605 // as this may push the branch ranges and load offsets of accessing constant
606 // pools out of range..
608 // Finalises Low-Overhead Loops. This replaces pseudo instructions with real
609 // instructions, but the pseudos all have conservative sizes so that block
610 // sizes will only be decreased by this pass.
612
613 if (TM->getTargetTriple().isOSWindows()) {
614 // Identify valid longjmp targets for Windows Control Flow Guard.
615 addPass(createCFGuardLongjmpPass());
616 // Identify valid eh continuation targets for Windows EHCont Guard.
618 }
619}
Falkor HW Prefetch Fix
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
This header is deprecated in favour of llvm/TargetParser/Triple.h.
static cl::opt< bool > DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden, cl::desc("Inhibit optimization of S->D register accesses on A15"), cl::init(false))
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("arm-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget()
static ARMBaseTargetMachine::ARMABI computeTargetABI(const Triple &TT, StringRef CPU, const TargetOptions &Options)
arm execution domain fix
static cl::opt< bool > EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden, cl::desc("Enable ARM load/store optimization pass"), cl::init(true))
static cl::opt< bool > EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional< Reloc::Model > RM)
This file a TargetTransformInfo::Concept conforming object specific to the ARM target machine.
This file contains the simple types necessary to represent the attributes associated with functions a...
basic Basic Alias true
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Provides analysis for continuously CSEing during GISel passes.
This file describes how to lower LLVM calls to machine code calls.
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableGlobalMerge("enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"), cl::init(true))
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
Interface for Targets to specify which operations they can successfully select and how the others sho...
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
Basic Register Allocator
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
speculative execution
This header is deprecated in favour of llvm/TargetParser/ARMTargetParser.h.
This header is deprecated in favour of llvm/TargetParser/TargetParser.h.
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool isLittle)
Create an ARM architecture model.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
const ARMSubtarget * getSubtargetImpl() const =delete
StringMap< std::unique_ptr< ARMSubtarget > > SubtargetMap
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
bool restrictIT() const
Definition: ARMSubtarget.h:459
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:312
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:185
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:153
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class provides the reaching def analysis.
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:44
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:222
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
bool startswith(StringRef Prefix) const
Definition: StringRef.h:261
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:97
void setMachineOutliner(bool Enable)
void setSupportsDefaultOutlining(bool Enable)
std::string TargetFS
Definition: TargetMachine.h:99
std::string TargetCPU
Definition: TargetMachine.h:98
std::unique_ptr< const MCSubtargetInfo > STI
TargetOptions Options
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
FloatABI::ABIType FloatABIType
FloatABIType - This setting is set by -float-abi=xxx option is specfied on the command line.
EABI EABIVersion
EABIVersion - This flag specifies the EABI version.
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Target-Independent Code Generator Pass Configuration Options.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
@ MuslEABIHF
Definition: Triple.h:247
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
Definition: Triple.h:372
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:583
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, or DriverKit).
Definition: Triple.h:518
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Level
Code generation optimization level.
Definition: CodeGen.h:57
@ Default
-O2, -Os
Definition: CodeGen.h:60
@ Aggressive
-O3
Definition: CodeGen.h:61
@ DynamicNoPIC
Definition: CodeGen.h:25
@ ROPI_RWPI
Definition: CodeGen.h:25
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializeARMConstantIslandsPass(PassRegistry &)
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
FunctionPass * createMVETPAndVPTOptimisationsPass()
createMVETPAndVPTOptimisationsPass
Pass * createMVELaneInterleavingPass()
FunctionPass * createARMOptimizeBarriersPass()
createARMOptimizeBarriersPass - Returns an instance of the remove double barriers pass.
FunctionPass * createIfConverter(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createTypePromotionLegacyPass()
Create IR Type Promotion pass.
void initializeMVETailPredicationPass(PassRegistry &)
void initializeMVELaneInterleavingPass(PassRegistry &)
Pass * createMVEGatherScatterLoweringPass()
Target & getTheThumbBETarget()
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createARMLowOverheadLoopsPass()
FunctionPass * createARMLoadStoreOptimizationPass(bool PreAlloc=false)
Returns an instance of the load / store optimization pass.
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:79
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createARMBranchTargetsPass()
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
void initializeARMBranchTargetsPass(PassRegistry &)
Pass * createMVETailPredicationPass()
FunctionPass * createComplexDeinterleavingPass(const TargetMachine *TM)
This pass implements generation of target-specific intrinsics to support handling of complex number a...
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
FunctionPass * createARMBlockPlacementPass()
std::unique_ptr< ScheduleDAGMutation > createARMMacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createARMMacroFusionDAGMutation()); to ARMPassConfig::crea...
Pass * createLowerAtomicPass()
void initializeARMDAGToDAGISelPass(PassRegistry &)
void initializeARMParallelDSPPass(PassRegistry &)
void initializeARMExpandPseudoPass(PassRegistry &)
FunctionPass * createA15SDOptimizerPass()
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
void initializeARMSLSHardeningPass(PassRegistry &)
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createARMISelDag(ARMBaseTargetMachine &TM, CodeGenOpt::Level OptLevel)
createARMISelDag - This pass converts a legalized DAG into a ARM-specific DAG, ready for instruction ...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
ModulePass * createBarrierNoopPass()
createBarrierNoopPass - This pass is purely a module pass barrier in a pass manager.
FunctionPass * createARMSLSHardeningPass()
FunctionPass * createARMConstantIslandPass()
createARMConstantIslandPass - returns an instance of the constpool island pass.
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
void initializeARMLowOverheadLoopsPass(PassRegistry &)
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:307
void initializeMVETPAndVPTOptimisationsPass(PassRegistry &)
void initializeARMExecutionDomainFixPass(PassRegistry &)
void initializeThumb2SizeReducePass(PassRegistry &)
FunctionPass * createThumb2ITBlockPass()
createThumb2ITBlockPass - Returns an instance of the Thumb2 IT blocks insertion pass.
void initializeMVEGatherScatterLoweringPass(PassRegistry &)
FunctionPass * createARMExpandPseudoPass()
createARMExpandPseudoPass - returns an instance of the pseudo instruction expansion pass.
FunctionPass * createARMIndirectThunks()
FunctionPass * createHardwareLoopsPass()
Create Hardware Loop pass.
void initializeARMFixCortexA57AES1742098Pass(PassRegistry &)
FunctionPass * createARMFixCortexA57AES1742098Pass()
Pass * createARMParallelDSPPass()
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
FunctionPass * createThumb2SizeReductionPass(std::function< bool(const Function &)> Ftor=nullptr)
createThumb2SizeReductionPass - Returns an instance of the Thumb2 size reduction pass.
Target & getTheARMLETarget()
void initializeMVEVPTBlockPass(PassRegistry &)
FunctionPass * createMLxExpansionPass()
void initializeARMLoadStoreOptPass(PassRegistry &)
void initializeARMPreAllocLoadStoreOptPass(PassRegistry &)
void initializeARMBlockPlacementPass(PassRegistry &)
Target & getTheARMBETarget()
Target & getTheThumbLETarget()
FunctionPass * createMVEVPTBlockPass()
createMVEVPTBlock - Returns an instance of the MVE VPT block insertion pass.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
RegisterTargetMachine - Helper template for registering a target machine implementation,...