30 #include "llvm/IR/IntrinsicsMips.h"
38 #define DEBUG_TYPE "mips-isel"
47 void MipsSEDAGToDAGISel::getAnalysisUsage(
AnalysisUsage &AU)
const {
52 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(
bool IsDef,
MachineInstr &
MI,
55 unsigned Mask =
MI.getOperand(1).getImm();
60 MIB.addReg(Mips::DSPPos,
Flag);
63 MIB.addReg(Mips::DSPSCount,
Flag);
66 MIB.addReg(Mips::DSPCarry,
Flag);
69 MIB.addReg(Mips::DSPOutFlag,
Flag);
72 MIB.addReg(Mips::DSPCCond,
Flag);
75 MIB.addReg(Mips::DSPEFI,
Flag);
78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(
const SDValue RegIdx)
const {
79 uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue();
80 return Mips::MSACtrlRegClass.getRegister(RegNum);
85 unsigned DstReg = 0, ZeroReg = 0;
88 if ((
MI.getOpcode() == Mips::ADDiu) &&
89 (
MI.getOperand(1).getReg() == Mips::ZERO) &&
90 (
MI.getOperand(2).isImm()) &&
91 (
MI.getOperand(2).getImm() == 0)) {
92 DstReg =
MI.getOperand(0).getReg();
94 }
else if ((
MI.getOpcode() == Mips::DADDiu) &&
95 (
MI.getOperand(1).getReg() == Mips::ZERO_64) &&
96 (
MI.getOperand(2).isImm()) &&
97 (
MI.getOperand(2).getImm() == 0)) {
98 DstReg =
MI.getOperand(0).getReg();
99 ZeroReg = Mips::ZERO_64;
109 unsigned OpNo = U.getOperandNo();
114 if (
MI->isPHI() ||
MI->isRegTiedToDefOperand(OpNo) ||
MI->isPseudo())
155 void MipsSEDAGToDAGISel::processFunctionAfterISel(
MachineFunction &MF) {
160 for (
auto &
MBB:
MF) {
161 for (
auto &
MI:
MBB) {
162 switch (
MI.getOpcode()) {
164 addDSPCtrlRegOperands(
false,
MI,
MF);
167 addDSPCtrlRegOperands(
true,
MI,
MF);
169 case Mips::BuildPairF64_64:
170 case Mips::ExtractElementF64_64:
183 if (
MI.getOperand(0).isGlobal() &&
184 MI.getOperand(0).getGlobal()->getGlobalIdentifier() ==
"_mcount")
187 case Mips::JALRPseudo:
188 case Mips::JALR64Pseudo:
189 case Mips::JALR16_MM:
190 if (
MI.getOperand(2).isMCSymbol() &&
191 MI.getOperand(2).getMCSymbol()->getName() ==
"_mcount")
195 if (
MI.getOperand(3).isMCSymbol() &&
196 MI.getOperand(3).getMCSymbol()->getName() ==
"_mcount")
200 replaceUsesWithZeroReg(
MRI,
MI);
206 void MipsSEDAGToDAGISel::selectAddE(
SDNode *Node,
const SDLoc &
DL)
const {
207 SDValue InFlag = Node->getOperand(2);
209 SDValue LHS = Node->getOperand(0),
RHS = Node->getOperand(1);
210 EVT VT =
LHS.getValueType();
256 SDValue InsOps[4] = {Zero, OuFlag, CstOne,
SDValue(DSPCFWithCarry, 0)};
261 SDValue(DSPCtrlFinal, 0), CstOne);
271 EVT ValTy =
Addr.getValueType();
281 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
283 unsigned ShiftAmount = 0)
const {
285 auto *CN = cast<ConstantSDNode>(
Addr.getOperand(1));
286 if (
isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
287 EVT ValTy =
Addr.getValueType();
291 dyn_cast<FrameIndexSDNode>(
Addr.getOperand(0)))
298 if (!
isAligned(Alignment, CN->getZExtValue()))
315 if (selectAddrFrameIndex(
Addr,
Base, Offset))
332 if (selectAddrFrameIndexOffset(
Addr,
Base, Offset, 16))
348 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
349 isa<JumpTableSDNode>(Opnd0)) {
371 return selectAddrRegImm(
Addr,
Base, Offset) ||
372 selectAddrDefault(
Addr,
Base, Offset);
377 if (selectAddrFrameIndex(
Addr,
Base, Offset))
380 if (selectAddrFrameIndexOffset(
Addr,
Base, Offset, 9))
389 if (selectAddrFrameIndex(
Addr,
Base, Offset))
392 if (selectAddrFrameIndexOffset(
Addr,
Base, Offset, 11))
401 if (selectAddrFrameIndex(
Addr,
Base, Offset))
404 if (selectAddrFrameIndexOffset(
Addr,
Base, Offset, 12))
412 if (selectAddrFrameIndex(
Addr,
Base, Offset))
415 if (selectAddrFrameIndexOffset(
Addr,
Base, Offset, 16))
423 return selectAddrRegImm11(
Addr,
Base, Offset) ||
424 selectAddrDefault(
Addr,
Base, Offset);
429 return selectAddrRegImm12(
Addr,
Base, Offset) ||
430 selectAddrDefault(
Addr,
Base, Offset);
435 return selectAddrRegImm16(
Addr,
Base, Offset) ||
436 selectAddrDefault(
Addr,
Base, Offset);
441 if (selectAddrFrameIndexOffset(
Addr,
Base, Offset, 7)) {
442 if (isa<FrameIndexSDNode>(
Base))
446 unsigned CnstOff = CN->getZExtValue();
447 return (CnstOff == (CnstOff & 0x3c));
455 if (selectAddrRegImm(
Addr,
Base, Offset))
458 return selectAddrDefault(
Addr,
Base, Offset);
464 if (selectAddrFrameIndex(
Addr,
Base, Offset))
467 if (selectAddrFrameIndexOffset(
Addr,
Base, Offset, 10))
470 return selectAddrDefault(
Addr,
Base, Offset);
475 if (selectAddrFrameIndex(
Addr,
Base, Offset))
478 if (selectAddrFrameIndexOffset(
Addr,
Base, Offset, 10, 1))
481 return selectAddrDefault(
Addr,
Base, Offset);
486 if (selectAddrFrameIndex(
Addr,
Base, Offset))
489 if (selectAddrFrameIndexOffset(
Addr,
Base, Offset, 10, 2))
492 return selectAddrDefault(
Addr,
Base, Offset);
497 if (selectAddrFrameIndex(
Addr,
Base, Offset))
500 if (selectAddrFrameIndexOffset(
Addr,
Base, Offset, 10, 3))
503 return selectAddrDefault(
Addr,
Base, Offset);
512 unsigned MinSizeInBits)
const {
521 APInt SplatValue, SplatUndef;
522 unsigned SplatBitSize;
525 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
550 bool MipsSEDAGToDAGISel::
552 unsigned ImmBitSize)
const {
554 EVT EltTy =
N->getValueType(0).getVectorElementType();
557 N =
N->getOperand(0);
573 bool MipsSEDAGToDAGISel::
575 return selectVSplatCommon(
N,
Imm,
false, 1);
578 bool MipsSEDAGToDAGISel::
580 return selectVSplatCommon(
N,
Imm,
false, 2);
583 bool MipsSEDAGToDAGISel::
585 return selectVSplatCommon(
N,
Imm,
false, 3);
589 bool MipsSEDAGToDAGISel::
591 return selectVSplatCommon(
N,
Imm,
false, 4);
595 bool MipsSEDAGToDAGISel::
597 return selectVSplatCommon(
N,
Imm,
false, 5);
601 bool MipsSEDAGToDAGISel::
603 return selectVSplatCommon(
N,
Imm,
false, 6);
607 bool MipsSEDAGToDAGISel::
609 return selectVSplatCommon(
N,
Imm,
false, 8);
613 bool MipsSEDAGToDAGISel::
615 return selectVSplatCommon(
N,
Imm,
true, 5);
630 EVT EltTy =
N->getValueType(0).getVectorElementType();
633 N =
N->getOperand(0);
661 EVT EltTy =
N->getValueType(0).getVectorElementType();
664 N =
N->getOperand(0);
671 if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
695 EVT EltTy =
N->getValueType(0).getVectorElementType();
698 N =
N->getOperand(0);
704 if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
714 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(
SDValue N,
717 EVT EltTy =
N->getValueType(0).getVectorElementType();
720 N =
N->getOperand(0);
724 int32_t
Log2 = (~ImmValue).exactLogBase2();
735 bool MipsSEDAGToDAGISel::trySelect(
SDNode *Node) {
736 unsigned Opcode = Node->getOpcode();
746 case Mips::PseudoD_SELECT_I:
747 case Mips::PseudoD_SELECT_I64: {
749 SDValue cond = Node->getOperand(0);
750 SDValue Hi1 = Node->getOperand(1);
751 SDValue Lo1 = Node->getOperand(2);
752 SDValue Hi2 = Node->getOperand(3);
753 SDValue Lo2 = Node->getOperand(4);
756 EVT NodeTys[] = {VT, VT};
758 ? Mips::PseudoD_SELECT_I64
759 : Mips::PseudoD_SELECT_I,
765 selectAddE(Node,
DL);
770 auto *CN = cast<ConstantFPSDNode>(Node);
771 if (Node->getValueType(0) ==
MVT::f64 && CN->isExactlyValue(+0.0)) {
794 auto *CN = cast<ConstantSDNode>(Node);
795 int64_t
Imm = CN->getSExtValue();
796 unsigned Size = CN->getValueSizeInBits(0);
815 if (Inst->Opc == Mips::LUi64)
824 for (++Inst; Inst != Seq.end(); ++Inst) {
836 const unsigned IntrinsicOpcode =
837 cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
838 switch (IntrinsicOpcode) {
842 case Intrinsic::mips_cfcmsa: {
843 SDValue ChainIn = Node->getOperand(0);
844 SDValue RegIdx = Node->getOperand(2);
850 case Intrinsic::mips_ldr_d:
851 case Intrinsic::mips_ldr_w: {
852 unsigned Op = (IntrinsicOpcode == Intrinsic::mips_ldr_d) ? Mips::LDR_D
856 assert(Node->getNumOperands() == 4 &&
"Unexpected number of operands.");
857 const SDValue &Chain = Node->getOperand(0);
866 "Invalid instruction operand.");
870 cast<ConstantSDNode>(
Constant)->getConstantIntValue();
876 assert(Node->getNumValues() == 2);
877 assert(Node->getValueType(0).is128BitVector());
890 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
894 case Intrinsic::mips_move_v:
898 Node->getValueType(0),
899 Node->getOperand(1)));
906 const unsigned IntrinsicOpcode =
907 cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
908 switch (IntrinsicOpcode) {
912 case Intrinsic::mips_ctcmsa: {
913 SDValue ChainIn = Node->getOperand(0);
914 SDValue RegIdx = Node->getOperand(2);
917 getMSACtrlReg(RegIdx),
Value);
921 case Intrinsic::mips_str_d:
922 case Intrinsic::mips_str_w: {
923 unsigned Op = (IntrinsicOpcode == Intrinsic::mips_str_d) ? Mips::STR_D
927 assert(Node->getNumOperands() == 5 &&
"Unexpected number of operands.");
928 const SDValue &Chain = Node->getOperand(0);
930 const SDValue &Vec = Node->getOperand(2);
938 "Invalid instruction operand.");
942 cast<ConstantSDNode>(
Constant)->getConstantIntValue();
948 assert(Node->getNumValues() == 1);
960 MVT ResTy = Node->getSimpleValueType(0);
962 "Unsupported float type!");
972 Opc = Mips::FABS_D64_MM;
975 Opc = Mips::FABS_D32_MM;
978 Opc = Mips::FABS_S_MM;
1000 if (Node->getValueType(0) !=
MVT::i32 && Node->getValueType(0) !=
MVT::i64)
1003 if (Node->getNumOperands() != 4)
1010 MVT ResTy = Node->getSimpleValueType(0);
1011 uint64_t Pos = Node->getConstantOperandVal(1);
1018 if (Pos + Size > 64)
1024 unsigned Opcode = 0;
1026 if (Pos + Size <= 32)
1029 if (Pos + Size <= 32)
1030 Opcode = Mips::DINS;
1031 else if (Pos < 32 && 1 < Size)
1032 Opcode = Mips::DINSM;
1034 Opcode = Mips::DINSU;
1051 unsigned RdhwrOpc, DestReg;
1054 RdhwrOpc = Mips::RDHWR;
1057 RdhwrOpc = Mips::RDHWR64;
1058 DestReg = Mips::V1_64;
1090 APInt SplatValue, SplatUndef;
1091 unsigned SplatBitSize;
1105 switch (SplatBitSize) {
1109 LdiOp = Mips::LDI_B;
1113 LdiOp = Mips::LDI_H;
1117 LdiOp = Mips::LDI_W;
1121 LdiOp = Mips::LDI_D;
1138 ((
ABI.IsO32() && SplatBitSize < 64) ||
1139 (
ABI.IsN32() ||
ABI.IsN64()))) {
1145 bool Is32BitSplat =
ABI.IsO32() || SplatBitSize < 64;
1146 const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
1149 Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT);
1151 const unsigned FILLOp =
1154 : (SplatBitSize == 32 ? Mips::FILL_W
1155 : (SplatBitSize == 64 ? Mips::FILL_D : 0));
1157 assert(FILLOp != 0 &&
"Unknown FILL Op for splat synthesis!");
1158 assert((!
ABI.IsO32() || (FILLOp != Mips::FILL_D)) &&
1159 "Attempting to use fill.d on MIPS32!");
1167 }
else if (SplatValue.
isSignedIntN(32) && SplatBitSize == 32) {
1182 Hi ?
SDValue(Res, 0) : ZeroVal, LoVal);
1184 assert((Hi || Lo) &&
"Zero case reached 32 bit case splat synthesis!");
1188 }
else if (SplatValue.
isSignedIntN(32) && SplatBitSize == 64 &&
1189 (
ABI.IsN32() ||
ABI.IsN64())) {
1205 Hi ?
SDValue(Res, 0) : ZeroVal, LoVal);
1274 Hi ?
SDValue(Res, 0) : ZeroVal, LoVal);
1288 (Hi || Lo) ?
SDValue(Res, 0) : ZeroVal);
1300 Mips::COPY_TO_REGCLASS,
DL, ViaVecTy,
SDValue(Res, 0),
1306 }
else if (
ABI.IsN64() ||
ABI.IsN32()) {
1310 const bool ResNonZero =
Hi ||
Lo;
1343 }
else if (HiResNonZero) {
1349 "Zero splat value handled by non-zero 64bit splat synthesis!");
1359 if (ResVecTy != ViaVecTy) {
1382 bool MipsSEDAGToDAGISel::
1383 SelectInlineAsmMemoryOperand(
const SDValue &
Op,
unsigned ConstraintID,
1384 std::vector<SDValue> &OutOps) {
1387 switch(ConstraintID) {
1393 if (selectAddrRegImm16(
Op,
Base, Offset)) {
1394 OutOps.push_back(
Base);
1395 OutOps.push_back(Offset);
1398 OutOps.push_back(
Op);
1407 if (selectAddrRegImm9(
Op,
Base, Offset)) {
1408 OutOps.push_back(
Base);
1409 OutOps.push_back(Offset);
1412 OutOps.push_back(
Op);
1420 if (selectAddrRegImm12(
Op,
Base, Offset)) {
1421 OutOps.push_back(
Base);
1422 OutOps.push_back(Offset);
1427 if (selectAddrRegImm9(
Op,
Base, Offset)) {
1428 OutOps.push_back(
Base);
1429 OutOps.push_back(Offset);
1432 }
else if (selectAddrRegImm16(
Op,
Base, Offset)) {
1434 OutOps.push_back(
Base);
1435 OutOps.push_back(Offset);
1439 OutOps.push_back(
Op);