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41 unsigned Opc =
MI->getOpcode();
43 case TargetOpcode::COPY: {
54 EM.insert(std::make_pair(DstR, SrcR));
57 case TargetOpcode::REG_SEQUENCE:
64 CopyMap.insert(std::make_pair(SA.
Id, EM));
65 Copies.push_back(SA.
Id);
83 Changed |= scanBlock(
I->getBlock());
95 if (
NodeId RD =
RA.Addr->getReachingDef())
105 dbgs() <<
"Copies:\n";
109 for (
auto J : CopyMap[
I])
116 bool Changed =
false;
118 bool HasLimit =
CpLimit.getNumOccurrences() > 0;
121 auto MinPhysReg = [
this] (
RegisterRef RR) ->
unsigned {
128 return S.getSubReg();
139 auto FS = CopyMap.find(SA.
Id);
140 if (
FS == CopyMap.end())
146 auto FR = EM.find(DR);
153 NodeId AtCopy = getLocalReachingDef(SR, SA);
155 for (
NodeId N =
DA.Addr->getReachedUse(), NextN;
N;
N = NextN) {
161 if (UA.Addr->getRegRef(DFG) != DR)
166 NodeId AtUse = getLocalReachingDef(SR, IA);
179 unsigned NewReg = MinPhysReg(SR);
184 UA.Addr->linkToDef(UA.Id, DFG.
addr<
DefNode*>(AtCopy));
186 UA.Addr->setReachingDef(0);
187 UA.Addr->setSibling(0);
197 auto FC = CopyMap.find(IA.
Id);
198 if (
FC != CopyMap.end()) {
200 auto &
M =
FC->second;
MachineFunction & getMF() const
NodeId getSibling() const
This is an optimization pass for GlobalISel generic memory operations.
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Iterator that enumerates the sub-registers of a Reg and the associated sub-register indices.
NodeList members_if(Predicate P, const DataFlowGraph &G) const
virtual bool interpretAsCopy(const MachineInstr *MI, EqualityMap &EM)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
void unlinkUse(NodeAddr< UseNode * > UA, bool RemoveFromOwner)
NodeAddr< RefNode * > getNearestAliasedRef(RegisterRef RefRR, NodeAddr< InstrNode * > IA)
Find the nearest ref node aliased to RefRR, going upwards in the data flow, starting from the instruc...
unsigned const TargetRegisterInfo * TRI
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const MachineBasicBlock & front() const
LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const
Return a bitmask representing the parts of a register that are covered by SubIdx.
(vector float) vec_cmpeq(*A, *B) C
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
MachineOperand class - Representation of each machine instruction operand.
static bool IsDef(const NodeAddr< NodeBase * > BA)
RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const
static bool IsCode(const NodeAddr< NodeBase * > BA)
const LaneBitmask LaneMask
NodeAddr< T > addr(NodeId N) const
Representation of each machine instruction.
const TargetRegisterInfo & getTRI() const
NodeList members(const DataFlowGraph &G) const
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
initializer< Ty > init(const Ty &Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
SI optimize exec mask operations pre RA
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Base class for the actual dominator tree node.
this could be done in SelectionDAGISel along with other special for
MachineInstr * getCode() const
static cl::opt< unsigned > CpLimit("rdf-cp-limit", cl::init(0), cl::Hidden)
std::map< RegisterRef, RegisterRef > EqualityMap
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
NodeAddr< BlockNode * > findBlock(MachineBasicBlock *BB) const
NodeAddr< NodeBase * > getOwner(const DataFlowGraph &G)