23#include "llvm/IR/IntrinsicsSPIRV.h"
31#define DEBUG_TYPE "spirv-legalizer"
34 return [IsExtendedInts, TypeIdx](
const LegalityQuery &Query) {
35 const LLT Ty = Query.Types[TypeIdx];
36 return IsExtendedInts && Ty.isValid() && Ty.isScalar();
83 const unsigned PSize = ST.getPointerSize();
101 auto allPtrsScalarsAndVectors = {
102 p0, p1, p2, p3, p4, p5, p6, p7, p8,
103 p9, p10, p11, p12, s1, s8, s16, s32, s64,
104 v2s1, v2s8, v2s16, v2s32, v2s64, v3s1, v3s8, v3s16, v3s32,
105 v3s64, v4s1, v4s8, v4s16, v4s32, v4s64, v8s1, v8s8, v8s16,
106 v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
108 auto allVectors = {v2s1, v2s8, v2s16, v2s32, v2s64, v3s1, v3s8,
109 v3s16, v3s32, v3s64, v4s1, v4s8, v4s16, v4s32,
110 v4s64, v8s1, v8s8, v8s16, v8s32, v8s64, v16s1,
111 v16s8, v16s16, v16s32, v16s64};
113 auto allShaderVectors = {v2s1, v2s8, v2s16, v2s32, v2s64,
114 v3s1, v3s8, v3s16, v3s32, v3s64,
115 v4s1, v4s8, v4s16, v4s32, v4s64};
117 auto allScalars = {s1, s8, s16, s32, s64};
119 auto allScalarsAndVectors = {
120 s1, s8, s16, s32, s64, s128, v2s1, v2s8,
121 v2s16, v2s32, v2s64, v3s1, v3s8, v3s16, v3s32, v3s64,
122 v4s1, v4s8, v4s16, v4s32, v4s64, v8s1, v8s8, v8s16,
123 v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
125 auto allIntScalarsAndVectors = {
126 s8, s16, s32, s64, s128, v2s8, v2s16, v2s32, v2s64,
127 v3s8, v3s16, v3s32, v3s64, v4s8, v4s16, v4s32, v4s64, v8s8,
128 v8s16, v8s32, v8s64, v16s8, v16s16, v16s32, v16s64};
130 auto allBoolScalarsAndVectors = {s1, v2s1, v3s1, v4s1, v8s1, v16s1};
132 auto allIntScalars = {s8, s16, s32, s64, s128};
134 auto allFloatScalarsAndF16Vector2AndVector4s = {s16, s32, s64, v2s16, v4s16};
136 auto allFloatScalarsAndVectors = {
137 s16, s32, s64, v2s16, v2s32, v2s64, v3s16, v3s32, v3s64,
138 v4s16, v4s32, v4s64, v8s16, v8s32, v8s64, v16s16, v16s32, v16s64};
140 auto allFloatAndIntScalarsAndPtrs = {s8, s16, s32, s64, p0, p1, p2, p3, p4,
141 p5, p6, p7, p8, p9, p10, p11, p12};
143 auto allPtrs = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12};
145 auto &allowedVectorTypes = ST.isShader() ? allShaderVectors : allVectors;
147 bool IsExtendedInts =
149 SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||
150 ST.canUseExtension(SPIRV::Extension::SPV_KHR_bit_instructions) ||
151 ST.canUseExtension(SPIRV::Extension::SPV_INTEL_int4);
152 auto extendedScalarsAndVectors =
154 const LLT Ty = Query.Types[0];
155 return IsExtendedInts && Ty.isValid() && !Ty.isPointerOrPointerVector();
157 auto extendedScalarsAndVectorsProduct = [IsExtendedInts](
159 const LLT Ty1 = Query.Types[0], Ty2 = Query.Types[1];
160 return IsExtendedInts && Ty1.
isValid() && Ty2.isValid() &&
163 auto extendedPtrsScalarsAndVectors =
165 const LLT Ty = Query.Types[0];
166 return IsExtendedInts && Ty.isValid();
175 uint32_t MaxVectorSize = ST.isShader() ? 4 : 16;
179 case G_EXTRACT_VECTOR_ELT:
200 .customFor(allScalars)
209 .legalFor(allScalars)
278 {G_VECREDUCE_SMIN, G_VECREDUCE_SMAX, G_VECREDUCE_UMIN, G_VECREDUCE_UMAX,
279 G_VECREDUCE_ADD, G_VECREDUCE_MUL, G_VECREDUCE_FMUL, G_VECREDUCE_FMIN,
280 G_VECREDUCE_FMAX, G_VECREDUCE_FMINIMUM, G_VECREDUCE_FMAXIMUM,
281 G_VECREDUCE_OR, G_VECREDUCE_AND, G_VECREDUCE_XOR})
282 .legalFor(allowedVectorTypes)
310 .unsupportedIf(
typeIs(1, p9))
314 G_BITREVERSE, G_SADDSAT, G_UADDSAT, G_SSUBSAT,
315 G_USUBSAT, G_SCMP, G_UCMP})
316 .legalFor(allIntScalarsAndVectors)
317 .
legalIf(extendedScalarsAndVectors);
323 .legalForCartesianProduct(allIntScalarsAndVectors,
324 allFloatScalarsAndVectors);
327 .legalForCartesianProduct(allIntScalarsAndVectors,
328 allFloatScalarsAndVectors);
331 .legalForCartesianProduct(allFloatScalarsAndVectors,
332 allScalarsAndVectors);
336 .
legalIf(extendedScalarsAndVectorsProduct);
340 .legalForCartesianProduct(allScalarsAndVectors)
341 .
legalIf(extendedScalarsAndVectorsProduct);
345 .
legalIf(extendedPtrsScalarsAndVectors);
349 typeInSet(1, allPtrsScalarsAndVectors)));
352 .legalFor({s1, s128})
353 .legalFor(allFloatAndIntScalarsAndPtrs)
382 typeInSet(1, allPtrsScalarsAndVectors)));
386 typeInSet(1, allFloatScalarsAndVectors)));
389 G_ATOMICRMW_MAX, G_ATOMICRMW_MIN,
390 G_ATOMICRMW_SUB, G_ATOMICRMW_XOR,
391 G_ATOMICRMW_UMAX, G_ATOMICRMW_UMIN})
392 .legalForCartesianProduct(allIntScalars, allPtrs);
395 {G_ATOMICRMW_FADD, G_ATOMICRMW_FSUB, G_ATOMICRMW_FMIN, G_ATOMICRMW_FMAX})
396 .legalForCartesianProduct(allFloatScalarsAndF16Vector2AndVector4s,
407 {G_UADDO, G_SADDO, G_USUBO, G_SSUBO, G_UMULO, G_SMULO})
411 .legalForCartesianProduct(allFloatScalarsAndVectors,
412 allIntScalarsAndVectors);
416 .legalForCartesianProduct(allFloatScalarsAndVectors);
427 allFloatScalarsAndVectors, {s32, v2s32, v3s32, v4s32, v8s32, v16s32});
463 G_INTRINSIC_ROUNDEVEN})
464 .legalFor(allFloatScalarsAndVectors);
468 allFloatScalarsAndVectors);
471 allFloatScalarsAndVectors, allIntScalarsAndVectors);
473 if (ST.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
475 {G_CTTZ, G_CTTZ_ZERO_UNDEF, G_CTLZ, G_CTLZ_ZERO_UNDEF})
476 .legalForCartesianProduct(allIntScalarsAndVectors,
477 allIntScalarsAndVectors);
486 verify(*ST.getInstrInfo());
500 MI.eraseFromParent();
517 MI.eraseFromParent();
525 Register ConvReg =
MRI.createGenericVirtualRegister(ConvTy);
538 switch (
MI.getOpcode()) {
542 case TargetOpcode::G_BITCAST:
543 return legalizeBitcast(Helper,
MI);
544 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
546 case TargetOpcode::G_INSERT_VECTOR_ELT:
548 case TargetOpcode::G_INTRINSIC:
549 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
551 case TargetOpcode::G_IS_FPCLASS:
552 return legalizeIsFPClass(Helper,
MI, LocObserver);
553 case TargetOpcode::G_ICMP: {
554 assert(GR->getSPIRVTypeForVReg(
MI.getOperand(0).getReg()));
555 auto &Op0 =
MI.getOperand(2);
556 auto &Op1 =
MI.getOperand(3);
561 if ((!ST->canDirectlyComparePointers() ||
563 MRI.getType(Reg0).isPointer() &&
MRI.getType(Reg1).isPointer()) {
566 ST->getPointerSize());
567 SPIRVType *SpirvTy = GR->getOrCreateSPIRVType(
568 LLVMTy, Helper.
MIRBuilder, SPIRV::AccessQualifier::ReadWrite,
true);
580 unsigned NumElements = Ty.getNumElements();
581 unsigned MaxVectorSize = ST.isShader() ? 4 : 16;
583 NumElements > MaxVectorSize;
595 if (IntrinsicID == Intrinsic::spv_bitcast) {
599 LLT DstTy =
MRI.getType(DstReg);
600 LLT SrcTy =
MRI.getType(SrcReg);
608 MI.eraseFromParent();
611 }
else if (IntrinsicID == Intrinsic::spv_insertelt) {
613 LLT DstTy =
MRI.getType(DstReg);
620 MI.eraseFromParent();
623 }
else if (IntrinsicID == Intrinsic::spv_extractelt) {
625 LLT SrcTy =
MRI.getType(SrcReg);
631 MI.eraseFromParent();
649 MI.eraseFromParent();
656bool SPIRVLegalizerInfo::legalizeIsFPClass(
659 auto [DstReg, DstTy, SrcReg, SrcTy] =
MI.getFirst2RegLLTs();
663 auto &MF = MIRBuilder.
getMF();
664 MachineRegisterInfo &
MRI = MF.getRegInfo();
668 if (DstTy.isVector())
670 SPIRVType *SPIRVDstTy = GR->getOrCreateSPIRVType(
671 LLVMDstTy, MIRBuilder, SPIRV::AccessQualifier::ReadWrite,
674 unsigned BitSize = SrcTy.getScalarSizeInBits();
679 if (SrcTy.isVector()) {
680 IntTy =
LLT::vector(SrcTy.getElementCount(), IntTy);
683 SPIRVType *SPIRVIntTy = GR->getOrCreateSPIRVType(
684 LLVMIntTy, MIRBuilder, SPIRV::AccessQualifier::ReadWrite,
688 LLT DstTyCopy = DstTy;
689 const auto assignSPIRVTy = [&](MachineInstrBuilder &&
MI) {
693 LLT MITy =
MRI.getType(
MI.getReg(0));
694 assert((MITy == IntTy || MITy == DstTyCopy) &&
695 "Unexpected LLT type while lowering G_IS_FPCLASS");
696 auto *SPVTy = MITy == IntTy ? SPIRVIntTy : SPIRVDstTy;
697 GR->assignSPIRVTypeToVReg(SPVTy,
MI.getReg(0), MF);
702 const auto buildSPIRVConstant = [&](LLT Ty,
auto &&
C) -> MachineInstrBuilder {
706 assert((Ty == IntTy || Ty == DstTyCopy) &&
707 "Unexpected LLT type while lowering constant for G_IS_FPCLASS");
708 SPIRVType *VecEltTy = GR->getOrCreateSPIRVType(
709 (Ty == IntTy ? LLVMIntTy : LLVMDstTy)->getScalarType(), MIRBuilder,
710 SPIRV::AccessQualifier::ReadWrite,
712 GR->assignSPIRVTypeToVReg(VecEltTy, ScalarC.getReg(0), MF);
717 MIRBuilder.
buildCopy(DstReg, buildSPIRVConstant(DstTy, 0));
718 MI.eraseFromParent();
722 MIRBuilder.
buildCopy(DstReg, buildSPIRVConstant(DstTy, 1));
723 MI.eraseFromParent();
731 Register ResVReg =
MRI.createGenericVirtualRegister(IntTy);
732 MRI.setRegClass(ResVReg, GR->getRegClass(SPIRVIntTy));
733 GR->assignSPIRVTypeToVReg(SPIRVIntTy, ResVReg, Helper.
MIRBuilder.
getMF());
734 auto AsInt = MIRBuilder.
buildInstr(SPIRV::OpBitcast)
736 .
addUse(GR->getSPIRVTypeID(SPIRVIntTy))
738 AsInt = assignSPIRVTy(std::move(AsInt));
750 auto SignBitC = buildSPIRVConstant(IntTy, SignBit);
751 auto ValueMaskC = buildSPIRVConstant(IntTy, ValueMask);
752 auto InfC = buildSPIRVConstant(IntTy, Inf);
753 auto ExpMaskC = buildSPIRVConstant(IntTy, ExpMask);
754 auto ZeroC = buildSPIRVConstant(IntTy, 0);
756 auto Abs = assignSPIRVTy(MIRBuilder.
buildAnd(IntTy, AsInt, ValueMaskC));
757 auto Sign = assignSPIRVTy(
760 auto Res = buildSPIRVConstant(DstTy, 0);
762 const auto appendToRes = [&](MachineInstrBuilder &&ToAppend) {
764 MIRBuilder.
buildOr(DstTyCopy, Res, assignSPIRVTy(std::move(ToAppend))));
777 Mask &= ~fcPosFinite;
781 DstTy, Abs, ExpMaskC));
782 appendToRes(MIRBuilder.
buildAnd(DstTy, Cmp, Sign));
783 Mask &= ~fcNegFinite;
791 auto ExpBits = assignSPIRVTy(MIRBuilder.
buildAnd(IntTy, AsInt, ExpMaskC));
794 Mask &= ~PartialCheck;
803 else if (PartialCheck ==
fcZero)
815 auto OneC = buildSPIRVConstant(IntTy, 1);
816 auto VMinusOne = MIRBuilder.
buildSub(IntTy, V, OneC);
817 auto SubnormalRes = assignSPIRVTy(
819 buildSPIRVConstant(IntTy, AllOneMantissa)));
821 SubnormalRes = MIRBuilder.
buildAnd(DstTy, SubnormalRes, Sign);
822 appendToRes(std::move(SubnormalRes));
829 else if (PartialCheck ==
fcInf)
834 auto NegInfC = buildSPIRVConstant(IntTy, NegInf);
841 auto InfWithQnanBitC =
842 buildSPIRVConstant(IntTy, std::move(Inf) | QNaNBitMask);
843 if (PartialCheck ==
fcNan) {
847 }
else if (PartialCheck ==
fcQNan) {
854 auto IsNan = assignSPIRVTy(
856 auto IsNotQnan = assignSPIRVTy(MIRBuilder.
buildICmp(
858 appendToRes(MIRBuilder.
buildAnd(DstTy, IsNan, IsNotQnan));
865 APInt ExpLSB = ExpMask & ~(ExpMask.
shl(1));
866 auto ExpMinusOne = assignSPIRVTy(
867 MIRBuilder.
buildSub(IntTy, Abs, buildSPIRVConstant(IntTy, ExpLSB)));
868 APInt MaxExpMinusOne = std::move(ExpMask) - ExpLSB;
869 auto NormalRes = assignSPIRVTy(
871 buildSPIRVConstant(IntTy, MaxExpMinusOne)));
873 NormalRes = MIRBuilder.
buildAnd(DstTy, NormalRes, Sign);
875 auto PosSign = assignSPIRVTy(MIRBuilder.
buildXor(
876 DstTy, Sign, buildSPIRVConstant(DstTy, InversionMask)));
877 NormalRes = MIRBuilder.
buildAnd(DstTy, NormalRes, PosSign);
879 appendToRes(std::move(NormalRes));
883 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static void scalarize(Instruction *I, SmallVectorImpl< Instruction * > &Worklist)
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
This file declares the MachineIRBuilder class.
Promote Memory to Register
const SmallVectorImpl< MachineOperand > & Cond
static bool needsVectorLegalization(const LLT &Ty, const SPIRVSubtarget &ST)
static Register convertPtrToInt(Register Reg, LLT ConvTy, SPIRVType *SpvType, LegalizerHelper &Helper, MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR)
LegalityPredicate typeOfExtendedScalars(unsigned TypeIdx, bool IsExtendedInts)
static bool legalizeExtractVectorElt(LegalizerHelper &Helper, MachineInstr &MI, SPIRVGlobalRegistry *GR)
static bool legalizeInsertVectorElt(LegalizerHelper &Helper, MachineInstr &MI, SPIRVGlobalRegistry *GR)
APInt bitcastToAPInt() const
static APFloat getLargest(const fltSemantics &Sem, bool Negative=false)
Returns the largest finite number in the given semantics.
static APFloat getInf(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Infinity.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
unsigned getActiveBits() const
Compute the number of active bits in the value.
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
APInt shl(unsigned shiftAmt) const
Left-shift function.
static APInt getOneBitSet(unsigned numBits, unsigned BitNo)
Return an APInt with exactly one bit set in the result.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_ULT
unsigned less than
static constexpr ElementCount getFixed(ScalarTy MinVal)
static LLVM_ABI IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
constexpr bool isPointerOrPointerVector() const
constexpr bool isFixedVector() const
Returns true if the LLT is a fixed vector.
constexpr LLT getScalarType() const
LLVM_ABI void computeTables()
Compute any ancillary tables needed to quickly decide how an operation should be handled.
LegalizeRuleSet & legalFor(std::initializer_list< LLT > Types)
The instruction is legal when type index 0 is any type in the given list.
LegalizeRuleSet & fewerElementsIf(LegalityPredicate Predicate, LegalizeMutation Mutation)
Remove elements to reach the type selected by the mutation if the predicate is true.
LegalizeRuleSet & moreElementsToNextPow2(unsigned TypeIdx)
Add more elements to the vector to reach the next power of two.
LegalizeRuleSet & lower()
The instruction is lowered.
LegalizeRuleSet & scalarizeIf(LegalityPredicate Predicate, unsigned TypeIdx)
LegalizeRuleSet & lowerIf(LegalityPredicate Predicate)
The instruction is lowered if predicate is true.
LegalizeRuleSet & custom()
Unconditionally custom lower.
LegalizeRuleSet & unsupportedIf(LegalityPredicate Predicate)
LegalizeRuleSet & alwaysLegal()
LegalizeRuleSet & customIf(LegalityPredicate Predicate)
LegalizeRuleSet & scalarize(unsigned TypeIdx)
LegalizeRuleSet & legalForCartesianProduct(std::initializer_list< LLT > Types)
The instruction is legal when type indexes 0 and 1 are both in the given list.
LegalizeRuleSet & legalIf(LegalityPredicate Predicate)
The instruction is legal if predicate is true.
LegalizeRuleSet & customFor(std::initializer_list< LLT > Types)
MachineIRBuilder & MIRBuilder
Expose MIRBuilder so clients can set their own RecordInsertInstruction functions.
LegalizeRuleSet & getActionDefinitionsBuilder(unsigned Opcode)
Get the action definition builder for the given opcode.
const LegacyLegalizerInfo & getLegacyLegalizerInfo() const
Helper class to build MachineInstr.
LLVMContext & getContext() const
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_SUB Op0, Op1.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)
Build and insert a G_INTRINSIC instruction.
MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_OR Op0, Op1.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, const MachineFunction &MF)
const TargetRegisterClass * getRegClass(SPIRVType *SpvType) const
SPIRVLegalizerInfo(const SPIRVSubtarget &ST)
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI, LostDebugLocObserver &LocObserver) const override
Called for instructions with the Custom LegalizationAction.
bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override
SPIRVGlobalRegistry * getSPIRVGlobalRegistry() const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
The instances of the Type class are immutable: once they are created, they are never changed.
static LLVM_ABI VectorType * get(Type *ElementType, ElementCount EC)
This static method is the primary way to construct an VectorType.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ C
The default llvm calling convention, compatible with C.
LLVM_ABI LegalityPredicate numElementsNotPow2(unsigned TypeIdx)
True iff the specified type index is a vector whose element count is not a power of 2.
LLVM_ABI LegalityPredicate vectorElementCountIsLessThanOrEqualTo(unsigned TypeIdx, unsigned Size)
True iff the specified type index is a vector with a number of elements that's less than or equal to ...
LLVM_ABI LegalityPredicate typeInSet(unsigned TypeIdx, std::initializer_list< LLT > TypesInit)
True iff the given type index is one of the specified types.
LLVM_ABI LegalityPredicate vectorElementCountIsGreaterThan(unsigned TypeIdx, unsigned Size)
True iff the specified type index is a vector with a number of elements that's greater than the given...
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
LegalityPredicate typeIsNot(unsigned TypeIdx, LLT Type)
True iff the given type index is not the specified type.
Predicate all(Predicate P0, Predicate P1)
True iff P0 and P1 are true.
LLVM_ABI LegalityPredicate typeIs(unsigned TypeIdx, LLT TypesInit)
True iff the given type index is the specified type.
LLVM_ABI LegalizeMutation changeElementCountTo(unsigned TypeIdx, unsigned FromTypeIdx)
Keep the same scalar or element type as TypeIdx, but take the number of elements from FromTypeIdx.
LLVM_ABI LegalizeMutation changeElementSizeTo(unsigned TypeIdx, unsigned FromTypeIdx)
Change the scalar size or element size to have the same scalar size as type index FromIndex.
Invariant opcodes: All instruction sets have these as their low opcodes.
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)
Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.
std::function< bool(const LegalityQuery &)> LegalityPredicate
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
FPClassTest
Floating-point class tests, supported by 'is_fpclass' intrinsic.
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const MachineInstr SPIRVType
const std::set< unsigned > & getTypeFoldingSupportedOpcodes()
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
The LegalityQuery object bundles together all the information that's needed to decide whether a given...