23#include "llvm/IR/IntrinsicsSPIRV.h"
31#define DEBUG_TYPE "spirv-legalizer"
34 return [IsExtendedInts, TypeIdx](
const LegalityQuery &Query) {
35 const LLT Ty = Query.Types[TypeIdx];
36 return IsExtendedInts && Ty.isValid() && Ty.isScalar();
83 const unsigned PSize = ST.getPointerSize();
102 auto allPtrsScalarsAndVectors = {
103 p0, p1, p2, p3, p4, p5, p6, p7, p8,
104 p9, p10, p11, p12, p13, s1, s8, s16, s32,
105 s64, v2s1, v2s8, v2s16, v2s32, v2s64, v3s1, v3s8, v3s16,
106 v3s32, v3s64, v4s1, v4s8, v4s16, v4s32, v4s64, v8s1, v8s8,
107 v8s16, v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
109 auto allVectors = {v2s1, v2s8, v2s16, v2s32, v2s64, v3s1, v3s8,
110 v3s16, v3s32, v3s64, v4s1, v4s8, v4s16, v4s32,
111 v4s64, v8s1, v8s8, v8s16, v8s32, v8s64, v16s1,
112 v16s8, v16s16, v16s32, v16s64};
114 auto allShaderVectors = {v2s1, v2s8, v2s16, v2s32, v2s64,
115 v3s1, v3s8, v3s16, v3s32, v3s64,
116 v4s1, v4s8, v4s16, v4s32, v4s64};
118 auto allScalars = {s1, s8, s16, s32, s64};
120 auto allScalarsAndVectors = {
121 s1, s8, s16, s32, s64, s128, v2s1, v2s8,
122 v2s16, v2s32, v2s64, v3s1, v3s8, v3s16, v3s32, v3s64,
123 v4s1, v4s8, v4s16, v4s32, v4s64, v8s1, v8s8, v8s16,
124 v8s32, v8s64, v16s1, v16s8, v16s16, v16s32, v16s64};
126 auto allIntScalarsAndVectors = {
127 s8, s16, s32, s64, s128, v2s8, v2s16, v2s32, v2s64,
128 v3s8, v3s16, v3s32, v3s64, v4s8, v4s16, v4s32, v4s64, v8s8,
129 v8s16, v8s32, v8s64, v16s8, v16s16, v16s32, v16s64};
131 auto allBoolScalarsAndVectors = {s1, v2s1, v3s1, v4s1, v8s1, v16s1};
133 auto allIntScalars = {s8, s16, s32, s64, s128};
135 auto allFloatScalarsAndF16Vector2AndVector4s = {s16, s32, s64, v2s16, v4s16};
137 auto allFloatScalarsAndVectors = {
138 s16, s32, s64, v2s16, v2s32, v2s64, v3s16, v3s32, v3s64,
139 v4s16, v4s32, v4s64, v8s16, v8s32, v8s64, v16s16, v16s32, v16s64};
141 auto allFloatAndIntScalarsAndPtrs = {s8, s16, s32, s64, p0, p1,
142 p2, p3, p4, p5, p6, p7,
143 p8, p9, p10, p11, p12, p13};
145 auto allPtrs = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13};
147 auto &allowedVectorTypes = ST.isShader() ? allShaderVectors : allVectors;
149 bool IsExtendedInts =
151 SPIRV::Extension::SPV_ALTERA_arbitrary_precision_integers) ||
152 ST.canUseExtension(SPIRV::Extension::SPV_KHR_bit_instructions) ||
153 ST.canUseExtension(SPIRV::Extension::SPV_INTEL_int4);
154 auto extendedScalarsAndVectors =
156 const LLT Ty = Query.Types[0];
157 return IsExtendedInts && Ty.isValid() && !Ty.isPointerOrPointerVector();
159 auto extendedScalarsAndVectorsProduct = [IsExtendedInts](
161 const LLT Ty1 = Query.Types[0], Ty2 = Query.Types[1];
162 return IsExtendedInts && Ty1.
isValid() && Ty2.isValid() &&
165 auto extendedPtrsScalarsAndVectors =
167 const LLT Ty = Query.Types[0];
168 return IsExtendedInts && Ty.isValid();
177 uint32_t MaxVectorSize = ST.isShader() ? 4 : 16;
181 case G_EXTRACT_VECTOR_ELT:
202 .customFor(allScalars)
211 .legalFor(allScalars)
280 {G_VECREDUCE_SMIN, G_VECREDUCE_SMAX, G_VECREDUCE_UMIN, G_VECREDUCE_UMAX,
281 G_VECREDUCE_ADD, G_VECREDUCE_MUL, G_VECREDUCE_FMUL, G_VECREDUCE_FMIN,
282 G_VECREDUCE_FMAX, G_VECREDUCE_FMINIMUM, G_VECREDUCE_FMAXIMUM,
283 G_VECREDUCE_OR, G_VECREDUCE_AND, G_VECREDUCE_XOR})
284 .legalFor(allowedVectorTypes)
312 .unsupportedIf(
typeIs(1, p9))
316 G_BITREVERSE, G_SADDSAT, G_UADDSAT, G_SSUBSAT,
317 G_USUBSAT, G_SCMP, G_UCMP})
318 .legalFor(allIntScalarsAndVectors)
319 .
legalIf(extendedScalarsAndVectors);
325 .legalForCartesianProduct(allIntScalarsAndVectors,
326 allFloatScalarsAndVectors);
329 .legalForCartesianProduct(allIntScalarsAndVectors,
330 allFloatScalarsAndVectors);
333 .legalForCartesianProduct(allFloatScalarsAndVectors,
334 allScalarsAndVectors);
338 .
legalIf(extendedScalarsAndVectorsProduct);
342 .legalForCartesianProduct(allScalarsAndVectors)
343 .
legalIf(extendedScalarsAndVectorsProduct);
347 .
legalIf(extendedPtrsScalarsAndVectors);
351 typeInSet(1, allPtrsScalarsAndVectors)));
354 .legalFor({s1, s128})
355 .legalFor(allFloatAndIntScalarsAndPtrs)
384 typeInSet(1, allPtrsScalarsAndVectors)));
388 typeInSet(1, allFloatScalarsAndVectors)));
391 G_ATOMICRMW_MAX, G_ATOMICRMW_MIN,
392 G_ATOMICRMW_SUB, G_ATOMICRMW_XOR,
393 G_ATOMICRMW_UMAX, G_ATOMICRMW_UMIN})
394 .legalForCartesianProduct(allIntScalars, allPtrs);
397 {G_ATOMICRMW_FADD, G_ATOMICRMW_FSUB, G_ATOMICRMW_FMIN, G_ATOMICRMW_FMAX})
398 .legalForCartesianProduct(allFloatScalarsAndF16Vector2AndVector4s,
409 {G_UADDO, G_SADDO, G_USUBO, G_SSUBO, G_UMULO, G_SMULO})
413 .legalForCartesianProduct(allFloatScalarsAndVectors,
414 allIntScalarsAndVectors);
418 .legalForCartesianProduct(allFloatScalarsAndVectors);
429 allFloatScalarsAndVectors, {s32, v2s32, v3s32, v4s32, v8s32, v16s32});
465 G_INTRINSIC_ROUNDEVEN})
466 .legalFor(allFloatScalarsAndVectors);
470 allFloatScalarsAndVectors);
473 allFloatScalarsAndVectors, allIntScalarsAndVectors);
475 if (ST.canUseExtInstSet(SPIRV::InstructionSet::OpenCL_std)) {
477 {G_CTTZ, G_CTTZ_ZERO_UNDEF, G_CTLZ, G_CTLZ_ZERO_UNDEF})
478 .legalForCartesianProduct(allIntScalarsAndVectors,
479 allIntScalarsAndVectors);
488 verify(*ST.getInstrInfo());
502 MI.eraseFromParent();
519 MI.eraseFromParent();
527 Register ConvReg =
MRI.createGenericVirtualRegister(ConvTy);
540 switch (
MI.getOpcode()) {
544 case TargetOpcode::G_BITCAST:
545 return legalizeBitcast(Helper,
MI);
546 case TargetOpcode::G_EXTRACT_VECTOR_ELT:
548 case TargetOpcode::G_INSERT_VECTOR_ELT:
550 case TargetOpcode::G_INTRINSIC:
551 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
553 case TargetOpcode::G_IS_FPCLASS:
554 return legalizeIsFPClass(Helper,
MI, LocObserver);
555 case TargetOpcode::G_ICMP: {
556 assert(GR->getSPIRVTypeForVReg(
MI.getOperand(0).getReg()));
557 auto &Op0 =
MI.getOperand(2);
558 auto &Op1 =
MI.getOperand(3);
563 if ((!ST->canDirectlyComparePointers() ||
565 MRI.getType(Reg0).isPointer() &&
MRI.getType(Reg1).isPointer()) {
568 ST->getPointerSize());
569 SPIRVType *SpirvTy = GR->getOrCreateSPIRVType(
570 LLVMTy, Helper.
MIRBuilder, SPIRV::AccessQualifier::ReadWrite,
true);
582 unsigned NumElements = Ty.getNumElements();
583 unsigned MaxVectorSize = ST.isShader() ? 4 : 16;
585 NumElements > MaxVectorSize;
597 if (IntrinsicID == Intrinsic::spv_bitcast) {
601 LLT DstTy =
MRI.getType(DstReg);
602 LLT SrcTy =
MRI.getType(SrcReg);
610 MI.eraseFromParent();
613 }
else if (IntrinsicID == Intrinsic::spv_insertelt) {
615 LLT DstTy =
MRI.getType(DstReg);
622 MI.eraseFromParent();
625 }
else if (IntrinsicID == Intrinsic::spv_extractelt) {
627 LLT SrcTy =
MRI.getType(SrcReg);
633 MI.eraseFromParent();
651 MI.eraseFromParent();
658bool SPIRVLegalizerInfo::legalizeIsFPClass(
661 auto [DstReg, DstTy, SrcReg, SrcTy] =
MI.getFirst2RegLLTs();
665 auto &MF = MIRBuilder.
getMF();
666 MachineRegisterInfo &
MRI = MF.getRegInfo();
670 if (DstTy.isVector())
672 SPIRVType *SPIRVDstTy = GR->getOrCreateSPIRVType(
673 LLVMDstTy, MIRBuilder, SPIRV::AccessQualifier::ReadWrite,
676 unsigned BitSize = SrcTy.getScalarSizeInBits();
681 if (SrcTy.isVector()) {
682 IntTy =
LLT::vector(SrcTy.getElementCount(), IntTy);
685 SPIRVType *SPIRVIntTy = GR->getOrCreateSPIRVType(
686 LLVMIntTy, MIRBuilder, SPIRV::AccessQualifier::ReadWrite,
690 LLT DstTyCopy = DstTy;
691 const auto assignSPIRVTy = [&](MachineInstrBuilder &&
MI) {
695 LLT MITy =
MRI.getType(
MI.getReg(0));
696 assert((MITy == IntTy || MITy == DstTyCopy) &&
697 "Unexpected LLT type while lowering G_IS_FPCLASS");
698 auto *SPVTy = MITy == IntTy ? SPIRVIntTy : SPIRVDstTy;
699 GR->assignSPIRVTypeToVReg(SPVTy,
MI.getReg(0), MF);
704 const auto buildSPIRVConstant = [&](LLT Ty,
auto &&
C) -> MachineInstrBuilder {
708 assert((Ty == IntTy || Ty == DstTyCopy) &&
709 "Unexpected LLT type while lowering constant for G_IS_FPCLASS");
710 SPIRVType *VecEltTy = GR->getOrCreateSPIRVType(
711 (Ty == IntTy ? LLVMIntTy : LLVMDstTy)->getScalarType(), MIRBuilder,
712 SPIRV::AccessQualifier::ReadWrite,
714 GR->assignSPIRVTypeToVReg(VecEltTy, ScalarC.getReg(0), MF);
719 MIRBuilder.
buildCopy(DstReg, buildSPIRVConstant(DstTy, 0));
720 MI.eraseFromParent();
724 MIRBuilder.
buildCopy(DstReg, buildSPIRVConstant(DstTy, 1));
725 MI.eraseFromParent();
733 Register ResVReg =
MRI.createGenericVirtualRegister(IntTy);
734 MRI.setRegClass(ResVReg, GR->getRegClass(SPIRVIntTy));
735 GR->assignSPIRVTypeToVReg(SPIRVIntTy, ResVReg, Helper.
MIRBuilder.
getMF());
736 auto AsInt = MIRBuilder.
buildInstr(SPIRV::OpBitcast)
738 .
addUse(GR->getSPIRVTypeID(SPIRVIntTy))
740 AsInt = assignSPIRVTy(std::move(AsInt));
752 auto SignBitC = buildSPIRVConstant(IntTy, SignBit);
753 auto ValueMaskC = buildSPIRVConstant(IntTy, ValueMask);
754 auto InfC = buildSPIRVConstant(IntTy, Inf);
755 auto ExpMaskC = buildSPIRVConstant(IntTy, ExpMask);
756 auto ZeroC = buildSPIRVConstant(IntTy, 0);
758 auto Abs = assignSPIRVTy(MIRBuilder.
buildAnd(IntTy, AsInt, ValueMaskC));
759 auto Sign = assignSPIRVTy(
762 auto Res = buildSPIRVConstant(DstTy, 0);
764 const auto appendToRes = [&](MachineInstrBuilder &&ToAppend) {
766 MIRBuilder.
buildOr(DstTyCopy, Res, assignSPIRVTy(std::move(ToAppend))));
779 Mask &= ~fcPosFinite;
783 DstTy, Abs, ExpMaskC));
784 appendToRes(MIRBuilder.
buildAnd(DstTy, Cmp, Sign));
785 Mask &= ~fcNegFinite;
793 auto ExpBits = assignSPIRVTy(MIRBuilder.
buildAnd(IntTy, AsInt, ExpMaskC));
796 Mask &= ~PartialCheck;
805 else if (PartialCheck ==
fcZero)
817 auto OneC = buildSPIRVConstant(IntTy, 1);
818 auto VMinusOne = MIRBuilder.
buildSub(IntTy, V, OneC);
819 auto SubnormalRes = assignSPIRVTy(
821 buildSPIRVConstant(IntTy, AllOneMantissa)));
823 SubnormalRes = MIRBuilder.
buildAnd(DstTy, SubnormalRes, Sign);
824 appendToRes(std::move(SubnormalRes));
831 else if (PartialCheck ==
fcInf)
836 auto NegInfC = buildSPIRVConstant(IntTy, NegInf);
843 auto InfWithQnanBitC =
844 buildSPIRVConstant(IntTy, std::move(Inf) | QNaNBitMask);
845 if (PartialCheck ==
fcNan) {
849 }
else if (PartialCheck ==
fcQNan) {
856 auto IsNan = assignSPIRVTy(
858 auto IsNotQnan = assignSPIRVTy(MIRBuilder.
buildICmp(
860 appendToRes(MIRBuilder.
buildAnd(DstTy, IsNan, IsNotQnan));
867 APInt ExpLSB = ExpMask & ~(ExpMask.
shl(1));
868 auto ExpMinusOne = assignSPIRVTy(
869 MIRBuilder.
buildSub(IntTy, Abs, buildSPIRVConstant(IntTy, ExpLSB)));
870 APInt MaxExpMinusOne = std::move(ExpMask) - ExpLSB;
871 auto NormalRes = assignSPIRVTy(
873 buildSPIRVConstant(IntTy, MaxExpMinusOne)));
875 NormalRes = MIRBuilder.
buildAnd(DstTy, NormalRes, Sign);
877 auto PosSign = assignSPIRVTy(MIRBuilder.
buildXor(
878 DstTy, Sign, buildSPIRVConstant(DstTy, InversionMask)));
879 NormalRes = MIRBuilder.
buildAnd(DstTy, NormalRes, PosSign);
881 appendToRes(std::move(NormalRes));
885 MI.eraseFromParent();
unsigned const MachineRegisterInfo * MRI
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static void scalarize(Instruction *I, SmallVectorImpl< Instruction * > &Worklist)
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
This file declares the MachineIRBuilder class.
Promote Memory to Register
const SmallVectorImpl< MachineOperand > & Cond
static bool needsVectorLegalization(const LLT &Ty, const SPIRVSubtarget &ST)
static Register convertPtrToInt(Register Reg, LLT ConvTy, SPIRVType *SpvType, LegalizerHelper &Helper, MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR)
LegalityPredicate typeOfExtendedScalars(unsigned TypeIdx, bool IsExtendedInts)
static bool legalizeExtractVectorElt(LegalizerHelper &Helper, MachineInstr &MI, SPIRVGlobalRegistry *GR)
static bool legalizeInsertVectorElt(LegalizerHelper &Helper, MachineInstr &MI, SPIRVGlobalRegistry *GR)
APInt bitcastToAPInt() const
static APFloat getLargest(const fltSemantics &Sem, bool Negative=false)
Returns the largest finite number in the given semantics.
static APFloat getInf(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Infinity.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
unsigned getActiveBits() const
Compute the number of active bits in the value.
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
APInt shl(unsigned shiftAmt) const
Left-shift function.
static APInt getOneBitSet(unsigned numBits, unsigned BitNo)
Return an APInt with exactly one bit set in the result.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
@ ICMP_UGE
unsigned greater or equal
@ ICMP_UGT
unsigned greater than
@ ICMP_ULT
unsigned less than
static constexpr ElementCount getFixed(ScalarTy MinVal)
static LLVM_ABI IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
static constexpr LLT vector(ElementCount EC, unsigned ScalarSizeInBits)
Get a low-level vector of some number of elements and element width.
static constexpr LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
constexpr bool isValid() const
static constexpr LLT pointer(unsigned AddressSpace, unsigned SizeInBits)
Get a low-level pointer in the given address space.
static constexpr LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits)
Get a low-level fixed-width vector of some number of elements and element width.
constexpr bool isPointerOrPointerVector() const
constexpr bool isFixedVector() const
Returns true if the LLT is a fixed vector.
constexpr LLT getScalarType() const
LLVM_ABI void computeTables()
Compute any ancillary tables needed to quickly decide how an operation should be handled.
LegalizeRuleSet & legalFor(std::initializer_list< LLT > Types)
The instruction is legal when type index 0 is any type in the given list.
LegalizeRuleSet & fewerElementsIf(LegalityPredicate Predicate, LegalizeMutation Mutation)
Remove elements to reach the type selected by the mutation if the predicate is true.
LegalizeRuleSet & moreElementsToNextPow2(unsigned TypeIdx)
Add more elements to the vector to reach the next power of two.
LegalizeRuleSet & lower()
The instruction is lowered.
LegalizeRuleSet & scalarizeIf(LegalityPredicate Predicate, unsigned TypeIdx)
LegalizeRuleSet & lowerIf(LegalityPredicate Predicate)
The instruction is lowered if predicate is true.
LegalizeRuleSet & custom()
Unconditionally custom lower.
LegalizeRuleSet & unsupportedIf(LegalityPredicate Predicate)
LegalizeRuleSet & alwaysLegal()
LegalizeRuleSet & customIf(LegalityPredicate Predicate)
LegalizeRuleSet & scalarize(unsigned TypeIdx)
LegalizeRuleSet & legalForCartesianProduct(std::initializer_list< LLT > Types)
The instruction is legal when type indexes 0 and 1 are both in the given list.
LegalizeRuleSet & legalIf(LegalityPredicate Predicate)
The instruction is legal if predicate is true.
LegalizeRuleSet & customFor(std::initializer_list< LLT > Types)
MachineIRBuilder & MIRBuilder
Expose MIRBuilder so clients can set their own RecordInsertInstruction functions.
LegalizeRuleSet & getActionDefinitionsBuilder(unsigned Opcode)
Get the action definition builder for the given opcode.
const LegacyLegalizerInfo & getLegacyLegalizerInfo() const
Helper class to build MachineInstr.
LLVMContext & getContext() const
MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_AND Op0, Op1.
MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res, const SrcOp &Op0, const SrcOp &Op1, std::optional< unsigned > Flags=std::nullopt)
Build and insert a Res = G_ICMP Pred, Op0, Op1.
MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_SUB Op0, Op1.
MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef< Register > Res, bool HasSideEffects, bool isConvergent)
Build and insert a G_INTRINSIC instruction.
MachineInstrBuilder buildSplatBuildVector(const DstOp &Res, const SrcOp &Src)
Build and insert Res = G_BUILD_VECTOR with Src replicated to fill the number of elements.
MachineInstrBuilder buildExtractVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Idx)
Build and insert Res = G_EXTRACT_VECTOR_ELT Val, Idx.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
MachineFunction & getMF()
Getter for the function we currently build.
MachineInstrBuilder buildInsertVectorElement(const DstOp &Res, const SrcOp &Val, const SrcOp &Elt, const SrcOp &Idx)
Build and insert Res = G_INSERT_VECTOR_ELT Val, Elt, Idx.
MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src)
Build and insert Dst = G_BITCAST Src.
MachineRegisterInfo * getMRI()
Getter for MRI.
MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1, std::optional< unsigned > Flags=std::nullopt)
Build and insert Res = G_OR Op0, Op1.
MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op)
Build and insert Res = COPY Op.
MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, const SrcOp &Src1)
Build and insert Res = G_XOR Op0, Op1.
virtual MachineInstrBuilder buildConstant(const DstOp &Res, const ConstantInt &Val)
Build and insert Res = G_CONSTANT Val.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
void assignSPIRVTypeToVReg(SPIRVType *Type, Register VReg, const MachineFunction &MF)
const TargetRegisterClass * getRegClass(SPIRVType *SpvType) const
SPIRVLegalizerInfo(const SPIRVSubtarget &ST)
bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI, LostDebugLocObserver &LocObserver) const override
Called for instructions with the Custom LegalizationAction.
bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override
SPIRVGlobalRegistry * getSPIRVGlobalRegistry() const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
The instances of the Type class are immutable: once they are created, they are never changed.
static LLVM_ABI VectorType * get(Type *ElementType, ElementCount EC)
This static method is the primary way to construct an VectorType.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ C
The default llvm calling convention, compatible with C.
LLVM_ABI LegalityPredicate numElementsNotPow2(unsigned TypeIdx)
True iff the specified type index is a vector whose element count is not a power of 2.
LLVM_ABI LegalityPredicate vectorElementCountIsLessThanOrEqualTo(unsigned TypeIdx, unsigned Size)
True iff the specified type index is a vector with a number of elements that's less than or equal to ...
LLVM_ABI LegalityPredicate typeInSet(unsigned TypeIdx, std::initializer_list< LLT > TypesInit)
True iff the given type index is one of the specified types.
LLVM_ABI LegalityPredicate vectorElementCountIsGreaterThan(unsigned TypeIdx, unsigned Size)
True iff the specified type index is a vector with a number of elements that's greater than the given...
Predicate any(Predicate P0, Predicate P1)
True iff P0 or P1 are true.
LegalityPredicate typeIsNot(unsigned TypeIdx, LLT Type)
True iff the given type index is not the specified type.
Predicate all(Predicate P0, Predicate P1)
True iff P0 and P1 are true.
LLVM_ABI LegalityPredicate typeIs(unsigned TypeIdx, LLT TypesInit)
True iff the given type index is the specified type.
LLVM_ABI LegalizeMutation changeElementCountTo(unsigned TypeIdx, unsigned FromTypeIdx)
Keep the same scalar or element type as TypeIdx, but take the number of elements from FromTypeIdx.
LLVM_ABI LegalizeMutation changeElementSizeTo(unsigned TypeIdx, unsigned FromTypeIdx)
Change the scalar size or element size to have the same scalar size as type index FromIndex.
Invariant opcodes: All instruction sets have these as their low opcodes.
This is an optimization pass for GlobalISel generic memory operations.
LLVM_ABI const llvm::fltSemantics & getFltSemanticForLLT(LLT Ty)
Get the appropriate floating point arithmetic semantic based on the bit size of the given scalar LLT.
std::function< bool(const LegalityQuery &)> LegalityPredicate
MachineInstr * getImm(const MachineOperand &MO, const MachineRegisterInfo *MRI)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
FPClassTest
Floating-point class tests, supported by 'is_fpclass' intrinsic.
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
const MachineInstr SPIRVType
const std::set< unsigned > & getTypeFoldingSupportedOpcodes()
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
The LegalityQuery object bundles together all the information that's needed to decide whether a given...