LLVM  14.0.0git
X86SelectionDAGInfo.cpp
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1 //===-- X86SelectionDAGInfo.cpp - X86 SelectionDAG Info -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the X86SelectionDAGInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86SelectionDAGInfo.h"
14 #include "X86ISelLowering.h"
15 #include "X86InstrInfo.h"
16 #include "X86RegisterInfo.h"
17 #include "X86Subtarget.h"
21 #include "llvm/IR/DerivedTypes.h"
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "x86-selectiondag-info"
26 
27 static cl::opt<bool>
28  UseFSRMForMemcpy("x86-use-fsrm-for-memcpy", cl::Hidden, cl::init(false),
29  cl::desc("Use fast short rep mov in memcpy lowering"));
30 
31 bool X86SelectionDAGInfo::isBaseRegConflictPossible(
32  SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const {
33  // We cannot use TRI->hasBasePointer() until *after* we select all basic
34  // blocks. Legalization may introduce new stack temporaries with large
35  // alignment requirements. Fall back to generic code if there are any
36  // dynamic stack adjustments (hopefully rare) and the base pointer would
37  // conflict if we had to use it.
39  if (!MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
40  return false;
41 
42  const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>(
44  return llvm::is_contained(ClobberSet, TRI->getBaseRegister());
45 }
46 
48  SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Val,
49  SDValue Size, Align Alignment, bool isVolatile,
50  MachinePointerInfo DstPtrInfo) const {
51  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
52  const X86Subtarget &Subtarget =
54 
55 #ifndef NDEBUG
56  // If the base register might conflict with our physical registers, bail out.
57  const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
59  assert(!isBaseRegConflictPossible(DAG, ClobberSet));
60 #endif
61 
62  // If to a segment-relative address space, use the default lowering.
63  if (DstPtrInfo.getAddrSpace() >= 256)
64  return SDValue();
65 
66  // If not DWORD aligned or size is more than the threshold, call the library.
67  // The libc version is likely to be faster for these cases. It can use the
68  // address value and run time information about the CPU.
69  if (Alignment < Align(4) || !ConstantSize ||
70  ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) {
71  // Check to see if there is a specialized entry-point for memory zeroing.
72  ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Val);
73 
74  if (const char *bzeroName =
75  (ValC && ValC->isZero())
76  ? DAG.getTargetLoweringInfo().getLibcallName(RTLIB::BZERO)
77  : nullptr) {
78  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
79  EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
80  Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
83  Entry.Node = Dst;
84  Entry.Ty = IntPtrTy;
85  Args.push_back(Entry);
86  Entry.Node = Size;
87  Args.push_back(Entry);
88 
90  CLI.setDebugLoc(dl)
91  .setChain(Chain)
93  DAG.getExternalSymbol(bzeroName, IntPtr),
94  std::move(Args))
96 
97  std::pair<SDValue,SDValue> CallResult = TLI.LowerCallTo(CLI);
98  return CallResult.second;
99  }
100 
101  // Otherwise have the target-independent code call memset.
102  return SDValue();
103  }
104 
105  uint64_t SizeVal = ConstantSize->getZExtValue();
106  SDValue InFlag;
107  EVT AVT;
108  SDValue Count;
109  ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Val);
110  unsigned BytesLeft = 0;
111  if (ValC) {
112  unsigned ValReg;
113  uint64_t Val = ValC->getZExtValue() & 255;
114 
115  // If the value is a constant, then we can potentially use larger sets.
116  if (Alignment > Align(2)) {
117  // DWORD aligned
118  AVT = MVT::i32;
119  ValReg = X86::EAX;
120  Val = (Val << 8) | Val;
121  Val = (Val << 16) | Val;
122  if (Subtarget.is64Bit() && Alignment > Align(8)) { // QWORD aligned
123  AVT = MVT::i64;
124  ValReg = X86::RAX;
125  Val = (Val << 32) | Val;
126  }
127  } else if (Alignment == Align(2)) {
128  // WORD aligned
129  AVT = MVT::i16;
130  ValReg = X86::AX;
131  Val = (Val << 8) | Val;
132  } else {
133  // Byte aligned
134  AVT = MVT::i8;
135  ValReg = X86::AL;
136  Count = DAG.getIntPtrConstant(SizeVal, dl);
137  }
138 
139  if (AVT.bitsGT(MVT::i8)) {
140  unsigned UBytes = AVT.getSizeInBits() / 8;
141  Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl);
142  BytesLeft = SizeVal % UBytes;
143  }
144 
145  Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT),
146  InFlag);
147  InFlag = Chain.getValue(1);
148  } else {
149  AVT = MVT::i8;
150  Count = DAG.getIntPtrConstant(SizeVal, dl);
151  Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Val, InFlag);
152  InFlag = Chain.getValue(1);
153  }
154 
155  bool Use64BitRegs = Subtarget.isTarget64BitLP64();
156  Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RCX : X86::ECX,
157  Count, InFlag);
158  InFlag = Chain.getValue(1);
159  Chain = DAG.getCopyToReg(Chain, dl, Use64BitRegs ? X86::RDI : X86::EDI,
160  Dst, InFlag);
161  InFlag = Chain.getValue(1);
162 
164  SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
165  Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
166 
167  if (BytesLeft) {
168  // Handle the last 1 - 7 bytes.
169  unsigned Offset = SizeVal - BytesLeft;
170  EVT AddrVT = Dst.getValueType();
171  EVT SizeVT = Size.getValueType();
172 
173  Chain =
174  DAG.getMemset(Chain, dl,
175  DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
176  DAG.getConstant(Offset, dl, AddrVT)),
177  Val, DAG.getConstant(BytesLeft, dl, SizeVT), Alignment,
178  isVolatile, false, DstPtrInfo.getWithOffset(Offset));
179  }
180 
181  // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
182  return Chain;
183 }
184 
185 /// Emit a single REP MOVS{B,W,D,Q} instruction.
186 static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG,
187  const SDLoc &dl, SDValue Chain, SDValue Dst,
188  SDValue Src, SDValue Size, MVT AVT) {
189  const bool Use64BitRegs = Subtarget.isTarget64BitLP64();
190  const unsigned CX = Use64BitRegs ? X86::RCX : X86::ECX;
191  const unsigned DI = Use64BitRegs ? X86::RDI : X86::EDI;
192  const unsigned SI = Use64BitRegs ? X86::RSI : X86::ESI;
193 
194  SDValue InFlag;
195  Chain = DAG.getCopyToReg(Chain, dl, CX, Size, InFlag);
196  InFlag = Chain.getValue(1);
197  Chain = DAG.getCopyToReg(Chain, dl, DI, Dst, InFlag);
198  InFlag = Chain.getValue(1);
199  Chain = DAG.getCopyToReg(Chain, dl, SI, Src, InFlag);
200  InFlag = Chain.getValue(1);
201 
203  SDValue Ops[] = {Chain, DAG.getValueType(AVT), InFlag};
204  return DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops);
205 }
206 
207 /// Emit a single REP MOVSB instruction for a particular constant size.
208 static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG,
209  const SDLoc &dl, SDValue Chain, SDValue Dst,
210  SDValue Src, uint64_t Size) {
211  return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src,
212  DAG.getIntPtrConstant(Size, dl), MVT::i8);
213 }
214 
215 /// Returns the best type to use with repmovs depending on alignment.
216 static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget,
217  uint64_t Align) {
218  assert((Align != 0) && "Align is normalized");
219  assert(isPowerOf2_64(Align) && "Align is a power of 2");
220  switch (Align) {
221  case 1:
222  return MVT::i8;
223  case 2:
224  return MVT::i16;
225  case 4:
226  return MVT::i32;
227  default:
228  return Subtarget.is64Bit() ? MVT::i64 : MVT::i32;
229  }
230 }
231 
232 /// Returns a REP MOVS instruction, possibly with a few load/stores to implement
233 /// a constant size memory copy. In some cases where we know REP MOVS is
234 /// inefficient we return an empty SDValue so the calling code can either
235 /// generate a load/store sequence or call the runtime memcpy function.
237  SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &dl,
238  SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, EVT SizeVT,
239  unsigned Align, bool isVolatile, bool AlwaysInline,
240  MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) {
241 
242  /// TODO: Revisit next line: big copy with ERMSB on march >= haswell are very
243  /// efficient.
244  if (!AlwaysInline && Size > Subtarget.getMaxInlineSizeThreshold())
245  return SDValue();
246 
247  /// If we have enhanced repmovs we use it.
248  if (Subtarget.hasERMSB())
249  return emitRepmovsB(Subtarget, DAG, dl, Chain, Dst, Src, Size);
250 
251  assert(!Subtarget.hasERMSB() && "No efficient RepMovs");
252  /// We assume runtime memcpy will do a better job for unaligned copies when
253  /// ERMS is not present.
254  if (!AlwaysInline && (Align & 3) != 0)
255  return SDValue();
256 
257  const MVT BlockType = getOptimalRepmovsType(Subtarget, Align);
258  const uint64_t BlockBytes = BlockType.getSizeInBits() / 8;
259  const uint64_t BlockCount = Size / BlockBytes;
260  const uint64_t BytesLeft = Size % BlockBytes;
261  SDValue RepMovs =
262  emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src,
263  DAG.getIntPtrConstant(BlockCount, dl), BlockType);
264 
265  /// RepMov can process the whole length.
266  if (BytesLeft == 0)
267  return RepMovs;
268 
269  assert(BytesLeft && "We have leftover at this point");
270 
271  /// In case we optimize for size we use repmovsb even if it's less efficient
272  /// so we can save the loads/stores of the leftover.
274  return emitRepmovsB(Subtarget, DAG, dl, Chain, Dst, Src, Size);
275 
276  // Handle the last 1 - 7 bytes.
278  Results.push_back(RepMovs);
279  unsigned Offset = Size - BytesLeft;
280  EVT DstVT = Dst.getValueType();
281  EVT SrcVT = Src.getValueType();
282  Results.push_back(DAG.getMemcpy(
283  Chain, dl,
284  DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)),
285  DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, dl, SrcVT)),
286  DAG.getConstant(BytesLeft, dl, SizeVT), llvm::Align(Align), isVolatile,
287  /*AlwaysInline*/ true, /*isTailCall*/ false,
288  DstPtrInfo.getWithOffset(Offset), SrcPtrInfo.getWithOffset(Offset)));
289  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results);
290 }
291 
293  SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
294  SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline,
295  MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
296  // If to a segment-relative address space, use the default lowering.
297  if (DstPtrInfo.getAddrSpace() >= 256 || SrcPtrInfo.getAddrSpace() >= 256)
298  return SDValue();
299 
300  // If the base registers conflict with our physical registers, use the default
301  // lowering.
302  const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI,
304  if (isBaseRegConflictPossible(DAG, ClobberSet))
305  return SDValue();
306 
307  const X86Subtarget &Subtarget =
309 
310  // If enabled and available, use fast short rep mov.
311  if (UseFSRMForMemcpy && Subtarget.hasFSRM())
312  return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, Size, MVT::i8);
313 
314  /// Handle constant sizes,
315  if (ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size))
316  return emitConstantSizeRepmov(
317  DAG, Subtarget, dl, Chain, Dst, Src, ConstantSize->getZExtValue(),
318  Size.getValueType(), Alignment.value(), isVolatile, AlwaysInline,
319  DstPtrInfo, SrcPtrInfo);
320 
321  return SDValue();
322 }
llvm::CallingConv::C
@ C
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::MachineFrameInfo::hasVarSizedObjects
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
Definition: MachineFrameInfo.h:353
llvm::ConstantSDNode
Definition: SelectionDAGNodes.h:1556
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::X86Subtarget::hasERMSB
bool hasERMSB() const
Definition: X86Subtarget.h:735
llvm::AArch64CC::AL
@ AL
Definition: AArch64BaseInfo.h:269
llvm::N86::ECX
@ ECX
Definition: X86MCTargetDesc.h:51
llvm::SDLoc
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Definition: SelectionDAGNodes.h:1086
llvm::TargetLowering::CallLoweringInfo::setChain
CallLoweringInfo & setChain(SDValue InChain)
Definition: TargetLowering.h:3791
X86Subtarget.h
llvm::SelectionDAG::getCopyToReg
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
Definition: SelectionDAG.h:735
llvm::SelectionDAG::getValueType
SDValue getValueType(EVT)
Definition: SelectionDAG.cpp:1722
X86SelectionDAGInfo.h
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::SelectionDAG::getVTList
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
Definition: SelectionDAG.cpp:8551
llvm::X86Subtarget
Definition: X86Subtarget.h:52
llvm::TargetLoweringBase::getLibcallName
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
Definition: TargetLowering.h:2859
llvm::N86::ESI
@ ESI
Definition: X86MCTargetDesc.h:51
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::MVT::Glue
@ Glue
Definition: MachineValueType.h:262
UseFSRMForMemcpy
static cl::opt< bool > UseFSRMForMemcpy("x86-use-fsrm-for-memcpy", cl::Hidden, cl::init(false), cl::desc("Use fast short rep mov in memcpy lowering"))
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::N86::EDI
@ EDI
Definition: X86MCTargetDesc.h:51
llvm::TargetLowering::LowerCallTo
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
Definition: SelectionDAGBuilder.cpp:9534
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
Results
Function Alias Analysis Results
Definition: AliasAnalysis.cpp:847
llvm::ConstantSDNode::isZero
bool isZero() const
Definition: SelectionDAGNodes.h:1580
emitConstantSizeRepmov
static SDValue emitConstantSizeRepmov(SelectionDAG &DAG, const X86Subtarget &Subtarget, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, EVT SizeVT, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
Returns a REP MOVS instruction, possibly with a few load/stores to implement a constant size memory c...
Definition: X86SelectionDAGInfo.cpp:236
SelectionDAG.h
llvm::SelectionDAG::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
Definition: SelectionDAG.h:442
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
emitRepmovsB
static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size)
Emit a single REP MOVSB instruction for a particular constant size.
Definition: X86SelectionDAGInfo.cpp:208
llvm::SelectionDAG::getContext
LLVMContext * getContext() const
Definition: SelectionDAG.h:447
TargetLowering.h
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::SelectionDAG::getTargetLoweringInfo
const TargetLowering & getTargetLoweringInfo() const
Definition: SelectionDAG.h:443
llvm::EVT
Extended Value Type.
Definition: ValueTypes.h:35
llvm::SelectionDAG::getConstant
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
Definition: SelectionDAG.cpp:1373
llvm::TargetLowering
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Definition: TargetLowering.h:3189
llvm::X86SelectionDAGInfo::EmitTargetCodeForMemset
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo) const override
Emit target-specific code that performs a memset.
Definition: X86SelectionDAGInfo.cpp:47
llvm::X86SelectionDAGInfo::EmitTargetCodeForMemcpy
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const override
Emit target-specific code that performs a memcpy.
Definition: X86SelectionDAGInfo.cpp:292
llvm::TargetLowering::CallLoweringInfo::setDebugLoc
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
Definition: TargetLowering.h:3786
Align
uint64_t Align
Definition: ELFObjHandler.cpp:83
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::X86Subtarget::isTarget64BitLP64
bool isTarget64BitLP64() const
Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Definition: X86Subtarget.h:624
emitRepmovs
static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, MVT AVT)
Emit a single REP MOVS{B,W,D,Q} instruction.
Definition: X86SelectionDAGInfo.cpp:186
llvm::TargetLowering::CallLoweringInfo::setLibCallee
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
Definition: TargetLowering.h:3797
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::cl::opt< bool >
llvm::EVT::getSizeInBits
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:341
getOptimalRepmovsType
static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget, uint64_t Align)
Returns the best type to use with repmovs depending on alignment.
Definition: X86SelectionDAGInfo.cpp:216
uint64_t
llvm::SelectionDAG::getIntPtrConstant
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
Definition: SelectionDAG.cpp:1496
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::SelectionDAG::getNode
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Definition: SelectionDAG.cpp:8316
llvm::X86Subtarget::hasFSRM
bool hasFSRM() const
Definition: X86Subtarget.h:736
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
llvm::is_contained
bool is_contained(R &&Range, const E &Element)
Wrapper function around std::find to detect if an element exists in a container.
Definition: STLExtras.h:1616
llvm::SDValue::getValue
SDValue getValue(unsigned R) const
Definition: SelectionDAGNodes.h:172
llvm::MVT::i8
@ i8
Definition: MachineValueType.h:44
llvm::TargetLowering::CallLoweringInfo
This structure contains all information that is necessary for lowering calls.
Definition: TargetLowering.h:3747
llvm::X86ISD::REP_STOS
@ REP_STOS
Repeat fill, corresponds to X86::REP_STOSx.
Definition: X86ISelLowering.h:137
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MVT::Other
@ Other
Definition: MachineValueType.h:42
llvm::TargetLoweringBase::ArgListEntry
Definition: TargetLowering.h:274
llvm::MachineFunction::getFrameInfo
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Definition: MachineFunction.h:642
SI
StandardInstrumentations SI(Debug, VerifyEach)
llvm::ConstantSDNode::getZExtValue
uint64_t getZExtValue() const
Definition: SelectionDAGNodes.h:1571
llvm::MVT
Machine Value Type.
Definition: MachineValueType.h:31
llvm::MachinePointerInfo::getWithOffset
MachinePointerInfo getWithOffset(int64_t O) const
Definition: MachineMemOperand.h:80
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::MVT::i64
@ i64
Definition: MachineValueType.h:47
llvm::X86ISD::REP_MOVS
@ REP_MOVS
Repeat move, corresponds to X86::REP_MOVSx.
Definition: X86ISelLowering.h:140
llvm::N86::EAX
@ EAX
Definition: X86MCTargetDesc.h:51
llvm::SDVTList
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Definition: SelectionDAGNodes.h:79
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition: MachineOperand.cpp:978
llvm::TargetLoweringBase::ArgListTy
std::vector< ArgListEntry > ArgListTy
Definition: TargetLowering.h:304
llvm::DataLayout::getIntPtrType
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space.
Definition: DataLayout.cpp:834
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:592
uint16_t
MachineFrameInfo.h
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::TargetLowering::CallLoweringInfo::setDiscardResult
CallLoweringInfo & setDiscardResult(bool Value=true)
Definition: TargetLowering.h:3866
llvm::SelectionDAG::getDataLayout
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:440
llvm::MVT::i32
@ i32
Definition: MachineValueType.h:46
llvm::SDValue
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
Definition: SelectionDAGNodes.h:138
X86ISelLowering.h
llvm::ISD::ADD
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
X86RegisterInfo.h
llvm::Type::getVoidTy
static Type * getVoidTy(LLVMContext &C)
Definition: Type.cpp:186
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:107
llvm::SelectionDAG::getMemset
SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
Definition: SelectionDAG.cpp:7055
llvm::WebAssembly::BlockType
BlockType
Used as immediate MachineOperands for block signatures.
Definition: WebAssemblyTypeUtilities.h:26
llvm::Function::hasMinSize
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
Definition: Function.h:668
llvm::X86Subtarget::is64Bit
bool is64Bit() const
Is this x86_64? (disregarding specific ABI / programming model)
Definition: X86Subtarget.h:606
DerivedTypes.h
llvm::EVT::bitsGT
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
Definition: ValueTypes.h:257
llvm::MVT::i16
@ i16
Definition: MachineValueType.h:45
llvm::MachineFrameInfo::hasOpaqueSPAdjustment
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
Definition: MachineFrameInfo.h:585
llvm::SelectionDAG::getMachineFunction
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:437
llvm::SelectionDAG::getExternalSymbol
SDValue getExternalSymbol(const char *Sym, EVT VT)
Definition: SelectionDAG.cpp:1736
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:389
llvm::cl::desc
Definition: CommandLine.h:414
llvm::SelectionDAG::getMemcpy
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
Definition: SelectionDAG.cpp:6837
llvm::X86Subtarget::getMaxInlineSizeThreshold
unsigned getMaxInlineSizeThreshold() const
Returns the maximum memset / memcpy size that still makes it profitable to inline the call.
Definition: X86Subtarget.h:584
X86InstrInfo.h
llvm::isPowerOf2_64
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
Definition: MathExtras.h:496
llvm::TargetLoweringBase::getPointerTy
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
Definition: TargetLowering.h:346
llvm::ISD::TokenFactor
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
Definition: ISDOpcodes.h:52
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24