38#define DEBUG_TYPE "xcore-reg-info"
40#define GET_REGINFO_TARGET_DESC
41#include "XCoreGenRegisterInfo.inc"
53 return val < (1 << 6);
57 return val < (1 << 16);
63 unsigned Reg,
unsigned FrameReg,
int Offset ) {
68 switch (
MI.getOpcode()) {
94 unsigned Reg,
unsigned FrameReg,
96 assert(RS &&
"requiresRegisterScavenging failed");
104 switch (
MI.getOpcode()) {
130 unsigned Reg,
int Offset) {
136 switch (
MI.getOpcode()) {
139 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
145 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
152 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
164 assert(RS &&
"requiresRegisterScavenging failed");
168 unsigned OpCode =
MI.getOpcode();
170 unsigned ScratchBase;
171 if (OpCode==XCore::STWFI) {
213 static const MCPhysReg CalleeSavedRegs[] = {
214 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
215 XCore::R8, XCore::R9, XCore::R10,
218 static const MCPhysReg CalleeSavedRegsFP[] = {
219 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
220 XCore::R8, XCore::R9,
225 return CalleeSavedRegsFP;
226 return CalleeSavedRegs;
237 if (TFI->
hasFP(MF)) {
255 int SPAdj,
unsigned FIOperandNum,
257 assert(SPAdj == 0 &&
"Unexpected");
260 int FrameIndex = FrameOp.
getIndex();
284 if (
MI.isDebugValue()) {
285 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg,
false );
286 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(
Offset);
291 Offset +=
MI.getOperand(FIOperandNum + 1).getImm();
292 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
300 assert(XCore::GRRegsRegClass.
contains(Reg) &&
"Unexpected register operand");
302 if (TFI->
hasFP(MF)) {
323 return TFI->
hasFP(MF) ? XCore::R10 : XCore::SP;
This file implements the BitVector class.
const HexagonInstrInfo * TII
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
static bool isImmU16(unsigned val)
static bool isImmU6(unsigned val)
static bool isImmUs(int64_t val)
static void InsertFPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, RegScavenger *RS)
static void InsertSPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset)
static void InsertFPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset)
static void InsertSPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset, RegScavenger *RS)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Register scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available and do the appropriate bookkeeping.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Wrapper class representing virtual and physical registers.
virtual const TargetInstrInfo * getInstrInfo() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
unsigned getKillRegState(bool B)
bool requiresRegisterScavenging(const MachineFunction &MF) const override
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
static bool needsFrameMoves(const MachineFunction &MF)
Return whether to emit frame moves.
Register getFrameRegister(const MachineFunction &MF) const override
bool useFPForScavengingIndex(const MachineFunction &MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override