LLVM 17.0.0git
XCoreRegisterInfo.cpp
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1//===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the XCore implementation of the MRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "XCoreRegisterInfo.h"
14#include "XCore.h"
15#include "XCoreInstrInfo.h"
17#include "XCoreSubtarget.h"
18#include "llvm/ADT/BitVector.h"
19#include "llvm/ADT/STLExtras.h"
26#include "llvm/IR/Function.h"
27#include "llvm/IR/Type.h"
28#include "llvm/Support/Debug.h"
35
36using namespace llvm;
37
38#define DEBUG_TYPE "xcore-reg-info"
39
40#define GET_REGINFO_TARGET_DESC
41#include "XCoreGenRegisterInfo.inc"
42
44 : XCoreGenRegisterInfo(XCore::LR) {
45}
46
47// helper functions
48static inline bool isImmUs(unsigned val) {
49 return val <= 11;
50}
51
52static inline bool isImmU6(unsigned val) {
53 return val < (1 << 6);
54}
55
56static inline bool isImmU16(unsigned val) {
57 return val < (1 << 16);
58}
59
60
62 const XCoreInstrInfo &TII,
63 unsigned Reg, unsigned FrameReg, int Offset ) {
64 MachineInstr &MI = *II;
65 MachineBasicBlock &MBB = *MI.getParent();
66 DebugLoc dl = MI.getDebugLoc();
67
68 switch (MI.getOpcode()) {
69 case XCore::LDWFI:
70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
71 .addReg(FrameReg)
73 .addMemOperand(*MI.memoperands_begin());
74 break;
75 case XCore::STWFI:
76 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
78 .addReg(FrameReg)
80 .addMemOperand(*MI.memoperands_begin());
81 break;
82 case XCore::LDAWFI:
83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
84 .addReg(FrameReg)
85 .addImm(Offset);
86 break;
87 default:
88 llvm_unreachable("Unexpected Opcode");
89 }
90}
91
93 const XCoreInstrInfo &TII,
94 unsigned Reg, unsigned FrameReg,
95 int Offset, RegScavenger *RS ) {
96 assert(RS && "requiresRegisterScavenging failed");
97 MachineInstr &MI = *II;
98 MachineBasicBlock &MBB = *MI.getParent();
99 DebugLoc dl = MI.getDebugLoc();
100 Register ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
101 RS->setRegUsed(ScratchOffset);
102 TII.loadImmediate(MBB, II, ScratchOffset, Offset);
103
104 switch (MI.getOpcode()) {
105 case XCore::LDWFI:
106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
107 .addReg(FrameReg)
108 .addReg(ScratchOffset, RegState::Kill)
109 .addMemOperand(*MI.memoperands_begin());
110 break;
111 case XCore::STWFI:
112 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
114 .addReg(FrameReg)
115 .addReg(ScratchOffset, RegState::Kill)
116 .addMemOperand(*MI.memoperands_begin());
117 break;
118 case XCore::LDAWFI:
119 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
120 .addReg(FrameReg)
121 .addReg(ScratchOffset, RegState::Kill);
122 break;
123 default:
124 llvm_unreachable("Unexpected Opcode");
125 }
126}
127
129 const XCoreInstrInfo &TII,
130 unsigned Reg, int Offset) {
131 MachineInstr &MI = *II;
132 MachineBasicBlock &MBB = *MI.getParent();
133 DebugLoc dl = MI.getDebugLoc();
134 bool isU6 = isImmU6(Offset);
135
136 switch (MI.getOpcode()) {
137 int NewOpcode;
138 case XCore::LDWFI:
139 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
141 .addImm(Offset)
142 .addMemOperand(*MI.memoperands_begin());
143 break;
144 case XCore::STWFI:
145 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
146 BuildMI(MBB, II, dl, TII.get(NewOpcode))
147 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
148 .addImm(Offset)
149 .addMemOperand(*MI.memoperands_begin());
150 break;
151 case XCore::LDAWFI:
152 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
154 .addImm(Offset);
155 break;
156 default:
157 llvm_unreachable("Unexpected Opcode");
158 }
159}
160
162 const XCoreInstrInfo &TII,
163 unsigned Reg, int Offset, RegScavenger *RS ) {
164 assert(RS && "requiresRegisterScavenging failed");
165 MachineInstr &MI = *II;
166 MachineBasicBlock &MBB = *MI.getParent();
167 DebugLoc dl = MI.getDebugLoc();
168 unsigned OpCode = MI.getOpcode();
169
170 unsigned ScratchBase;
171 if (OpCode==XCore::STWFI) {
172 ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
173 RS->setRegUsed(ScratchBase);
174 } else
175 ScratchBase = Reg;
176 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
177 Register ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
178 RS->setRegUsed(ScratchOffset);
179 TII.loadImmediate(MBB, II, ScratchOffset, Offset);
180
181 switch (OpCode) {
182 case XCore::LDWFI:
183 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
184 .addReg(ScratchBase, RegState::Kill)
185 .addReg(ScratchOffset, RegState::Kill)
186 .addMemOperand(*MI.memoperands_begin());
187 break;
188 case XCore::STWFI:
189 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
190 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
191 .addReg(ScratchBase, RegState::Kill)
192 .addReg(ScratchOffset, RegState::Kill)
193 .addMemOperand(*MI.memoperands_begin());
194 break;
195 case XCore::LDAWFI:
196 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
197 .addReg(ScratchBase, RegState::Kill)
198 .addReg(ScratchOffset, RegState::Kill);
199 break;
200 default:
201 llvm_unreachable("Unexpected Opcode");
202 }
203}
204
206 return MF.needsFrameMoves();
207}
208
209const MCPhysReg *
211 // The callee saved registers LR & FP are explicitly handled during
212 // emitPrologue & emitEpilogue and related functions.
213 static const MCPhysReg CalleeSavedRegs[] = {
214 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
215 XCore::R8, XCore::R9, XCore::R10,
216 0
217 };
218 static const MCPhysReg CalleeSavedRegsFP[] = {
219 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
220 XCore::R8, XCore::R9,
221 0
222 };
223 const XCoreFrameLowering *TFI = getFrameLowering(*MF);
224 if (TFI->hasFP(*MF))
225 return CalleeSavedRegsFP;
226 return CalleeSavedRegs;
227}
228
230 BitVector Reserved(getNumRegs());
231 const XCoreFrameLowering *TFI = getFrameLowering(MF);
232
233 Reserved.set(XCore::CP);
234 Reserved.set(XCore::DP);
235 Reserved.set(XCore::SP);
236 Reserved.set(XCore::LR);
237 if (TFI->hasFP(MF)) {
238 Reserved.set(XCore::R10);
239 }
240 return Reserved;
241}
242
243bool
245 return true;
246}
247
248bool
250 return false;
251}
252
253bool
255 int SPAdj, unsigned FIOperandNum,
256 RegScavenger *RS) const {
257 assert(SPAdj == 0 && "Unexpected");
258 MachineInstr &MI = *II;
259 MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
260 int FrameIndex = FrameOp.getIndex();
261
262 MachineFunction &MF = *MI.getParent()->getParent();
263 const XCoreInstrInfo &TII =
264 *static_cast<const XCoreInstrInfo *>(MF.getSubtarget().getInstrInfo());
265
266 const XCoreFrameLowering *TFI = getFrameLowering(MF);
267 int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex);
268 int StackSize = MF.getFrameInfo().getStackSize();
269
270 #ifndef NDEBUG
271 LLVM_DEBUG(errs() << "\nFunction : " << MF.getName() << "\n");
272 LLVM_DEBUG(errs() << "<--------->\n");
274 LLVM_DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
275 LLVM_DEBUG(errs() << "FrameOffset : " << Offset << "\n");
276 LLVM_DEBUG(errs() << "StackSize : " << StackSize << "\n");
277#endif
278
279 Offset += StackSize;
280
281 Register FrameReg = getFrameRegister(MF);
282
283 // Special handling of DBG_VALUE instructions.
284 if (MI.isDebugValue()) {
285 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
286 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
287 return false;
288 }
289
290 // fold constant into offset.
291 Offset += MI.getOperand(FIOperandNum + 1).getImm();
292 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
293
294 assert(Offset%4 == 0 && "Misaligned stack offset");
295 LLVM_DEBUG(errs() << "Offset : " << Offset << "\n"
296 << "<--------->\n");
297 Offset/=4;
298
299 Register Reg = MI.getOperand(0).getReg();
300 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
301
302 if (TFI->hasFP(MF)) {
303 if (isImmUs(Offset))
304 InsertFPImmInst(II, TII, Reg, FrameReg, Offset);
305 else
306 InsertFPConstInst(II, TII, Reg, FrameReg, Offset, RS);
307 } else {
308 if (isImmU16(Offset))
309 InsertSPImmInst(II, TII, Reg, Offset);
310 else
311 InsertSPConstInst(II, TII, Reg, Offset, RS);
312 }
313 // Erase old instruction.
314 MachineBasicBlock &MBB = *MI.getParent();
315 MBB.erase(II);
316 return true;
317}
318
319
321 const XCoreFrameLowering *TFI = getFrameLowering(MF);
322
323 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
324}
MachineBasicBlock & MBB
This file implements the BitVector class.
#define LLVM_DEBUG(X)
Definition: Debug.h:101
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
Definition: Value.cpp:469
static bool isImmU16(unsigned val)
static bool isImmU6(unsigned val)
static bool isImmUs(int64_t val)
static void InsertFPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset, RegScavenger *RS)
static void InsertSPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset)
static void InsertFPImmInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, unsigned FrameReg, int Offset)
static void InsertSPConstInst(MachineBasicBlock::iterator II, const XCoreInstrInfo &TII, unsigned Reg, int Offset, RegScavenger *RS)
A debug info location.
Definition: DebugLoc.h:33
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
bool needsFrameMoves() const
True if this function needs frame moves for debug or exceptions.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
Definition: Pass.cpp:130
Register scavengeRegister(const TargetRegisterClass *RC, MachineBasicBlock::iterator I, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available and do the appropriate bookkeeping.
void setRegUsed(Register Reg, LaneBitmask LaneMask=LaneBitmask::getAll())
Tell the scavenger a register is used.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
virtual const TargetInstrInfo * getInstrInfo() const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
unsigned getKillRegState(bool B)
bool requiresRegisterScavenging(const MachineFunction &MF) const override
bool eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Code Generation virtual methods...
static bool needsFrameMoves(const MachineFunction &MF)
Return whether to emit frame moves.
Register getFrameRegister(const MachineFunction &MF) const override
bool useFPForScavengingIndex(const MachineFunction &MF) const override
BitVector getReservedRegs(const MachineFunction &MF) const override