Go to the documentation of this file.
39 return val < (1 << 6);
43 return val < (1 << 16);
48 struct StackSlotInfo {
52 StackSlotInfo(
int f,
int o,
int r) : FI(
f),
Offset(o),
Reg(r){};
57 return a.Offset <
b.Offset;
101 int &Adjusted,
int FrameSize,
bool emitFrameMoves) {
102 while (OffsetFromTop > Adjusted) {
103 assert(Adjusted < FrameSize &&
"OffsetFromTop is beyond FrameSize");
104 int remaining = FrameSize - Adjusted;
106 int Opcode =
isImmU6(OpImm) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
125 while (OffsetFromTop < RemainingAdj -
MaxImmU16) {
126 assert(RemainingAdj &&
"OffsetFromTop is beyond FrameSize");
128 int Opcode =
isImmU6(OpImm) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
130 RemainingAdj -= OpImm;
140 bool fetchLR,
bool fetchFP) {
195 for (
unsigned i = 0,
e = SpillList.size();
i !=
e; ++
i) {
196 assert(SpillList[
i].Offset % 4 == 0 &&
"Misaligned stack offset");
197 assert(SpillList[
i].Offset <= 0 &&
"Unexpected positive stack offset");
198 int OffsetFromTop = - SpillList[
i].Offset/4;
200 int Offset = RemainingAdj - OffsetFromTop;
201 int Opcode =
isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
225 assert(&MF.
front() == &
MBB &&
"Shrink-wrapping not yet supported");
252 bool UseENTSP = saveLR && FrameSize
262 int Opcode =
isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
268 if (emitFrameMoves) {
270 unsigned DRegNum =
MRI->getDwarfRegNum(XCore::LR,
true);
280 for (
unsigned i = 0,
e = SpillList.size();
i !=
e; ++
i) {
281 assert(SpillList[
i].Offset % 4 == 0 &&
"Misaligned stack offset");
282 assert(SpillList[
i].Offset <= 0 &&
"Unexpected positive stack offset");
283 int OffsetFromTop = - SpillList[
i].Offset/4;
286 int Offset = Adjusted - OffsetFromTop;
287 int Opcode =
isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
294 if (emitFrameMoves) {
295 unsigned DRegNum =
MRI->getDwarfRegNum(SpillList[
i].
Reg,
true);
303 assert(Adjusted==FrameSize &&
"IfNeededExtSP has not completed adjustment");
313 if (emitFrameMoves) {
320 unsigned DRegNum =
MRI->getDwarfRegNum(CSI.
getReg(),
true);
332 assert(SpillList.size()==2 &&
"Unexpected SpillList size");
334 MRI->getDwarfRegNum(SpillList[0].Reg,
true),
335 SpillList[0].Offset);
337 MRI->getDwarfRegNum(SpillList[1].Reg,
true),
338 SpillList[1].Offset);
350 unsigned RetOpcode =
MBBI->getOpcode();
355 assert(RemainingAdj%4 == 0 &&
"Misaligned frame size");
379 bool UseRETSP = restoreLR && RemainingAdj
398 assert(RetOpcode == XCore::RETSP_u6
399 || RetOpcode == XCore::RETSP_lu6);
400 int Opcode =
isImmU6(RemainingAdj) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
403 for (
unsigned i = 3,
e =
MBBI->getNumOperands();
i <
e; ++
i)
407 int Opcode =
isImmU6(RemainingAdj) ? XCore::LDAWSP_ru6 :
428 DL =
MI->getDebugLoc();
433 "LR & FP are always handled in emitPrologue");
439 if (emitFrameMoves) {
460 "LR & FP are always handled in emitEpilogue");
465 "loadRegFromStackSlot didn't insert any code!");
502 errs() <<
"eliminateCallFramePseudoInstr size too big: "
509 if (Old.
getOpcode() == XCore::ADJCALLSTACKDOWN) {
510 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
514 int Opcode = isU6 ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
555 SavedRegs.
reset(XCore::LR);
568 assert(RS &&
"requiresRegisterScavenging failed");
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
This is an optimization pass for GlobalISel generic memory operations.
static void RestoreSpillList(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, int &RemainingAdj, SmallVectorImpl< StackSlotInfo > &SpillList)
Restore clobbered registers with their spill slot value.
int createLRSpillSlot(MachineFunction &MF)
Information about stack frame layout on the target.
bool hasAttrSomewhere(Attribute::AttrKind Kind, unsigned *Index=nullptr) const
Return true if the specified attribute is set for at least one parameter or for the return value.
const MCContext & getContext() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MCRegisterInfo * getRegisterInfo() const
virtual const TargetInstrInfo * getInstrInfo() const
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
Reg
All possible values of the reg field in the ModR/M byte.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
auto reverse(ContainerTy &&C, std::enable_if_t< has_rbegin< ContainerTy >::value > *=nullptr)
A description of a memory reference used in the backend.
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
int createFPSpillSlot(MachineFunction &MF)
bool callsUnwindInit() const
static bool isImmU6(unsigned val)
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
static const int MaxImmU16
static bool needsFrameMoves(const MachineFunction &MF)
Return whether to emit frame moves.
unsigned const TargetRegisterInfo * TRI
bool empty() const
empty - Check if the array is empty.
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset)
.cfi_def_cfa_offset modifies a rule for computing CFA.
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
const MachineBasicBlock & front() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
const MachineOperand & getOperand(unsigned i) const
int getLRSpillSlot() const
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
@ Kill
The last use of a register.
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
static const unsigned FramePtr
static void EmitCfiOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, unsigned DRegNum, int Offset)
const HexagonInstrInfo * TII
This class contains meta information specific to a module.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
static bool CompareSSIOffset(const StackSlotInfo &a, const StackSlotInfo &b)
bool hasPersonalityFn() const
Check whether this function has a personality function.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
XCoreFrameLowering(const XCoreSubtarget &STI)
int getFPSpillSlot() const
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
This struct is a compact representation of a valid (non-zero power of two) alignment.
static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Register)
.cfi_def_cfa_register modifies a rule for computing CFA.
AttributeList getAttributes() const
Return the attribute list for this Function.
static void IfNeededLDAWSP(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, int OffsetFromTop, int &RemainingAdj)
The SP register is moved in steps of 'MaxImmU16' towards the top of the frame.
static bool isImmU16(unsigned val)
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
MachineModuleInfo & getMMI() const
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
The initial backend is deliberately restricted to z10 We should add support for later architectures at some point If an asm ties an i32 r result to an i64 the input will be treated as an leaving the upper bits uninitialised For i64 store i32 val
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
This is an important base class in LLVM.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
Representation of each machine instruction.
bool callsEHReturn() const
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Store the specified register of the given register class to the specified stack frame index.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
static void EmitDefCfaRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, MachineFunction &MF, unsigned DRegNum)
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
Flags
Flags values. These may be or'd together.
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
std::vector< std::pair< MachineBasicBlock::iterator, CalleeSavedInfo > > & getSpillLabels()
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
bool isLargeFrame(const MachineFunction &MF) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
XCoreFunctionInfo - This class is derived from MachineFunction private XCore target-specific informat...
static void EmitDefCfaOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, int Offset)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
Load the specified register of the given register class from the specified stack frame index.
MachineBasicBlock MachineBasicBlock::iterator MBBI
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
@ MOLoad
The memory access reads data.
unsigned const MachineRegisterInfo * MRI
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
Wrapper class representing virtual and physical registers.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
virtual Register getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
static MachineMemOperand * getFrameIndexMMO(MachineBasicBlock &MBB, int FrameIndex, MachineMemOperand::Flags flags)
Function & getFunction()
Return the LLVM function that this machine code represents.
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
static void IfNeededExtSP(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &dl, const TargetInstrInfo &TII, int OffsetFromTop, int &Adjusted, int FrameSize, bool emitFrameMoves)
The SP register is moved in steps of 'MaxImmU16' towards the bottom of the frame.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
uint64_t value() const
This is a hole in the type system and should not be abused.
void sort(IteratorTy Start, IteratorTy End)
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef=false) const
Return true if the specified register is modified in this function.
Constant * getPersonalityFn() const
Get the personality function associated with this function.
@ MOStore
The memory access writes data.
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
LLVM_NODISCARD unsigned addFrameInst(const MCCFIInstruction &Inst)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
virtual const TargetLowering * getTargetLowering() const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS=nullptr) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
static void GetEHSpillList(SmallVectorImpl< StackSlotInfo > &SpillList, MachineFrameInfo &MFI, XCoreFunctionInfo *XFI, const Constant *PersonalityFn, const TargetLowering *TL)
Creates an ordered list of EH info register 'spills'.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const int * createEHSpillSlot(MachineFunction &MF)
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset)
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
MachineBasicBlock iterator that automatically skips over MIs that are inside bundles (i....
const int * getEHSpillSlot() const
static void GetSpillList(SmallVectorImpl< StackSlotInfo > &SpillList, MachineFrameInfo &MFI, XCoreFunctionInfo *XFI, bool fetchLR, bool fetchFP)
Creates an ordered list of registers that are spilled during the emitPrologue/emitEpilogue.