45#define DEBUG_TYPE "asm-printer"
48 "Number of RISC-V Compressed instructions emitted");
60 std::unique_ptr<MCStreamer> Streamer)
84 bool emitPseudoExpansionLowering(
MCStreamer &OutStreamer,
87 typedef std::tuple<unsigned, uint32_t> HwasanMemaccessTuple;
88 std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
91 void EmitHwasanMemaccessSymbols(
Module &M);
100 bool emitDirectiveOptionArch();
113 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
117 MCSymbol *MILabel = Ctx.createTempSymbol();
121 assert(NumNOPBytes % NOPBytes == 0 &&
122 "Invalid number of NOP bytes requested!");
128 while (NumNOPBytes > 0) {
129 if (MII ==
MBB.
end() || MII->isCall() ||
130 MII->getOpcode() == RISCV::DBG_VALUE ||
131 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
132 MII->getOpcode() == TargetOpcode::STACKMAP)
139 emitNops(NumNOPBytes / NOPBytes);
146 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
149 MCSymbol *MILabel = Ctx.createTempSymbol();
155 unsigned EncodedBytes = 0;
158 unsigned NumBytes = Opers.getNumPatchBytes();
159 assert(NumBytes >= EncodedBytes &&
160 "Patchpoint can't request size less than the length of a call.");
161 assert((NumBytes - EncodedBytes) % NOPBytes == 0 &&
162 "Invalid number of NOP bytes requested!");
163 emitNops((NumBytes - EncodedBytes) / NOPBytes);
168 unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4;
171 if (
unsigned PatchBytes = SOpers.getNumPatchBytes()) {
172 assert(PatchBytes % NOPBytes == 0 &&
173 "Invalid number of NOP bytes requested!");
174 emitNops(PatchBytes / NOPBytes);
178 MCSymbol *MILabel = Ctx.createTempSymbol();
187 ++RISCVNumInstrsCompressed;
193#include "RISCVGenMCPseudoLowering.inc"
198 if (!STI->hasStdExtZihintntl())
201 if (
MI->memoperands_empty())
208 unsigned NontemporalMode = 0;
210 NontemporalMode += 0b1;
212 NontemporalMode += 0b10;
215 if (STI->hasStdExtCOrZca() && STI->enableRVCHintInstrs())
224 EmitToStreamer(*OutStreamer, Hint);
228 RISCV_MC::verifyInstructionPredicates(
MI->getOpcode(),
229 getSubtargetInfo().getFeatureBits());
234 if (emitPseudoExpansionLowering(*OutStreamer,
MI))
238 switch (
MI->getOpcode()) {
239 case RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
240 LowerHWASAN_CHECK_MEMACCESS(*
MI);
242 case RISCV::KCFI_CHECK:
243 LowerKCFI_CHECK(*
MI);
245 case RISCV::PseudoRVVInitUndefM1:
246 case RISCV::PseudoRVVInitUndefM2:
247 case RISCV::PseudoRVVInitUndefM4:
248 case RISCV::PseudoRVVInitUndefM8:
250 case TargetOpcode::STACKMAP:
251 return LowerSTACKMAP(*OutStreamer, SM, *
MI);
252 case TargetOpcode::PATCHPOINT:
253 return LowerPATCHPOINT(*OutStreamer, SM, *
MI);
254 case TargetOpcode::STATEPOINT:
255 return LowerSTATEPOINT(*OutStreamer, SM, *
MI);
259 if (!lowerToMCInst(
MI, OutInst))
260 EmitToStreamer(*OutStreamer, OutInst);
263bool RISCVAsmPrinter::PrintAsmOperand(
const MachineInstr *
MI,
unsigned OpNo,
270 if (ExtraCode && ExtraCode[0]) {
271 if (ExtraCode[1] != 0)
274 switch (ExtraCode[0]) {
298 PrintSymbolOperand(MO,
OS);
312bool RISCVAsmPrinter::PrintAsmMemoryOperand(
const MachineInstr *
MI,
314 const char *ExtraCode,
320 assert(
MI->getNumOperands() > OpNo + 1 &&
"Expected additional operand");
324 if (!AddrReg.
isReg())
331 if (!lowerOperand(
Offset, MCO))
342bool RISCVAsmPrinter::emitDirectiveOptionArch() {
348 if (STI->hasFeature(Feature.Value) == MCSTI.
hasFeature(Feature.Value))
354 auto Delta = STI->hasFeature(Feature.Value) ? RISCVOptionArchArgType::Plus
355 : RISCVOptionArchArgType::Minus;
358 if (!NeedEmitStdOptionArgs.
empty()) {
372 bool EmittedOptionArch = emitDirectiveOptionArch();
374 SetupMachineFunction(MF);
377 if (EmittedOptionArch)
378 RTS.emitDirectiveOptionPop();
382void RISCVAsmPrinter::emitStartOfAsmFile(
Module &M) {
385 if (
const MDString *ModuleTargetABI =
386 dyn_cast_or_null<MDString>(
M.getModuleFlag(
"target-abi")))
392 if (
auto *MD = dyn_cast_or_null<MDNode>(
M.getModuleFlag(
"riscv-isa"))) {
393 for (
auto &ISA : MD->operands()) {
394 if (
auto *ISAString = dyn_cast_or_null<MDString>(ISA)) {
396 ISAString->getString(),
true,
399 auto &ISAInfo = *ParseResult;
401 if (ISAInfo->hasExtension(Feature.Key) &&
412 if (
TM.getTargetTriple().isOSBinFormatELF())
413 emitAttributes(SubtargetInfo);
416void RISCVAsmPrinter::emitEndOfAsmFile(
Module &M) {
420 if (
TM.getTargetTriple().isOSBinFormatELF())
422 EmitHwasanMemaccessSymbols(M);
425void RISCVAsmPrinter::emitAttributes(
const MCSubtargetInfo &SubtargetInfo) {
434void RISCVAsmPrinter::emitFunctionEntryLabel() {
436 if (RMFI->isVectorCall()) {
450void RISCVAsmPrinter::LowerHWASAN_CHECK_MEMACCESS(
const MachineInstr &
MI) {
452 uint32_t AccessInfo =
MI.getOperand(1).getImm();
454 HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, AccessInfo)];
457 if (!
TM.getTargetTriple().isOSBinFormatELF())
460 std::string SymName =
"__hwasan_check_x" + utostr(Reg - RISCV::X0) +
"_" +
461 utostr(AccessInfo) +
"_short";
462 Sym = OutContext.getOrCreateSymbol(SymName);
467 EmitToStreamer(*OutStreamer,
MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr));
472 assert(std::next(
MI.getIterator())->isCall() &&
473 "KCFI_CHECK not followed by a call instruction");
474 assert(std::next(
MI.getIterator())->getOperand(0).getReg() == AddrReg &&
475 "KCFI_CHECK call target doesn't match call operand");
482 unsigned ScratchRegs[] = {RISCV::X6, RISCV::X7};
483 unsigned NextReg = RISCV::X28;
484 auto isRegAvailable = [&](
unsigned Reg) {
485 return Reg != AddrReg && !STI->isRegisterReservedByUser(Reg);
487 for (
auto &Reg : ScratchRegs) {
488 if (isRegAvailable(Reg))
490 while (!isRegAvailable(NextReg))
493 if (Reg > RISCV::X31)
497 if (AddrReg == RISCV::X0) {
501 .addReg(ScratchRegs[0])
507 int NopSize = STI->hasStdExtCOrZca() ? 2 : 4;
508 int64_t PrefixNops = 0;
511 .getFnAttribute(
"patchable-function-prefix")
513 .getAsInteger(10, PrefixNops);
517 .addReg(ScratchRegs[0])
519 .addImm(-(PrefixNops * NopSize + 4)));
523 const int64_t
Type =
MI.getOperand(1).getImm();
524 const int64_t Hi20 = ((
Type + 0x800) >> 12) & 0xFFFFF;
525 const int64_t Lo12 = SignExtend64<12>(
Type);
529 MCInstBuilder(RISCV::LUI).addReg(ScratchRegs[1]).addImm(Hi20));
531 if (Lo12 || Hi20 == 0) {
532 EmitToStreamer(*OutStreamer,
543 EmitToStreamer(*OutStreamer,
545 .addReg(ScratchRegs[0])
546 .addReg(ScratchRegs[1])
552 emitKCFITrapEntry(*
MI.getMF(),
Trap);
556void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(
Module &M) {
557 if (HwasanMemaccessSymbols.empty())
560 assert(
TM.getTargetTriple().isOSBinFormatELF());
567 OutContext.getOrCreateSymbol(
"__hwasan_tag_mismatch_v2");
579 for (
auto &
P : HwasanMemaccessSymbols) {
580 unsigned Reg = std::get<0>(
P.first);
581 uint32_t AccessInfo = std::get<1>(
P.first);
618 MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
627 MCSymbol *ReturnSym = OutContext.createTempSymbol();
634 OutStreamer->
emitLabel(HandleMismatchOrPartialSym);
641 MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
679 OutStreamer->
emitLabel(HandleMismatchSym);
745 if (Reg != RISCV::X10)
880 RISCVVPseudosTable::getPseudoInfo(
MI->getOpcode());
887 assert(
MBB &&
"MI expected to be in a basic block");
889 assert(MF &&
"MBB expected to be in a machine function");
894 assert(
TRI &&
"TargetRegisterInfo expected");
898 unsigned NumOps =
MI->getNumExplicitOperands();
912 for (
unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
915 if (hasVLOutput && OpNo == 1)
919 if (OpNo ==
MI->getNumExplicitDefs() && MO.
isReg() && MO.
isTied()) {
921 "Expected tied to first def.");
938 if (RISCV::VRM2RegClass.
contains(Reg) ||
939 RISCV::VRM4RegClass.
contains(Reg) ||
940 RISCV::VRM8RegClass.
contains(Reg)) {
941 Reg =
TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
942 assert(Reg &&
"Subregister does not exist");
943 }
else if (RISCV::FPR16RegClass.
contains(Reg)) {
945 TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
946 assert(Reg &&
"Subregister does not exist");
947 }
else if (RISCV::FPR64RegClass.
contains(Reg)) {
948 Reg =
TRI->getSubReg(Reg, RISCV::sub_32);
949 assert(Reg &&
"Superregister does not exist");
950 }
else if (RISCV::VRN2M1RegClass.
contains(Reg) ||
951 RISCV::VRN2M2RegClass.
contains(Reg) ||
952 RISCV::VRN2M4RegClass.
contains(Reg) ||
953 RISCV::VRN3M1RegClass.
contains(Reg) ||
954 RISCV::VRN3M2RegClass.
contains(Reg) ||
955 RISCV::VRN4M1RegClass.
contains(Reg) ||
956 RISCV::VRN4M2RegClass.
contains(Reg) ||
957 RISCV::VRN5M1RegClass.
contains(Reg) ||
958 RISCV::VRN6M1RegClass.
contains(Reg) ||
959 RISCV::VRN7M1RegClass.
contains(Reg) ||
960 RISCV::VRN8M1RegClass.
contains(Reg)) {
961 Reg =
TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
962 assert(Reg &&
"Subregister does not exist");
980 RISCV::VMV0RegClassID &&
981 "Expected only mask operand to be missing");
997 if (lowerOperand(MO, MCOp))
1002 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
1003 const Function &
F =
MI->getParent()->getParent()->getFunction();
1004 if (
F.hasFnAttribute(
"patchable-function-entry")) {
1006 if (
F.getFnAttribute(
"patchable-function-entry")
1008 .getAsInteger(10, Num))
This file implements a class to represent arbitrary precision integral constant values and operations...
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter()
static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym, const AsmPrinter &AP)
static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
#define STATISTIC(VARNAME, DESC)
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
This class is intended to be used as a driving class for all asm writers.
virtual void emitInstruction(const MachineInstr *)
Targets should implement this to emit instructions.
void EmitToStreamer(MCStreamer &S, const MCInst &Inst)
virtual void emitStartOfAsmFile(Module &)
This virtual method can be overridden by targets that want to emit something at the start of their fi...
virtual void emitEndOfAsmFile(Module &)
This virtual method can be overridden by targets that want to emit something at the end of their file...
MCContext & OutContext
This is the context for the output file that we are streaming.
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant as...
virtual void emitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
MCInstBuilder & addReg(unsigned Reg)
Add a new register operand.
MCInstBuilder & addImm(int64_t Val)
Add a new integer immediate operand.
MCInstBuilder & addExpr(const MCExpr *Val)
Add a new MCExpr operand.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
void addOperand(const MCOperand Op)
void setOpcode(unsigned Op)
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
const MCExpr * getExpr() const
Streaming machine code generation interface.
virtual void emitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI)
Emit the given Instruction into the current section.
virtual bool emitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute)=0
Add the given Attribute to Symbol.
MCContext & getContext() const
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
MCTargetStreamer * getTargetStreamer()
virtual void switchSection(MCSection *Section, const MCExpr *Subsection=nullptr)
Set the current section where code is being emitted to Section.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
Represent a reference to a symbol from inside an expression.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
MCSymbol * getSymbol() const
Return the MCSymbol for this basic block.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Representation of each machine instruction.
A description of a memory reference used in the backend.
bool isNonTemporal() const
Flags getFlags() const
Return the raw flags of the source value,.
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isJTI() const
isJTI - Tests if this is a MO_JumpTableIndex operand.
const BlockAddress * getBlockAddress() const
unsigned getTargetFlags() const
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
MCSymbol * getMCSymbol() const
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
@ MO_GlobalAddress
Address of a global value.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_BlockAddress
Address of a basic block.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_Register
Register operand.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
int64_t getOffset() const
Return the offset from the symbol in this operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
A Module instance is used to store all the information related to an LLVM module.
Pass interface - Implemented by all 'passes'.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
MI-level patchpoint operands.
static bool isSupportedExtensionFeature(StringRef Ext)
static llvm::Expected< std::unique_ptr< RISCVISAInfo > > parseArchString(StringRef Arch, bool EnableExperimentalExtension, bool ExperimentalExtensionVersionCheck=true, bool IgnoreUnknown=false)
Parse RISC-V ISA info from arch string.
static const char * getRegisterName(MCRegister Reg)
static const RISCVMCExpr * create(const MCExpr *Expr, VariantKind Kind, MCContext &Ctx)
@ VK_RISCV_TLSDESC_ADD_LO
@ VK_RISCV_TLSDESC_LOAD_LO
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
virtual void emitDirectiveVariantCC(MCSymbol &Symbol)
void emitTargetAttributes(const MCSubtargetInfo &STI, bool EmitStackAlign)
void setFlagsFromFeatures(const MCSubtargetInfo &STI)
void setTargetABI(RISCVABI::ABI ABI)
virtual void emitDirectiveOptionArch(ArrayRef< RISCVOptionArchArg > Args)
virtual void finishAttributeSection()
virtual void emitDirectiveOptionPush()
Wrapper class representing virtual and physical registers.
reference emplace_back(ArgTypes &&... Args)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MI-level stackmap operands.
uint32_t getNumPatchBytes() const
Return the number of patchable bytes the given stackmap should emit.
void recordStatepoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a statepoint instruction.
void recordPatchPoint(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a patchpoint instruction.
void recordStackMap(const MCSymbol &L, const MachineInstr &MI)
Generate a stackmap record for a stackmap instruction.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
ABI getTargetABI(StringRef ABIName)
static bool hasRoundModeOp(uint64_t TSFlags)
static bool isTiedPseudo(uint64_t TSFlags)
static bool hasVLOp(uint64_t TSFlags)
static bool hasVecPolicyOp(uint64_t TSFlags)
static bool hasSEWOp(uint64_t TSFlags)
bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI)
bool isFaultFirstLoad(const MachineInstr &MI)
Reg
All possible values of the reg field in the ModR/M byte.
This is an optimization pass for GlobalISel generic memory operations.
bool errorToBool(Error Err)
Helper for converting an Error to a bool.
static const MachineMemOperand::Flags MONontemporalBit1
Target & getTheRISCV32Target()
static const MachineMemOperand::Flags MONontemporalBit0
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Target & getTheRISCV64Target()
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures]
@ MCSA_ELF_TypeFunction
.type _foo, STT_FUNC # aka @function
@ MCSA_Hidden
.hidden (ELF)
Implement std::hash so that hash_code can be used in STL containers.
RegisterAsmPrinter - Helper template for registering a target specific assembly printer,...
Used to provide key value pairs for feature and CPU bit flags.