LLVM 19.0.0git
RISCVFrameLowering.cpp
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1//===-- RISCVFrameLowering.cpp - RISC-V Frame Information -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of TargetFrameLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVFrameLowering.h"
15#include "RISCVSubtarget.h"
23#include "llvm/MC/MCDwarf.h"
24#include "llvm/Support/LEB128.h"
25
26#include <algorithm>
27
28using namespace llvm;
29
31 if (ABI == RISCVABI::ABI_ILP32E)
32 return Align(4);
33 if (ABI == RISCVABI::ABI_LP64E)
34 return Align(8);
35 return Align(16);
36}
37
40 StackGrowsDown, getABIStackAlignment(STI.getTargetABI()),
41 /*LocalAreaOffset=*/0,
42 /*TransientStackAlignment=*/getABIStackAlignment(STI.getTargetABI())),
43 STI(STI) {}
44
45static const MCPhysReg AllPopRegs[] = {
46 RISCV::X1, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19,
47 RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24,
48 RISCV::X25, RISCV::X26, RISCV::X27};
49
50// For now we use x3, a.k.a gp, as pointer to shadow call stack.
51// User should not use x3 in their asm.
54 const DebugLoc &DL) {
55 if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
56 return;
57
58 const auto &STI = MF.getSubtarget<RISCVSubtarget>();
59 const llvm::RISCVRegisterInfo *TRI = STI.getRegisterInfo();
60 Register RAReg = TRI->getRARegister();
61
62 // Do not save RA to the SCS if it's not saved to the regular stack,
63 // i.e. RA is not at risk of being overwritten.
64 std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
65 if (llvm::none_of(
66 CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
67 return;
68
69 const RISCVInstrInfo *TII = STI.getInstrInfo();
70 if (!STI.hasForcedSWShadowStack() && STI.hasStdExtZicfiss()) {
71 BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
72 return;
73 }
74
76
77 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
78 int64_t SlotSize = STI.getXLen() / 8;
79 // Store return address to shadow call stack
80 // addi gp, gp, [4|8]
81 // s[w|d] ra, -[4|8](gp)
82 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
83 .addReg(SCSPReg, RegState::Define)
84 .addReg(SCSPReg)
85 .addImm(SlotSize)
87 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
88 .addReg(RAReg)
89 .addReg(SCSPReg)
90 .addImm(-SlotSize)
92
93 // Emit a CFI instruction that causes SlotSize to be subtracted from the value
94 // of the shadow stack pointer when unwinding past this frame.
95 char DwarfSCSReg = TRI->getDwarfRegNum(SCSPReg, /*IsEH*/ true);
96 assert(DwarfSCSReg < 32 && "SCS Register should be < 32 (X3).");
97
98 char Offset = static_cast<char>(-SlotSize) & 0x7f;
99 const char CFIInst[] = {
100 dwarf::DW_CFA_val_expression,
101 DwarfSCSReg, // register
102 2, // length
103 static_cast<char>(unsigned(dwarf::DW_OP_breg0 + DwarfSCSReg)),
104 Offset, // addend (sleb128)
105 };
106
107 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createEscape(
108 nullptr, StringRef(CFIInst, sizeof(CFIInst))));
109 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
110 .addCFIIndex(CFIIndex)
112}
113
116 const DebugLoc &DL) {
117 if (!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack))
118 return;
119
120 const auto &STI = MF.getSubtarget<RISCVSubtarget>();
121 Register RAReg = STI.getRegisterInfo()->getRARegister();
122
123 // See emitSCSPrologue() above.
124 std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
125 if (llvm::none_of(
126 CSI, [&](CalleeSavedInfo &CSR) { return CSR.getReg() == RAReg; }))
127 return;
128
129 const RISCVInstrInfo *TII = STI.getInstrInfo();
130 if (!STI.hasForcedSWShadowStack() && STI.hasStdExtZicfiss()) {
131 BuildMI(MBB, MI, DL, TII->get(RISCV::SSPOPCHK)).addReg(RAReg);
132 return;
133 }
134
135 Register SCSPReg = RISCVABI::getSCSPReg();
136
137 bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
138 int64_t SlotSize = STI.getXLen() / 8;
139 // Load return address from shadow call stack
140 // l[w|d] ra, -[4|8](gp)
141 // addi gp, gp, -[4|8]
142 BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW))
143 .addReg(RAReg, RegState::Define)
144 .addReg(SCSPReg)
145 .addImm(-SlotSize)
147 BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
148 .addReg(SCSPReg, RegState::Define)
149 .addReg(SCSPReg)
150 .addImm(-SlotSize)
152 // Restore the SCS pointer
153 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
154 nullptr, STI.getRegisterInfo()->getDwarfRegNum(SCSPReg, /*IsEH*/ true)));
155 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
156 .addCFIIndex(CFIIndex)
158}
159
160// Get the ID of the libcall used for spilling and restoring callee saved
161// registers. The ID is representative of the number of registers saved or
162// restored by the libcall, except it is zero-indexed - ID 0 corresponds to a
163// single register.
164static int getLibCallID(const MachineFunction &MF,
165 const std::vector<CalleeSavedInfo> &CSI) {
166 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
167
168 if (CSI.empty() || !RVFI->useSaveRestoreLibCalls(MF))
169 return -1;
170
171 Register MaxReg = RISCV::NoRegister;
172 for (auto &CS : CSI)
173 // RISCVRegisterInfo::hasReservedSpillSlot assigns negative frame indexes to
174 // registers which can be saved by libcall.
175 if (CS.getFrameIdx() < 0)
176 MaxReg = std::max(MaxReg.id(), CS.getReg().id());
177
178 if (MaxReg == RISCV::NoRegister)
179 return -1;
180
181 switch (MaxReg) {
182 default:
183 llvm_unreachable("Something has gone wrong!");
184 case /*s11*/ RISCV::X27: return 12;
185 case /*s10*/ RISCV::X26: return 11;
186 case /*s9*/ RISCV::X25: return 10;
187 case /*s8*/ RISCV::X24: return 9;
188 case /*s7*/ RISCV::X23: return 8;
189 case /*s6*/ RISCV::X22: return 7;
190 case /*s5*/ RISCV::X21: return 6;
191 case /*s4*/ RISCV::X20: return 5;
192 case /*s3*/ RISCV::X19: return 4;
193 case /*s2*/ RISCV::X18: return 3;
194 case /*s1*/ RISCV::X9: return 2;
195 case /*s0*/ RISCV::X8: return 1;
196 case /*ra*/ RISCV::X1: return 0;
197 }
198}
199
200// Get the name of the libcall used for spilling callee saved registers.
201// If this function will not use save/restore libcalls, then return a nullptr.
202static const char *
204 const std::vector<CalleeSavedInfo> &CSI) {
205 static const char *const SpillLibCalls[] = {
206 "__riscv_save_0",
207 "__riscv_save_1",
208 "__riscv_save_2",
209 "__riscv_save_3",
210 "__riscv_save_4",
211 "__riscv_save_5",
212 "__riscv_save_6",
213 "__riscv_save_7",
214 "__riscv_save_8",
215 "__riscv_save_9",
216 "__riscv_save_10",
217 "__riscv_save_11",
218 "__riscv_save_12"
219 };
220
221 int LibCallID = getLibCallID(MF, CSI);
222 if (LibCallID == -1)
223 return nullptr;
224 return SpillLibCalls[LibCallID];
225}
226
227// Get the name of the libcall used for restoring callee saved registers.
228// If this function will not use save/restore libcalls, then return a nullptr.
229static const char *
231 const std::vector<CalleeSavedInfo> &CSI) {
232 static const char *const RestoreLibCalls[] = {
233 "__riscv_restore_0",
234 "__riscv_restore_1",
235 "__riscv_restore_2",
236 "__riscv_restore_3",
237 "__riscv_restore_4",
238 "__riscv_restore_5",
239 "__riscv_restore_6",
240 "__riscv_restore_7",
241 "__riscv_restore_8",
242 "__riscv_restore_9",
243 "__riscv_restore_10",
244 "__riscv_restore_11",
245 "__riscv_restore_12"
246 };
247
248 int LibCallID = getLibCallID(MF, CSI);
249 if (LibCallID == -1)
250 return nullptr;
251 return RestoreLibCalls[LibCallID];
252}
253
254// Return encoded value and register count for PUSH/POP instruction,
255// representing registers to store/load.
256static std::pair<unsigned, unsigned>
258 switch (MaxReg) {
259 default:
260 llvm_unreachable("Unexpected Reg for Push/Pop Inst");
261 case RISCV::X27: /*s11*/
262 case RISCV::X26: /*s10*/
263 return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S11, 13);
264 case RISCV::X25: /*s9*/
265 return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S9, 11);
266 case RISCV::X24: /*s8*/
267 return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S8, 10);
268 case RISCV::X23: /*s7*/
269 return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S7, 9);
270 case RISCV::X22: /*s6*/
271 return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S6, 8);
272 case RISCV::X21: /*s5*/
273 return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S5, 7);
274 case RISCV::X20: /*s4*/
275 return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S4, 6);
276 case RISCV::X19: /*s3*/
277 return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S3, 5);
278 case RISCV::X18: /*s2*/
279 return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S2, 4);
280 case RISCV::X9: /*s1*/
281 return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S1, 3);
282 case RISCV::X8: /*s0*/
283 return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0, 2);
284 case RISCV::X1: /*ra*/
285 return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA, 1);
286 }
287}
288
289// Get the max reg of Push/Pop for restoring callee saved registers.
291 const std::vector<CalleeSavedInfo> &CSI) {
292 Register MaxPushPopReg = RISCV::NoRegister;
293 for (auto &CS : CSI) {
294 if (llvm::is_contained(AllPopRegs, CS.getReg().id()))
295 MaxPushPopReg = std::max(MaxPushPopReg.id(), CS.getReg().id());
296 }
297 // if rlist is {rs, s0-s10}, then s11 will also be included
298 if (MaxPushPopReg == RISCV::X26)
299 MaxPushPopReg = RISCV::X27;
300 return MaxPushPopReg;
301}
302
303// Return true if the specified function should have a dedicated frame
304// pointer register. This is true if frame pointer elimination is
305// disabled, if it needs dynamic stack realignment, if the function has
306// variable sized allocas, or if the frame address is taken.
308 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
309
310 const MachineFrameInfo &MFI = MF.getFrameInfo();
311 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
312 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
314}
315
317 const MachineFrameInfo &MFI = MF.getFrameInfo();
319
320 // If we do not reserve stack space for outgoing arguments in prologue,
321 // we will adjust the stack pointer before call instruction. After the
322 // adjustment, we can not use SP to access the stack objects for the
323 // arguments. Instead, use BP to access these stack objects.
324 return (MFI.hasVarSizedObjects() ||
326 MFI.getMaxCallFrameSize() != 0))) &&
327 TRI->hasStackRealignment(MF);
328}
329
330// Determines the size of the frame and maximum call frame size.
331void RISCVFrameLowering::determineFrameLayout(MachineFunction &MF) const {
332 MachineFrameInfo &MFI = MF.getFrameInfo();
333 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
334
335 // Get the number of bytes to allocate from the FrameInfo.
336 uint64_t FrameSize = MFI.getStackSize();
337
338 // Get the alignment.
339 Align StackAlign = getStackAlign();
340
341 // Make sure the frame is aligned.
342 FrameSize = alignTo(FrameSize, StackAlign);
343
344 // Update frame info.
345 MFI.setStackSize(FrameSize);
346
347 // When using SP or BP to access stack objects, we may require extra padding
348 // to ensure the bottom of the RVV stack is correctly aligned within the main
349 // stack. We calculate this as the amount required to align the scalar local
350 // variable section up to the RVV alignment.
352 if (RVFI->getRVVStackSize() && (!hasFP(MF) || TRI->hasStackRealignment(MF))) {
353 int ScalarLocalVarSize = FrameSize - RVFI->getCalleeSavedStackSize() -
354 RVFI->getVarArgsSaveSize();
355 if (auto RVVPadding =
356 offsetToAlignment(ScalarLocalVarSize, RVFI->getRVVStackAlign()))
357 RVFI->setRVVPadding(RVVPadding);
358 }
359}
360
361// Returns the stack size including RVV padding (when required), rounded back
362// up to the required stack alignment.
364 const MachineFunction &MF) const {
365 const MachineFrameInfo &MFI = MF.getFrameInfo();
366 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
367 return alignTo(MFI.getStackSize() + RVFI->getRVVPadding(), getStackAlign());
368}
369
370// Returns the register used to hold the frame pointer.
371static Register getFPReg(const RISCVSubtarget &STI) { return RISCV::X8; }
372
373// Returns the register used to hold the stack pointer.
374static Register getSPReg(const RISCVSubtarget &STI) { return RISCV::X2; }
375
378 const std::vector<CalleeSavedInfo> &CSI) {
379 const MachineFrameInfo &MFI = MF.getFrameInfo();
381
382 for (auto &CS : CSI) {
383 int FI = CS.getFrameIdx();
384 if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::Default)
385 NonLibcallCSI.push_back(CS);
386 }
387
388 return NonLibcallCSI;
389}
390
393 const std::vector<CalleeSavedInfo> &CSI) {
394 const MachineFrameInfo &MFI = MF.getFrameInfo();
396
397 for (auto &CS : CSI) {
398 int FI = CS.getFrameIdx();
399 if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::ScalableVector)
400 RVVCSI.push_back(CS);
401 }
402
403 return RVVCSI;
404}
405
406void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF,
409 const DebugLoc &DL, int64_t Amount,
410 MachineInstr::MIFlag Flag) const {
411 assert(Amount != 0 && "Did not need to adjust stack pointer for RVV.");
412
413 const Register SPReg = getSPReg(STI);
414
415 // Optimize compile time offset case
417 if (auto VLEN = STI.getRealVLen()) {
418 // 1. Multiply the number of v-slots by the (constant) length of register
419 const int64_t VLENB = *VLEN / 8;
420 assert(Amount % 8 == 0 &&
421 "Reserve the stack by the multiple of one vector size.");
422 const int64_t NumOfVReg = Amount / 8;
423 const int64_t FixedOffset = NumOfVReg * VLENB;
424 if (!isInt<32>(FixedOffset)) {
426 "Frame size outside of the signed 32-bit range not supported");
427 }
428 Offset = StackOffset::getFixed(FixedOffset);
429 }
430
432 // We must keep the stack pointer aligned through any intermediate
433 // updates.
434 RI.adjustReg(MBB, MBBI, DL, SPReg, SPReg, Offset,
435 Flag, getStackAlign());
436}
437
439 Register Reg,
440 uint64_t FixedOffset,
441 uint64_t ScalableOffset) {
442 assert(ScalableOffset != 0 && "Did not need to adjust CFA for RVV");
443 SmallString<64> Expr;
444 std::string CommentBuffer;
445 llvm::raw_string_ostream Comment(CommentBuffer);
446 // Build up the expression (Reg + FixedOffset + ScalableOffset * VLENB).
447 unsigned DwarfReg = TRI.getDwarfRegNum(Reg, true);
448 Expr.push_back((uint8_t)(dwarf::DW_OP_breg0 + DwarfReg));
449 Expr.push_back(0);
450 if (Reg == RISCV::X2)
451 Comment << "sp";
452 else
453 Comment << printReg(Reg, &TRI);
454
455 uint8_t buffer[16];
456 if (FixedOffset) {
457 Expr.push_back(dwarf::DW_OP_consts);
458 Expr.append(buffer, buffer + encodeSLEB128(FixedOffset, buffer));
459 Expr.push_back((uint8_t)dwarf::DW_OP_plus);
460 Comment << " + " << FixedOffset;
461 }
462
463 Expr.push_back((uint8_t)dwarf::DW_OP_consts);
464 Expr.append(buffer, buffer + encodeSLEB128(ScalableOffset, buffer));
465
466 unsigned DwarfVlenb = TRI.getDwarfRegNum(RISCV::VLENB, true);
467 Expr.push_back((uint8_t)dwarf::DW_OP_bregx);
468 Expr.append(buffer, buffer + encodeULEB128(DwarfVlenb, buffer));
469 Expr.push_back(0);
470
471 Expr.push_back((uint8_t)dwarf::DW_OP_mul);
472 Expr.push_back((uint8_t)dwarf::DW_OP_plus);
473
474 Comment << " + " << ScalableOffset << " * vlenb";
475
476 SmallString<64> DefCfaExpr;
477 DefCfaExpr.push_back(dwarf::DW_CFA_def_cfa_expression);
478 DefCfaExpr.append(buffer, buffer + encodeULEB128(Expr.size(), buffer));
479 DefCfaExpr.append(Expr.str());
480
481 return MCCFIInstruction::createEscape(nullptr, DefCfaExpr.str(), SMLoc(),
482 Comment.str());
483}
484
486 MachineBasicBlock &MBB) const {
487 MachineFrameInfo &MFI = MF.getFrameInfo();
488 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
492
493 Register FPReg = getFPReg(STI);
494 Register SPReg = getSPReg(STI);
496
497 // Debug location must be unknown since the first debug location is used
498 // to determine the end of the prologue.
499 DebugLoc DL;
500
501 // All calls are tail calls in GHC calling conv, and functions have no
502 // prologue/epilogue.
504 return;
505
506 // Emit prologue for shadow call stack.
507 emitSCSPrologue(MF, MBB, MBBI, DL);
508
509 auto FirstFrameSetup = MBBI;
510
511 // Since spillCalleeSavedRegisters may have inserted a libcall, skip past
512 // any instructions marked as FrameSetup
513 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
514 ++MBBI;
515
516 // Determine the correct frame layout
517 determineFrameLayout(MF);
518
519 // If libcalls are used to spill and restore callee-saved registers, the frame
520 // has two sections; the opaque section managed by the libcalls, and the
521 // section managed by MachineFrameInfo which can also hold callee saved
522 // registers in fixed stack slots, both of which have negative frame indices.
523 // This gets even more complicated when incoming arguments are passed via the
524 // stack, as these too have negative frame indices. An example is detailed
525 // below:
526 //
527 // | incoming arg | <- FI[-3]
528 // | libcallspill |
529 // | calleespill | <- FI[-2]
530 // | calleespill | <- FI[-1]
531 // | this_frame | <- FI[0]
532 //
533 // For negative frame indices, the offset from the frame pointer will differ
534 // depending on which of these groups the frame index applies to.
535 // The following calculates the correct offset knowing the number of callee
536 // saved registers spilt by the two methods.
537 if (int LibCallRegs = getLibCallID(MF, MFI.getCalleeSavedInfo()) + 1) {
538 // Calculate the size of the frame managed by the libcall. The stack
539 // alignment of these libcalls should be the same as how we set it in
540 // getABIStackAlignment.
541 unsigned LibCallFrameSize =
542 alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign());
543 RVFI->setLibCallStackSize(LibCallFrameSize);
544 }
545
546 // FIXME (note copied from Lanai): This appears to be overallocating. Needs
547 // investigation. Get the number of bytes to allocate from the FrameInfo.
548 uint64_t RealStackSize = getStackSizeWithRVVPadding(MF);
549 uint64_t StackSize = RealStackSize - RVFI->getReservedSpillsSize();
550 uint64_t RVVStackSize = RVFI->getRVVStackSize();
551
552 // Early exit if there is no need to allocate on the stack
553 if (RealStackSize == 0 && !MFI.adjustsStack() && RVVStackSize == 0)
554 return;
555
556 // If the stack pointer has been marked as reserved, then produce an error if
557 // the frame requires stack allocation
558 if (STI.isRegisterReservedByUser(SPReg))
560 MF.getFunction(), "Stack pointer required, but has been reserved."});
561
562 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
563 // Split the SP adjustment to reduce the offsets of callee saved spill.
564 if (FirstSPAdjustAmount) {
565 StackSize = FirstSPAdjustAmount;
566 RealStackSize = FirstSPAdjustAmount;
567 }
568
569 if (RVFI->isPushable(MF) && FirstFrameSetup != MBB.end() &&
570 FirstFrameSetup->getOpcode() == RISCV::CM_PUSH) {
571 // Use available stack adjustment in push instruction to allocate additional
572 // stack space. Align the stack size down to a multiple of 16. This is
573 // needed for RVE.
574 // FIXME: Can we increase the stack size to a multiple of 16 instead?
575 uint64_t Spimm = std::min(alignDown(StackSize, 16), (uint64_t)48);
576 FirstFrameSetup->getOperand(1).setImm(Spimm);
577 StackSize -= Spimm;
578 }
579
580 if (StackSize != 0) {
581 // Allocate space on the stack if necessary.
582 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg,
584 getStackAlign());
585 }
586
587 // Emit ".cfi_def_cfa_offset RealStackSize"
588 unsigned CFIIndex = MF.addFrameInst(
589 MCCFIInstruction::cfiDefCfaOffset(nullptr, RealStackSize));
590 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
591 .addCFIIndex(CFIIndex)
593
594 const auto &CSI = MFI.getCalleeSavedInfo();
595
596 // The frame pointer is callee-saved, and code has been generated for us to
597 // save it to the stack. We need to skip over the storing of callee-saved
598 // registers as the frame pointer must be modified after it has been saved
599 // to the stack, not before.
600 // FIXME: assumes exactly one instruction is used to save each callee-saved
601 // register.
602 std::advance(MBBI, getUnmanagedCSI(MF, CSI).size());
603
604 // Iterate over list of callee-saved registers and emit .cfi_offset
605 // directives.
606 for (const auto &Entry : CSI) {
607 int FrameIdx = Entry.getFrameIdx();
608 if (FrameIdx >= 0 &&
610 continue;
611
612 int64_t Offset = MFI.getObjectOffset(FrameIdx);
613 Register Reg = Entry.getReg();
614 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
615 nullptr, RI->getDwarfRegNum(Reg, true), Offset));
616 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
617 .addCFIIndex(CFIIndex)
619 }
620
621 // Generate new FP.
622 if (hasFP(MF)) {
623 if (STI.isRegisterReservedByUser(FPReg))
625 MF.getFunction(), "Frame pointer required, but has been reserved."});
626 // The frame pointer does need to be reserved from register allocation.
627 assert(MF.getRegInfo().isReserved(FPReg) && "FP not reserved");
628
629 RI->adjustReg(MBB, MBBI, DL, FPReg, SPReg,
630 StackOffset::getFixed(RealStackSize - RVFI->getVarArgsSaveSize()),
632
633 // Emit ".cfi_def_cfa $fp, RVFI->getVarArgsSaveSize()"
634 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
635 nullptr, RI->getDwarfRegNum(FPReg, true), RVFI->getVarArgsSaveSize()));
636 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
637 .addCFIIndex(CFIIndex)
639 }
640
641 // Emit the second SP adjustment after saving callee saved registers.
642 if (FirstSPAdjustAmount) {
643 uint64_t SecondSPAdjustAmount =
644 getStackSizeWithRVVPadding(MF) - FirstSPAdjustAmount;
645 assert(SecondSPAdjustAmount > 0 &&
646 "SecondSPAdjustAmount should be greater than zero");
647 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg,
648 StackOffset::getFixed(-SecondSPAdjustAmount),
650
651 // If we are using a frame-pointer, and thus emitted ".cfi_def_cfa fp, 0",
652 // don't emit an sp-based .cfi_def_cfa_offset
653 if (!hasFP(MF)) {
654 // Emit ".cfi_def_cfa_offset StackSize"
655 unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(
656 nullptr, getStackSizeWithRVVPadding(MF)));
657 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
658 .addCFIIndex(CFIIndex)
660 }
661 }
662
663 if (RVVStackSize) {
664 adjustStackForRVV(MF, MBB, MBBI, DL, -RVVStackSize,
666 if (!hasFP(MF)) {
667 // Emit .cfi_def_cfa_expression "sp + StackSize + RVVStackSize * vlenb".
668 unsigned CFIIndex = MF.addFrameInst(createDefCFAExpression(
669 *RI, SPReg, getStackSizeWithRVVPadding(MF), RVVStackSize / 8));
670 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
671 .addCFIIndex(CFIIndex)
673 }
674 }
675
676 if (hasFP(MF)) {
677 // Realign Stack
679 if (RI->hasStackRealignment(MF)) {
680 Align MaxAlignment = MFI.getMaxAlign();
681
683 if (isInt<12>(-(int)MaxAlignment.value())) {
684 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
685 .addReg(SPReg)
686 .addImm(-(int)MaxAlignment.value())
688 } else {
689 unsigned ShiftAmount = Log2(MaxAlignment);
690 Register VR =
691 MF.getRegInfo().createVirtualRegister(&RISCV::GPRRegClass);
692 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)
693 .addReg(SPReg)
694 .addImm(ShiftAmount)
696 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)
697 .addReg(VR)
698 .addImm(ShiftAmount)
700 }
701 // FP will be used to restore the frame in the epilogue, so we need
702 // another base register BP to record SP after re-alignment. SP will
703 // track the current stack after allocating variable sized objects.
704 if (hasBP(MF)) {
705 // move BP, SP
706 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), BPReg)
707 .addReg(SPReg)
708 .addImm(0)
710 }
711 }
712 }
713}
714
716 MachineBasicBlock &MBB) const {
718 MachineFrameInfo &MFI = MF.getFrameInfo();
719 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
720 Register FPReg = getFPReg(STI);
721 Register SPReg = getSPReg(STI);
722
723 // All calls are tail calls in GHC calling conv, and functions have no
724 // prologue/epilogue.
726 return;
727
728 // Get the insert location for the epilogue. If there were no terminators in
729 // the block, get the last instruction.
731 DebugLoc DL;
732 if (!MBB.empty()) {
734 if (MBBI != MBB.end())
735 DL = MBBI->getDebugLoc();
736
738
739 // If callee-saved registers are saved via libcall, place stack adjustment
740 // before this call.
741 while (MBBI != MBB.begin() &&
742 std::prev(MBBI)->getFlag(MachineInstr::FrameDestroy))
743 --MBBI;
744 }
745
746 const auto &CSI = getUnmanagedCSI(MF, MFI.getCalleeSavedInfo());
747
748 // Skip to before the restores of scalar callee-saved registers
749 // FIXME: assumes exactly one instruction is used to restore each
750 // callee-saved register.
751 auto LastFrameDestroy = MBBI;
752 if (!CSI.empty())
753 LastFrameDestroy = std::prev(MBBI, CSI.size());
754
755 uint64_t RealStackSize = getStackSizeWithRVVPadding(MF);
756 uint64_t StackSize = RealStackSize - RVFI->getReservedSpillsSize();
757 uint64_t FPOffset = RealStackSize - RVFI->getVarArgsSaveSize();
758 uint64_t RVVStackSize = RVFI->getRVVStackSize();
759
760 // Restore the stack pointer using the value of the frame pointer. Only
761 // necessary if the stack pointer was modified, meaning the stack size is
762 // unknown.
763 //
764 // In order to make sure the stack point is right through the EH region,
765 // we also need to restore stack pointer from the frame pointer if we
766 // don't preserve stack space within prologue/epilogue for outgoing variables,
767 // normally it's just checking the variable sized object is present or not
768 // is enough, but we also don't preserve that at prologue/epilogue when
769 // have vector objects in stack.
770 if (RI->hasStackRealignment(MF) || MFI.hasVarSizedObjects() ||
772 assert(hasFP(MF) && "frame pointer should not have been eliminated");
773 RI->adjustReg(MBB, LastFrameDestroy, DL, SPReg, FPReg,
774 StackOffset::getFixed(-FPOffset),
776 } else {
777 if (RVVStackSize)
778 adjustStackForRVV(MF, MBB, LastFrameDestroy, DL, RVVStackSize,
780 }
781
782 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
783 if (FirstSPAdjustAmount) {
784 uint64_t SecondSPAdjustAmount =
785 getStackSizeWithRVVPadding(MF) - FirstSPAdjustAmount;
786 assert(SecondSPAdjustAmount > 0 &&
787 "SecondSPAdjustAmount should be greater than zero");
788
789 RI->adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg,
790 StackOffset::getFixed(SecondSPAdjustAmount),
792 }
793
794 if (FirstSPAdjustAmount)
795 StackSize = FirstSPAdjustAmount;
796
797 if (RVFI->isPushable(MF) && MBBI != MBB.end() &&
798 MBBI->getOpcode() == RISCV::CM_POP) {
799 // Use available stack adjustment in pop instruction to deallocate stack
800 // space. Align the stack size down to a multiple of 16. This is needed for
801 // RVE.
802 // FIXME: Can we increase the stack size to a multiple of 16 instead?
803 uint64_t Spimm = std::min(alignDown(StackSize, 16), (uint64_t)48);
804 MBBI->getOperand(1).setImm(Spimm);
805 StackSize -= Spimm;
806 }
807
808 // Deallocate stack
809 if (StackSize != 0) {
810 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(StackSize),
812 }
813
814 // Emit epilogue for shadow call stack.
815 emitSCSEpilogue(MF, MBB, MBBI, DL);
816}
817
820 Register &FrameReg) const {
821 const MachineFrameInfo &MFI = MF.getFrameInfo();
823 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
824
825 // Callee-saved registers should be referenced relative to the stack
826 // pointer (positive offset), otherwise use the frame pointer (negative
827 // offset).
828 const auto &CSI = getUnmanagedCSI(MF, MFI.getCalleeSavedInfo());
829 int MinCSFI = 0;
830 int MaxCSFI = -1;
832 auto StackID = MFI.getStackID(FI);
833
834 assert((StackID == TargetStackID::Default ||
835 StackID == TargetStackID::ScalableVector) &&
836 "Unexpected stack ID for the frame object.");
837 if (StackID == TargetStackID::Default) {
838 Offset =
840 MFI.getOffsetAdjustment());
841 } else if (StackID == TargetStackID::ScalableVector) {
843 }
844
845 uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
846
847 if (CSI.size()) {
848 MinCSFI = CSI[0].getFrameIdx();
849 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
850 }
851
852 if (FI >= MinCSFI && FI <= MaxCSFI) {
853 FrameReg = RISCV::X2;
854
855 if (FirstSPAdjustAmount)
856 Offset += StackOffset::getFixed(FirstSPAdjustAmount);
857 else
859 return Offset;
860 }
861
862 if (RI->hasStackRealignment(MF) && !MFI.isFixedObjectIndex(FI)) {
863 // If the stack was realigned, the frame pointer is set in order to allow
864 // SP to be restored, so we need another base register to record the stack
865 // after realignment.
866 // |--------------------------| -- <-- FP
867 // | callee-allocated save | | <----|
868 // | area for register varargs| | |
869 // |--------------------------| | |
870 // | callee-saved registers | | |
871 // |--------------------------| -- |
872 // | realignment (the size of | | |
873 // | this area is not counted | | |
874 // | in MFI.getStackSize()) | | |
875 // |--------------------------| -- |-- MFI.getStackSize()
876 // | RVV alignment padding | | |
877 // | (not counted in | | |
878 // | MFI.getStackSize() but | | |
879 // | counted in | | |
880 // | RVFI.getRVVStackSize()) | | |
881 // |--------------------------| -- |
882 // | RVV objects | | |
883 // | (not counted in | | |
884 // | MFI.getStackSize()) | | |
885 // |--------------------------| -- |
886 // | padding before RVV | | |
887 // | (not counted in | | |
888 // | MFI.getStackSize() or in | | |
889 // | RVFI.getRVVStackSize()) | | |
890 // |--------------------------| -- |
891 // | scalar local variables | | <----'
892 // |--------------------------| -- <-- BP (if var sized objects present)
893 // | VarSize objects | |
894 // |--------------------------| -- <-- SP
895 if (hasBP(MF)) {
896 FrameReg = RISCVABI::getBPReg();
897 } else {
898 // VarSize objects must be empty in this case!
900 FrameReg = RISCV::X2;
901 }
902 } else {
903 FrameReg = RI->getFrameRegister(MF);
904 }
905
906 if (FrameReg == getFPReg(STI)) {
907 Offset += StackOffset::getFixed(RVFI->getVarArgsSaveSize());
908 // When using FP to access scalable vector objects, we need to minus
909 // the frame size.
910 //
911 // |--------------------------| -- <-- FP
912 // | callee-allocated save | |
913 // | area for register varargs| |
914 // |--------------------------| |
915 // | callee-saved registers | |
916 // |--------------------------| | MFI.getStackSize()
917 // | scalar local variables | |
918 // |--------------------------| -- (Offset of RVV objects is from here.)
919 // | RVV objects |
920 // |--------------------------|
921 // | VarSize objects |
922 // |--------------------------| <-- SP
924 assert(!RI->hasStackRealignment(MF) &&
925 "Can't index across variable sized realign");
926 // We don't expect any extra RVV alignment padding, as the stack size
927 // and RVV object sections should be correct aligned in their own
928 // right.
930 "Inconsistent stack layout");
932 }
933 return Offset;
934 }
935
936 // This case handles indexing off both SP and BP.
937 // If indexing off SP, there must not be any var sized objects
938 assert(FrameReg == RISCVABI::getBPReg() || !MFI.hasVarSizedObjects());
939
940 // When using SP to access frame objects, we need to add RVV stack size.
941 //
942 // |--------------------------| -- <-- FP
943 // | callee-allocated save | | <----|
944 // | area for register varargs| | |
945 // |--------------------------| | |
946 // | callee-saved registers | | |
947 // |--------------------------| -- |
948 // | RVV alignment padding | | |
949 // | (not counted in | | |
950 // | MFI.getStackSize() but | | |
951 // | counted in | | |
952 // | RVFI.getRVVStackSize()) | | |
953 // |--------------------------| -- |
954 // | RVV objects | | |-- MFI.getStackSize()
955 // | (not counted in | | |
956 // | MFI.getStackSize()) | | |
957 // |--------------------------| -- |
958 // | padding before RVV | | |
959 // | (not counted in | | |
960 // | MFI.getStackSize()) | | |
961 // |--------------------------| -- |
962 // | scalar local variables | | <----'
963 // |--------------------------| -- <-- BP (if var sized objects present)
964 // | VarSize objects | |
965 // |--------------------------| -- <-- SP
966 //
967 // The total amount of padding surrounding RVV objects is described by
968 // RVV->getRVVPadding() and it can be zero. It allows us to align the RVV
969 // objects to the required alignment.
970 if (MFI.getStackID(FI) == TargetStackID::Default) {
971 if (MFI.isFixedObjectIndex(FI)) {
972 assert(!RI->hasStackRealignment(MF) &&
973 "Can't index across variable sized realign");
975 RVFI->getRVVStackSize());
976 } else {
978 }
979 } else if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
980 // Ensure the base of the RVV stack is correctly aligned: add on the
981 // alignment padding.
982 int ScalarLocalVarSize = MFI.getStackSize() -
983 RVFI->getCalleeSavedStackSize() -
984 RVFI->getRVPushStackSize() -
985 RVFI->getVarArgsSaveSize() + RVFI->getRVVPadding();
986 Offset += StackOffset::get(ScalarLocalVarSize, RVFI->getRVVStackSize());
987 }
988 return Offset;
989}
990
992 BitVector &SavedRegs,
993 RegScavenger *RS) const {
995 // Unconditionally spill RA and FP only if the function uses a frame
996 // pointer.
997 if (hasFP(MF)) {
998 SavedRegs.set(RISCV::X1);
999 SavedRegs.set(RISCV::X8);
1000 }
1001 // Mark BP as used if function has dedicated base pointer.
1002 if (hasBP(MF))
1003 SavedRegs.set(RISCVABI::getBPReg());
1004}
1005
1006std::pair<int64_t, Align>
1007RISCVFrameLowering::assignRVVStackObjectOffsets(MachineFunction &MF) const {
1008 MachineFrameInfo &MFI = MF.getFrameInfo();
1009 // Create a buffer of RVV objects to allocate.
1010 SmallVector<int, 8> ObjectsToAllocate;
1011 auto pushRVVObjects = [&](int FIBegin, int FIEnd) {
1012 for (int I = FIBegin, E = FIEnd; I != E; ++I) {
1013 unsigned StackID = MFI.getStackID(I);
1014 if (StackID != TargetStackID::ScalableVector)
1015 continue;
1016 if (MFI.isDeadObjectIndex(I))
1017 continue;
1018
1019 ObjectsToAllocate.push_back(I);
1020 }
1021 };
1022 // First push RVV Callee Saved object, then push RVV stack object
1023 std::vector<CalleeSavedInfo> &CSI = MF.getFrameInfo().getCalleeSavedInfo();
1024 const auto &RVVCSI = getRVVCalleeSavedInfo(MF, CSI);
1025 if (!RVVCSI.empty())
1026 pushRVVObjects(RVVCSI[0].getFrameIdx(),
1027 RVVCSI[RVVCSI.size() - 1].getFrameIdx() + 1);
1028 pushRVVObjects(0, MFI.getObjectIndexEnd() - RVVCSI.size());
1029
1030 // The minimum alignment is 16 bytes.
1031 Align RVVStackAlign(16);
1032 const auto &ST = MF.getSubtarget<RISCVSubtarget>();
1033
1034 if (!ST.hasVInstructions()) {
1035 assert(ObjectsToAllocate.empty() &&
1036 "Can't allocate scalable-vector objects without V instructions");
1037 return std::make_pair(0, RVVStackAlign);
1038 }
1039
1040 // Allocate all RVV locals and spills
1041 int64_t Offset = 0;
1042 for (int FI : ObjectsToAllocate) {
1043 // ObjectSize in bytes.
1044 int64_t ObjectSize = MFI.getObjectSize(FI);
1045 auto ObjectAlign = std::max(Align(8), MFI.getObjectAlign(FI));
1046 // If the data type is the fractional vector type, reserve one vector
1047 // register for it.
1048 if (ObjectSize < 8)
1049 ObjectSize = 8;
1050 Offset = alignTo(Offset + ObjectSize, ObjectAlign);
1051 MFI.setObjectOffset(FI, -Offset);
1052 // Update the maximum alignment of the RVV stack section
1053 RVVStackAlign = std::max(RVVStackAlign, ObjectAlign);
1054 }
1055
1056 // Ensure the alignment of the RVV stack. Since we want the most-aligned
1057 // object right at the bottom (i.e., any padding at the top of the frame),
1058 // readjust all RVV objects down by the alignment padding.
1059 uint64_t StackSize = Offset;
1060 if (auto AlignmentPadding = offsetToAlignment(StackSize, RVVStackAlign)) {
1061 StackSize += AlignmentPadding;
1062 for (int FI : ObjectsToAllocate)
1063 MFI.setObjectOffset(FI, MFI.getObjectOffset(FI) - AlignmentPadding);
1064 }
1065
1066 return std::make_pair(StackSize, RVVStackAlign);
1067}
1068
1070 // For RVV spill, scalable stack offsets computing requires up to two scratch
1071 // registers
1072 static constexpr unsigned ScavSlotsNumRVVSpillScalableObject = 2;
1073
1074 // For RVV spill, non-scalable stack offsets computing requires up to one
1075 // scratch register.
1076 static constexpr unsigned ScavSlotsNumRVVSpillNonScalableObject = 1;
1077
1078 // ADDI instruction's destination register can be used for computing
1079 // offsets. So Scalable stack offsets require up to one scratch register.
1080 static constexpr unsigned ScavSlotsADDIScalableObject = 1;
1081
1082 static constexpr unsigned MaxScavSlotsNumKnown =
1083 std::max({ScavSlotsADDIScalableObject, ScavSlotsNumRVVSpillScalableObject,
1084 ScavSlotsNumRVVSpillNonScalableObject});
1085
1086 unsigned MaxScavSlotsNum = 0;
1088 return false;
1089 for (const MachineBasicBlock &MBB : MF)
1090 for (const MachineInstr &MI : MBB) {
1091 bool IsRVVSpill = RISCV::isRVVSpill(MI);
1092 for (auto &MO : MI.operands()) {
1093 if (!MO.isFI())
1094 continue;
1095 bool IsScalableVectorID = MF.getFrameInfo().getStackID(MO.getIndex()) ==
1097 if (IsRVVSpill) {
1098 MaxScavSlotsNum = std::max(
1099 MaxScavSlotsNum, IsScalableVectorID
1100 ? ScavSlotsNumRVVSpillScalableObject
1101 : ScavSlotsNumRVVSpillNonScalableObject);
1102 } else if (MI.getOpcode() == RISCV::ADDI && IsScalableVectorID) {
1103 MaxScavSlotsNum =
1104 std::max(MaxScavSlotsNum, ScavSlotsADDIScalableObject);
1105 }
1106 }
1107 if (MaxScavSlotsNum == MaxScavSlotsNumKnown)
1108 return MaxScavSlotsNumKnown;
1109 }
1110 return MaxScavSlotsNum;
1111}
1112
1113static bool hasRVVFrameObject(const MachineFunction &MF) {
1114 // Originally, the function will scan all the stack objects to check whether
1115 // if there is any scalable vector object on the stack or not. However, it
1116 // causes errors in the register allocator. In issue 53016, it returns false
1117 // before RA because there is no RVV stack objects. After RA, it returns true
1118 // because there are spilling slots for RVV values during RA. It will not
1119 // reserve BP during register allocation and generate BP access in the PEI
1120 // pass due to the inconsistent behavior of the function.
1121 //
1122 // The function is changed to use hasVInstructions() as the return value. It
1123 // is not precise, but it can make the register allocation correct.
1124 //
1125 // FIXME: Find a better way to make the decision or revisit the solution in
1126 // D103622.
1127 //
1128 // Refer to https://github.com/llvm/llvm-project/issues/53016.
1129 return MF.getSubtarget<RISCVSubtarget>().hasVInstructions();
1130}
1131
1133 const RISCVInstrInfo &TII) {
1134 unsigned FnSize = 0;
1135 for (auto &MBB : MF) {
1136 for (auto &MI : MBB) {
1137 // Far branches over 20-bit offset will be relaxed in branch relaxation
1138 // pass. In the worst case, conditional branches will be relaxed into
1139 // the following instruction sequence. Unconditional branches are
1140 // relaxed in the same way, with the exception that there is no first
1141 // branch instruction.
1142 //
1143 // foo
1144 // bne t5, t6, .rev_cond # `TII->getInstSizeInBytes(MI)` bytes
1145 // sd s11, 0(sp) # 4 bytes, or 2 bytes in RVC
1146 // jump .restore, s11 # 8 bytes
1147 // .rev_cond
1148 // bar
1149 // j .dest_bb # 4 bytes, or 2 bytes in RVC
1150 // .restore:
1151 // ld s11, 0(sp) # 4 bytes, or 2 bytes in RVC
1152 // .dest:
1153 // baz
1154 if (MI.isConditionalBranch())
1155 FnSize += TII.getInstSizeInBytes(MI);
1156 if (MI.isConditionalBranch() || MI.isUnconditionalBranch()) {
1158 FnSize += 2 + 8 + 2 + 2;
1159 else
1160 FnSize += 4 + 8 + 4 + 4;
1161 continue;
1162 }
1163
1164 FnSize += TII.getInstSizeInBytes(MI);
1165 }
1166 }
1167 return FnSize;
1168}
1169
1171 MachineFunction &MF, RegScavenger *RS) const {
1172 const RISCVRegisterInfo *RegInfo =
1173 MF.getSubtarget<RISCVSubtarget>().getRegisterInfo();
1174 const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
1175 MachineFrameInfo &MFI = MF.getFrameInfo();
1176 const TargetRegisterClass *RC = &RISCV::GPRRegClass;
1177 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
1178
1179 int64_t RVVStackSize;
1180 Align RVVStackAlign;
1181 std::tie(RVVStackSize, RVVStackAlign) = assignRVVStackObjectOffsets(MF);
1182
1183 RVFI->setRVVStackSize(RVVStackSize);
1184 RVFI->setRVVStackAlign(RVVStackAlign);
1185
1186 if (hasRVVFrameObject(MF)) {
1187 // Ensure the entire stack is aligned to at least the RVV requirement: some
1188 // scalable-vector object alignments are not considered by the
1189 // target-independent code.
1190 MFI.ensureMaxAlignment(RVVStackAlign);
1191 }
1192
1193 unsigned ScavSlotsNum = 0;
1194
1195 // estimateStackSize has been observed to under-estimate the final stack
1196 // size, so give ourselves wiggle-room by checking for stack size
1197 // representable an 11-bit signed field rather than 12-bits.
1198 if (!isInt<11>(MFI.estimateStackSize(MF)))
1199 ScavSlotsNum = 1;
1200
1201 // Far branches over 20-bit offset require a spill slot for scratch register.
1202 bool IsLargeFunction = !isInt<20>(estimateFunctionSizeInBytes(MF, *TII));
1203 if (IsLargeFunction)
1204 ScavSlotsNum = std::max(ScavSlotsNum, 1u);
1205
1206 // RVV loads & stores have no capacity to hold the immediate address offsets
1207 // so we must always reserve an emergency spill slot if the MachineFunction
1208 // contains any RVV spills.
1209 ScavSlotsNum = std::max(ScavSlotsNum, getScavSlotsNumForRVV(MF));
1210
1211 for (unsigned I = 0; I < ScavSlotsNum; I++) {
1212 int FI = MFI.CreateStackObject(RegInfo->getSpillSize(*RC),
1213 RegInfo->getSpillAlign(*RC), false);
1215
1216 if (IsLargeFunction && RVFI->getBranchRelaxationScratchFrameIndex() == -1)
1217 RVFI->setBranchRelaxationScratchFrameIndex(FI);
1218 }
1219
1220 unsigned Size = RVFI->getReservedSpillsSize();
1221 for (const auto &Info : MFI.getCalleeSavedInfo()) {
1222 int FrameIdx = Info.getFrameIdx();
1223 if (FrameIdx < 0 || MFI.getStackID(FrameIdx) != TargetStackID::Default)
1224 continue;
1225
1226 Size += MFI.getObjectSize(FrameIdx);
1227 }
1228 RVFI->setCalleeSavedStackSize(Size);
1229}
1230
1231// Not preserve stack space within prologue for outgoing variables when the
1232// function contains variable size objects or there are vector objects accessed
1233// by the frame pointer.
1234// Let eliminateCallFramePseudoInstr preserve stack space for it.
1236 return !MF.getFrameInfo().hasVarSizedObjects() &&
1237 !(hasFP(MF) && hasRVVFrameObject(MF));
1238}
1239
1240// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions.
1244 Register SPReg = RISCV::X2;
1245 DebugLoc DL = MI->getDebugLoc();
1246
1247 if (!hasReservedCallFrame(MF)) {
1248 // If space has not been reserved for a call frame, ADJCALLSTACKDOWN and
1249 // ADJCALLSTACKUP must be converted to instructions manipulating the stack
1250 // pointer. This is necessary when there is a variable length stack
1251 // allocation (e.g. alloca), which means it's not possible to allocate
1252 // space for outgoing arguments from within the function prologue.
1253 int64_t Amount = MI->getOperand(0).getImm();
1254
1255 if (Amount != 0) {
1256 // Ensure the stack remains aligned after adjustment.
1257 Amount = alignSPAdjust(Amount);
1258
1259 if (MI->getOpcode() == RISCV::ADJCALLSTACKDOWN)
1260 Amount = -Amount;
1261
1262 const RISCVRegisterInfo &RI = *STI.getRegisterInfo();
1263 RI.adjustReg(MBB, MI, DL, SPReg, SPReg, StackOffset::getFixed(Amount),
1265 }
1266 }
1267
1268 return MBB.erase(MI);
1269}
1270
1271// We would like to split the SP adjustment to reduce prologue/epilogue
1272// as following instructions. In this way, the offset of the callee saved
1273// register could fit in a single store. Supposed that the first sp adjust
1274// amount is 2032.
1275// add sp,sp,-2032
1276// sw ra,2028(sp)
1277// sw s0,2024(sp)
1278// sw s1,2020(sp)
1279// sw s3,2012(sp)
1280// sw s4,2008(sp)
1281// add sp,sp,-64
1284 const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
1285 const MachineFrameInfo &MFI = MF.getFrameInfo();
1286 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
1287 uint64_t StackSize = getStackSizeWithRVVPadding(MF);
1288
1289 // Disable SplitSPAdjust if save-restore libcall is used. The callee-saved
1290 // registers will be pushed by the save-restore libcalls, so we don't have to
1291 // split the SP adjustment in this case.
1292 if (RVFI->getReservedSpillsSize())
1293 return 0;
1294
1295 // Return the FirstSPAdjustAmount if the StackSize can not fit in a signed
1296 // 12-bit and there exists a callee-saved register needing to be pushed.
1297 if (!isInt<12>(StackSize) && (CSI.size() > 0)) {
1298 // FirstSPAdjustAmount is chosen at most as (2048 - StackAlign) because
1299 // 2048 will cause sp = sp + 2048 in the epilogue to be split into multiple
1300 // instructions. Offsets smaller than 2048 can fit in a single load/store
1301 // instruction, and we have to stick with the stack alignment. 2048 has
1302 // 16-byte alignment. The stack alignment for RV32 and RV64 is 16 and for
1303 // RV32E it is 4. So (2048 - StackAlign) will satisfy the stack alignment.
1304 const uint64_t StackAlign = getStackAlign().value();
1305
1306 // Amount of (2048 - StackAlign) will prevent callee saved and restored
1307 // instructions be compressed, so try to adjust the amount to the largest
1308 // offset that stack compression instructions accept when target supports
1309 // compression instructions.
1310 if (STI.hasStdExtCOrZca()) {
1311 // The compression extensions may support the following instructions:
1312 // riscv32: c.lwsp rd, offset[7:2] => 2^(6 + 2)
1313 // c.swsp rs2, offset[7:2] => 2^(6 + 2)
1314 // c.flwsp rd, offset[7:2] => 2^(6 + 2)
1315 // c.fswsp rs2, offset[7:2] => 2^(6 + 2)
1316 // riscv64: c.ldsp rd, offset[8:3] => 2^(6 + 3)
1317 // c.sdsp rs2, offset[8:3] => 2^(6 + 3)
1318 // c.fldsp rd, offset[8:3] => 2^(6 + 3)
1319 // c.fsdsp rs2, offset[8:3] => 2^(6 + 3)
1320 const uint64_t RVCompressLen = STI.getXLen() * 8;
1321 // Compared with amount (2048 - StackAlign), StackSize needs to
1322 // satisfy the following conditions to avoid using more instructions
1323 // to adjust the sp after adjusting the amount, such as
1324 // StackSize meets the condition (StackSize <= 2048 + RVCompressLen),
1325 // case1: Amount is 2048 - StackAlign: use addi + addi to adjust sp.
1326 // case2: Amount is RVCompressLen: use addi + addi to adjust sp.
1327 auto CanCompress = [&](uint64_t CompressLen) -> bool {
1328 if (StackSize <= 2047 + CompressLen ||
1329 (StackSize > 2048 * 2 - StackAlign &&
1330 StackSize <= 2047 * 2 + CompressLen) ||
1331 StackSize > 2048 * 3 - StackAlign)
1332 return true;
1333
1334 return false;
1335 };
1336 // In the epilogue, addi sp, sp, 496 is used to recover the sp and it
1337 // can be compressed(C.ADDI16SP, offset can be [-512, 496]), but
1338 // addi sp, sp, 512 can not be compressed. So try to use 496 first.
1339 const uint64_t ADDI16SPCompressLen = 496;
1340 if (STI.is64Bit() && CanCompress(ADDI16SPCompressLen))
1341 return ADDI16SPCompressLen;
1342 if (CanCompress(RVCompressLen))
1343 return RVCompressLen;
1344 }
1345 return 2048 - StackAlign;
1346 }
1347 return 0;
1348}
1349
1350// Offsets which need to be scale by XLen representing locations of CSRs which
1351// are given a fixed location by save/restore libcalls or Zcmp Push/Pop.
1352static const std::pair<MCPhysReg, int8_t> FixedCSRFIMap[] = {
1353 {/*ra*/ RISCV::X1, -1}, {/*s0*/ RISCV::X8, -2},
1354 {/*s1*/ RISCV::X9, -3}, {/*s2*/ RISCV::X18, -4},
1355 {/*s3*/ RISCV::X19, -5}, {/*s4*/ RISCV::X20, -6},
1356 {/*s5*/ RISCV::X21, -7}, {/*s6*/ RISCV::X22, -8},
1357 {/*s7*/ RISCV::X23, -9}, {/*s8*/ RISCV::X24, -10},
1358 {/*s9*/ RISCV::X25, -11}, {/*s10*/ RISCV::X26, -12},
1359 {/*s11*/ RISCV::X27, -13}};
1360
1363 std::vector<CalleeSavedInfo> &CSI, unsigned &MinCSFrameIndex,
1364 unsigned &MaxCSFrameIndex) const {
1365 // Early exit if no callee saved registers are modified!
1366 if (CSI.empty())
1367 return true;
1368
1369 auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
1370
1371 if (RVFI->isPushable(MF)) {
1372 // Determine how many GPRs we need to push and save it to RVFI.
1373 Register MaxReg = getMaxPushPopReg(MF, CSI);
1374 if (MaxReg != RISCV::NoRegister) {
1375 auto [RegEnc, PushedRegNum] = getPushPopEncodingAndNum(MaxReg);
1376 RVFI->setRVPushRegs(PushedRegNum);
1377 RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16));
1378
1379 // Use encoded number to represent registers to spill.
1380 RVFI->setRVPushRlist(RegEnc);
1381 }
1382 }
1383
1384 MachineFrameInfo &MFI = MF.getFrameInfo();
1385 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1386
1387 for (auto &CS : CSI) {
1388 unsigned Reg = CS.getReg();
1389 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
1390 unsigned Size = RegInfo->getSpillSize(*RC);
1391
1392 // This might need a fixed stack slot.
1393 if (RVFI->useSaveRestoreLibCalls(MF) || RVFI->isPushable(MF)) {
1394 const auto *FII = llvm::find_if(
1395 FixedCSRFIMap, [&](auto P) { return P.first == CS.getReg(); });
1396 if (FII != std::end(FixedCSRFIMap)) {
1397 int64_t Offset;
1398 if (RVFI->isPushable(MF))
1399 Offset = -((FII->second + RVFI->getRVPushRegs() + 1) * (int64_t)Size);
1400 else
1401 Offset = FII->second * (int64_t)Size;
1402
1403 int FrameIdx = MFI.CreateFixedSpillStackObject(Size, Offset);
1404 assert(FrameIdx < 0);
1405 CS.setFrameIdx(FrameIdx);
1406 continue;
1407 }
1408 }
1409
1410 // Not a fixed slot.
1411 Align Alignment = RegInfo->getSpillAlign(*RC);
1412 // We may not be able to satisfy the desired alignment specification of
1413 // the TargetRegisterClass if the stack alignment is smaller. Use the
1414 // min.
1415 Alignment = std::min(Alignment, getStackAlign());
1416 int FrameIdx = MFI.CreateStackObject(Size, Alignment, true);
1417 if ((unsigned)FrameIdx < MinCSFrameIndex)
1418 MinCSFrameIndex = FrameIdx;
1419 if ((unsigned)FrameIdx > MaxCSFrameIndex)
1420 MaxCSFrameIndex = FrameIdx;
1421 CS.setFrameIdx(FrameIdx);
1422 }
1423
1424 // Allocate a fixed object that covers the full push or libcall size.
1425 if (RVFI->isPushable(MF)) {
1426 if (int64_t PushSize = RVFI->getRVPushStackSize())
1427 MFI.CreateFixedSpillStackObject(PushSize, -PushSize);
1428 } else if (int LibCallRegs = getLibCallID(MF, CSI) + 1) {
1429 int64_t LibCallFrameSize =
1430 alignTo((STI.getXLen() / 8) * LibCallRegs, getStackAlign());
1431 MFI.CreateFixedSpillStackObject(LibCallFrameSize, -LibCallFrameSize);
1432 }
1433
1434 return true;
1435}
1436
1440 if (CSI.empty())
1441 return true;
1442
1444 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
1445 DebugLoc DL;
1446 if (MI != MBB.end() && !MI->isDebugInstr())
1447 DL = MI->getDebugLoc();
1448
1449 // Emit CM.PUSH with base SPimm & evaluate Push stack
1451 if (RVFI->isPushable(*MF)) {
1452 unsigned PushedRegNum = RVFI->getRVPushRegs();
1453 if (PushedRegNum > 0) {
1454 // Use encoded number to represent registers to spill.
1455 int RegEnc = RVFI->getRVPushRlist();
1456 MachineInstrBuilder PushBuilder =
1457 BuildMI(MBB, MI, DL, TII.get(RISCV::CM_PUSH))
1459 PushBuilder.addImm((int64_t)RegEnc);
1460 PushBuilder.addImm(0);
1461
1462 for (unsigned i = 0; i < PushedRegNum; i++)
1463 PushBuilder.addUse(AllPopRegs[i], RegState::Implicit);
1464 }
1465 } else if (const char *SpillLibCall = getSpillLibCallName(*MF, CSI)) {
1466 // Add spill libcall via non-callee-saved register t0.
1467 BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5)
1468 .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL)
1470
1471 // Add registers spilled in libcall as liveins.
1472 for (auto &CS : CSI)
1473 MBB.addLiveIn(CS.getReg());
1474 }
1475
1476 // Manually spill values not spilled by libcall & Push/Pop.
1477 const auto &UnmanagedCSI = getUnmanagedCSI(*MF, CSI);
1478 const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, CSI);
1479
1480 auto storeRegToStackSlot = [&](decltype(UnmanagedCSI) CSInfo) {
1481 for (auto &CS : CSInfo) {
1482 // Insert the spill to the stack frame.
1483 Register Reg = CS.getReg();
1484 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1486 CS.getFrameIdx(), RC, TRI, Register());
1487 }
1488 };
1489 storeRegToStackSlot(UnmanagedCSI);
1490 storeRegToStackSlot(RVVCSI);
1491
1492 return true;
1493}
1494
1498 if (CSI.empty())
1499 return true;
1500
1502 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
1503 DebugLoc DL;
1504 if (MI != MBB.end() && !MI->isDebugInstr())
1505 DL = MI->getDebugLoc();
1506
1507 // Manually restore values not restored by libcall & Push/Pop.
1508 // Reverse the restore order in epilog. In addition, the return
1509 // address will be restored first in the epilogue. It increases
1510 // the opportunity to avoid the load-to-use data hazard between
1511 // loading RA and return by RA. loadRegFromStackSlot can insert
1512 // multiple instructions.
1513 const auto &UnmanagedCSI = getUnmanagedCSI(*MF, CSI);
1514 const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, CSI);
1515
1516 auto loadRegFromStackSlot = [&](decltype(UnmanagedCSI) CSInfo) {
1517 for (auto &CS : CSInfo) {
1518 Register Reg = CS.getReg();
1519 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1520 TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI,
1521 Register());
1522 assert(MI != MBB.begin() &&
1523 "loadRegFromStackSlot didn't insert any code!");
1524 }
1525 };
1526 loadRegFromStackSlot(RVVCSI);
1527 loadRegFromStackSlot(UnmanagedCSI);
1528
1530 if (RVFI->isPushable(*MF)) {
1531 int RegEnc = RVFI->getRVPushRlist();
1533 MachineInstrBuilder PopBuilder =
1534 BuildMI(MBB, MI, DL, TII.get(RISCV::CM_POP))
1536 // Use encoded number to represent registers to restore.
1537 PopBuilder.addImm(RegEnc);
1538 PopBuilder.addImm(0);
1539
1540 for (unsigned i = 0; i < RVFI->getRVPushRegs(); i++)
1542 }
1543 } else {
1544 const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI);
1545 if (RestoreLibCall) {
1546 // Add restore libcall via tail call.
1548 BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL))
1549 .addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL)
1551
1552 // Remove trailing returns, since the terminator is now a tail call to the
1553 // restore function.
1554 if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) {
1555 NewMI->copyImplicitOps(*MF, *MI);
1556 MI->eraseFromParent();
1557 }
1558 }
1559 }
1560 return true;
1561}
1562
1564 // Keep the conventional code flow when not optimizing.
1565 if (MF.getFunction().hasOptNone())
1566 return false;
1567
1568 return true;
1569}
1570
1572 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
1573 const MachineFunction *MF = MBB.getParent();
1574 const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1575
1576 if (!RVFI->useSaveRestoreLibCalls(*MF))
1577 return true;
1578
1579 // Inserting a call to a __riscv_save libcall requires the use of the register
1580 // t0 (X5) to hold the return address. Therefore if this register is already
1581 // used we can't insert the call.
1582
1583 RegScavenger RS;
1584 RS.enterBasicBlock(*TmpMBB);
1585 return !RS.isRegUsed(RISCV::X5);
1586}
1587
1589 const MachineFunction *MF = MBB.getParent();
1590 MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
1591 const auto *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1592
1593 if (!RVFI->useSaveRestoreLibCalls(*MF))
1594 return true;
1595
1596 // Using the __riscv_restore libcalls to restore CSRs requires a tail call.
1597 // This means if we still need to continue executing code within this function
1598 // the restore cannot take place in this basic block.
1599
1600 if (MBB.succ_size() > 1)
1601 return false;
1602
1603 MachineBasicBlock *SuccMBB =
1604 MBB.succ_empty() ? TmpMBB->getFallThrough() : *MBB.succ_begin();
1605
1606 // Doing a tail call should be safe if there are no successors, because either
1607 // we have a returning block or the end of the block is unreachable, so the
1608 // restore will be eliminated regardless.
1609 if (!SuccMBB)
1610 return true;
1611
1612 // The successor can only contain a return, since we would effectively be
1613 // replacing the successor with our own tail return at the end of our block.
1614 return SuccMBB->isReturnBlock() && SuccMBB->size() == 1;
1615}
1616
1618 switch (ID) {
1621 return true;
1625 return false;
1626 }
1627 llvm_unreachable("Invalid TargetStackID::Value");
1628}
1629
1632}
static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI, unsigned Reg, const StackOffset &Offset)
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static Register getFPReg(const CSKYSubtarget &STI)
This file contains constants used for implementing Dwarf debug support.
uint64_t Size
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static uint64_t estimateFunctionSizeInBytes(const LoongArchInstrInfo *TII, const MachineFunction &MF)
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
#define P(N)
static const char * getRestoreLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static const char * getSpillLibCallName(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static bool hasRVVFrameObject(const MachineFunction &MF)
static std::pair< unsigned, unsigned > getPushPopEncodingAndNum(const Register MaxReg)
static const std::pair< MCPhysReg, int8_t > FixedCSRFIMap[]
static SmallVector< CalleeSavedInfo, 8 > getRVVCalleeSavedInfo(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static Align getABIStackAlignment(RISCVABI::ABI ABI)
static int getLibCallID(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static Register getSPReg(const RISCVSubtarget &STI)
static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL)
static SmallVector< CalleeSavedInfo, 8 > getUnmanagedCSI(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static Register getMaxPushPopReg(const MachineFunction &MF, const std::vector< CalleeSavedInfo > &CSI)
static const MCPhysReg AllPopRegs[]
static unsigned getScavSlotsNumForRVV(MachineFunction &MF)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
BitVector & set()
Definition: BitVector.h:351
The CalleeSavedInfo class tracks the information need to locate where a callee saved register is in t...
Register getReg() const
A debug info location.
Definition: DebugLoc.h:33
Diagnostic information for unsupported feature in backend.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:263
bool hasOptNone() const
Do not optimize this function (-O0).
Definition: Function.h:675
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:356
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:683
void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Store the specified register of the given register class to the specified stack frame index.
void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override
Load the specified register of the given register class from the specified stack frame index.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_offset Previous value of Register is saved at offset Offset from CFA.
Definition: MCDwarf.h:583
static MCCFIInstruction cfiDefCfaOffset(MCSymbol *L, int Offset, SMLoc Loc={})
.cfi_def_cfa_offset modifies a rule for computing CFA.
Definition: MCDwarf.h:556
static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register, SMLoc Loc={})
.cfi_restore says that the rule for Register is now the same as it was at the beginning of the functi...
Definition: MCDwarf.h:616
static MCCFIInstruction cfiDefCfa(MCSymbol *L, unsigned Register, int Offset, SMLoc Loc={})
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it.
Definition: MCDwarf.h:541
static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals, SMLoc Loc={}, StringRef Comment="")
.cfi_escape Allows the user to add arbitrary bytes to the unwind info.
Definition: MCDwarf.h:647
MachineBasicBlock * getFallThrough(bool JumpToFallThrough=true)
Return the fallthrough block if the block can implicitly transfer control to the block after it by fa...
bool isLiveIn(MCPhysReg Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
iterator getFirstTerminator()
Returns an iterator to the first terminator instruction of this basic block.
unsigned succ_size() const
bool isReturnBlock() const
Convenience function that returns true if the block ends in a return instruction.
iterator getLastNonDebugInstr(bool SkipPseudoOp=true)
Returns an iterator to the last non-debug instruction in the basic block, or end().
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
bool adjustsStack() const
Return true if this function adjusts the stack – e.g., when calling another function.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void ensureMaxAlignment(Align Alignment)
Make sure the function is at least Align bytes aligned.
bool isFrameAddressTaken() const
This method may be called any time after instruction selection is complete to determine if there is a...
Align getMaxAlign() const
Return the alignment in bytes that this function must be aligned to, which is greater than the defaul...
void setObjectOffset(int ObjectIdx, int64_t SPOffset)
Set the stack frame offset of the specified object.
uint64_t estimateStackSize(const MachineFunction &MF) const
Estimate and return the size of the stack frame.
int getOffsetAdjustment() const
Return the correction for frame offsets.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool isMaxCallFrameSizeComputed() const
const std::vector< CalleeSavedInfo > & getCalleeSavedInfo() const
Returns a reference to call saved info vector for the current function.
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
int getObjectIndexEnd() const
Return one past the maximum frame object index.
int CreateFixedSpillStackObject(uint64_t Size, int64_t SPOffset, bool IsImmutable=false)
Create a spill slot at a fixed location on the stack.
uint8_t getStackID(int ObjectIdx) const
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void setStackSize(uint64_t Size)
Set the size of the stack.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
bool isDeadObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a dead object.
unsigned addFrameInst(const MCCFIInstruction &Inst)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addCFIIndex(unsigned CFIIndex) const
const MachineInstrBuilder & setMIFlag(MachineInstr::MIFlag Flag) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
bool isReserved(MCRegister PhysReg) const
isReserved - Returns true when PhysReg is a reserved register.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override
emitProlog/emitEpilog - These methods insert prolog and epilog code into the function.
uint64_t getFirstSPAdjustAmount(const MachineFunction &MF) const
bool enableShrinkWrapping(const MachineFunction &MF) const override
Returns true if the target will correctly handle shrink wrapping.
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, ArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
spillCalleeSavedRegisters - Issues instruction(s) to spill all callee saved registers and returns tru...
bool hasBP(const MachineFunction &MF) const
bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a epilogue for the target.
bool assignCalleeSavedSpillSlots(MachineFunction &MF, const TargetRegisterInfo *TRI, std::vector< CalleeSavedInfo > &CSI, unsigned &MinCSFrameIndex, unsigned &MaxCSFrameIndex) const override
assignCalleeSavedSpillSlots - Allows target to override spill slot assignment logic.
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, MutableArrayRef< CalleeSavedInfo > CSI, const TargetRegisterInfo *TRI) const override
restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee saved registers and returns...
bool hasReservedCallFrame(const MachineFunction &MF) const override
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
bool hasFP(const MachineFunction &MF) const override
hasFP - Return true if the specified function should have a dedicated frame pointer register.
const RISCVSubtarget & STI
StackOffset getFrameIndexReference(const MachineFunction &MF, int FI, Register &FrameReg) const override
getFrameIndexReference - This method should return the base register and offset used to reference a f...
bool isSupportedStackID(TargetStackID::Value ID) const override
void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS) const override
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override
TargetStackID::Value getStackIDForScalableVectors() const override
Returns the StackID that scalable vectors should be associated with.
void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override
processFunctionBeforeFrameFinalized - This method is called immediately before the specified function...
MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
This method is called during prolog/epilog code insertion to eliminate call frame setup and destroy p...
bool canUseAsPrologue(const MachineBasicBlock &MBB) const override
Check whether or not the given MBB can be used as a prologue for the target.
RISCVFrameLowering(const RISCVSubtarget &STI)
uint64_t getStackSizeWithRVVPadding(const MachineFunction &MF) const
RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo and contains private RISCV-...
bool isPushable(const MachineFunction &MF) const
bool hasStdExtCOrZca() const
unsigned getXLen() const
bool isRegisterReservedByUser(Register i) const
bool hasVInstructions() const
std::optional< unsigned > getRealVLen() const
const RISCVRegisterInfo * getRegisterInfo() const override
const RISCVInstrInfo * getInstrInfo() const override
bool isRegUsed(Register Reg, bool includeReserved=true) const
Return if a specific register is currently used.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
void addScavengingFrameIndex(int FI)
Add a scavenging frame index.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr unsigned id() const
Definition: Register.h:103
Represents a location in source code.
Definition: SMLoc.h:23
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
void append(StringRef RHS)
Append from a StringRef.
Definition: SmallString.h:68
StringRef str() const
Explicit conversion to StringRef.
Definition: SmallString.h:254
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StackOffset holds a fixed and a scalable offset in bytes.
Definition: TypeSize.h:33
int64_t getFixed() const
Returns the fixed component of the stack.
Definition: TypeSize.h:49
int64_t getScalable() const
Returns the scalable component of the stack.
Definition: TypeSize.h:52
static StackOffset get(int64_t Fixed, int64_t Scalable)
Definition: TypeSize.h:44
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Information about stack frame layout on the target.
virtual void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, RegScavenger *RS=nullptr) const
This method determines which of the registers reported by TargetRegisterInfo::getCalleeSavedRegs() sh...
int getOffsetOfLocalArea() const
getOffsetOfLocalArea - This method returns the offset of the local area from the stack pointer on ent...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
int alignSPAdjust(int SPAdj) const
alignSPAdjust - This method aligns the stack adjustment to the correct alignment.
TargetInstrInfo - Interface to description of machine instruction set.
TargetOptions Options
bool DisableFramePointerElim(const MachineFunction &MF) const
DisableFramePointerElim - This returns true if frame pointer elimination optimization should be disab...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
const TargetRegisterClass * getMinimalPhysRegClass(MCRegister Reg, MVT VT=MVT::Other) const
Returns the Register Class of a physical register of the given type, picking the most sub register cl...
Align getSpillAlign(const TargetRegisterClass &RC) const
Return the minimum required alignment in bytes for a spill slot for a register of this class.
bool hasStackRealignment(const MachineFunction &MF) const
True if stack realignment is required and still possible.
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
virtual Register getFrameRegister(const MachineFunction &MF) const =0
Debug information queries.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:660
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
Definition: CallingConv.h:50
MCRegister getBPReg()
MCRegister getSCSPReg()
bool isRVVSpill(const MachineInstr &MI)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
Definition: STLExtras.h:1680
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1736
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
uint64_t offsetToAlignment(uint64_t Value, Align Alignment)
Returns the offset to the next integer (mod 2**64) that is greater than or equal to Value and is a mu...
Definition: Alignment.h:197
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
unsigned encodeSLEB128(int64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a SLEB128 value to an output stream.
Definition: LEB128.h:23
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1749
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1879
unsigned encodeULEB128(uint64_t Value, raw_ostream &OS, unsigned PadTo=0)
Utility function to encode a ULEB128 value to an output stream.
Definition: LEB128.h:80
unsigned Log2(Align A)
Returns the log2 of the alignment.
Definition: Alignment.h:208
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:428
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
void adjustReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, Register SrcReg, StackOffset Offset, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) const