LLVM 22.0.0git
Public Member Functions | Static Public Member Functions | List of all members
llvm::RISCVRegisterInfo Struct Reference

#include "Target/RISCV/RISCVRegisterInfo.h"

Inheritance diagram for llvm::RISCVRegisterInfo:
[legend]

Public Member Functions

 RISCVRegisterInfo (unsigned HwMode)
const uint32_t * getCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const override
unsigned getCSRFirstUseCost () const override
const MCPhysReg * getCalleeSavedRegs (const MachineFunction *MF) const override
const MCPhysReg * getIPRACSRegs (const MachineFunction *MF) const override
BitVector getReservedRegs (const MachineFunction &MF) const override
bool isAsmClobberable (const MachineFunction &MF, MCRegister PhysReg) const override
const uint32_t * getNoPreservedMask () const override
void adjustReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, Register SrcReg, StackOffset Offset, MachineInstr::MIFlag Flag, MaybeAlign RequiredAlign) const
bool eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool requiresVirtualBaseRegisters (const MachineFunction &MF) const override
bool needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const override
bool isFrameOffsetLegal (const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
Register materializeFrameBaseRegister (MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
void resolveFrameIndex (MachineInstr &MI, Register BaseReg, int64_t Offset) const override
int64_t getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const override
void lowerSegmentSpillReload (MachineBasicBlock::iterator II, bool IsSpill) const
Register getFrameRegister (const MachineFunction &MF) const override
StringRef getRegAsmName (MCRegister Reg) const override
bool requiresRegisterScavenging (const MachineFunction &MF) const override
bool requiresFrameIndexScavenging (const MachineFunction &MF) const override
const TargetRegisterClass * getPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const override
const TargetRegisterClass * getLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &) const override
void getOffsetOpcodes (const StackOffset &Offset, SmallVectorImpl< uint64_t > &Ops) const override
unsigned getRegisterCostTableIndex (const MachineFunction &MF) const override
float getSpillWeightScaleFactor (const TargetRegisterClass *RC) const override
bool getRegAllocationHints (Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
Register findVRegWithEncoding (const TargetRegisterClass &RegClass, uint16_t Encoding) const

Static Public Member Functions

static bool isVRRegClass (const TargetRegisterClass *RC)
static bool isVRNRegClass (const TargetRegisterClass *RC)
static bool isRVVRegClass (const TargetRegisterClass *RC)

Detailed Description

Definition at line 57 of file RISCVRegisterInfo.h.

Constructor & Destructor Documentation

◆ RISCVRegisterInfo()

RISCVRegisterInfo::RISCVRegisterInfo ( unsigned HwMode)

Definition at line 57 of file RISCVRegisterInfo.cpp.

Member Function Documentation

◆ adjustReg()

void RISCVRegisterInfo::adjustReg ( MachineBasicBlock & MBB,
MachineBasicBlock::iterator II,
const DebugLoc & DL,
Register DestReg,
Register SrcReg,
StackOffset Offset,
MachineInstr::MIFlag Flag,
MaybeAlign RequiredAlign ) const

Definition at line 194 of file RISCVRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), DL, llvm::MachineInstr::FrameDestroy, llvm::MachineInstr::FrameSetup, llvm::StackOffset::getFixed(), llvm::getKillRegState(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), II, llvm::isInt(), llvm::isShiftedInt(), llvm::isUInt(), llvm::RegState::Kill, MBB, MRI, llvm::Offset, Opc, llvm::reportFatalUsageError(), llvm::RISCV::RVVBytesPerBlock, llvm::MachineInstrBuilder::setMIFlag(), TII, llvm::Align::value(), and llvm::MaybeAlign::valueOrOne().

Referenced by llvm::RISCVFrameLowering::allocateStack(), llvm::RISCVFrameLowering::eliminateCallFramePseudoInstr(), eliminateFrameIndex(), and llvm::RISCVFrameLowering::emitEpilogue().

◆ eliminateFrameIndex()

bool RISCVRegisterInfo::eliminateFrameIndex ( MachineBasicBlock::iterator MI,
int SPAdj,
unsigned FIOperandNum,
RegScavenger * RS = nullptr ) const
override

Definition at line 495 of file RISCVRegisterInfo.cpp.

References adjustReg(), assert(), DL, llvm::StackOffset::get(), llvm::StackOffset::getFixed(), llvm::MachineFunction::getRegInfo(), II, llvm::isInt(), llvm::RISCV::isRVVSpill(), llvm::isUInt(), lowerSegmentSpillReload(), MI, MRI, llvm::MachineInstr::NoFlags, llvm::Offset, Opc, llvm::reportFatalUsageError(), and llvm::SignExtend64().

◆ findVRegWithEncoding()

Register RISCVRegisterInfo::findVRegWithEncoding ( const TargetRegisterClass & RegClass,
uint16_t Encoding ) const

Definition at line 998 of file RISCVRegisterInfo.cpp.

References llvm::RISCVRI::getLMul(), llvm::RISCVVType::LMUL_1, and llvm::TargetRegisterClass::TSFlags.

Referenced by lowerSegmentSpillReload().

◆ getCalleeSavedRegs()

const MCPhysReg * RISCVRegisterInfo::getCalleeSavedRegs ( const MachineFunction * MF) const
override

Definition at line 67 of file RISCVRegisterInfo.cpp.

References llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32D, llvm::RISCVABI::ABI_ILP32E, llvm::RISCVABI::ABI_ILP32F, llvm::RISCVABI::ABI_LP64, llvm::RISCVABI::ABI_LP64D, llvm::RISCVABI::ABI_LP64E, llvm::RISCVABI::ABI_LP64F, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getSubtarget(), llvm::CallingConv::GHC, llvm::Function::hasFnAttribute(), llvm_unreachable, llvm::CallingConv::PreserveMost, and llvm::CallingConv::RISCV_VectorCall.

◆ getCallPreservedMask()

const uint32_t * RISCVRegisterInfo::getCallPreservedMask ( const MachineFunction & MF,
CallingConv::ID CC ) const
override

Definition at line 756 of file RISCVRegisterInfo.cpp.

References llvm::RISCVABI::ABI_ILP32, llvm::RISCVABI::ABI_ILP32D, llvm::RISCVABI::ABI_ILP32E, llvm::RISCVABI::ABI_ILP32F, llvm::RISCVABI::ABI_LP64, llvm::RISCVABI::ABI_LP64D, llvm::RISCVABI::ABI_LP64E, llvm::RISCVABI::ABI_LP64F, llvm::MachineFunction::getSubtarget(), llvm::CallingConv::GHC, llvm_unreachable, llvm::CallingConv::PreserveMost, and llvm::CallingConv::RISCV_VectorCall.

◆ getCSRFirstUseCost()

unsigned llvm::RISCVRegisterInfo::getCSRFirstUseCost ( ) const
inlineoverride

Definition at line 64 of file RISCVRegisterInfo.h.

◆ getFrameIndexInstrOffset()

int64_t RISCVRegisterInfo::getFrameIndexInstrOffset ( const MachineInstr * MI,
int Idx ) const
override

Definition at line 734 of file RISCVRegisterInfo.cpp.

References assert(), llvm::RISCVII::getFormat(), llvm::RISCVII::InstFormatI, llvm::RISCVII::InstFormatS, and MI.

Referenced by isFrameOffsetLegal(), and resolveFrameIndex().

◆ getFrameRegister()

Register RISCVRegisterInfo::getFrameRegister ( const MachineFunction & MF) const
override

Definition at line 744 of file RISCVRegisterInfo.cpp.

References llvm::TargetFrameLowering::hasFP().

◆ getIPRACSRegs()

const MCPhysReg * RISCVRegisterInfo::getIPRACSRegs ( const MachineFunction * MF) const
override

Definition at line 62 of file RISCVRegisterInfo.cpp.

◆ getLargestLegalSuperClass()

const TargetRegisterClass * RISCVRegisterInfo::getLargestLegalSuperClass ( const TargetRegisterClass * RC,
const MachineFunction &  ) const
override

Definition at line 793 of file RISCVRegisterInfo.cpp.

◆ getNoPreservedMask()

const uint32_t * RISCVRegisterInfo::getNoPreservedMask ( ) const
override

Definition at line 190 of file RISCVRegisterInfo.cpp.

◆ getOffsetOpcodes()

void RISCVRegisterInfo::getOffsetOpcodes ( const StackOffset & Offset,
SmallVectorImpl< uint64_t > & Ops ) const
override

Definition at line 808 of file RISCVRegisterInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::DIExpression::appendOffset(), assert(), getDwarfRegNum(), and llvm::Offset.

◆ getPointerRegClass()

const TargetRegisterClass * llvm::RISCVRegisterInfo::getPointerRegClass ( const MachineFunction & MF,
unsigned Kind = 0 ) const
inlineoverride

Definition at line 126 of file RISCVRegisterInfo.h.

◆ getRegAllocationHints()

bool RISCVRegisterInfo::getRegAllocationHints ( Register VirtReg,
ArrayRef< MCPhysReg > Order,
SmallVectorImpl< MCPhysReg > & Hints,
const MachineFunction & MF,
const VirtRegMap * VRM,
const LiveRegMatrix * Matrix ) const
override

Definition at line 849 of file RISCVRegisterInfo.cpp.

References contains(), llvm::SmallSet< T, N, C >::count(), DisableRegAllocHints, llvm::VirtRegMap::getPhys(), llvm::TargetRegisterInfo::getRegAllocationHints(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), I, llvm::SmallSet< T, N, C >::insert(), llvm::is_contained(), llvm::isInt(), llvm::Register::isPhysical(), Matrix, MBB, MI, MRI, OpIdx, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Register, and llvm::skipDebugInstructionsBackward().

◆ getRegAsmName()

StringRef RISCVRegisterInfo::getRegAsmName ( MCRegister Reg) const
override

Definition at line 749 of file RISCVRegisterInfo.cpp.

References llvm::TargetRegisterInfo::getRegAsmName().

◆ getRegisterCostTableIndex()

unsigned RISCVRegisterInfo::getRegisterCostTableIndex ( const MachineFunction & MF) const
override

Definition at line 836 of file RISCVRegisterInfo.cpp.

References DisableCostPerUse, and llvm::MachineFunction::getSubtarget().

◆ getReservedRegs()

BitVector RISCVRegisterInfo::getReservedRegs ( const MachineFunction & MF) const
override

Definition at line 123 of file RISCVRegisterInfo.cpp.

References assert(), llvm::RISCVABI::getBPReg(), llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getSubtarget(), llvm::CallingConv::GRAAL, llvm::RISCVFrameLowering::hasBP(), llvm::TargetFrameLowering::hasFP(), llvm::reportFatalUsageError(), and llvm::Reserved.

◆ getSpillWeightScaleFactor()

float RISCVRegisterInfo::getSpillWeightScaleFactor ( const TargetRegisterClass * RC) const
override

Definition at line 842 of file RISCVRegisterInfo.cpp.

◆ isAsmClobberable()

bool RISCVRegisterInfo::isAsmClobberable ( const MachineFunction & MF,
MCRegister PhysReg ) const
override

Definition at line 185 of file RISCVRegisterInfo.cpp.

References llvm::MachineFunction::getSubtarget(), and llvm::TargetSubtargetInfo::isRegisterReservedByUser().

◆ isFrameOffsetLegal()

bool RISCVRegisterInfo::isFrameOffsetLegal ( const MachineInstr * MI,
Register BaseReg,
int64_t Offset ) const
override

Definition at line 679 of file RISCVRegisterInfo.cpp.

References assert(), getFrameIndexInstrOffset(), llvm::isInt(), MI, and llvm::Offset.

Referenced by needsFrameBaseReg().

◆ isRVVRegClass()

bool llvm::RISCVRegisterInfo::isRVVRegClass ( const TargetRegisterClass * RC)
inlinestatic

Definition at line 159 of file RISCVRegisterInfo.h.

References llvm::RISCVRI::isVRegClass(), and llvm::TargetRegisterClass::TSFlags.

Referenced by llvm::RISCVFrameLowering::assignCalleeSavedSpillSlots(), llvm::RISCVInstrInfo::copyPhysReg(), llvm::RISCVInstrInfo::loadRegFromStackSlot(), and llvm::RISCVInstrInfo::storeRegToStackSlot().

◆ isVRNRegClass()

bool llvm::RISCVRegisterInfo::isVRNRegClass ( const TargetRegisterClass * RC)
inlinestatic

Definition at line 155 of file RISCVRegisterInfo.h.

References llvm::RISCVRI::getNF(), llvm::RISCVRI::isVRegClass(), and llvm::TargetRegisterClass::TSFlags.

◆ isVRRegClass()

bool llvm::RISCVRegisterInfo::isVRRegClass ( const TargetRegisterClass * RC)
inlinestatic

Definition at line 150 of file RISCVRegisterInfo.h.

References llvm::RISCVRI::getNF(), llvm::RISCVRI::isVRegClass(), and llvm::TargetRegisterClass::TSFlags.

◆ lowerSegmentSpillReload()

void RISCVRegisterInfo::lowerSegmentSpillReload ( MachineBasicBlock::iterator II,
bool IsSpill ) const

Definition at line 409 of file RISCVRegisterInfo.cpp.

References _, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::sampleprof::Base, llvm::BuildMI(), llvm::RISCVVType::decodeVLMUL(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::divideCoefficientBy(), DL, findVRegWithEncoding(), llvm::getDefRegState(), llvm::RISCVSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::RISCVSubtarget::getRealVLen(), llvm::MachineFunction::getRegInfo(), llvm::RISCVSubtarget::getRegisterInfo(), getSpillReloadInfo(), llvm::MachineFunction::getSubtarget(), llvm::LocationSize::getValue(), I, II, llvm::RegState::Implicit, llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf(), llvm::LocationSize::isPrecise(), llvm::RISCV::isRVVSpillForZvlsseg(), llvm::Log2_32(), MBB, llvm::RISCVInstrInfo::movImm(), MRI, llvm::Offset, TII, and TRI.

Referenced by eliminateFrameIndex().

◆ materializeFrameBaseRegister()

Register RISCVRegisterInfo::materializeFrameBaseRegister ( MachineBasicBlock * MBB,
int FrameIdx,
int64_t Offset ) const
override

Definition at line 696 of file RISCVRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), MBB, MBBI, llvm::Offset, and TII.

◆ needsFrameBaseReg()

bool RISCVRegisterInfo::needsFrameBaseReg ( MachineInstr * MI,
int64_t Offset ) const
override

Definition at line 623 of file RISCVRegisterInfo.cpp.

References assert(), contains(), llvm::RISCVII::getFormat(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFrameInfo::getLocalFrameSize(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::TargetFrameLowering::hasFP(), llvm::RISCVII::InstFormatI, llvm::RISCVII::InstFormatS, isFrameOffsetLegal(), MI, MRI, and llvm::Offset.

◆ requiresFrameIndexScavenging()

bool llvm::RISCVRegisterInfo::requiresFrameIndexScavenging ( const MachineFunction & MF) const
inlineoverride

Definition at line 121 of file RISCVRegisterInfo.h.

◆ requiresRegisterScavenging()

bool llvm::RISCVRegisterInfo::requiresRegisterScavenging ( const MachineFunction & MF) const
inlineoverride

Definition at line 117 of file RISCVRegisterInfo.h.

◆ requiresVirtualBaseRegisters()

bool RISCVRegisterInfo::requiresVirtualBaseRegisters ( const MachineFunction & MF) const
override

Definition at line 614 of file RISCVRegisterInfo.cpp.

◆ resolveFrameIndex()

void RISCVRegisterInfo::resolveFrameIndex ( MachineInstr & MI,
Register BaseReg,
int64_t Offset ) const
override

Definition at line 716 of file RISCVRegisterInfo.cpp.

References assert(), getFrameIndexInstrOffset(), MI, and llvm::Offset.

The documentation for this struct was generated from the following files:
Generated on for LLVM by doxygen 1.14.0