77#define DEBUG_TYPE "riscv-make-compressible"
78#define RISCV_COMPRESS_INSTRS_NAME "RISC-V Make Compressible"
95char RISCVMakeCompressibleOpt::ID = 0;
100static
unsigned log2LdstWidth(
unsigned Opcode) {
120 return 0x1f << log2LdstWidth(Opcode);
126 return log2LdstWidth(Opcode) == 2 ? isShiftedUInt<6, 2>(
Offset)
127 : isShiftedUInt<6, 3>(
Offset);
135 return Offset & ~compressedLDSTOffsetMask(Opcode);
140 return RISCV::GPRCRegClass.contains(Reg) ||
141 RISCV::FPR32CRegClass.contains(Reg) ||
142 RISCV::FPR64CRegClass.contains(Reg);
148 const unsigned Opcode =
MI.getOpcode();
150 return Opcode == RISCV::LW || (!STI.
is64Bit() && Opcode == RISCV::FLW) ||
151 Opcode == RISCV::LD || Opcode == RISCV::FLD;
157 const unsigned Opcode =
MI.getOpcode();
159 return Opcode == RISCV::SW || (!STI.
is64Bit() && Opcode == RISCV::FSW) ||
160 Opcode == RISCV::SD || Opcode == RISCV::FSD;
176 const unsigned Opcode =
MI.getOpcode();
199 if ((!BaseCompressed || NewBaseAdjust) && SrcDestCompressed)
208 if (!SrcDestCompressed && (BaseCompressed || SrcDest ==
Base) &&
238 if (CandidateRegImm.
Reg == RegImm.Reg && CandidateRegImm.
Imm == RegImm.Imm)
246 if (
MI.modifiesRegister(RegImm.Reg,
TRI))
255 if (MIs.
size() < 2 || (RegImm.Imm != 0 && MIs.
size() < 3))
256 return RISCV::NoRegister;
263 if (RISCV::GPRRegClass.
contains(RegImm.Reg))
264 RCToScavenge = &RISCV::GPRCRegClass;
265 else if (RISCV::FPR32RegClass.
contains(RegImm.Reg))
266 RCToScavenge = &RISCV::FPR32CRegClass;
267 else if (RISCV::FPR64RegClass.
contains(RegImm.Reg))
268 RCToScavenge = &RISCV::FPR64CRegClass;
270 return RISCV::NoRegister;
283 unsigned Opcode =
MI.getOpcode();
288 "Unsupported instruction for this optimization.");
300 if (MO.isReg() && MO.getReg() == OldRegImm.
Reg) {
320bool RISCVMakeCompressibleOpt::runOnMachineFunction(
MachineFunction &Fn) {
330 if (!STI.hasStdExtC())
362 unsigned Opcode = RISCV::FPR32RegClass.contains(
RegImm.Reg)
384 return new RISCVMakeCompressibleOpt();
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const HexagonInstrInfo * TII
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
static bool isCompressibleLoad(const MachineInstr &MI)
#define RISCV_COMPRESS_INSTRS_NAME
static bool isCompressibleStore(const MachineInstr &MI)
static uint8_t compressedLDSTOffsetMask(unsigned Opcode)
static bool isCompressedReg(Register Reg)
static Register analyzeCompressibleUses(MachineInstr &FirstMI, RegImmPair RegImm, SmallVectorImpl< MachineInstr * > &MIs)
static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode)
static void updateOperands(MachineInstr &MI, RegImmPair OldRegImm, Register NewReg)
static bool compressibleSPOffset(int64_t Offset, unsigned Opcode)
static RegImmPair getRegImmPairPreventingCompression(const MachineInstr &MI)
This file declares the machine register scavenger class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
FunctionPass class - This class is used to implement most global optimizations.
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
instr_iterator instr_end()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
const MachineBasicBlock * getParent() const
MachineOperand class - Representation of each machine instruction operand.
void setImm(int64_t immVal)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
const RISCVInstrInfo * getInstrInfo() const override
void enterBasicBlockEnd(MachineBasicBlock &MBB)
Start tracking liveness from the end of basic block MBB.
void backward()
Update internal register state and move MBB iterator backwards.
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Iterator for intrusive lists based on ilist_node.
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
FunctionPass * createRISCVMakeCompressibleOptPass()
Returns an instance of the Make Compressible Optimization pass.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void initializeRISCVMakeCompressibleOptPass(PassRegistry &)
Used to describe a register and immediate addition.