Go to the documentation of this file.
77 #define DEBUG_TYPE "riscv-make-compressible"
78 #define RISCV_COMPRESS_INSTRS_NAME "RISCV Make Compressible"
100 static
unsigned log2LdstWidth(
unsigned Opcode) {
120 return 0x1f << log2LdstWidth(Opcode);
126 return log2LdstWidth(Opcode) == 2 ? isShiftedUInt<6, 2>(Offset)
127 : isShiftedUInt<6, 3>(Offset);
140 return RISCV::GPRCRegClass.contains(
Reg) ||
141 RISCV::FPR32CRegClass.contains(
Reg) ||
142 RISCV::FPR64CRegClass.contains(
Reg);
148 const unsigned Opcode =
MI.getOpcode();
150 return Opcode == RISCV::LW || (!STI.
is64Bit() && Opcode == RISCV::FLW) ||
157 const unsigned Opcode =
MI.getOpcode();
159 return Opcode == RISCV::SW || (!STI.
is64Bit() && Opcode == RISCV::FSW) ||
160 Opcode == RISCV::SD || Opcode == RISCV::FSD;
176 const unsigned Opcode =
MI.getOpcode();
183 int64_t Offset = MOImm.
getImm();
199 if ((!BaseCompressed || NewBaseAdjust) && SrcDestCompressed)
208 if (!SrcDestCompressed && (BaseCompressed || SrcDest ==
Base) &&
264 if (MIs.size() < 2 || (
RegImm.Imm != 0 && MIs.size() < 3))
265 return RISCV::NoRegister;
273 RCToScavenge = &RISCV::GPRCRegClass;
275 RCToScavenge = &RISCV::FPR32CRegClass;
277 RCToScavenge = &RISCV::FPR64CRegClass;
279 return RISCV::NoRegister;
289 unsigned Opcode =
MI.getOpcode();
294 "Unsupported instruction for this optimization.");
298 if (MO.isReg() && MO.getReg() == OldRegImm.
Reg) {
318 bool RISCVMakeCompressibleOpt::runOnMachineFunction(
MachineFunction &Fn) {
359 unsigned Opcode = RISCV::FPR32RegClass.contains(
RegImm.Reg)
381 return new RISCVMakeCompressibleOpt();
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
#define RISCV_COMPRESS_INSTRS_NAME
static bool isCompressibleStore(const MachineInstr &MI)
Register scavengeRegisterBackwards(const TargetRegisterClass &RC, MachineBasicBlock::iterator To, bool RestoreAfter, int SPAdj, bool AllowSpill=true)
Make a register of the specific register class available from the current position backwards to the p...
return AArch64::GPR64RegClass contains(Reg)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Reg
All possible values of the reg field in the ModR/M byte.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
void setImm(int64_t immVal)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode)
unsigned const TargetRegisterInfo * TRI
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
static RegImmPair getRegImmPairPreventingCompression(const MachineInstr &MI)
INITIALIZE_PASS(RISCVMakeCompressibleOpt, "riscv-make-compressible", RISCV_COMPRESS_INSTRS_NAME, false, false) static unsigned log2LdstWidth(unsigned Opcode)
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
const RISCVInstrInfo * getInstrInfo() const override
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
static bool isCompressedReg(Register Reg)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static bool compressibleSPOffset(int64_t Offset, unsigned Opcode)
static uint8_t compressedLDSTOffsetMask(unsigned Opcode)
Representation of each machine instruction.
void initializeRISCVMakeCompressibleOptPass(PassRegistry &)
FunctionPass * createRISCVMakeCompressibleOptPass()
Returns an instance of the Make Compressible Optimization pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Used to describe a register and immediate addition.
instr_iterator instr_end()
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ FLD
This instruction implements an extending load to FP stack slots.
self_iterator getIterator()
const MachineBasicBlock * getParent() const
Wrapper class representing virtual and physical registers.
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
Function & getFunction()
Return the LLVM function that this machine code represents.
Iterator for intrusive lists based on ilist_node.
void forward()
Move the internal MBB iterator and update register states.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
static void updateOperands(MachineInstr &MI, RegImmPair OldRegImm, Register NewReg)
static Register analyzeCompressibleUses(MachineInstr &FirstMI, RegImmPair RegImm, SmallVectorImpl< MachineInstr * > &MIs)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
FunctionPass class - This class is used to implement most global optimizations.
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
static bool isCompressibleLoad(const MachineInstr &MI)