llvm::RISCVInstrInfo Class Reference

#include "Target/RISCV/RISCVInstrInfo.h"

Inheritance diagram for llvm::RISCVInstrInfo:

Public Member Functions
	RISCVInstrInfo (const RISCVSubtarget &STI)
const RISCVRegisterInfo &	getRegisterInfo () const
MCInst	getNop () const override
Register	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
Register	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex, TypeSize &MemBytes) const override
Register	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
Register	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex, TypeSize &MemBytes) const override
bool	isReMaterializableImpl (const MachineInstr &MI) const override
bool	shouldBreakCriticalEdgeToSink (MachineInstr &MI) const override
void	copyPhysRegVector (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc, const TargetRegisterClass *RegClass) const
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass *RC, Register VReg, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass *RC, Register VReg, unsigned SubReg=0, MachineInstr::MIFlag Flags=MachineInstr::NoFlags) const override
MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const override
MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const override
void	movImm (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, Register DstReg, uint64_t Val, MachineInstr::MIFlag Flag=MachineInstr::NoFlags, bool DstRenamable=false, bool DstIsDead=false) const
unsigned	getInstSizeInBytes (const MachineInstr &MI) const override
bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &dl, int *BytesAdded=nullptr) const override
void	insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override
unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool	optimizeCondBranch (MachineInstr &MI) const override
MachineBasicBlock *	getBranchDestBlock (const MachineInstr &MI) const override
bool	isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
bool	analyzeSelect (const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const override
MachineInstr *	optimizeSelect (MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &SeenMIs, bool) const override
bool	isAsCheapAsAMove (const MachineInstr &MI) const override
std::optional< DestSourcePair >	isCopyInstrImpl (const MachineInstr &MI) const override
bool	verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
bool	canFoldIntoAddrMode (const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const override
MachineInstr *	emitLdStWithAddr (MachineInstr &MemI, const ExtAddrMode &AM) const override
bool	getMemOperandsWithOffsetWidth (const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const override
bool	shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const override
bool	getMemOperandWithOffsetWidth (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, LocationSize &Width, const TargetRegisterInfo *TRI) const
bool	areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override
std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override
ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override
bool	isFunctionSafeToOutlineFrom (MachineFunction &MF, bool OutlineFromLinkOnceODRs) const override
bool	isMBBSafeToOutlineFrom (MachineBasicBlock &MBB, unsigned &Flags) const override
bool	shouldOutlineFromFunctionByDefault (MachineFunction &MF) const override
bool	analyzeCandidate (outliner::Candidate &C) const
std::optional< std::unique_ptr< outliner::OutlinedFunction > >	getOutliningCandidateInfo (const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs, unsigned MinRepeats) const override
outliner::InstrType	getOutliningTypeImpl (const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MBBI, unsigned Flags) const override
void	buildOutlinedFrame (MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const override
MachineBasicBlock::iterator	insertOutlinedCall (Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const override
std::optional< RegImmPair >	isAddImmediate (const MachineInstr &MI, Register Reg) const override
bool	findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
MachineInstr *	commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const override
bool	simplifyInstruction (MachineInstr &MI) const override
MachineInstr *	convertToThreeAddress (MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const override
std::string	createMIROperandComment (const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const override
void	mulImm (MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, const DebugLoc &DL, Register DestReg, uint32_t Amt, MachineInstr::MIFlag Flag) const
	Generate code to multiply the value in DestReg by Amt - handles all the common optimizations for this idiom, and supports fallback for subtargets which don't support multiply instructions.
bool	useMachineCombiner () const override
MachineTraceStrategy	getMachineCombinerTraceStrategy () const override
CombinerObjective	getCombinerObjective (unsigned Pattern) const override
bool	getMachineCombinerPatterns (MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const override
void	finalizeInsInstrs (MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const override
void	genAlternativeCodeSequence (MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< Register, unsigned > &InstrIdxForVirtReg) const override
bool	hasReassociableOperands (const MachineInstr &Inst, const MachineBasicBlock *MBB) const override
bool	hasReassociableSibling (const MachineInstr &Inst, bool &Commuted) const override
bool	isAssociativeAndCommutative (const MachineInstr &Inst, bool Invert) const override
std::optional< unsigned >	getInverseOpcode (unsigned Opcode) const override
void	getReassociateOperandIndices (const MachineInstr &Root, unsigned Pattern, std::array< unsigned, 5 > &OperandIndices) const override
ArrayRef< std::pair< MachineMemOperand::Flags, const char * > >	getSerializableMachineMemOperandTargetFlags () const override
unsigned	getTailDuplicateSize (CodeGenOptLevel OptLevel) const override
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo >	analyzeLoopForPipelining (MachineBasicBlock *LoopBB) const override
bool	isHighLatencyDef (int Opc) const override
bool	isVRegCopy (const MachineInstr *MI, unsigned LMul=0) const
	Return true if MI is a COPY to a vector register of a specific LMul, or any kind of vector registers when LMul is zero.

Static Public Member Functions
static bool	isPairableLdStInstOpc (unsigned Opc)
	Return true if pairing the given load or store may be paired with another.
static bool	isLdStSafeToPair (const MachineInstr &LdSt, const TargetRegisterInfo *TRI)
static RISCVCC::CondCode	getCondFromBranchOpc (unsigned Opc)
static bool	evaluateCondBranch (RISCVCC::CondCode CC, int64_t C0, int64_t C1)
	Return the result of the evaluation of C0 CC C1, where CC is a RISCVCC::CondCode.
static bool	isFromLoadImm (const MachineRegisterInfo &MRI, const MachineOperand &Op, int64_t &Imm)
	Return true if the operand is a load immediate instruction and sets Imm to the immediate value.

Protected Attributes
const RISCVSubtarget &	STI

Detailed Description

Definition at line 81 of file RISCVInstrInfo.h.

Constructor & Destructor Documentation

RISCVInstrInfo()

RISCVInstrInfo::RISCVInstrInfo ( const RISCVSubtarget & STI )

explicit

Definition at line 84 of file RISCVInstrInfo.cpp.

References STI.

Member Function Documentation

analyzeBranch()

bool RISCVInstrInfo::analyzeBranch ( MachineBasicBlock & MBB, MachineBasicBlock *& TBB, MachineBasicBlock *& FBB, SmallVectorImpl< MachineOperand > & Cond, bool AllowModify ) const

override

Definition at line 1289 of file RISCVInstrInfo.cpp.

References Cond, getBranchDestBlock(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), I, MBB, parseCondBranch(), and TBB.

Referenced by analyzeLoopForPipelining().

analyzeCandidate()

bool RISCVInstrInfo::analyzeCandidate

(

outliner::Candidate &

C

)

const

Definition at line 3645 of file RISCVInstrInfo.cpp.

References llvm::any_of(), assert(), llvm::CallingConv::C, cannotInsertTailCall(), llvm::dbgs(), llvm::RISCVII::getTailExpandUseRegNo(), isMIModifiesReg(), LLVM_DEBUG, MI, and STI.

Referenced by getOutliningCandidateInfo().

analyzeLoopForPipelining()

std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > RISCVInstrInfo::analyzeLoopForPipelining ( MachineBasicBlock * LoopBB ) const

override

Definition at line 5206 of file RISCVInstrInfo.cpp.

References analyzeBranch(), assert(), Cond, llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), MRI, reverseBranchCondition(), and TBB.

analyzeSelect()

bool RISCVInstrInfo::analyzeSelect ( const MachineInstr & MI, SmallVectorImpl< MachineOperand > & Cond, unsigned & TrueOp, unsigned & FalseOp, bool & Optimizable ) const

override

Definition at line 1901 of file RISCVInstrInfo.cpp.

References assert(), Cond, MI, and STI.

areMemAccessesTriviallyDisjoint()

bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr & MIa, const MachineInstr & MIb ) const

override

Definition at line 3511 of file RISCVInstrInfo.cpp.

References assert(), getMemOperandWithOffsetWidth(), llvm::LocationSize::getValue(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::LocationSize::hasValue(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineInstr::mayLoadOrStore(), llvm::LocationSize::precise(), STI, and TRI.

buildOutlinedFrame()

void RISCVInstrInfo::buildOutlinedFrame ( MachineBasicBlock & MBB, MachineFunction & MF, const outliner::OutlinedFunction & OF ) const

override

Definition at line 3790 of file RISCVInstrInfo.cpp.

References llvm::BuildMI(), llvm::dwarf_linker::DebugLoc, llvm::Define, llvm::get(), MachineOutlinerTailCall, and MBB.

canFoldIntoAddrMode()

bool RISCVInstrInfo::canFoldIntoAddrMode ( const MachineInstr & MemI, Register Reg, const MachineInstr & AddrI, ExtAddrMode & AM ) const

override

Definition at line 3267 of file RISCVInstrInfo.cpp.

References llvm::ExtAddrMode::BaseReg, llvm::ExtAddrMode::Basic, llvm::ExtAddrMode::Displacement, llvm::ExtAddrMode::Form, llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImm(), llvm::isInt(), llvm::MachineOperand::isReg(), llvm::ExtAddrMode::Scale, llvm::ExtAddrMode::ScaledReg, llvm::SignExtend64(), and STI.

commuteInstructionImpl()

MachineInstr * RISCVInstrInfo::commuteInstructionImpl ( MachineInstr & MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2 ) const

override

Definition at line 4222 of file RISCVInstrInfo.cpp.

References assert(), CASE_VFMA_CHANGE_OPCODE_SPLATS, CASE_VFMA_CHANGE_OPCODE_VV, CASE_VFMA_OPCODE_VV, CASE_VFMA_SPLATS, CASE_VMA_CHANGE_OPCODE_LMULS, CASE_VMA_OPCODE_LMULS, llvm::TargetInstrInfo::commuteInstructionImpl(), llvm::FMSUB, llvm::FNMADD, llvm::FNMSUB, llvm::get(), llvm::getImm(), llvm::RISCVCC::getInverseBranchCondition(), getInverseXqcicmOpcode(), llvm_unreachable, MI, and Opc.

convertToThreeAddress()

MachineInstr * RISCVInstrInfo::convertToThreeAddress ( MachineInstr & MI, LiveVariables * LV, LiveIntervals * LIS ) const

override

Definition at line 4695 of file RISCVInstrInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS, CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_ALT, CASE_FP_WIDEOP_OPCODE_LMULS, CASE_FP_WIDEOP_OPCODE_LMULS_ALT, CASE_WIDEOP_CHANGE_OPCODE_LMULS, CASE_WIDEOP_OPCODE_LMULS, llvm::MachineInstrBuilder::copyImplicitOps(), llvm::LiveRange::Segment::end, llvm::get(), llvm::LiveIntervals::getInterval(), llvm::SlotIndex::getRegSlot(), llvm::LiveRange::getSegmentContaining(), llvm::RISCVII::getVecPolicyOpNum(), llvm::RISCVII::hasVecPolicyOp(), I, llvm_unreachable, MBB, MI, llvm::LiveVariables::replaceKillInstruction(), llvm::LiveIntervals::ReplaceMachineInstrInMaps(), and llvm::Undef.

copyPhysReg()

void RISCVInstrInfo::copyPhysReg ( MachineBasicBlock & MBB, MachineBasicBlock::iterator MBBI, const DebugLoc & DL, Register DstReg, Register SrcReg, bool KillSrc, bool RenamableDest = false, bool RenamableSrc = false ) const

override

Definition at line 506 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), copyPhysRegVector(), DL, llvm::get(), llvm::getKillRegState(), llvm::getRenamableRegState(), llvm::RISCVRegisterInfo::isRVVRegClass(), llvm_unreachable, MBB, MBBI, Opc, STI, and TRI.

copyPhysRegVector()

void RISCVInstrInfo::copyPhysRegVector	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		const DebugLoc &	DL,
		MCRegister	DstReg,
		MCRegister	SrcReg,
		bool	KillSrc,
		const TargetRegisterClass *	RegClass ) const

Definition at line 383 of file RISCVInstrInfo.cpp.

References _, assert(), llvm::BuildMI(), llvm::RISCVVType::decodeVLMUL(), DL, forwardCopyWillClobberTuple(), llvm::get(), llvm::getKillRegState(), llvm::RISCVRI::getLMul(), llvm::RISCVRI::getNF(), llvm::RISCV::getRVVMCOpcode(), llvm::RISCVII::getSEWOpNum(), llvm::RISCVII::getVLOpNum(), I, llvm::Implicit, isConvertibleToVMV_V_V(), llvm::RISCVVType::LMUL_1, llvm::RISCVVType::LMUL_2, llvm::RISCVVType::LMUL_4, llvm::RISCVVType::LMUL_8, MBB, MBBI, Opc, STI, TRI, llvm::TargetRegisterClass::TSFlags, and llvm::Undef.

Referenced by copyPhysReg().

createMIROperandComment()

std::string RISCVInstrInfo::createMIROperandComment ( const MachineInstr & MI, const MachineOperand & Op, unsigned OpIdx, const TargetRegisterInfo * TRI ) const

override

Definition at line 3843 of file RISCVInstrInfo.cpp.

References assert(), llvm::TargetInstrInfo::createMIROperandComment(), llvm::RISCVVType::isValidSEW(), llvm::RISCVVType::MASK_AGNOSTIC, MI, llvm::RISCVOp::OPERAND_SEW, llvm::RISCVOp::OPERAND_SEW_MASK, llvm::RISCVOp::OPERAND_VEC_POLICY, llvm::RISCVOp::OPERAND_VTYPEI10, llvm::RISCVOp::OPERAND_VTYPEI11, llvm::RISCVOp::OPERAND_XSFMM_TWIDEN, llvm::RISCVOp::OPERAND_XSFMM_VTYPE, OpIdx, llvm::RISCVVType::printVType(), llvm::RISCVVType::printXSfmmVType(), llvm::RISCVVType::TAIL_AGNOSTIC, and TRI.

decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > RISCVInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned TF ) const

override

Definition at line 3545 of file RISCVInstrInfo.cpp.

References llvm::RISCVII::MO_DIRECT_FLAG_MASK.

emitLdStWithAddr()

MachineInstr * RISCVInstrInfo::emitLdStWithAddr ( MachineInstr & MemI, const ExtAddrMode & AM ) const

override

Definition at line 3323 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::ExtAddrMode::BaseReg, llvm::BuildMI(), llvm::ExtAddrMode::Displacement, DL, llvm::get(), llvm::MachineInstr::getDebugLoc(), llvm::getDefRegState(), llvm::MachineInstr::getFlags(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::mayLoad(), MBB, llvm::MachineInstr::memoperands(), llvm::ExtAddrMode::Scale, llvm::ExtAddrMode::ScaledReg, llvm::MachineInstrBuilder::setMemRefs(), and llvm::MachineInstrBuilder::setMIFlags().

evaluateCondBranch()

bool RISCVInstrInfo::evaluateCondBranch ( RISCVCC::CondCode CC, int64_t C0, int64_t C1 )

static

Return the result of the evaluation of C0 CC C1, where CC is a RISCVCC::CondCode.

Definition at line 1094 of file RISCVInstrInfo.cpp.

References llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, llvm::RISCVCC::COND_NE, and llvm_unreachable.

Referenced by INITIALIZE_PASS(), and optimizeCondBranch().

finalizeInsInstrs()

void RISCVInstrInfo::finalizeInsInstrs ( MachineInstr & Root, unsigned & Pattern, SmallVectorImpl< MachineInstr * > & InsInstrs ) const

override

Definition at line 2169 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addUse(), llvm::all_of(), assert(), llvm::RISCVFPRndMode::DYN, llvm::MachineOperand::getImm(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::Implicit, and MI.

findCommutedOpIndices()

bool RISCVInstrInfo::findCommutedOpIndices ( const MachineInstr & MI, unsigned & SrcOpIdx1, unsigned & SrcOpIdx2 ) const

override

Definition at line 3992 of file RISCVInstrInfo.cpp.

References assert(), CASE_RVV_OPCODE, CASE_RVV_OPCODE_MASK, CASE_RVV_OPCODE_UNMASK, CASE_RVV_OPCODE_WIDEN, CASE_VFMA_OPCODE_VV, CASE_VFMA_SPLATS, CASE_VMA_OPCODE_LMULS, llvm::TargetInstrInfo::findCommutedOpIndices(), llvm::FMSUB, llvm::FNMADD, llvm::FNMSUB, llvm::RISCVII::getVecPolicyOpNum(), llvm::RISCVII::hasVecPolicyOp(), and MI.

foldMemoryOperandImpl() [1/2]

MachineInstr * RISCVInstrInfo::foldMemoryOperandImpl ( MachineFunction & MF, MachineInstr & MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals * LIS = nullptr, VirtRegMap * VRM = nullptr ) const

override

Definition at line 897 of file RISCVInstrInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::get(), getFoldedOpcode(), MI, and STI.

foldMemoryOperandImpl() [2/2]

MachineInstr * RISCVInstrInfo::foldMemoryOperandImpl ( MachineFunction & MF, MachineInstr & MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr & LoadMI, LiveIntervals * LIS = nullptr ) const

override

Definition at line 943 of file RISCVInstrInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::get(), llvm::MachineInstr::getDesc(), llvm::getImm(), llvm::RISCVCC::getInverseBranchCondition(), getLoadPredicatedOpcode(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), MI, MRI, and STI.

genAlternativeCodeSequence()

void RISCVInstrInfo::genAlternativeCodeSequence ( MachineInstr & Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > & InsInstrs, SmallVectorImpl< MachineInstr * > & DelInstrs, DenseMap< Register, unsigned > & InstrIdxForVirtReg ) const

override

Definition at line 2912 of file RISCVInstrInfo.cpp.

References combineFPFusedMultiply(), llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, llvm::TargetInstrInfo::genAlternativeCodeSequence(), genShXAddAddShift(), llvm::MachineInstr::getMF(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), MRI, llvm::SHXADD_ADD_SLLI_OP1, and llvm::SHXADD_ADD_SLLI_OP2.

getBranchDestBlock()

MachineBasicBlock * RISCVInstrInfo::getBranchDestBlock ( const MachineInstr & MI ) const

override

Definition at line 1744 of file RISCVInstrInfo.cpp.

References assert(), and MI.

Referenced by analyzeBranch().

getCombinerObjective()

CombinerObjective RISCVInstrInfo::getCombinerObjective ( unsigned Pattern ) const

override

Definition at line 2747 of file RISCVInstrInfo.cpp.

References llvm::FMADD_AX, llvm::FMADD_XA, llvm::FMSUB, llvm::FNMSUB, llvm::TargetInstrInfo::getCombinerObjective(), and llvm::MustReduceDepth.

getCondFromBranchOpc()

RISCVCC::CondCode RISCVInstrInfo::getCondFromBranchOpc ( unsigned Opc )

static

Definition at line 1055 of file RISCVInstrInfo.cpp.

References llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_INVALID, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, llvm::RISCVCC::COND_NE, and Opc.

Referenced by INITIALIZE_PASS(), and optimizeCondBranch().

getInstSizeInBytes()

unsigned RISCVInstrInfo::getInstSizeInBytes ( const MachineInstr & MI ) const

override

Definition at line 1990 of file RISCVInstrInfo.cpp.

References F, llvm::get(), llvm::MachineFunction::getFunction(), llvm::TargetMachine::getMCAsmInfo(), llvm::PatchPointOpers::getNumPatchBytes(), llvm::StackMapOpers::getNumPatchBytes(), llvm::StatepointOpers::getNumPatchBytes(), llvm::MachineFunction::getTarget(), llvm::MachineMemOperand::isNonTemporal(), MI, and STI.

Referenced by getOutliningCandidateInfo(), insertBranch(), and removeBranch().

getInverseOpcode()

std::optional< unsigned > RISCVInstrInfo::getInverseOpcode ( unsigned Opcode ) const

override

Definition at line 2529 of file RISCVInstrInfo.cpp.

References RVV_OPC_LMUL_CASE, and RVV_OPC_LMUL_MASK_CASE.

Referenced by isAssociativeAndCommutative().

getMachineCombinerPatterns()

bool RISCVInstrInfo::getMachineCombinerPatterns ( MachineInstr & Root, SmallVectorImpl< unsigned > & Patterns, bool DoRegPressureReduce ) const

override

Definition at line 2759 of file RISCVInstrInfo.cpp.

References getFPPatterns(), llvm::TargetInstrInfo::getMachineCombinerPatterns(), and getSHXADDPatterns().

getMachineCombinerTraceStrategy()

MachineTraceStrategy RISCVInstrInfo::getMachineCombinerTraceStrategy ( ) const

override

Definition at line 2155 of file RISCVInstrInfo.cpp.

References ForceMachineCombinerStrategy, STI, llvm::TS_Local, and llvm::TS_MinInstrCount.

getMemOperandsWithOffsetWidth()

bool RISCVInstrInfo::getMemOperandsWithOffsetWidth ( const MachineInstr & MI, SmallVectorImpl< const MachineOperand * > & BaseOps, int64_t & Offset, bool & OffsetIsScalable, LocationSize & Width, const TargetRegisterInfo * TRI ) const

override

Definition at line 3376 of file RISCVInstrInfo.cpp.

References getMemOperandWithOffsetWidth(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::mayLoadOrStore(), llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and TRI.

getMemOperandWithOffsetWidth()

bool RISCVInstrInfo::getMemOperandWithOffsetWidth	(	const MachineInstr &	LdSt,
		const MachineOperand *&	BaseOp,
		int64_t &	Offset,
		LocationSize &	Width,
		const TargetRegisterInfo *	TRI ) const

Definition at line 3487 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::hasOneMemOperand(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineInstr::mayLoadOrStore(), llvm::MachineInstr::memoperands_begin(), llvm::Offset, and TRI.

Referenced by areMemAccessesTriviallyDisjoint(), and getMemOperandsWithOffsetWidth().

getNop()

MCInst RISCVInstrInfo::getNop ( ) const

override

Definition at line 92 of file RISCVInstrInfo.cpp.

References llvm::MCInstBuilder::addImm(), llvm::MCInstBuilder::addReg(), and STI.

getOutliningCandidateInfo()

std::optional< std::unique_ptr< outliner::OutlinedFunction > > RISCVInstrInfo::getOutliningCandidateInfo ( const MachineModuleInfo & MMI, std::vector< outliner::Candidate > & RepeatedSequenceLocs, unsigned MinRepeats ) const

override

Definition at line 3681 of file RISCVInstrInfo.cpp.

References analyzeCandidate(), llvm::outliner::Candidate::back(), llvm::CallingConv::C, llvm::erase_if(), getInstSizeInBytes(), llvm::outliner::Candidate::getMF(), llvm::MachineFunction::getSubtarget(), I, llvm::MachineInstr::isReturn(), MachineOutlinerDefault, MachineOutlinerTailCall, and MI.

getOutliningTypeImpl()

outliner::InstrType RISCVInstrInfo::getOutliningTypeImpl ( const MachineModuleInfo & MMI, MachineBasicBlock::iterator & MBBI, unsigned Flags ) const

override

Definition at line 3754 of file RISCVInstrInfo.cpp.

References cannotInsertTailCall(), F, llvm::outliner::Illegal, isMIModifiesReg(), llvm::outliner::Legal, MBB, MBBI, MI, llvm::RISCVII::MO_PCREL_LO, and TRI.

getReassociateOperandIndices()

void RISCVInstrInfo::getReassociateOperandIndices ( const MachineInstr & Root, unsigned Pattern, std::array< unsigned, 5 > & OperandIndices ) const

override

Definition at line 2439 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::TargetInstrInfo::getReassociateOperandIndices(), llvm::RISCV::getRVVMCOpcode(), and I.

getRegisterInfo()

const RISCVRegisterInfo & llvm::RISCVInstrInfo::getRegisterInfo ( ) const

inline

Definition at line 87 of file RISCVInstrInfo.h.

getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const

override

Definition at line 3551 of file RISCVInstrInfo.cpp.

References llvm::ArrayRef().

getSerializableMachineMemOperandTargetFlags()

ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > RISCVInstrInfo::getSerializableMachineMemOperandTargetFlags ( ) const

override

Definition at line 4914 of file RISCVInstrInfo.cpp.

References llvm::ArrayRef(), llvm::MONontemporalBit0, and llvm::MONontemporalBit1.

getTailDuplicateSize()

unsigned RISCVInstrInfo::getTailDuplicateSize ( CodeGenOptLevel OptLevel ) const

override

Definition at line 4921 of file RISCVInstrInfo.cpp.

References llvm::Aggressive, and STI.

hasReassociableOperands()

bool RISCVInstrInfo::hasReassociableOperands ( const MachineInstr & Inst, const MachineBasicBlock * MBB ) const

override

Definition at line 2416 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::TargetInstrInfo::hasReassociableOperands(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), MBB, and MRI.

hasReassociableSibling()

bool RISCVInstrInfo::hasReassociableSibling ( const MachineInstr & Inst, bool & Commuted ) const

override

Definition at line 2450 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::getMF(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::RISCV::hasEqualFRM(), llvm::TargetInstrInfo::hasReassociableSibling(), and MRI.

insertBranch()

unsigned RISCVInstrInfo::insertBranch ( MachineBasicBlock & MBB, MachineBasicBlock * TBB, MachineBasicBlock * FBB, ArrayRef< MachineOperand > Cond, const DebugLoc & dl, int * BytesAdded = nullptr ) const

override

Definition at line 1395 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, DL, llvm::get(), llvm::getImm(), getInstSizeInBytes(), MBB, MI, and TBB.

insertIndirectBranch()

void RISCVInstrInfo::insertIndirectBranch ( MachineBasicBlock & MBB, MachineBasicBlock & NewDestBB, MachineBasicBlock & RestoreBB, const DebugLoc & DL, int64_t BrOffset, RegScavenger * RS ) const

override

Definition at line 1433 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MachineBasicBlock::back(), llvm::BuildMI(), llvm::Dead, llvm::Define, DL, llvm::MachineBasicBlock::empty(), llvm::MachineBasicBlock::end(), llvm::get(), llvm::RISCVMachineFunctionInfo::getBranchRelaxationScratchFrameIndex(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getRegInfo(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), II, llvm::isInt(), llvm::Register::isValid(), loadRegFromStackSlot(), MBB, MI, llvm::RISCVII::MO_CALL, MRI, Register, llvm::report_fatal_error(), STI, storeRegToStackSlot(), and TRI.

insertOutlinedCall()

MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall ( Module & M, MachineBasicBlock & MBB, MachineBasicBlock::iterator & It, MachineFunction & MF, outliner::Candidate & C ) const

override

Definition at line 3806 of file RISCVInstrInfo.cpp.

References llvm::BuildMI(), llvm::CallingConv::C, llvm::dwarf_linker::DebugLoc, llvm::get(), llvm::MachineFunction::getName(), MachineOutlinerTailCall, MBB, and llvm::RISCVII::MO_CALL.

isAddImmediate()

std::optional< RegImmPair > RISCVInstrInfo::isAddImmediate ( const MachineInstr & MI, Register Reg ) const

override

Definition at line 3825 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), and MI.

isAsCheapAsAMove()

bool RISCVInstrInfo::isAsCheapAsAMove ( const MachineInstr & MI ) const

override

Definition at line 2076 of file RISCVInstrInfo.cpp.

References MI.

isAssociativeAndCommutative()

bool RISCVInstrInfo::isAssociativeAndCommutative ( const MachineInstr & Inst, bool Invert ) const

override

Definition at line 2473 of file RISCVInstrInfo.cpp.

References llvm::MachineInstr::FmNsz, llvm::MachineInstr::FmReassoc, llvm::MachineInstr::getFlag(), getInverseOpcode(), llvm::MachineInstr::getOpcode(), isFADD(), isFMUL(), and Opc.

isBranchOffsetInRange()

bool RISCVInstrInfo::isBranchOffsetInRange ( unsigned BranchOpc, int64_t BrOffset ) const

override

Definition at line 1751 of file RISCVInstrInfo.cpp.

References llvm::isInt(), llvm_unreachable, llvm::SignExtend64(), and STI.

isCopyInstrImpl()

std::optional< DestSourcePair > RISCVInstrInfo::isCopyInstrImpl ( const MachineInstr & MI ) const

override

Definition at line 2102 of file RISCVInstrInfo.cpp.

References MI.

isFromLoadImm()

bool RISCVInstrInfo::isFromLoadImm ( const MachineRegisterInfo & MRI, const MachineOperand & Op, int64_t & Imm )

static

Return true if the operand is a load immediate instruction and sets Imm to the immediate value.

Definition at line 1604 of file RISCVInstrInfo.cpp.

References isLoadImm(), and MRI.

Referenced by INITIALIZE_PASS(), and optimizeCondBranch().

isFunctionSafeToOutlineFrom()

bool RISCVInstrInfo::isFunctionSafeToOutlineFrom ( MachineFunction & MF, bool OutlineFromLinkOnceODRs ) const

override

Definition at line 3571 of file RISCVInstrInfo.cpp.

References F, and llvm::MachineFunction::getFunction().

isHighLatencyDef()

bool RISCVInstrInfo::isHighLatencyDef ( int Opc ) const

override

Definition at line 5248 of file RISCVInstrInfo.cpp.

References llvm::RISCV::getRVVMCOpcode(), and Opc.

isLdStSafeToPair()

bool RISCVInstrInfo::isLdStSafeToPair ( const MachineInstr & LdSt, const TargetRegisterInfo * TRI )

static

Definition at line 3355 of file RISCVInstrInfo.cpp.

References assert(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineInstr::modifiesRegister(), and TRI.

isLoadFromStackSlot() [1/2]

Register RISCVInstrInfo::isLoadFromStackSlot ( const MachineInstr & MI, int & FrameIndex ) const

override

Definition at line 101 of file RISCVInstrInfo.cpp.

References llvm::TypeSize::getZero(), isLoadFromStackSlot(), and MI.

Referenced by isLoadFromStackSlot().

isLoadFromStackSlot() [2/2]

Register RISCVInstrInfo::isLoadFromStackSlot ( const MachineInstr & MI, int & FrameIndex, TypeSize & MemBytes ) const

override

Definition at line 138 of file RISCVInstrInfo.cpp.

References llvm::TypeSize::getFixed(), getLMULForRVVWholeLoadStore(), llvm::TypeSize::getScalable(), MI, Register, and llvm::RISCV::RVVBytesPerBlock.

isMBBSafeToOutlineFrom()

bool RISCVInstrInfo::isMBBSafeToOutlineFrom ( MachineBasicBlock & MBB, unsigned & Flags ) const

override

Definition at line 3588 of file RISCVInstrInfo.cpp.

References llvm::TargetInstrInfo::isMBBSafeToOutlineFrom(), and MBB.

isPairableLdStInstOpc()

bool RISCVInstrInfo::isPairableLdStInstOpc ( unsigned Opc )

static

Return true if pairing the given load or store may be paired with another.

Definition at line 3343 of file RISCVInstrInfo.cpp.

References Opc.

isReMaterializableImpl()

bool RISCVInstrInfo::isReMaterializableImpl ( const MachineInstr & MI ) const

override

Definition at line 237 of file RISCVInstrInfo.cpp.

References llvm::RISCV::getRVVMCOpcode(), llvm::TargetInstrInfo::isReMaterializableImpl(), and MI.

isStoreToStackSlot() [1/2]

Register RISCVInstrInfo::isStoreToStackSlot ( const MachineInstr & MI, int & FrameIndex ) const

override

Definition at line 186 of file RISCVInstrInfo.cpp.

References llvm::TypeSize::getZero(), isStoreToStackSlot(), and MI.

Referenced by isStoreToStackSlot().

isStoreToStackSlot() [2/2]

Register RISCVInstrInfo::isStoreToStackSlot ( const MachineInstr & MI, int & FrameIndex, TypeSize & MemBytes ) const

override

Definition at line 192 of file RISCVInstrInfo.cpp.

References llvm::TypeSize::getFixed(), getLMULForRVVWholeLoadStore(), llvm::TypeSize::getScalable(), MI, Register, and llvm::RISCV::RVVBytesPerBlock.

isVRegCopy()

bool RISCVInstrInfo::isVRegCopy	(	const MachineInstr *	MI,
		unsigned	LMul = 0 ) const

Return true if MI is a COPY to a vector register of a specific LMul, or any kind of vector registers when LMul is zero.

Definition at line 5297 of file RISCVInstrInfo.cpp.

References llvm::RISCVVType::decodeVLMUL(), llvm::RISCVRI::getLMul(), llvm::RISCVRegisterInfo::isRVVRegClass(), llvm::Register::isVirtual(), MI, MRI, TRI, and llvm::TargetRegisterClass::TSFlags.

loadRegFromStackSlot()

void RISCVInstrInfo::loadRegFromStackSlot ( MachineBasicBlock & MBB, MachineBasicBlock::iterator MBBI, Register DstReg, int FrameIndex, const TargetRegisterClass * RC, Register VReg, unsigned SubReg = 0, MachineInstr::MIFlag Flags = MachineInstr::NoFlags ) const

override

Definition at line 737 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::BuildMI(), llvm::dwarf_linker::DebugLoc, DL, llvm::MachineInstr::FrameDestroy, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::TypeSize::getScalable(), I, llvm::RISCVRegisterInfo::isRVVRegClass(), llvm_unreachable, MBB, llvm::MachineMemOperand::MOLoad, llvm::RISCV::RVVBitsPerBlock, llvm::TargetStackID::ScalableVector, llvm::MachineInstrBuilder::setMIFlag(), llvm::MachineFrameInfo::setStackID(), STI, and SubReg.

Referenced by insertIndirectBranch().

movImm()

void RISCVInstrInfo::movImm	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		const DebugLoc &	DL,
		Register	DstReg,
		uint64_t	Val,
		MachineInstr::MIFlag	Flag = MachineInstr::NoFlags,
		bool	DstRenamable = false,
		bool	DstIsDead = false ) const

Definition at line 990 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::Define, DL, llvm::SmallVectorTemplateCommon< T, typename >::empty(), llvm::RISCVMatInt::generateInstSeq(), llvm::get(), llvm::getDeadRegState(), llvm::getKillRegState(), llvm::getRenamableRegState(), llvm::RISCVMatInt::Imm, llvm::isInt(), llvm::isUInt(), MBB, MBBI, llvm::RISCVMatInt::RegImm, llvm::RISCVMatInt::RegReg, llvm::RISCVMatInt::RegX0, llvm::report_fatal_error(), llvm::MachineInstrBuilder::setMIFlag(), llvm::SignExtend64(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and STI.

Referenced by llvm::RISCVRegisterInfo::lowerSegmentSpillReload(), and mulImm().

mulImm()

void RISCVInstrInfo::mulImm	(	MachineFunction &	MF,
		MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	II,
		const DebugLoc &	DL,
		Register	DestReg,
		uint32_t	Amt,
		MachineInstr::MIFlag	Flag ) const

Generate code to multiply the value in DestReg by Amt - handles all the common optimizations for this idiom, and supports fallback for subtargets which don't support multiply instructions.

Definition at line 4809 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::get(), llvm::MachineFunction::getRegInfo(), llvm::has_single_bit(), II, llvm::isShifted359(), llvm::Kill, llvm_unreachable, llvm::Log2_32(), MBB, movImm(), MRI, N, Opc, llvm::MachineInstrBuilder::setMIFlag(), and STI.

optimizeCondBranch()

bool RISCVInstrInfo::optimizeCondBranch ( MachineInstr & MI ) const

override

Definition at line 1618 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::RISCVCC::COND_INVALID, evaluateCondBranch(), llvm::get(), llvm::RISCVCC::getBrCond(), getCondFromBranchOpc(), I, II, isFromLoadImm(), llvm::isInt(), isLoadImm(), MBB, MI, MRI, Register, and TBB.

optimizeSelect()

MachineInstr * RISCVInstrInfo::optimizeSelect ( MachineInstr & MI, SmallPtrSetImpl< MachineInstr * > & SeenMIs, bool PreferFalse ) const

override

Definition at line 1925 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), canFoldAsPredicatedOp(), llvm::MachineInstr::clearKillInfo(), DefMI, llvm::SmallPtrSetImpl< PtrType >::erase(), llvm::get(), llvm::getImm(), llvm::RISCVCC::getInverseBranchCondition(), llvm::MCInstrDesc::getNumOperands(), getPredicatedOpcode(), llvm::MachineOperand::getReg(), llvm::SmallPtrSetImpl< PtrType >::insert(), MI, MRI, and STI.

removeBranch()

unsigned RISCVInstrInfo::removeBranch ( MachineBasicBlock & MBB, int * BytesRemoved = nullptr ) const

override

Definition at line 1361 of file RISCVInstrInfo.cpp.

References getInstSizeInBytes(), I, and MBB.

reverseBranchCondition()

bool RISCVInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > & Cond ) const

override

Definition at line 1504 of file RISCVInstrInfo.cpp.

References assert(), Cond, llvm::getImm(), and llvm_unreachable.

Referenced by analyzeLoopForPipelining().

shouldBreakCriticalEdgeToSink()

bool llvm::RISCVInstrInfo::shouldBreakCriticalEdgeToSink ( MachineInstr & MI ) const

inlineoverride

Definition at line 102 of file RISCVInstrInfo.h.

References MI.

shouldClusterMemOps()

bool RISCVInstrInfo::shouldClusterMemOps ( ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes ) const

override

Definition at line 3453 of file RISCVInstrInfo.cpp.

References CacheLineSize, llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::front(), and memOpsHaveSameBasePtr().

shouldOutlineFromFunctionByDefault()

bool RISCVInstrInfo::shouldOutlineFromFunctionByDefault ( MachineFunction & MF ) const

override

Definition at line 3600 of file RISCVInstrInfo.cpp.

References llvm::MachineFunction::getFunction(), and llvm::Function::hasMinSize().

simplifyInstruction()

bool RISCVInstrInfo::simplifyInstruction ( MachineInstr & MI ) const

override

Definition at line 4387 of file RISCVInstrInfo.cpp.

References llvm::MachineOperand::CreateImm(), llvm::get(), getSHXADDShiftAmount(), getSHXADDUWShiftAmount(), MI, and Opc.

storeRegToStackSlot()

void RISCVInstrInfo::storeRegToStackSlot ( MachineBasicBlock & MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, bool IsKill, int FrameIndex, const TargetRegisterClass * RC, Register VReg, MachineInstr::MIFlag Flags = MachineInstr::NoFlags ) const

override

Definition at line 647 of file RISCVInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::dwarf_linker::DebugLoc, llvm::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectSize(), llvm::TypeSize::getScalable(), I, llvm::RISCVRegisterInfo::isRVVRegClass(), llvm_unreachable, MBB, llvm::MachineMemOperand::MOStore, llvm::RISCV::RVVBitsPerBlock, llvm::TargetStackID::ScalableVector, llvm::MachineInstrBuilder::setMIFlag(), llvm::MachineFrameInfo::setStackID(), and STI.

Referenced by insertIndirectBranch().

useMachineCombiner()

bool llvm::RISCVInstrInfo::useMachineCombiner ( ) const

inlineoverride

Definition at line 289 of file RISCVInstrInfo.h.

verifyInstruction()

bool RISCVInstrInfo::verifyInstruction ( const MachineInstr & MI, StringRef & ErrInfo ) const

override

Definition at line 2944 of file RISCVInstrInfo.cpp.

References assert(), CASE_OPERAND_SIMM, CASE_OPERAND_UIMM, CASE_OPERAND_UIMM_LSB_ZEROS, llvm::RISCVCC::COND_INVALID, llvm::RISCVFPRndMode::DYN, llvm::enumerate(), llvm::RISCVII::getFRMOpNum(), llvm::getImm(), llvm::MachineOperand::getImm(), llvm::RISCVII::getSEWOpNum(), llvm::RISCVII::getVecPolicyOpNum(), llvm::RISCVII::getVLOpNum(), llvm::RISCVII::hasRoundModeOp(), llvm::RISCVII::hasSEWOp(), llvm::RISCVII::hasVecPolicyOp(), llvm::RISCVII::hasVLOp(), llvm::MachineOperand::isImm(), llvm::isInt(), llvm::MachineOperand::isReg(), llvm::isShiftedInt(), llvm::isShiftedUInt(), llvm::isUInt(), llvm::isValidAtomicOrdering(), llvm::RISCVFPRndMode::isValidRoundingMode(), llvm::RISCVVType::isValidSEW(), llvm::RISCVVType::isValidXSfmmVType(), llvm_unreachable, llvm::RISCVVType::MASK_AGNOSTIC, MI, MRI, llvm::RISCVOp::OPERAND_ATOMIC_ORDERING, llvm::RISCVOp::OPERAND_AVL, llvm::RISCVOp::OPERAND_BARE_SIMM32, llvm::RISCVOp::OPERAND_CLUI_IMM, llvm::RISCVOp::OPERAND_COND_CODE, llvm::RISCVOp::OPERAND_FIRST_RISCV_IMM, llvm::RISCVOp::OPERAND_FOUR, llvm::RISCVOp::OPERAND_FRMARG, llvm::RISCVOp::OPERAND_IMM5_ZIBI, llvm::RISCVOp::OPERAND_LAST_RISCV_IMM, llvm::RISCVOp::OPERAND_RLIST, llvm::RISCVOp::OPERAND_RLIST_S0, llvm::RISCVOp::OPERAND_RTZARG, llvm::RISCVOp::OPERAND_RVKRNUM, llvm::RISCVOp::OPERAND_RVKRNUM_0_7, llvm::RISCVOp::OPERAND_RVKRNUM_1_10, llvm::RISCVOp::OPERAND_RVKRNUM_2_14, llvm::RISCVOp::OPERAND_SEW, llvm::RISCVOp::OPERAND_SEW_MASK, llvm::RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO, llvm::RISCVOp::OPERAND_SIMM12_LO, llvm::RISCVOp::OPERAND_SIMM12_LSB00000, llvm::RISCVOp::OPERAND_SIMM16_NONZERO, llvm::RISCVOp::OPERAND_SIMM20_LI, llvm::RISCVOp::OPERAND_SIMM5_NONZERO, llvm::RISCVOp::OPERAND_SIMM5_PLUS1, llvm::RISCVOp::OPERAND_SIMM6_NONZERO, llvm::RISCVOp::OPERAND_SIMM8_UNSIGNED, llvm::RISCVOp::OPERAND_STACKADJ, llvm::RISCVOp::OPERAND_THREE, llvm::RISCVOp::OPERAND_UIMM10_LSB00_NONZERO, llvm::RISCVOp::OPERAND_UIMM16_NONZERO, llvm::RISCVOp::OPERAND_UIMM20_AUIPC, llvm::RISCVOp::OPERAND_UIMM20_LUI, llvm::RISCVOp::OPERAND_UIMM5_GT3, llvm::RISCVOp::OPERAND_UIMM5_NONZERO, llvm::RISCVOp::OPERAND_UIMM5_PLUS1, llvm::RISCVOp::OPERAND_UIMM8_GE32, llvm::RISCVOp::OPERAND_UIMMLOG2XLEN, llvm::RISCVOp::OPERAND_UIMMLOG2XLEN_NONZERO, llvm::RISCVOp::OPERAND_VEC_POLICY, llvm::RISCVOp::OPERAND_VEC_RM, llvm::RISCVOp::OPERAND_VTYPEI10, llvm::RISCVOp::OPERAND_VTYPEI11, llvm::RISCVOp::OPERAND_XSFMM_TWIDEN, llvm::RISCVOp::OPERAND_XSFMM_VTYPE, OpIdx, llvm::RISCVZC::RA, llvm::RISCVZC::RA_S0, llvm::RISCVZC::RA_S0_S11, llvm::RISCVFPRndMode::RTZ, STI, llvm::RISCVVType::TAIL_AGNOSTIC, and llvm::RISCVII::usesVXRM().

Member Data Documentation

STI

const RISCVSubtarget& llvm::RISCVInstrInfo::STI

protected

Definition at line 358 of file RISCVInstrInfo.h.

Referenced by analyzeCandidate(), analyzeSelect(), areMemAccessesTriviallyDisjoint(), canFoldIntoAddrMode(), copyPhysReg(), copyPhysRegVector(), foldMemoryOperandImpl(), foldMemoryOperandImpl(), getInstSizeInBytes(), getMachineCombinerTraceStrategy(), getNop(), getTailDuplicateSize(), insertIndirectBranch(), isBranchOffsetInRange(), loadRegFromStackSlot(), movImm(), mulImm(), optimizeSelect(), RISCVInstrInfo(), storeRegToStackSlot(), and verifyInstruction().

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The documentation for this class was generated from the following files:

• lib/Target/RISCV/RISCVInstrInfo.h
• lib/Target/RISCV/RISCVInstrInfo.cpp