LLVM 18.0.0git
AMDGPUTargetStreamer.cpp
Go to the documentation of this file.
1//===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AMDGPU specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
14#include "AMDGPUPTNote.h"
15#include "AMDKernelCodeT.h"
20#include "llvm/MC/MCAssembler.h"
21#include "llvm/MC/MCContext.h"
30
31using namespace llvm;
32using namespace llvm::AMDGPU;
33
34//===----------------------------------------------------------------------===//
35// AMDGPUTargetStreamer
36//===----------------------------------------------------------------------===//
37
38static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor,
39 uint32_t &Stepping, bool Sramecc, bool Xnack) {
40 if (Major == 9 && Minor == 0) {
41 switch (Stepping) {
42 case 0:
43 case 2:
44 case 4:
45 case 6:
46 if (Xnack)
47 Stepping++;
48 }
49 }
50}
51
53 HSAMD::Metadata HSAMetadata;
54 if (HSAMD::fromString(HSAMetadataString, HSAMetadata))
55 return false;
56 return EmitHSAMetadata(HSAMetadata);
57}
58
60 msgpack::Document HSAMetadataDoc;
61 if (!HSAMetadataDoc.fromYAML(HSAMetadataString))
62 return false;
63 return EmitHSAMetadata(HSAMetadataDoc, false);
64}
65
68
69 switch (ElfMach) {
70 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
71 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
81 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
128 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
129 default: AK = GK_NONE; break;
130 }
131
132 StringRef GPUName = getArchNameAMDGCN(AK);
133 if (GPUName != "")
134 return GPUName;
135 return getArchNameR600(AK);
136}
137
140 if (AK == AMDGPU::GPUKind::GK_NONE)
141 AK = parseArchR600(GPU);
142
143 switch (AK) {
203 }
204
205 llvm_unreachable("unknown GPU");
206}
207
208//===----------------------------------------------------------------------===//
209// AMDGPUTargetAsmStreamer
210//===----------------------------------------------------------------------===//
211
214 : AMDGPUTargetStreamer(S), OS(OS) { }
215
216// A hook for emitting stuff at the end.
217// We use it for emitting the accumulated PAL metadata as directives.
218// The PAL metadata is reset after it is emitted.
220 std::string S;
222 OS << S;
223
224 // Reset the pal metadata so its data will not affect a compilation that
225 // reuses this object.
227}
228
230 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n";
231}
232
234 uint32_t Major, uint32_t Minor) {
235 OS << "\t.hsa_code_object_version " <<
236 Twine(Major) << "," << Twine(Minor) << '\n';
237}
238
239void
241 uint32_t Minor,
242 uint32_t Stepping,
243 StringRef VendorName,
244 StringRef ArchName) {
245 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
246 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << ","
247 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n";
248}
249
250void
252 OS << "\t.amd_kernel_code_t\n";
253 dumpAmdKernelCode(&Header, OS, "\t\t");
254 OS << "\t.end_amd_kernel_code_t\n";
255}
256
258 unsigned Type) {
259 switch (Type) {
260 default: llvm_unreachable("Invalid AMDGPU symbol type");
262 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
263 break;
264 }
265}
266
268 Align Alignment) {
269 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", "
270 << Alignment.value() << '\n';
271}
272
274 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n";
275 return true;
276}
277
279 const AMDGPU::HSAMD::Metadata &HSAMetadata) {
280 std::string HSAMetadataString;
281 if (HSAMD::toString(HSAMetadata, HSAMetadataString))
282 return false;
283
284 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n';
285 OS << HSAMetadataString << '\n';
286 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n';
287 return true;
288}
289
291 msgpack::Document &HSAMetadataDoc, bool Strict) {
293 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
294 return false;
295
296 std::string HSAMetadataString;
297 raw_string_ostream StrOS(HSAMetadataString);
298 HSAMetadataDoc.toYAML(StrOS);
299
300 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n';
301 OS << StrOS.str() << '\n';
302 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n';
303 return true;
304}
305
307 const uint32_t Encoded_s_code_end = 0xbf9f0000;
308 const uint32_t Encoded_s_nop = 0xbf800000;
309 uint32_t Encoded_pad = Encoded_s_code_end;
310
311 // Instruction cache line size in bytes.
312 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
313 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
314
315 // Extra padding amount in bytes to support prefetch mode 3.
316 unsigned FillSize = 3 * CacheLineSize;
317
318 if (AMDGPU::isGFX90A(STI)) {
319 Encoded_pad = Encoded_s_nop;
320 FillSize = 16 * CacheLineSize;
321 }
322
323 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n';
324 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n';
325 return true;
326}
327
329 const MCSubtargetInfo &STI, StringRef KernelName,
330 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
331 bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) {
332 IsaVersion IVersion = getIsaVersion(STI.getCPU());
333
334 OS << "\t.amdhsa_kernel " << KernelName << '\n';
335
336#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
337 STREAM << "\t\t" << DIRECTIVE << " " \
338 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
339
340 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
341 << '\n';
342 OS << "\t\t.amdhsa_private_segment_fixed_size "
343 << KD.private_segment_fixed_size << '\n';
344 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n';
345
346 PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD,
347 compute_pgm_rsrc2,
348 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT);
349
352 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
353 kernel_code_properties,
354 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
355 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
356 kernel_code_properties,
357 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
358 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
359 kernel_code_properties,
360 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
361 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
362 kernel_code_properties,
363 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
364 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
365 kernel_code_properties,
366 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
368 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
369 kernel_code_properties,
370 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
371 if (hasKernargPreload(STI)) {
372 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_preload_length ", KD,
373 kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_LENGTH);
374 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_preload_offset ", KD,
375 kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_OFFSET);
376 }
377 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD,
378 kernel_code_properties,
379 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
380 if (IVersion.Major >= 10)
381 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD,
382 kernel_code_properties,
383 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
384 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5)
385 PRINT_FIELD(OS, ".amdhsa_uses_dynamic_stack", KD, kernel_code_properties,
386 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
387 PRINT_FIELD(OS,
389 ? ".amdhsa_enable_private_segment"
390 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"),
391 KD, compute_pgm_rsrc2,
392 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
393 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
394 compute_pgm_rsrc2,
395 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
396 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
397 compute_pgm_rsrc2,
398 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
399 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
400 compute_pgm_rsrc2,
401 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
402 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
403 compute_pgm_rsrc2,
404 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
405 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
406 compute_pgm_rsrc2,
407 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
408
409 // These directives are required.
410 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
411 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
412
413 if (AMDGPU::isGFX90A(STI))
414 OS << "\t\t.amdhsa_accum_offset " <<
416 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4
417 << '\n';
418
419 if (!ReserveVCC)
420 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
421 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI))
422 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
423
424 switch (CodeObjectVersion) {
425 default:
426 break;
430 if (getTargetID()->isXnackSupported())
431 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n';
432 break;
433 }
434
435 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
436 compute_pgm_rsrc1,
437 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
438 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
439 compute_pgm_rsrc1,
440 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
441 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
442 compute_pgm_rsrc1,
443 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
444 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
445 compute_pgm_rsrc1,
446 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
447 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD,
448 compute_pgm_rsrc1,
449 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
450 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD,
451 compute_pgm_rsrc1,
452 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
453 if (IVersion.Major >= 9)
454 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
455 compute_pgm_rsrc1,
456 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL);
457 if (AMDGPU::isGFX90A(STI))
458 PRINT_FIELD(OS, ".amdhsa_tg_split", KD,
459 compute_pgm_rsrc3,
460 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT);
461 if (IVersion.Major >= 10) {
462 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD,
463 compute_pgm_rsrc1,
464 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE);
465 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD,
466 compute_pgm_rsrc1,
467 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED);
468 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD,
469 compute_pgm_rsrc1,
470 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS);
471 PRINT_FIELD(OS, ".amdhsa_shared_vgpr_count", KD, compute_pgm_rsrc3,
472 amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT);
473 }
475 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
476 compute_pgm_rsrc2,
477 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
478 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
479 compute_pgm_rsrc2,
480 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
482 OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
483 compute_pgm_rsrc2,
484 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
485 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
486 compute_pgm_rsrc2,
487 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
488 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
489 compute_pgm_rsrc2,
490 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
491 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
492 compute_pgm_rsrc2,
493 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
494 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
495 compute_pgm_rsrc2,
496 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
497#undef PRINT_FIELD
498
499 OS << "\t.end_amdhsa_kernel\n";
500}
501
502//===----------------------------------------------------------------------===//
503// AMDGPUTargetELFStreamer
504//===----------------------------------------------------------------------===//
505
507 const MCSubtargetInfo &STI)
508 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {}
509
511 return static_cast<MCELFStreamer &>(Streamer);
512}
513
514// A hook for emitting stuff at the end.
515// We use it for emitting the accumulated PAL metadata as a .note record.
516// The PAL metadata is reset after it is emitted.
519 MCA.setELFHeaderEFlags(getEFlags());
520
521 std::string Blob;
522 const char *Vendor = getPALMetadata()->getVendor();
523 unsigned Type = getPALMetadata()->getType();
524 getPALMetadata()->toBlob(Type, Blob);
525 if (Blob.empty())
526 return;
527 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
528 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); });
529
530 // Reset the pal metadata so its data will not affect a compilation that
531 // reuses this object.
533}
534
535void AMDGPUTargetELFStreamer::EmitNote(
536 StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
537 function_ref<void(MCELFStreamer &)> EmitDesc) {
538 auto &S = getStreamer();
539 auto &Context = S.getContext();
540
541 auto NameSZ = Name.size() + 1;
542
543 unsigned NoteFlags = 0;
544 // TODO Apparently, this is currently needed for OpenCL as mentioned in
545 // https://reviews.llvm.org/D74995
546 if (isHsaAbi(STI))
547 NoteFlags = ELF::SHF_ALLOC;
548
549 S.pushSection();
550 S.switchSection(
551 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
552 S.emitInt32(NameSZ); // namesz
553 S.emitValue(DescSZ, 4); // descz
554 S.emitInt32(NoteType); // type
555 S.emitBytes(Name); // name
556 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
557 EmitDesc(S); // desc
558 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
559 S.popSection();
560}
561
562unsigned AMDGPUTargetELFStreamer::getEFlags() {
563 switch (STI.getTargetTriple().getArch()) {
564 default:
565 llvm_unreachable("Unsupported Arch");
566 case Triple::r600:
567 return getEFlagsR600();
568 case Triple::amdgcn:
569 return getEFlagsAMDGCN();
570 }
571}
572
573unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
575
576 return getElfMach(STI.getCPU());
577}
578
579unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
581
582 switch (STI.getTargetTriple().getOS()) {
583 default:
584 // TODO: Why are some tests have "mingw" listed as OS?
585 // llvm_unreachable("Unsupported OS");
587 return getEFlagsUnknownOS();
588 case Triple::AMDHSA:
589 return getEFlagsAMDHSA();
590 case Triple::AMDPAL:
591 return getEFlagsAMDPAL();
592 case Triple::Mesa3D:
593 return getEFlagsMesa3D();
594 }
595}
596
597unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
598 // TODO: Why are some tests have "mingw" listed as OS?
599 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS);
600
601 return getEFlagsV3();
602}
603
604unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
605 assert(isHsaAbi(STI));
606
607 if (std::optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) {
608 switch (*HsaAbiVer) {
610 return getEFlagsV3();
613 return getEFlagsV4();
614 }
615 }
616
617 llvm_unreachable("HSA OS ABI Version identification must be defined");
618}
619
620unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
622
623 return getEFlagsV3();
624}
625
626unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
628
629 return getEFlagsV3();
630}
631
632unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
633 unsigned EFlagsV3 = 0;
634
635 // mach.
636 EFlagsV3 |= getElfMach(STI.getCPU());
637
638 // xnack.
639 if (getTargetID()->isXnackOnOrAny())
641 // sramecc.
642 if (getTargetID()->isSramEccOnOrAny())
644
645 return EFlagsV3;
646}
647
648unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
649 unsigned EFlagsV4 = 0;
650
651 // mach.
652 EFlagsV4 |= getElfMach(STI.getCPU());
653
654 // xnack.
655 switch (getTargetID()->getXnackSetting()) {
658 break;
661 break;
664 break;
667 break;
668 }
669 // sramecc.
670 switch (getTargetID()->getSramEccSetting()) {
673 break;
676 break;
679 break;
682 break;
683 }
684
685 return EFlagsV4;
686}
687
689
691 uint32_t Major, uint32_t Minor) {
692
695 OS.emitInt32(Major);
696 OS.emitInt32(Minor);
697 });
698}
699
700void
702 uint32_t Minor,
703 uint32_t Stepping,
704 StringRef VendorName,
705 StringRef ArchName) {
706 uint16_t VendorNameSize = VendorName.size() + 1;
707 uint16_t ArchNameSize = ArchName.size() + 1;
708
709 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
710 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
711 VendorNameSize + ArchNameSize;
712
713 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
716 OS.emitInt16(VendorNameSize);
717 OS.emitInt16(ArchNameSize);
718 OS.emitInt32(Major);
719 OS.emitInt32(Minor);
720 OS.emitInt32(Stepping);
721 OS.emitBytes(VendorName);
722 OS.emitInt8(0); // NULL terminate VendorName
723 OS.emitBytes(ArchName);
724 OS.emitInt8(0); // NULL terminate ArchName
725 });
726}
727
728void
730
732 OS.pushSection();
733 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header)));
734 OS.popSection();
735}
736
738 unsigned Type) {
739 MCSymbolELF *Symbol = cast<MCSymbolELF>(
740 getStreamer().getContext().getOrCreateSymbol(SymbolName));
741 Symbol->setType(Type);
742}
743
745 Align Alignment) {
746 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol);
747 SymbolELF->setType(ELF::STT_OBJECT);
748
749 if (!SymbolELF->isBindingSet()) {
750 SymbolELF->setBinding(ELF::STB_GLOBAL);
751 SymbolELF->setExternal(true);
752 }
753
754 if (SymbolELF->declareCommon(Size, Alignment, true)) {
755 report_fatal_error("Symbol: " + Symbol->getName() +
756 " redeclared as different type");
757 }
758
759 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS);
761}
762
764 // Create two labels to mark the beginning and end of the desc field
765 // and a MCExpr to calculate the size of the desc field.
766 auto &Context = getContext();
767 auto *DescBegin = Context.createTempSymbol();
768 auto *DescEnd = Context.createTempSymbol();
769 auto *DescSZ = MCBinaryExpr::createSub(
772
774 [&](MCELFStreamer &OS) {
775 OS.emitLabel(DescBegin);
776 OS.emitBytes(getTargetID()->toString());
777 OS.emitLabel(DescEnd);
778 });
779 return true;
780}
781
783 bool Strict) {
785 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
786 return false;
787
788 std::string HSAMetadataString;
789 HSAMetadataDoc.writeToBlob(HSAMetadataString);
790
791 // Create two labels to mark the beginning and end of the desc field
792 // and a MCExpr to calculate the size of the desc field.
793 auto &Context = getContext();
794 auto *DescBegin = Context.createTempSymbol();
795 auto *DescEnd = Context.createTempSymbol();
796 auto *DescSZ = MCBinaryExpr::createSub(
799
801 [&](MCELFStreamer &OS) {
802 OS.emitLabel(DescBegin);
803 OS.emitBytes(HSAMetadataString);
804 OS.emitLabel(DescEnd);
805 });
806 return true;
807}
808
810 const AMDGPU::HSAMD::Metadata &HSAMetadata) {
811 std::string HSAMetadataString;
812 if (HSAMD::toString(HSAMetadata, HSAMetadataString))
813 return false;
814
815 // Create two labels to mark the beginning and end of the desc field
816 // and a MCExpr to calculate the size of the desc field.
817 auto &Context = getContext();
818 auto *DescBegin = Context.createTempSymbol();
819 auto *DescEnd = Context.createTempSymbol();
820 auto *DescSZ = MCBinaryExpr::createSub(
823
825 [&](MCELFStreamer &OS) {
826 OS.emitLabel(DescBegin);
827 OS.emitBytes(HSAMetadataString);
828 OS.emitLabel(DescEnd);
829 });
830 return true;
831}
832
834 const uint32_t Encoded_s_code_end = 0xbf9f0000;
835 const uint32_t Encoded_s_nop = 0xbf800000;
836 uint32_t Encoded_pad = Encoded_s_code_end;
837
838 // Instruction cache line size in bytes.
839 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
840 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
841
842 // Extra padding amount in bytes to support prefetch mode 3.
843 unsigned FillSize = 3 * CacheLineSize;
844
845 if (AMDGPU::isGFX90A(STI)) {
846 Encoded_pad = Encoded_s_nop;
847 FillSize = 16 * CacheLineSize;
848 }
849
851 OS.pushSection();
852 OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4);
853 for (unsigned I = 0; I < FillSize; I += 4)
854 OS.emitInt32(Encoded_pad);
855 OS.popSection();
856 return true;
857}
858
860 const MCSubtargetInfo &STI, StringRef KernelName,
861 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
862 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
863 unsigned CodeObjectVersion) {
864 auto &Streamer = getStreamer();
865 auto &Context = Streamer.getContext();
866
867 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
868 Context.getOrCreateSymbol(Twine(KernelName)));
869 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
870 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
871
872 // Copy kernel descriptor symbol's binding, other and visibility from the
873 // kernel code symbol.
874 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding());
875 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther());
876 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility());
877 // Kernel descriptor symbol's type and size are fixed.
878 KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
879 KernelDescriptorSymbol->setSize(
880 MCConstantExpr::create(sizeof(KernelDescriptor), Context));
881
882 // The visibility of the kernel code symbol must be protected or less to allow
883 // static relocations from the kernel descriptor to be used.
884 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT)
885 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED);
886
887 Streamer.emitLabel(KernelDescriptorSymbol);
888 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size);
889 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size);
890 Streamer.emitInt32(KernelDescriptor.kernarg_size);
891
892 for (uint8_t Res : KernelDescriptor.reserved0)
893 Streamer.emitInt8(Res);
894
895 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
896 // expression being created is:
897 // (start of kernel code) - (start of kernel descriptor)
898 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
901 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
903 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context),
904 Context),
905 sizeof(KernelDescriptor.kernel_code_entry_byte_offset));
906 for (uint8_t Res : KernelDescriptor.reserved1)
907 Streamer.emitInt8(Res);
908 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3);
909 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1);
910 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2);
911 Streamer.emitInt16(KernelDescriptor.kernel_code_properties);
912 Streamer.emitInt16(KernelDescriptor.kernarg_preload);
913 for (uint8_t Res : KernelDescriptor.reserved3)
914 Streamer.emitInt8(Res);
915}
This is a verifier for AMDGPU HSA metadata, which can verify both well-typed metadata and untyped met...
AMDGPU metadata definitions and in-memory representations.
Enums and constants for AMDGPU PT_NOTE sections.
#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME)
static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, uint32_t &Stepping, bool Sramecc, bool Xnack)
AMDHSA kernel descriptor definitions.
#define AMDHSA_BITS_GET(SRC, MSK)
std::string Name
uint64_t Size
#define I(x, y, z)
Definition: MD5.cpp:58
LLVMContext & Context
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
verify safepoint Safepoint IR Verifier
raw_pwrite_stream & OS
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
const char * getVendor() const
void toBlob(unsigned Type, std::string &S)
void toString(std::string &S)
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) override
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) override
virtual bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict)
Emit HSA Metadata.
AMDGPUPALMetadata * getPALMetadata()
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
static unsigned getElfMach(StringRef GPU)
MCContext & getContext() const
static StringRef getArchNameFromElfMach(unsigned ElfMach)
const std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > & getTargetID() const
std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > TargetID
virtual bool EmitHSAMetadataV2(StringRef HSAMetadataString)
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:277
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:613
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
MCAssembler & getAssembler()
Streaming machine code generation interface.
Definition: MCStreamer.h:212
MCContext & getContext() const
Definition: MCStreamer.h:297
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:180
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:424
void emitInt16(uint64_t Value)
Definition: MCStreamer.h:753
void emitInt32(uint64_t Value)
Definition: MCStreamer.h:754
void emitInt8(uint64_t Value)
Definition: MCStreamer.h:752
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
StringRef getCPU() const
unsigned getOther() const
void setVisibility(unsigned Visibility)
void setSize(const MCExpr *SS)
Definition: MCSymbolELF.h:22
bool isBindingSet() const
void setBinding(unsigned Binding) const
Definition: MCSymbolELF.cpp:43
unsigned getVisibility() const
unsigned getBinding() const
Definition: MCSymbolELF.cpp:66
void setType(unsigned Type) const
Definition: MCSymbolELF.cpp:94
void setOther(unsigned Other)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:389
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
void setExternal(bool Value) const
Definition: MCSymbol.h:408
void setIndex(uint32_t Value) const
Set the (implementation defined) index.
Definition: MCSymbol.h:322
bool declareCommon(uint64_t Size, Align Alignment, bool Target=false)
Declare this symbol as being 'common'.
Definition: MCSymbol.h:376
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:364
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:355
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
An efficient, type-erasing, non-owning reference to a callable.
Simple in-memory representation of a document of msgpack objects with ability to find and create arra...
DocNode & getRoot()
Get ref to the document's root element.
void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:642
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:660
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const char NoteNameV2[]
Definition: AMDGPUPTNote.h:26
const char SectionName[]
Definition: AMDGPUPTNote.h:24
const char NoteNameV3[]
Definition: AMDGPUPTNote.h:27
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
std::error_code fromString(StringRef String, Metadata &HSAMetadata)
Converts String to HSAMetadata.
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
std::error_code toString(Metadata HSAMetadata, std::string &String)
Converts HSAMetadata to String.
StringRef getArchNameR600(GPUKind AK)
GPUKind
GPU kinds supported by the AMDGPU target.
Definition: TargetParser.h:35
bool isHsaAbi(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
bool isGFX90A(const MCSubtargetInfo &STI)
GPUKind parseArchAMDGCN(StringRef CPU)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
StringRef getArchNameAMDGCN(GPUKind AK)
std::optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
GPUKind parseArchR600(StringRef CPU)
@ STB_GLOBAL
Definition: ELF.h:1243
@ ELFABIVERSION_AMDGPU_HSA_V4
Definition: ELF.h:376
@ ELFABIVERSION_AMDGPU_HSA_V5
Definition: ELF.h:377
@ ELFABIVERSION_AMDGPU_HSA_V3
Definition: ELF.h:375
@ SHT_NOTE
Definition: ELF.h:1006
@ NT_AMDGPU_METADATA
Definition: ELF.h:1775
@ NT_AMD_HSA_ISA_NAME
Definition: ELF.h:1768
@ NT_AMD_HSA_ISA_VERSION
Definition: ELF.h:1765
@ NT_AMD_HSA_CODE_OBJECT_VERSION
Definition: ELF.h:1763
@ NT_AMD_HSA_METADATA
Definition: ELF.h:1767
@ EF_AMDGPU_FEATURE_XNACK_ANY_V4
Definition: ELF.h:820
@ EF_AMDGPU_MACH_AMDGCN_GFX703
Definition: ELF.h:746
@ EF_AMDGPU_MACH_AMDGCN_GFX1035
Definition: ELF.h:770
@ EF_AMDGPU_FEATURE_SRAMECC_V3
Definition: ELF.h:811
@ EF_AMDGPU_MACH_AMDGCN_GFX1031
Definition: ELF.h:764
@ EF_AMDGPU_MACH_R600_CAYMAN
Definition: ELF.h:729
@ EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
Definition: ELF.h:831
@ EF_AMDGPU_MACH_AMDGCN_GFX704
Definition: ELF.h:747
@ EF_AMDGPU_MACH_AMDGCN_GFX902
Definition: ELF.h:754
@ EF_AMDGPU_MACH_AMDGCN_GFX810
Definition: ELF.h:752
@ EF_AMDGPU_MACH_AMDGCN_GFX1036
Definition: ELF.h:778
@ EF_AMDGPU_MACH_AMDGCN_GFX1102
Definition: ELF.h:780
@ EF_AMDGPU_MACH_R600_RV730
Definition: ELF.h:718
@ EF_AMDGPU_MACH_R600_RV710
Definition: ELF.h:717
@ EF_AMDGPU_MACH_AMDGCN_GFX908
Definition: ELF.h:757
@ EF_AMDGPU_MACH_AMDGCN_GFX1011
Definition: ELF.h:761
@ EF_AMDGPU_MACH_R600_CYPRESS
Definition: ELF.h:722
@ EF_AMDGPU_MACH_AMDGCN_GFX1032
Definition: ELF.h:765
@ EF_AMDGPU_MACH_R600_R600
Definition: ELF.h:712
@ EF_AMDGPU_MACH_AMDGCN_GFX940
Definition: ELF.h:773
@ EF_AMDGPU_MACH_AMDGCN_GFX941
Definition: ELF.h:784
@ EF_AMDGPU_MACH_R600_TURKS
Definition: ELF.h:730
@ EF_AMDGPU_MACH_R600_JUNIPER
Definition: ELF.h:723
@ EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
Definition: ELF.h:835
@ EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
Definition: ELF.h:818
@ EF_AMDGPU_MACH_AMDGCN_GFX601
Definition: ELF.h:742
@ EF_AMDGPU_MACH_AMDGCN_GFX942
Definition: ELF.h:785
@ EF_AMDGPU_MACH_R600_R630
Definition: ELF.h:713
@ EF_AMDGPU_MACH_R600_REDWOOD
Definition: ELF.h:724
@ EF_AMDGPU_MACH_R600_RV770
Definition: ELF.h:719
@ EF_AMDGPU_FEATURE_XNACK_OFF_V4
Definition: ELF.h:822
@ EF_AMDGPU_MACH_AMDGCN_GFX600
Definition: ELF.h:741
@ EF_AMDGPU_FEATURE_XNACK_V3
Definition: ELF.h:806
@ EF_AMDGPU_MACH_AMDGCN_GFX602
Definition: ELF.h:767
@ EF_AMDGPU_MACH_AMDGCN_GFX1101
Definition: ELF.h:779
@ EF_AMDGPU_MACH_AMDGCN_GFX1100
Definition: ELF.h:774
@ EF_AMDGPU_MACH_AMDGCN_GFX1033
Definition: ELF.h:766
@ EF_AMDGPU_MACH_AMDGCN_GFX801
Definition: ELF.h:749
@ EF_AMDGPU_MACH_AMDGCN_GFX705
Definition: ELF.h:768
@ EF_AMDGPU_MACH_AMDGCN_GFX1010
Definition: ELF.h:760
@ EF_AMDGPU_MACH_R600_RV670
Definition: ELF.h:715
@ EF_AMDGPU_MACH_AMDGCN_GFX701
Definition: ELF.h:744
@ EF_AMDGPU_MACH_AMDGCN_GFX1012
Definition: ELF.h:762
@ EF_AMDGPU_MACH_AMDGCN_GFX1151
Definition: ELF.h:783
@ EF_AMDGPU_MACH_AMDGCN_GFX1030
Definition: ELF.h:763
@ EF_AMDGPU_MACH_R600_CEDAR
Definition: ELF.h:721
@ EF_AMDGPU_MACH_AMDGCN_GFX700
Definition: ELF.h:743
@ EF_AMDGPU_MACH_AMDGCN_GFX803
Definition: ELF.h:751
@ EF_AMDGPU_MACH_AMDGCN_GFX802
Definition: ELF.h:750
@ EF_AMDGPU_MACH_AMDGCN_GFX90C
Definition: ELF.h:759
@ EF_AMDGPU_FEATURE_XNACK_ON_V4
Definition: ELF.h:824
@ EF_AMDGPU_MACH_AMDGCN_GFX900
Definition: ELF.h:753
@ EF_AMDGPU_MACH_AMDGCN_GFX909
Definition: ELF.h:758
@ EF_AMDGPU_MACH_AMDGCN_GFX906
Definition: ELF.h:756
@ EF_AMDGPU_MACH_NONE
Definition: ELF.h:707
@ EF_AMDGPU_MACH_AMDGCN_GFX1103
Definition: ELF.h:777
@ EF_AMDGPU_MACH_R600_CAICOS
Definition: ELF.h:728
@ EF_AMDGPU_MACH_AMDGCN_GFX90A
Definition: ELF.h:772
@ EF_AMDGPU_MACH_AMDGCN_GFX1034
Definition: ELF.h:771
@ EF_AMDGPU_MACH_AMDGCN_GFX1013
Definition: ELF.h:775
@ EF_AMDGPU_MACH_AMDGCN_GFX904
Definition: ELF.h:755
@ EF_AMDGPU_MACH_R600_RS880
Definition: ELF.h:714
@ EF_AMDGPU_MACH_AMDGCN_GFX805
Definition: ELF.h:769
@ EF_AMDGPU_MACH_AMDGCN_GFX1150
Definition: ELF.h:776
@ EF_AMDGPU_MACH_R600_SUMO
Definition: ELF.h:725
@ EF_AMDGPU_MACH_R600_BARTS
Definition: ELF.h:727
@ EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
Definition: ELF.h:833
@ EF_AMDGPU_FEATURE_SRAMECC_ON_V4
Definition: ELF.h:837
@ EF_AMDGPU_MACH_AMDGCN_GFX702
Definition: ELF.h:745
@ STV_PROTECTED
Definition: ELF.h:1275
@ STV_DEFAULT
Definition: ELF.h:1272
@ SHN_AMDGPU_LDS
Definition: ELF.h:1758
@ SHF_ALLOC
Definition: ELF.h:1089
@ STT_AMDGPU_HSA_KERNEL
Definition: ELF.h:1268
@ STT_OBJECT
Definition: ELF.h:1255
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
void dumpAmdKernelCode(const amd_kernel_code_t *C, raw_ostream &OS, const char *tab)
AMD Kernel Code Object (amd_kernel_code_t).
In-memory representation of HSA metadata.
Instruction set architecture version.
Definition: TargetParser.h:114
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85