LLVM 17.0.0git
AMDGPUTargetStreamer.cpp
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1//===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AMDGPU specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
14#include "AMDGPUPTNote.h"
15#include "AMDKernelCodeT.h"
20#include "llvm/MC/MCAssembler.h"
21#include "llvm/MC/MCContext.h"
30
31using namespace llvm;
32using namespace llvm::AMDGPU;
33
34//===----------------------------------------------------------------------===//
35// AMDGPUTargetStreamer
36//===----------------------------------------------------------------------===//
37
38static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor,
39 uint32_t &Stepping, bool Sramecc, bool Xnack) {
40 if (Major == 9 && Minor == 0) {
41 switch (Stepping) {
42 case 0:
43 case 2:
44 case 4:
45 case 6:
46 if (Xnack)
47 Stepping++;
48 }
49 }
50}
51
53 HSAMD::Metadata HSAMetadata;
54 if (HSAMD::fromString(HSAMetadataString, HSAMetadata))
55 return false;
56 return EmitHSAMetadata(HSAMetadata);
57}
58
60 msgpack::Document HSAMetadataDoc;
61 if (!HSAMetadataDoc.fromYAML(HSAMetadataString))
62 return false;
63 return EmitHSAMetadata(HSAMetadataDoc, false);
64}
65
68
69 switch (ElfMach) {
70 default: llvm_unreachable("Unhandled ELF::EF_AMDGPU type");
71 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
72 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
82 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
125 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
126 }
127
128 StringRef GPUName = getArchNameAMDGCN(AK);
129 if (GPUName != "")
130 return GPUName;
131 return getArchNameR600(AK);
132}
133
136 if (AK == AMDGPU::GPUKind::GK_NONE)
137 AK = parseArchR600(GPU);
138
139 switch (AK) {
195 }
196
197 llvm_unreachable("unknown GPU");
198}
199
200//===----------------------------------------------------------------------===//
201// AMDGPUTargetAsmStreamer
202//===----------------------------------------------------------------------===//
203
206 : AMDGPUTargetStreamer(S), OS(OS) { }
207
208// A hook for emitting stuff at the end.
209// We use it for emitting the accumulated PAL metadata as directives.
210// The PAL metadata is reset after it is emitted.
212 std::string S;
214 OS << S;
215
216 // Reset the pal metadata so its data will not affect a compilation that
217 // reuses this object.
219}
220
222 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n";
223}
224
226 uint32_t Major, uint32_t Minor) {
227 OS << "\t.hsa_code_object_version " <<
228 Twine(Major) << "," << Twine(Minor) << '\n';
229}
230
231void
233 uint32_t Minor,
234 uint32_t Stepping,
235 StringRef VendorName,
236 StringRef ArchName) {
237 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
238 OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << ","
239 << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n";
240}
241
242void
244 OS << "\t.amd_kernel_code_t\n";
245 dumpAmdKernelCode(&Header, OS, "\t\t");
246 OS << "\t.end_amd_kernel_code_t\n";
247}
248
250 unsigned Type) {
251 switch (Type) {
252 default: llvm_unreachable("Invalid AMDGPU symbol type");
254 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
255 break;
256 }
257}
258
260 Align Alignment) {
261 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", "
262 << Alignment.value() << '\n';
263}
264
266 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n";
267 return true;
268}
269
271 const AMDGPU::HSAMD::Metadata &HSAMetadata) {
272 std::string HSAMetadataString;
273 if (HSAMD::toString(HSAMetadata, HSAMetadataString))
274 return false;
275
276 OS << '\t' << HSAMD::AssemblerDirectiveBegin << '\n';
277 OS << HSAMetadataString << '\n';
278 OS << '\t' << HSAMD::AssemblerDirectiveEnd << '\n';
279 return true;
280}
281
283 msgpack::Document &HSAMetadataDoc, bool Strict) {
285 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
286 return false;
287
288 std::string HSAMetadataString;
289 raw_string_ostream StrOS(HSAMetadataString);
290 HSAMetadataDoc.toYAML(StrOS);
291
292 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n';
293 OS << StrOS.str() << '\n';
294 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n';
295 return true;
296}
297
299 const uint32_t Encoded_s_code_end = 0xbf9f0000;
300 const uint32_t Encoded_s_nop = 0xbf800000;
301 uint32_t Encoded_pad = Encoded_s_code_end;
302
303 // Instruction cache line size in bytes.
304 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
305 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
306
307 // Extra padding amount in bytes to support prefetch mode 3.
308 unsigned FillSize = 3 * CacheLineSize;
309
310 if (AMDGPU::isGFX90A(STI)) {
311 Encoded_pad = Encoded_s_nop;
312 FillSize = 16 * CacheLineSize;
313 }
314
315 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n';
316 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n';
317 return true;
318}
319
321 const MCSubtargetInfo &STI, StringRef KernelName,
322 const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
323 bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) {
324 IsaVersion IVersion = getIsaVersion(STI.getCPU());
325
326 OS << "\t.amdhsa_kernel " << KernelName << '\n';
327
328#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME) \
329 STREAM << "\t\t" << DIRECTIVE << " " \
330 << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
331
332 OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
333 << '\n';
334 OS << "\t\t.amdhsa_private_segment_fixed_size "
335 << KD.private_segment_fixed_size << '\n';
336 OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n';
337
338 PRINT_FIELD(OS, ".amdhsa_user_sgpr_count", KD,
339 compute_pgm_rsrc2,
340 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT);
341
344 OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
345 kernel_code_properties,
346 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
347 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
348 kernel_code_properties,
349 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
350 PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
351 kernel_code_properties,
352 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
353 PRINT_FIELD(OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD,
354 kernel_code_properties,
355 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
356 PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_id", KD,
357 kernel_code_properties,
358 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
360 PRINT_FIELD(OS, ".amdhsa_user_sgpr_flat_scratch_init", KD,
361 kernel_code_properties,
362 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
363 PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_size", KD,
364 kernel_code_properties,
365 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
366 if (IVersion.Major >= 10)
367 PRINT_FIELD(OS, ".amdhsa_wavefront_size32", KD,
368 kernel_code_properties,
369 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
370 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5)
371 PRINT_FIELD(OS, ".amdhsa_uses_dynamic_stack", KD, kernel_code_properties,
372 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
373 PRINT_FIELD(OS,
375 ? ".amdhsa_enable_private_segment"
376 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"),
377 KD, compute_pgm_rsrc2,
378 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
379 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD,
380 compute_pgm_rsrc2,
381 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
382 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD,
383 compute_pgm_rsrc2,
384 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
385 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD,
386 compute_pgm_rsrc2,
387 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
388 PRINT_FIELD(OS, ".amdhsa_system_sgpr_workgroup_info", KD,
389 compute_pgm_rsrc2,
390 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
391 PRINT_FIELD(OS, ".amdhsa_system_vgpr_workitem_id", KD,
392 compute_pgm_rsrc2,
393 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
394
395 // These directives are required.
396 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
397 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
398
399 if (AMDGPU::isGFX90A(STI))
400 OS << "\t\t.amdhsa_accum_offset " <<
402 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4
403 << '\n';
404
405 if (!ReserveVCC)
406 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
407 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI))
408 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
409
410 switch (CodeObjectVersion) {
411 default:
412 break;
414 break;
418 if (getTargetID()->isXnackSupported())
419 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n';
420 break;
421 }
422
423 PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
424 compute_pgm_rsrc1,
425 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
426 PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
427 compute_pgm_rsrc1,
428 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
429 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,
430 compute_pgm_rsrc1,
431 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
432 PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_16_64", KD,
433 compute_pgm_rsrc1,
434 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
435 PRINT_FIELD(OS, ".amdhsa_dx10_clamp", KD,
436 compute_pgm_rsrc1,
437 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
438 PRINT_FIELD(OS, ".amdhsa_ieee_mode", KD,
439 compute_pgm_rsrc1,
440 amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
441 if (IVersion.Major >= 9)
442 PRINT_FIELD(OS, ".amdhsa_fp16_overflow", KD,
443 compute_pgm_rsrc1,
444 amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL);
445 if (AMDGPU::isGFX90A(STI))
446 PRINT_FIELD(OS, ".amdhsa_tg_split", KD,
447 compute_pgm_rsrc3,
448 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT);
449 if (IVersion.Major >= 10) {
450 PRINT_FIELD(OS, ".amdhsa_workgroup_processor_mode", KD,
451 compute_pgm_rsrc1,
452 amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE);
453 PRINT_FIELD(OS, ".amdhsa_memory_ordered", KD,
454 compute_pgm_rsrc1,
455 amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED);
456 PRINT_FIELD(OS, ".amdhsa_forward_progress", KD,
457 compute_pgm_rsrc1,
458 amdhsa::COMPUTE_PGM_RSRC1_FWD_PROGRESS);
459 PRINT_FIELD(OS, ".amdhsa_shared_vgpr_count", KD, compute_pgm_rsrc3,
460 amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT);
461 }
463 OS, ".amdhsa_exception_fp_ieee_invalid_op", KD,
464 compute_pgm_rsrc2,
465 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
466 PRINT_FIELD(OS, ".amdhsa_exception_fp_denorm_src", KD,
467 compute_pgm_rsrc2,
468 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
470 OS, ".amdhsa_exception_fp_ieee_div_zero", KD,
471 compute_pgm_rsrc2,
472 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
473 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_overflow", KD,
474 compute_pgm_rsrc2,
475 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
476 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_underflow", KD,
477 compute_pgm_rsrc2,
478 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
479 PRINT_FIELD(OS, ".amdhsa_exception_fp_ieee_inexact", KD,
480 compute_pgm_rsrc2,
481 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
482 PRINT_FIELD(OS, ".amdhsa_exception_int_div_zero", KD,
483 compute_pgm_rsrc2,
484 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
485#undef PRINT_FIELD
486
487 OS << "\t.end_amdhsa_kernel\n";
488}
489
490//===----------------------------------------------------------------------===//
491// AMDGPUTargetELFStreamer
492//===----------------------------------------------------------------------===//
493
495 const MCSubtargetInfo &STI)
496 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {}
497
499 return static_cast<MCELFStreamer &>(Streamer);
500}
501
502// A hook for emitting stuff at the end.
503// We use it for emitting the accumulated PAL metadata as a .note record.
504// The PAL metadata is reset after it is emitted.
507 MCA.setELFHeaderEFlags(getEFlags());
508
509 std::string Blob;
510 const char *Vendor = getPALMetadata()->getVendor();
511 unsigned Type = getPALMetadata()->getType();
512 getPALMetadata()->toBlob(Type, Blob);
513 if (Blob.empty())
514 return;
515 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
516 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); });
517
518 // Reset the pal metadata so its data will not affect a compilation that
519 // reuses this object.
521}
522
523void AMDGPUTargetELFStreamer::EmitNote(
524 StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
525 function_ref<void(MCELFStreamer &)> EmitDesc) {
526 auto &S = getStreamer();
527 auto &Context = S.getContext();
528
529 auto NameSZ = Name.size() + 1;
530
531 unsigned NoteFlags = 0;
532 // TODO Apparently, this is currently needed for OpenCL as mentioned in
533 // https://reviews.llvm.org/D74995
534 if (STI.getTargetTriple().getOS() == Triple::AMDHSA)
535 NoteFlags = ELF::SHF_ALLOC;
536
537 S.pushSection();
538 S.switchSection(
539 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
540 S.emitInt32(NameSZ); // namesz
541 S.emitValue(DescSZ, 4); // descz
542 S.emitInt32(NoteType); // type
543 S.emitBytes(Name); // name
544 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
545 EmitDesc(S); // desc
546 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
547 S.popSection();
548}
549
550unsigned AMDGPUTargetELFStreamer::getEFlags() {
551 switch (STI.getTargetTriple().getArch()) {
552 default:
553 llvm_unreachable("Unsupported Arch");
554 case Triple::r600:
555 return getEFlagsR600();
556 case Triple::amdgcn:
557 return getEFlagsAMDGCN();
558 }
559}
560
561unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
563
564 return getElfMach(STI.getCPU());
565}
566
567unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
569
570 switch (STI.getTargetTriple().getOS()) {
571 default:
572 // TODO: Why are some tests have "mingw" listed as OS?
573 // llvm_unreachable("Unsupported OS");
575 return getEFlagsUnknownOS();
576 case Triple::AMDHSA:
577 return getEFlagsAMDHSA();
578 case Triple::AMDPAL:
579 return getEFlagsAMDPAL();
580 case Triple::Mesa3D:
581 return getEFlagsMesa3D();
582 }
583}
584
585unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
586 // TODO: Why are some tests have "mingw" listed as OS?
587 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS);
588
589 return getEFlagsV3();
590}
591
592unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
594
595 if (std::optional<uint8_t> HsaAbiVer = getHsaAbiVersion(&STI)) {
596 switch (*HsaAbiVer) {
599 return getEFlagsV3();
602 return getEFlagsV4();
603 }
604 }
605
606 llvm_unreachable("HSA OS ABI Version identification must be defined");
607}
608
609unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
611
612 return getEFlagsV3();
613}
614
615unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
617
618 return getEFlagsV3();
619}
620
621unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
622 unsigned EFlagsV3 = 0;
623
624 // mach.
625 EFlagsV3 |= getElfMach(STI.getCPU());
626
627 // xnack.
628 if (getTargetID()->isXnackOnOrAny())
630 // sramecc.
631 if (getTargetID()->isSramEccOnOrAny())
633
634 return EFlagsV3;
635}
636
637unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
638 unsigned EFlagsV4 = 0;
639
640 // mach.
641 EFlagsV4 |= getElfMach(STI.getCPU());
642
643 // xnack.
644 switch (getTargetID()->getXnackSetting()) {
647 break;
650 break;
653 break;
656 break;
657 }
658 // sramecc.
659 switch (getTargetID()->getSramEccSetting()) {
662 break;
665 break;
668 break;
671 break;
672 }
673
674 return EFlagsV4;
675}
676
678
680 uint32_t Major, uint32_t Minor) {
681
684 OS.emitInt32(Major);
685 OS.emitInt32(Minor);
686 });
687}
688
689void
691 uint32_t Minor,
692 uint32_t Stepping,
693 StringRef VendorName,
694 StringRef ArchName) {
695 uint16_t VendorNameSize = VendorName.size() + 1;
696 uint16_t ArchNameSize = ArchName.size() + 1;
697
698 unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
699 sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
700 VendorNameSize + ArchNameSize;
701
702 convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
705 OS.emitInt16(VendorNameSize);
706 OS.emitInt16(ArchNameSize);
707 OS.emitInt32(Major);
708 OS.emitInt32(Minor);
709 OS.emitInt32(Stepping);
710 OS.emitBytes(VendorName);
711 OS.emitInt8(0); // NULL terminate VendorName
712 OS.emitBytes(ArchName);
713 OS.emitInt8(0); // NULL terminate ArchName
714 });
715}
716
717void
719
721 OS.pushSection();
722 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header)));
723 OS.popSection();
724}
725
727 unsigned Type) {
728 MCSymbolELF *Symbol = cast<MCSymbolELF>(
729 getStreamer().getContext().getOrCreateSymbol(SymbolName));
730 Symbol->setType(Type);
731}
732
734 Align Alignment) {
735 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol);
736 SymbolELF->setType(ELF::STT_OBJECT);
737
738 if (!SymbolELF->isBindingSet()) {
739 SymbolELF->setBinding(ELF::STB_GLOBAL);
740 SymbolELF->setExternal(true);
741 }
742
743 if (SymbolELF->declareCommon(Size, Alignment, true)) {
744 report_fatal_error("Symbol: " + Symbol->getName() +
745 " redeclared as different type");
746 }
747
748 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS);
750}
751
753 // Create two labels to mark the beginning and end of the desc field
754 // and a MCExpr to calculate the size of the desc field.
755 auto &Context = getContext();
756 auto *DescBegin = Context.createTempSymbol();
757 auto *DescEnd = Context.createTempSymbol();
758 auto *DescSZ = MCBinaryExpr::createSub(
761
763 [&](MCELFStreamer &OS) {
764 OS.emitLabel(DescBegin);
765 OS.emitBytes(getTargetID()->toString());
766 OS.emitLabel(DescEnd);
767 });
768 return true;
769}
770
772 bool Strict) {
774 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
775 return false;
776
777 std::string HSAMetadataString;
778 HSAMetadataDoc.writeToBlob(HSAMetadataString);
779
780 // Create two labels to mark the beginning and end of the desc field
781 // and a MCExpr to calculate the size of the desc field.
782 auto &Context = getContext();
783 auto *DescBegin = Context.createTempSymbol();
784 auto *DescEnd = Context.createTempSymbol();
785 auto *DescSZ = MCBinaryExpr::createSub(
788
790 [&](MCELFStreamer &OS) {
791 OS.emitLabel(DescBegin);
792 OS.emitBytes(HSAMetadataString);
793 OS.emitLabel(DescEnd);
794 });
795 return true;
796}
797
799 const AMDGPU::HSAMD::Metadata &HSAMetadata) {
800 std::string HSAMetadataString;
801 if (HSAMD::toString(HSAMetadata, HSAMetadataString))
802 return false;
803
804 // Create two labels to mark the beginning and end of the desc field
805 // and a MCExpr to calculate the size of the desc field.
806 auto &Context = getContext();
807 auto *DescBegin = Context.createTempSymbol();
808 auto *DescEnd = Context.createTempSymbol();
809 auto *DescSZ = MCBinaryExpr::createSub(
812
814 [&](MCELFStreamer &OS) {
815 OS.emitLabel(DescBegin);
816 OS.emitBytes(HSAMetadataString);
817 OS.emitLabel(DescEnd);
818 });
819 return true;
820}
821
823 const uint32_t Encoded_s_code_end = 0xbf9f0000;
824 const uint32_t Encoded_s_nop = 0xbf800000;
825 uint32_t Encoded_pad = Encoded_s_code_end;
826
827 // Instruction cache line size in bytes.
828 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
829 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
830
831 // Extra padding amount in bytes to support prefetch mode 3.
832 unsigned FillSize = 3 * CacheLineSize;
833
834 if (AMDGPU::isGFX90A(STI)) {
835 Encoded_pad = Encoded_s_nop;
836 FillSize = 16 * CacheLineSize;
837 }
838
840 OS.pushSection();
841 OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4);
842 for (unsigned I = 0; I < FillSize; I += 4)
843 OS.emitInt32(Encoded_pad);
844 OS.popSection();
845 return true;
846}
847
849 const MCSubtargetInfo &STI, StringRef KernelName,
850 const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
851 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
852 unsigned CodeObjectVersion) {
853 auto &Streamer = getStreamer();
854 auto &Context = Streamer.getContext();
855
856 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
857 Context.getOrCreateSymbol(Twine(KernelName)));
858 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
859 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
860
861 // Copy kernel descriptor symbol's binding, other and visibility from the
862 // kernel code symbol.
863 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding());
864 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther());
865 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility());
866 // Kernel descriptor symbol's type and size are fixed.
867 KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
868 KernelDescriptorSymbol->setSize(
869 MCConstantExpr::create(sizeof(KernelDescriptor), Context));
870
871 // The visibility of the kernel code symbol must be protected or less to allow
872 // static relocations from the kernel descriptor to be used.
873 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT)
874 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED);
875
876 Streamer.emitLabel(KernelDescriptorSymbol);
877 Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size);
878 Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size);
879 Streamer.emitInt32(KernelDescriptor.kernarg_size);
880
881 for (uint8_t Res : KernelDescriptor.reserved0)
882 Streamer.emitInt8(Res);
883
884 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
885 // expression being created is:
886 // (start of kernel code) - (start of kernel descriptor)
887 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
890 KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
892 KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context),
893 Context),
894 sizeof(KernelDescriptor.kernel_code_entry_byte_offset));
895 for (uint8_t Res : KernelDescriptor.reserved1)
896 Streamer.emitInt8(Res);
897 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3);
898 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1);
899 Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2);
900 Streamer.emitInt16(KernelDescriptor.kernel_code_properties);
901 for (uint8_t Res : KernelDescriptor.reserved2)
902 Streamer.emitInt8(Res);
903}
This is a verifier for AMDGPU HSA metadata, which can verify both well-typed metadata and untyped met...
AMDGPU metadata definitions and in-memory representations.
Enums and constants for AMDGPU PT_NOTE sections.
#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME)
static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor, uint32_t &Stepping, bool Sramecc, bool Xnack)
AMDHSA kernel descriptor definitions.
#define AMDHSA_BITS_GET(SRC, MSK)
std::string Name
uint64_t Size
#define I(x, y, z)
Definition: MD5.cpp:58
LLVMContext & Context
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
verify safepoint Safepoint IR Verifier
raw_pwrite_stream & OS
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
const char * getVendor() const
void toBlob(unsigned Type, std::string &S)
void toString(std::string &S)
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) override
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
void EmitDirectiveHSACodeObjectVersion(uint32_t Major, uint32_t Minor) override
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor, uint32_t Stepping, StringRef VendorName, StringRef ArchName) override
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr, unsigned CodeObjectVersion) override
virtual bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict)
Emit HSA Metadata.
AMDGPUPALMetadata * getPALMetadata()
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
static unsigned getElfMach(StringRef GPU)
MCContext & getContext() const
static StringRef getArchNameFromElfMach(unsigned ElfMach)
const std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > & getTargetID() const
std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > TargetID
virtual bool EmitHSAMetadataV2(StringRef HSAMetadataString)
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:277
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:610
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
MCAssembler & getAssembler()
Streaming machine code generation interface.
Definition: MCStreamer.h:212
MCContext & getContext() const
Definition: MCStreamer.h:297
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:180
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:423
void emitInt16(uint64_t Value)
Definition: MCStreamer.h:747
void emitInt32(uint64_t Value)
Definition: MCStreamer.h:748
void emitInt8(uint64_t Value)
Definition: MCStreamer.h:746
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
StringRef getCPU() const
unsigned getOther() const
void setVisibility(unsigned Visibility)
void setSize(const MCExpr *SS)
Definition: MCSymbolELF.h:22
bool isBindingSet() const
void setBinding(unsigned Binding) const
Definition: MCSymbolELF.cpp:43
unsigned getVisibility() const
unsigned getBinding() const
Definition: MCSymbolELF.cpp:66
void setType(unsigned Type) const
Definition: MCSymbolELF.cpp:94
void setOther(unsigned Other)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:41
void setExternal(bool Value) const
Definition: MCSymbol.h:405
void setIndex(uint32_t Value) const
Set the (implementation defined) index.
Definition: MCSymbol.h:319
bool declareCommon(uint64_t Size, Align Alignment, bool Target=false)
Declare this symbol as being 'common'.
Definition: MCSymbol.h:373
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:365
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:356
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
An efficient, type-erasing, non-owning reference to a callable.
Simple in-memory representation of a document of msgpack objects with ability to find and create arra...
DocNode & getRoot()
Get ref to the document's root element.
void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:642
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:660
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const char NoteNameV2[]
Definition: AMDGPUPTNote.h:26
const char SectionName[]
Definition: AMDGPUPTNote.h:24
const char NoteNameV3[]
Definition: AMDGPUPTNote.h:27
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
std::error_code fromString(StringRef String, Metadata &HSAMetadata)
Converts String to HSAMetadata.
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
std::error_code toString(Metadata HSAMetadata, std::string &String)
Converts HSAMetadata to String.
StringRef getArchNameR600(GPUKind AK)
GPUKind
GPU kinds supported by the AMDGPU target.
Definition: TargetParser.h:35
IsaVersion getIsaVersion(StringRef GPU)
bool isGFX90A(const MCSubtargetInfo &STI)
GPUKind parseArchAMDGCN(StringRef CPU)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
StringRef getArchNameAMDGCN(GPUKind AK)
std::optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
GPUKind parseArchR600(StringRef CPU)
@ SHF_ALLOC
Definition: ELF.h:1083
@ SHN_AMDGPU_LDS
Definition: ELF.h:1748
@ STV_PROTECTED
Definition: ELF.h:1269
@ STV_DEFAULT
Definition: ELF.h:1266
@ NT_AMD_HSA_ISA_NAME
Definition: ELF.h:1758
@ NT_AMD_HSA_ISA_VERSION
Definition: ELF.h:1755
@ NT_AMD_HSA_CODE_OBJECT_VERSION
Definition: ELF.h:1753
@ NT_AMD_HSA_METADATA
Definition: ELF.h:1757
@ ELFABIVERSION_AMDGPU_HSA_V4
Definition: ELF.h:376
@ ELFABIVERSION_AMDGPU_HSA_V5
Definition: ELF.h:377
@ ELFABIVERSION_AMDGPU_HSA_V3
Definition: ELF.h:375
@ ELFABIVERSION_AMDGPU_HSA_V2
Definition: ELF.h:374
@ SHT_NOTE
Definition: ELF.h:1001
@ EF_AMDGPU_FEATURE_XNACK_ANY_V4
Definition: ELF.h:815
@ EF_AMDGPU_MACH_AMDGCN_GFX703
Definition: ELF.h:746
@ EF_AMDGPU_MACH_AMDGCN_GFX1035
Definition: ELF.h:770
@ EF_AMDGPU_FEATURE_SRAMECC_V3
Definition: ELF.h:806
@ EF_AMDGPU_MACH_AMDGCN_GFX1031
Definition: ELF.h:764
@ EF_AMDGPU_MACH_R600_CAYMAN
Definition: ELF.h:729
@ EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
Definition: ELF.h:826
@ EF_AMDGPU_MACH_AMDGCN_GFX704
Definition: ELF.h:747
@ EF_AMDGPU_MACH_AMDGCN_GFX902
Definition: ELF.h:754
@ EF_AMDGPU_MACH_AMDGCN_GFX810
Definition: ELF.h:752
@ EF_AMDGPU_MACH_AMDGCN_GFX1036
Definition: ELF.h:778
@ EF_AMDGPU_MACH_AMDGCN_GFX1102
Definition: ELF.h:780
@ EF_AMDGPU_MACH_R600_RV730
Definition: ELF.h:718
@ EF_AMDGPU_MACH_R600_RV710
Definition: ELF.h:717
@ EF_AMDGPU_MACH_AMDGCN_GFX908
Definition: ELF.h:757
@ EF_AMDGPU_MACH_AMDGCN_GFX1011
Definition: ELF.h:761
@ EF_AMDGPU_MACH_R600_CYPRESS
Definition: ELF.h:722
@ EF_AMDGPU_MACH_AMDGCN_GFX1032
Definition: ELF.h:765
@ EF_AMDGPU_MACH_R600_R600
Definition: ELF.h:712
@ EF_AMDGPU_MACH_AMDGCN_GFX940
Definition: ELF.h:773
@ EF_AMDGPU_MACH_R600_TURKS
Definition: ELF.h:730
@ EF_AMDGPU_MACH_R600_JUNIPER
Definition: ELF.h:723
@ EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
Definition: ELF.h:830
@ EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
Definition: ELF.h:813
@ EF_AMDGPU_MACH_AMDGCN_GFX601
Definition: ELF.h:742
@ EF_AMDGPU_MACH_R600_R630
Definition: ELF.h:713
@ EF_AMDGPU_MACH_R600_REDWOOD
Definition: ELF.h:724
@ EF_AMDGPU_MACH_R600_RV770
Definition: ELF.h:719
@ EF_AMDGPU_FEATURE_XNACK_OFF_V4
Definition: ELF.h:817
@ EF_AMDGPU_MACH_AMDGCN_GFX600
Definition: ELF.h:741
@ EF_AMDGPU_FEATURE_XNACK_V3
Definition: ELF.h:801
@ EF_AMDGPU_MACH_AMDGCN_GFX602
Definition: ELF.h:767
@ EF_AMDGPU_MACH_AMDGCN_GFX1101
Definition: ELF.h:779
@ EF_AMDGPU_MACH_AMDGCN_GFX1100
Definition: ELF.h:774
@ EF_AMDGPU_MACH_AMDGCN_GFX1033
Definition: ELF.h:766
@ EF_AMDGPU_MACH_AMDGCN_GFX801
Definition: ELF.h:749
@ EF_AMDGPU_MACH_AMDGCN_GFX705
Definition: ELF.h:768
@ EF_AMDGPU_MACH_AMDGCN_GFX1010
Definition: ELF.h:760
@ EF_AMDGPU_MACH_R600_RV670
Definition: ELF.h:715
@ EF_AMDGPU_MACH_AMDGCN_GFX701
Definition: ELF.h:744
@ EF_AMDGPU_MACH_AMDGCN_GFX1012
Definition: ELF.h:762
@ EF_AMDGPU_MACH_AMDGCN_GFX1030
Definition: ELF.h:763
@ EF_AMDGPU_MACH_R600_CEDAR
Definition: ELF.h:721
@ EF_AMDGPU_MACH_AMDGCN_GFX700
Definition: ELF.h:743
@ EF_AMDGPU_MACH_AMDGCN_GFX803
Definition: ELF.h:751
@ EF_AMDGPU_MACH_AMDGCN_GFX802
Definition: ELF.h:750
@ EF_AMDGPU_MACH_AMDGCN_GFX90C
Definition: ELF.h:759
@ EF_AMDGPU_FEATURE_XNACK_ON_V4
Definition: ELF.h:819
@ EF_AMDGPU_MACH_AMDGCN_GFX900
Definition: ELF.h:753
@ EF_AMDGPU_MACH_AMDGCN_GFX909
Definition: ELF.h:758
@ EF_AMDGPU_MACH_AMDGCN_GFX906
Definition: ELF.h:756
@ EF_AMDGPU_MACH_NONE
Definition: ELF.h:707
@ EF_AMDGPU_MACH_AMDGCN_GFX1103
Definition: ELF.h:777
@ EF_AMDGPU_MACH_R600_CAICOS
Definition: ELF.h:728
@ EF_AMDGPU_MACH_AMDGCN_GFX90A
Definition: ELF.h:772
@ EF_AMDGPU_MACH_AMDGCN_GFX1034
Definition: ELF.h:771
@ EF_AMDGPU_MACH_AMDGCN_GFX1013
Definition: ELF.h:775
@ EF_AMDGPU_MACH_AMDGCN_GFX904
Definition: ELF.h:755
@ EF_AMDGPU_MACH_R600_RS880
Definition: ELF.h:714
@ EF_AMDGPU_MACH_AMDGCN_GFX805
Definition: ELF.h:769
@ EF_AMDGPU_MACH_R600_SUMO
Definition: ELF.h:725
@ EF_AMDGPU_MACH_R600_BARTS
Definition: ELF.h:727
@ EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
Definition: ELF.h:828
@ EF_AMDGPU_FEATURE_SRAMECC_ON_V4
Definition: ELF.h:832
@ EF_AMDGPU_MACH_AMDGCN_GFX702
Definition: ELF.h:745
@ STB_GLOBAL
Definition: ELF.h:1237
@ NT_AMDGPU_METADATA
Definition: ELF.h:1765
@ STT_AMDGPU_HSA_KERNEL
Definition: ELF.h:1262
@ STT_OBJECT
Definition: ELF.h:1249
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
void dumpAmdKernelCode(const amd_kernel_code_t *C, raw_ostream &OS, const char *tab)
AMD Kernel Code Object (amd_kernel_code_t).
In-memory representation of HSA metadata.
Instruction set architecture version.
Definition: TargetParser.h:110
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85