LLVM 19.0.0git
AMDGPUTargetStreamer.cpp
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1//===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AMDGPU specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
15#include "AMDGPUPTNote.h"
20#include "llvm/MC/MCAssembler.h"
21#include "llvm/MC/MCContext.h"
32
33using namespace llvm;
34using namespace llvm::AMDGPU;
35
36//===----------------------------------------------------------------------===//
37// AMDGPUTargetStreamer
38//===----------------------------------------------------------------------===//
39
41 ForceGenericVersion("amdgpu-force-generic-version",
42 cl::desc("Force a specific generic_v<N> flag to be "
43 "added. For testing purposes only."),
45
47 msgpack::Document HSAMetadataDoc;
48 if (!HSAMetadataDoc.fromYAML(HSAMetadataString))
49 return false;
50 return EmitHSAMetadata(HSAMetadataDoc, false);
51}
52
55
56 // clang-format off
57 switch (ElfMach) {
58 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
59 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
69 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
124 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
125 default: AK = GK_NONE; break;
126 }
127 // clang-format on
128
129 StringRef GPUName = getArchNameAMDGCN(AK);
130 if (GPUName != "")
131 return GPUName;
132 return getArchNameR600(AK);
133}
134
137 if (AK == AMDGPU::GPUKind::GK_NONE)
138 AK = parseArchR600(GPU);
139
140 // clang-format off
141 switch (AK) {
209 }
210 // clang-format on
211
212 llvm_unreachable("unknown GPU");
213}
214
215//===----------------------------------------------------------------------===//
216// AMDGPUTargetAsmStreamer
217//===----------------------------------------------------------------------===//
218
221 : AMDGPUTargetStreamer(S), OS(OS) { }
222
223// A hook for emitting stuff at the end.
224// We use it for emitting the accumulated PAL metadata as directives.
225// The PAL metadata is reset after it is emitted.
227 std::string S;
229 OS << S;
230
231 // Reset the pal metadata so its data will not affect a compilation that
232 // reuses this object.
234}
235
237 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n";
238}
239
241 unsigned COV) {
243 OS << "\t.amdhsa_code_object_version " << COV << '\n';
244}
245
247 OS << "\t.amd_kernel_code_t\n";
248 Header.EmitKernelCodeT(OS, getContext());
249 OS << "\t.end_amd_kernel_code_t\n";
250}
251
253 unsigned Type) {
254 switch (Type) {
255 default: llvm_unreachable("Invalid AMDGPU symbol type");
257 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
258 break;
259 }
260}
261
263 Align Alignment) {
264 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", "
265 << Alignment.value() << '\n';
266}
267
269 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n";
270 return true;
271}
272
274 msgpack::Document &HSAMetadataDoc, bool Strict) {
276 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
277 return false;
278
279 std::string HSAMetadataString;
280 raw_string_ostream StrOS(HSAMetadataString);
281 HSAMetadataDoc.toYAML(StrOS);
282
283 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n';
284 OS << StrOS.str() << '\n';
285 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n';
286 return true;
287}
288
290 const MCSubtargetInfo &STI, bool TrapEnabled) {
291 OS << (TrapEnabled ? "\ts_trap 2" : "\ts_endpgm")
292 << " ; Kernarg preload header. Trap with incompatible firmware that "
293 "doesn't support preloading kernel arguments.\n";
294 OS << "\t.fill 63, 4, 0xbf800000 ; s_nop 0\n";
295 return true;
296}
297
299 const uint32_t Encoded_s_code_end = 0xbf9f0000;
300 const uint32_t Encoded_s_nop = 0xbf800000;
301 uint32_t Encoded_pad = Encoded_s_code_end;
302
303 // Instruction cache line size in bytes.
304 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
305 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
306
307 // Extra padding amount in bytes to support prefetch mode 3.
308 unsigned FillSize = 3 * CacheLineSize;
309
310 if (AMDGPU::isGFX90A(STI)) {
311 Encoded_pad = Encoded_s_nop;
312 FillSize = 16 * CacheLineSize;
313 }
314
315 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n';
316 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n';
317 return true;
318}
319
321 const MCSubtargetInfo &STI, StringRef KernelName,
322 const MCKernelDescriptor &KD, uint64_t NextVGPR, uint64_t NextSGPR,
323 bool ReserveVCC, bool ReserveFlatScr) {
324 IsaVersion IVersion = getIsaVersion(STI.getCPU());
325 const MCAsmInfo *MAI = getContext().getAsmInfo();
326
327 OS << "\t.amdhsa_kernel " << KernelName << '\n';
328
329 auto PrintField = [&](const MCExpr *Expr, uint32_t Shift, uint32_t Mask,
331 int64_t IVal;
332 OS << "\t\t" << Directive << ' ';
333 const MCExpr *pgm_rsrc1_bits =
334 MCKernelDescriptor::bits_get(Expr, Shift, Mask, getContext());
335 if (pgm_rsrc1_bits->evaluateAsAbsolute(IVal))
336 OS << static_cast<uint64_t>(IVal);
337 else
338 pgm_rsrc1_bits->print(OS, MAI);
339 OS << '\n';
340 };
341
342 OS << "\t\t.amdhsa_group_segment_fixed_size ";
343 KD.group_segment_fixed_size->print(OS, MAI);
344 OS << '\n';
345
346 OS << "\t\t.amdhsa_private_segment_fixed_size ";
348 OS << '\n';
349
350 OS << "\t\t.amdhsa_kernarg_size ";
351 KD.kernarg_size->print(OS, MAI);
352 OS << '\n';
353
355 KD.compute_pgm_rsrc2, amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT_SHIFT,
356 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT, ".amdhsa_user_sgpr_count");
357
361 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT,
362 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,
363 ".amdhsa_user_sgpr_private_segment_buffer");
365 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_SHIFT,
366 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR,
367 ".amdhsa_user_sgpr_dispatch_ptr");
369 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_SHIFT,
370 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR,
371 ".amdhsa_user_sgpr_queue_ptr");
373 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT,
374 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR,
375 ".amdhsa_user_sgpr_kernarg_segment_ptr");
377 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_SHIFT,
378 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID,
379 ".amdhsa_user_sgpr_dispatch_id");
382 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT,
383 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT,
384 ".amdhsa_user_sgpr_flat_scratch_init");
385 if (hasKernargPreload(STI)) {
386 PrintField(KD.kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_LENGTH_SHIFT,
387 amdhsa::KERNARG_PRELOAD_SPEC_LENGTH,
388 ".amdhsa_user_sgpr_kernarg_preload_length");
389 PrintField(KD.kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_OFFSET_SHIFT,
390 amdhsa::KERNARG_PRELOAD_SPEC_OFFSET,
391 ".amdhsa_user_sgpr_kernarg_preload_offset");
392 }
395 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT,
396 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE,
397 ".amdhsa_user_sgpr_private_segment_size");
398 if (IVersion.Major >= 10)
400 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT,
401 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
402 ".amdhsa_wavefront_size32");
405 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK_SHIFT,
406 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK,
407 ".amdhsa_uses_dynamic_stack");
409 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT_SHIFT,
410 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT,
412 ? ".amdhsa_enable_private_segment"
413 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"));
415 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT,
416 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X,
417 ".amdhsa_system_sgpr_workgroup_id_x");
419 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT,
420 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y,
421 ".amdhsa_system_sgpr_workgroup_id_y");
423 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT,
424 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z,
425 ".amdhsa_system_sgpr_workgroup_id_z");
427 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO_SHIFT,
428 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO,
429 ".amdhsa_system_sgpr_workgroup_info");
431 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID_SHIFT,
432 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID,
433 ".amdhsa_system_vgpr_workitem_id");
434
435 // These directives are required.
436 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
437 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
438
439 if (AMDGPU::isGFX90A(STI)) {
440 // MCExpr equivalent of taking the (accum_offset + 1) * 4.
441 const MCExpr *accum_bits = MCKernelDescriptor::bits_get(
443 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET_SHIFT,
444 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET, getContext());
445 accum_bits = MCBinaryExpr::createAdd(
446 accum_bits, MCConstantExpr::create(1, getContext()), getContext());
447 accum_bits = MCBinaryExpr::createMul(
448 accum_bits, MCConstantExpr::create(4, getContext()), getContext());
449 OS << "\t\t.amdhsa_accum_offset ";
450 int64_t IVal;
451 if (accum_bits->evaluateAsAbsolute(IVal)) {
452 OS << static_cast<uint64_t>(IVal);
453 } else {
454 accum_bits->print(OS, MAI);
455 }
456 OS << '\n';
457 }
458
459 if (!ReserveVCC)
460 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
461 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI))
462 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
463
464 switch (CodeObjectVersion) {
465 default:
466 break;
469 if (getTargetID()->isXnackSupported())
470 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n';
471 break;
472 }
473
475 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32_SHIFT,
476 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32,
477 ".amdhsa_float_round_mode_32");
479 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64_SHIFT,
480 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64,
481 ".amdhsa_float_round_mode_16_64");
483 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32_SHIFT,
484 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32,
485 ".amdhsa_float_denorm_mode_32");
487 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64_SHIFT,
488 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
489 ".amdhsa_float_denorm_mode_16_64");
490 if (IVersion.Major < 12) {
492 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP_SHIFT,
493 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP,
494 ".amdhsa_dx10_clamp");
496 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE_SHIFT,
497 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE,
498 ".amdhsa_ieee_mode");
499 }
500 if (IVersion.Major >= 9) {
502 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL_SHIFT,
503 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL,
504 ".amdhsa_fp16_overflow");
505 }
506 if (AMDGPU::isGFX90A(STI))
508 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,
509 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, ".amdhsa_tg_split");
510 if (IVersion.Major >= 10) {
512 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE_SHIFT,
513 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE,
514 ".amdhsa_workgroup_processor_mode");
516 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED_SHIFT,
517 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED,
518 ".amdhsa_memory_ordered");
520 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS_SHIFT,
521 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS,
522 ".amdhsa_forward_progress");
523 }
524 if (IVersion.Major >= 10 && IVersion.Major < 12) {
526 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT_SHIFT,
527 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT,
528 ".amdhsa_shared_vgpr_count");
529 }
530 if (IVersion.Major >= 12) {
532 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN_SHIFT,
533 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN,
534 ".amdhsa_round_robin_scheduling");
535 }
538 amdhsa::
539 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT,
540 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION,
541 ".amdhsa_exception_fp_ieee_invalid_op");
544 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT,
545 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE,
546 ".amdhsa_exception_fp_denorm_src");
549 amdhsa::
550 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT,
551 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO,
552 ".amdhsa_exception_fp_ieee_div_zero");
555 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT,
556 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW,
557 ".amdhsa_exception_fp_ieee_overflow");
560 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT,
561 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW,
562 ".amdhsa_exception_fp_ieee_underflow");
565 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT,
566 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT,
567 ".amdhsa_exception_fp_ieee_inexact");
570 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO_SHIFT,
571 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,
572 ".amdhsa_exception_int_div_zero");
573
574 OS << "\t.end_amdhsa_kernel\n";
575}
576
577//===----------------------------------------------------------------------===//
578// AMDGPUTargetELFStreamer
579//===----------------------------------------------------------------------===//
580
582 const MCSubtargetInfo &STI)
583 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {}
584
586 return static_cast<MCELFStreamer &>(Streamer);
587}
588
589// A hook for emitting stuff at the end.
590// We use it for emitting the accumulated PAL metadata as a .note record.
591// The PAL metadata is reset after it is emitted.
594 MCA.setELFHeaderEFlags(getEFlags());
597
598 std::string Blob;
599 const char *Vendor = getPALMetadata()->getVendor();
600 unsigned Type = getPALMetadata()->getType();
601 getPALMetadata()->toBlob(Type, Blob);
602 if (Blob.empty())
603 return;
604 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
605 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); });
606
607 // Reset the pal metadata so its data will not affect a compilation that
608 // reuses this object.
610}
611
612void AMDGPUTargetELFStreamer::EmitNote(
613 StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
614 function_ref<void(MCELFStreamer &)> EmitDesc) {
615 auto &S = getStreamer();
616 auto &Context = S.getContext();
617
618 auto NameSZ = Name.size() + 1;
619
620 unsigned NoteFlags = 0;
621 // TODO Apparently, this is currently needed for OpenCL as mentioned in
622 // https://reviews.llvm.org/D74995
623 if (isHsaAbi(STI))
624 NoteFlags = ELF::SHF_ALLOC;
625
626 S.pushSection();
627 S.switchSection(
628 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
629 S.emitInt32(NameSZ); // namesz
630 S.emitValue(DescSZ, 4); // descz
631 S.emitInt32(NoteType); // type
632 S.emitBytes(Name); // name
633 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
634 EmitDesc(S); // desc
635 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
636 S.popSection();
637}
638
639unsigned AMDGPUTargetELFStreamer::getEFlags() {
640 switch (STI.getTargetTriple().getArch()) {
641 default:
642 llvm_unreachable("Unsupported Arch");
643 case Triple::r600:
644 return getEFlagsR600();
645 case Triple::amdgcn:
646 return getEFlagsAMDGCN();
647 }
648}
649
650unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
652
653 return getElfMach(STI.getCPU());
654}
655
656unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
658
659 switch (STI.getTargetTriple().getOS()) {
660 default:
661 // TODO: Why are some tests have "mingw" listed as OS?
662 // llvm_unreachable("Unsupported OS");
664 return getEFlagsUnknownOS();
665 case Triple::AMDHSA:
666 return getEFlagsAMDHSA();
667 case Triple::AMDPAL:
668 return getEFlagsAMDPAL();
669 case Triple::Mesa3D:
670 return getEFlagsMesa3D();
671 }
672}
673
674unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
675 // TODO: Why are some tests have "mingw" listed as OS?
676 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS);
677
678 return getEFlagsV3();
679}
680
681unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
682 assert(isHsaAbi(STI));
683
684 if (CodeObjectVersion >= 6)
685 return getEFlagsV6();
686 return getEFlagsV4();
687}
688
689unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
691
692 return getEFlagsV3();
693}
694
695unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
697
698 return getEFlagsV3();
699}
700
701unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
702 unsigned EFlagsV3 = 0;
703
704 // mach.
705 EFlagsV3 |= getElfMach(STI.getCPU());
706
707 // xnack.
708 if (getTargetID()->isXnackOnOrAny())
710 // sramecc.
711 if (getTargetID()->isSramEccOnOrAny())
713
714 return EFlagsV3;
715}
716
717unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
718 unsigned EFlagsV4 = 0;
719
720 // mach.
721 EFlagsV4 |= getElfMach(STI.getCPU());
722
723 // xnack.
724 switch (getTargetID()->getXnackSetting()) {
727 break;
730 break;
733 break;
736 break;
737 }
738 // sramecc.
739 switch (getTargetID()->getSramEccSetting()) {
742 break;
745 break;
748 break;
751 break;
752 }
753
754 return EFlagsV4;
755}
756
757unsigned AMDGPUTargetELFStreamer::getEFlagsV6() {
758 unsigned Flags = getEFlagsV4();
759
760 unsigned Version = ForceGenericVersion;
761 if (!Version) {
762 switch (parseArchAMDGCN(STI.getCPU())) {
765 break;
768 break;
771 break;
774 break;
777 break;
778 default:
779 break;
780 }
781 }
782
783 // Versions start at 1.
784 if (Version) {
786 report_fatal_error("Cannot encode generic code object version " +
787 Twine(Version) +
788 " - no ELF flag can represent this version!");
790 }
791
792 return Flags;
793}
794
796
799 OS.pushSection();
800 Header.EmitKernelCodeT(OS, getContext());
801 OS.popSection();
802}
803
805 unsigned Type) {
806 MCSymbolELF *Symbol = cast<MCSymbolELF>(
807 getStreamer().getContext().getOrCreateSymbol(SymbolName));
808 Symbol->setType(Type);
809}
810
812 Align Alignment) {
813 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol);
814 SymbolELF->setType(ELF::STT_OBJECT);
815
816 if (!SymbolELF->isBindingSet()) {
817 SymbolELF->setBinding(ELF::STB_GLOBAL);
818 SymbolELF->setExternal(true);
819 }
820
821 if (SymbolELF->declareCommon(Size, Alignment, true)) {
822 report_fatal_error("Symbol: " + Symbol->getName() +
823 " redeclared as different type");
824 }
825
826 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS);
828}
829
831 // Create two labels to mark the beginning and end of the desc field
832 // and a MCExpr to calculate the size of the desc field.
833 auto &Context = getContext();
834 auto *DescBegin = Context.createTempSymbol();
835 auto *DescEnd = Context.createTempSymbol();
836 auto *DescSZ = MCBinaryExpr::createSub(
837 MCSymbolRefExpr::create(DescEnd, Context),
838 MCSymbolRefExpr::create(DescBegin, Context), Context);
839
841 [&](MCELFStreamer &OS) {
842 OS.emitLabel(DescBegin);
843 OS.emitBytes(getTargetID()->toString());
844 OS.emitLabel(DescEnd);
845 });
846 return true;
847}
848
850 bool Strict) {
852 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
853 return false;
854
855 std::string HSAMetadataString;
856 HSAMetadataDoc.writeToBlob(HSAMetadataString);
857
858 // Create two labels to mark the beginning and end of the desc field
859 // and a MCExpr to calculate the size of the desc field.
860 auto &Context = getContext();
861 auto *DescBegin = Context.createTempSymbol();
862 auto *DescEnd = Context.createTempSymbol();
863 auto *DescSZ = MCBinaryExpr::createSub(
864 MCSymbolRefExpr::create(DescEnd, Context),
865 MCSymbolRefExpr::create(DescBegin, Context), Context);
866
868 [&](MCELFStreamer &OS) {
869 OS.emitLabel(DescBegin);
870 OS.emitBytes(HSAMetadataString);
871 OS.emitLabel(DescEnd);
872 });
873 return true;
874}
875
877 const MCSubtargetInfo &STI, bool TrapEnabled) {
878 const uint32_t Encoded_s_nop = 0xbf800000;
879 const uint32_t Encoded_s_trap = 0xbf920002;
880 const uint32_t Encoded_s_endpgm = 0xbf810000;
881 const uint32_t TrapInstr = TrapEnabled ? Encoded_s_trap : Encoded_s_endpgm;
883 OS.emitInt32(TrapInstr);
884 for (int i = 0; i < 63; ++i) {
885 OS.emitInt32(Encoded_s_nop);
886 }
887 return true;
888}
889
891 const uint32_t Encoded_s_code_end = 0xbf9f0000;
892 const uint32_t Encoded_s_nop = 0xbf800000;
893 uint32_t Encoded_pad = Encoded_s_code_end;
894
895 // Instruction cache line size in bytes.
896 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
897 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
898
899 // Extra padding amount in bytes to support prefetch mode 3.
900 unsigned FillSize = 3 * CacheLineSize;
901
902 if (AMDGPU::isGFX90A(STI)) {
903 Encoded_pad = Encoded_s_nop;
904 FillSize = 16 * CacheLineSize;
905 }
906
908 OS.pushSection();
909 OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4);
910 for (unsigned I = 0; I < FillSize; I += 4)
911 OS.emitInt32(Encoded_pad);
912 OS.popSection();
913 return true;
914}
915
917 const MCSubtargetInfo &STI, StringRef KernelName,
918 const MCKernelDescriptor &KernelDescriptor, uint64_t NextVGPR,
919 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) {
920 auto &Streamer = getStreamer();
921 auto &Context = Streamer.getContext();
922
923 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
924 Context.getOrCreateSymbol(Twine(KernelName)));
925 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
926 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
927
928 // Copy kernel descriptor symbol's binding, other and visibility from the
929 // kernel code symbol.
930 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding());
931 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther());
932 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility());
933 // Kernel descriptor symbol's type and size are fixed.
934 KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
935 KernelDescriptorSymbol->setSize(
937
938 // The visibility of the kernel code symbol must be protected or less to allow
939 // static relocations from the kernel descriptor to be used.
940 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT)
941 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED);
942
943 Streamer.emitLabel(KernelDescriptorSymbol);
944 Streamer.emitValue(
945 KernelDescriptor.group_segment_fixed_size,
947 Streamer.emitValue(
948 KernelDescriptor.private_segment_fixed_size,
950 Streamer.emitValue(KernelDescriptor.kernarg_size,
952
953 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved0); ++i)
954 Streamer.emitInt8(0u);
955
956 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
957 // expression being created is:
958 // (start of kernel code) - (start of kernel descriptor)
959 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
960 Streamer.emitValue(
962 MCSymbolRefExpr::create(KernelCodeSymbol,
964 MCSymbolRefExpr::create(KernelDescriptorSymbol,
965 MCSymbolRefExpr::VK_None, Context),
966 Context),
968 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved1); ++i)
969 Streamer.emitInt8(0u);
970 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc3,
972 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc1,
974 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc2,
976 Streamer.emitValue(
977 KernelDescriptor.kernel_code_properties,
979 Streamer.emitValue(KernelDescriptor.kernarg_preload,
981 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved3); ++i)
982 Streamer.emitInt8(0u);
983}
AMDHSA kernel descriptor MCExpr struct for use in MC layer.
This is a verifier for AMDGPU HSA metadata, which can verify both well-typed metadata and untyped met...
AMDGPU metadata definitions and in-memory representations.
Enums and constants for AMDGPU PT_NOTE sections.
static cl::opt< unsigned > ForceGenericVersion("amdgpu-force-generic-version", cl::desc("Force a specific generic_v<N> flag to be " "added. For testing purposes only."), cl::ReallyHidden, cl::init(0))
AMDHSA kernel descriptor definitions.
MC layer struct for AMDGPUMCKernelCodeT, provides MCExpr functionality where required.
std::string Name
uint64_t Size
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
verify safepoint Safepoint IR Verifier
raw_pwrite_stream & OS
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
const char * getVendor() const
void toBlob(unsigned Type, std::string &S)
void toString(std::string &S)
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override
void EmitAMDKernelCodeT(AMDGPU::AMDGPUMCKernelCodeT &Header) override
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI, bool TrapEnabled) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void EmitAMDKernelCodeT(AMDGPU::AMDGPUMCKernelCodeT &Header) override
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI, bool TrapEnabled) override
virtual bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict)
Emit HSA Metadata.
AMDGPUPALMetadata * getPALMetadata()
virtual void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV)
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
static unsigned getElfMach(StringRef GPU)
MCContext & getContext() const
static StringRef getArchNameFromElfMach(unsigned ElfMach)
const std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > & getTargetID() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
MCObjectWriter & getWriter() const
Definition: MCAssembler.h:334
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:278
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:536
static const MCBinaryExpr * createMul(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:591
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:621
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
const MCAsmInfo * getAsmInfo() const
Definition: MCContext.h:415
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
MCAssembler & getAssembler()
virtual void setOverrideABIVersion(uint8_t ABIVersion)
ELF only, override the default ABIVersion in the ELF header.
Streaming machine code generation interface.
Definition: MCStreamer.h:212
MCContext & getContext() const
Definition: MCStreamer.h:297
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:180
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:424
void emitInt8(uint64_t Value)
Definition: MCStreamer.h:754
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
StringRef getCPU() const
unsigned getOther() const
void setVisibility(unsigned Visibility)
void setSize(const MCExpr *SS)
Definition: MCSymbolELF.h:22
bool isBindingSet() const
void setBinding(unsigned Binding) const
Definition: MCSymbolELF.cpp:43
unsigned getVisibility() const
unsigned getBinding() const
Definition: MCSymbolELF.cpp:66
void setType(unsigned Type) const
Definition: MCSymbolELF.cpp:94
void setOther(unsigned Other)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:397
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
void setExternal(bool Value) const
Definition: MCSymbol.h:407
void setIndex(uint32_t Value) const
Set the (implementation defined) index.
Definition: MCSymbol.h:321
bool declareCommon(uint64_t Size, Align Alignment, bool Target=false)
Declare this symbol as being 'common'.
Definition: MCSymbol.h:375
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:382
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:373
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
An efficient, type-erasing, non-owning reference to a callable.
Simple in-memory representation of a document of msgpack objects with ability to find and create arra...
DocNode & getRoot()
Get ref to the document's root element.
void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:661
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:679
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const char NoteNameV2[]
Definition: AMDGPUPTNote.h:26
const char SectionName[]
Definition: AMDGPUPTNote.h:24
const char NoteNameV3[]
Definition: AMDGPUPTNote.h:27
static constexpr unsigned GFX10_1
static constexpr unsigned GFX10_3
static constexpr unsigned GFX11
static constexpr unsigned GFX9
static constexpr unsigned GFX12
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
StringRef getArchNameR600(GPUKind AK)
GPUKind
GPU kinds supported by the AMDGPU target.
Definition: TargetParser.h:35
bool isHsaAbi(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
bool isGFX90A(const MCSubtargetInfo &STI)
GPUKind parseArchAMDGCN(StringRef CPU)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
StringRef getArchNameAMDGCN(GPUKind AK)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
GPUKind parseArchR600(StringRef CPU)
@ STB_GLOBAL
Definition: ELF.h:1315
@ SHT_NOTE
Definition: ELF.h:1073
@ SHN_AMDGPU_LDS
Definition: ELF.h:1854
@ NT_AMDGPU_METADATA
Definition: ELF.h:1871
@ EF_AMDGPU_GENERIC_VERSION_MAX
Definition: ELF.h:861
@ EF_AMDGPU_FEATURE_XNACK_ANY_V4
Definition: ELF.h:838
@ EF_AMDGPU_MACH_AMDGCN_GFX703
Definition: ELF.h:750
@ EF_AMDGPU_MACH_AMDGCN_GFX1035
Definition: ELF.h:774
@ EF_AMDGPU_FEATURE_SRAMECC_V3
Definition: ELF.h:829
@ EF_AMDGPU_MACH_AMDGCN_GFX1031
Definition: ELF.h:768
@ EF_AMDGPU_GENERIC_VERSION_OFFSET
Definition: ELF.h:859
@ EF_AMDGPU_MACH_R600_CAYMAN
Definition: ELF.h:732
@ EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
Definition: ELF.h:849
@ EF_AMDGPU_MACH_AMDGCN_GFX704
Definition: ELF.h:751
@ EF_AMDGPU_MACH_AMDGCN_GFX902
Definition: ELF.h:758
@ EF_AMDGPU_MACH_AMDGCN_GFX810
Definition: ELF.h:756
@ EF_AMDGPU_MACH_AMDGCN_GFX1036
Definition: ELF.h:782
@ EF_AMDGPU_MACH_AMDGCN_GFX1102
Definition: ELF.h:784
@ EF_AMDGPU_MACH_R600_RV730
Definition: ELF.h:721
@ EF_AMDGPU_MACH_R600_RV710
Definition: ELF.h:720
@ EF_AMDGPU_MACH_AMDGCN_GFX908
Definition: ELF.h:761
@ EF_AMDGPU_MACH_AMDGCN_GFX1011
Definition: ELF.h:765
@ EF_AMDGPU_MACH_R600_CYPRESS
Definition: ELF.h:725
@ EF_AMDGPU_MACH_AMDGCN_GFX1032
Definition: ELF.h:769
@ EF_AMDGPU_MACH_R600_R600
Definition: ELF.h:715
@ EF_AMDGPU_MACH_AMDGCN_GFX940
Definition: ELF.h:777
@ EF_AMDGPU_MACH_AMDGCN_GFX941
Definition: ELF.h:788
@ EF_AMDGPU_MACH_R600_TURKS
Definition: ELF.h:733
@ EF_AMDGPU_MACH_R600_JUNIPER
Definition: ELF.h:726
@ EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
Definition: ELF.h:853
@ EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
Definition: ELF.h:836
@ EF_AMDGPU_MACH_AMDGCN_GFX601
Definition: ELF.h:746
@ EF_AMDGPU_MACH_AMDGCN_GFX942
Definition: ELF.h:789
@ EF_AMDGPU_MACH_AMDGCN_GFX1152
Definition: ELF.h:798
@ EF_AMDGPU_MACH_R600_R630
Definition: ELF.h:716
@ EF_AMDGPU_MACH_R600_REDWOOD
Definition: ELF.h:727
@ EF_AMDGPU_MACH_R600_RV770
Definition: ELF.h:722
@ EF_AMDGPU_FEATURE_XNACK_OFF_V4
Definition: ELF.h:840
@ EF_AMDGPU_MACH_AMDGCN_GFX600
Definition: ELF.h:745
@ EF_AMDGPU_FEATURE_XNACK_V3
Definition: ELF.h:824
@ EF_AMDGPU_MACH_AMDGCN_GFX602
Definition: ELF.h:771
@ EF_AMDGPU_MACH_AMDGCN_GFX1101
Definition: ELF.h:783
@ EF_AMDGPU_MACH_AMDGCN_GFX1100
Definition: ELF.h:778
@ EF_AMDGPU_MACH_AMDGCN_GFX1033
Definition: ELF.h:770
@ EF_AMDGPU_MACH_AMDGCN_GFX801
Definition: ELF.h:753
@ EF_AMDGPU_MACH_AMDGCN_GFX705
Definition: ELF.h:772
@ EF_AMDGPU_MACH_AMDGCN_GFX1010
Definition: ELF.h:764
@ EF_AMDGPU_MACH_R600_RV670
Definition: ELF.h:718
@ EF_AMDGPU_MACH_AMDGCN_GFX701
Definition: ELF.h:748
@ EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC
Definition: ELF.h:796
@ EF_AMDGPU_MACH_AMDGCN_GFX1012
Definition: ELF.h:766
@ EF_AMDGPU_MACH_AMDGCN_GFX1151
Definition: ELF.h:787
@ EF_AMDGPU_MACH_AMDGCN_GFX1030
Definition: ELF.h:767
@ EF_AMDGPU_MACH_R600_CEDAR
Definition: ELF.h:724
@ EF_AMDGPU_MACH_AMDGCN_GFX1200
Definition: ELF.h:785
@ EF_AMDGPU_MACH_AMDGCN_GFX700
Definition: ELF.h:747
@ EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC
Definition: ELF.h:797
@ EF_AMDGPU_MACH_AMDGCN_GFX803
Definition: ELF.h:755
@ EF_AMDGPU_MACH_AMDGCN_GFX802
Definition: ELF.h:754
@ EF_AMDGPU_MACH_AMDGCN_GFX90C
Definition: ELF.h:763
@ EF_AMDGPU_FEATURE_XNACK_ON_V4
Definition: ELF.h:842
@ EF_AMDGPU_MACH_AMDGCN_GFX900
Definition: ELF.h:757
@ EF_AMDGPU_MACH_AMDGCN_GFX909
Definition: ELF.h:762
@ EF_AMDGPU_MACH_AMDGCN_GFX906
Definition: ELF.h:760
@ EF_AMDGPU_MACH_NONE
Definition: ELF.h:710
@ EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC
Definition: ELF.h:794
@ EF_AMDGPU_MACH_AMDGCN_GFX1103
Definition: ELF.h:781
@ EF_AMDGPU_MACH_R600_CAICOS
Definition: ELF.h:731
@ EF_AMDGPU_MACH_AMDGCN_GFX90A
Definition: ELF.h:776
@ EF_AMDGPU_MACH_AMDGCN_GFX1034
Definition: ELF.h:775
@ EF_AMDGPU_MACH_AMDGCN_GFX1013
Definition: ELF.h:779
@ EF_AMDGPU_MACH_AMDGCN_GFX12_GENERIC
Definition: ELF.h:802
@ EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC
Definition: ELF.h:795
@ EF_AMDGPU_MACH_AMDGCN_GFX904
Definition: ELF.h:759
@ EF_AMDGPU_MACH_R600_RS880
Definition: ELF.h:717
@ EF_AMDGPU_MACH_AMDGCN_GFX805
Definition: ELF.h:773
@ EF_AMDGPU_MACH_AMDGCN_GFX1201
Definition: ELF.h:791
@ EF_AMDGPU_MACH_AMDGCN_GFX1150
Definition: ELF.h:780
@ EF_AMDGPU_MACH_R600_SUMO
Definition: ELF.h:728
@ EF_AMDGPU_MACH_R600_BARTS
Definition: ELF.h:730
@ EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
Definition: ELF.h:851
@ EF_AMDGPU_FEATURE_SRAMECC_ON_V4
Definition: ELF.h:855
@ EF_AMDGPU_MACH_AMDGCN_GFX702
Definition: ELF.h:749
@ NT_AMD_HSA_ISA_NAME
Definition: ELF.h:1864
@ STV_PROTECTED
Definition: ELF.h:1347
@ STV_DEFAULT
Definition: ELF.h:1344
@ SHF_ALLOC
Definition: ELF.h:1161
@ STT_AMDGPU_HSA_KERNEL
Definition: ELF.h:1340
@ STT_OBJECT
Definition: ELF.h:1327
@ ReallyHidden
Definition: CommandLine.h:139
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
Instruction set architecture version.
Definition: TargetParser.h:127
static const MCExpr * bits_get(const MCExpr *Src, uint32_t Shift, uint32_t Mask, MCContext &Ctx)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85