43 cl::desc(
"Force a specific generic_v<N> flag to be "
44 "added. For testing purposes only."),
49 if (!HSAMetadataDoc.
fromYAML(HSAMetadataString))
234 OS <<
"\t.amdgcn_target \"" <<
getTargetID()->toString() <<
"\"\n";
240 OS <<
"\t.amdhsa_code_object_version " << COV <<
'\n';
245 OS <<
"\t.amd_kernel_code_t\n";
247 OS <<
"\t.end_amd_kernel_code_t\n";
255 OS <<
"\t.amdgpu_hsa_kernel " << SymbolName <<
'\n' ;
262 OS <<
"\t.amdgpu_lds " << Symbol->getName() <<
", " <<
Size <<
", "
263 << Alignment.
value() <<
'\n';
267 OS <<
"\t.amd_amdgpu_isa \"" <<
getTargetID()->toString() <<
"\"\n";
277 std::string HSAMetadataString;
279 HSAMetadataDoc.
toYAML(StrOS);
282 OS << StrOS.
str() <<
'\n';
289 OS << (TrapEnabled ?
"\ts_trap 2" :
"\ts_endpgm")
290 <<
" ; Kernarg preload header. Trap with incompatible firmware that "
291 "doesn't support preloading kernel arguments.\n";
292 OS <<
"\t.fill 63, 4, 0xbf800000 ; s_nop 0\n";
297 const uint32_t Encoded_s_code_end = 0xbf9f0000;
298 const uint32_t Encoded_s_nop = 0xbf800000;
299 uint32_t Encoded_pad = Encoded_s_code_end;
309 Encoded_pad = Encoded_s_nop;
313 OS <<
"\t.p2alignl " << Log2CacheLineSize <<
", " << Encoded_pad <<
'\n';
314 OS <<
"\t.fill " << (FillSize / 4) <<
", 4, " << Encoded_pad <<
'\n';
321 bool ReserveVCC,
bool ReserveFlatScr) {
325 OS <<
"\t.amdhsa_kernel " << KernelName <<
'\n';
331 const MCExpr *pgm_rsrc1_bits =
333 if (pgm_rsrc1_bits->evaluateAsAbsolute(IVal))
334 OS << static_cast<uint64_t>(IVal);
336 pgm_rsrc1_bits->
print(OS, MAI);
340 OS <<
"\t\t.amdhsa_group_segment_fixed_size ";
344 OS <<
"\t\t.amdhsa_private_segment_fixed_size ";
348 OS <<
"\t\t.amdhsa_kernarg_size ";
354 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT,
".amdhsa_user_sgpr_count");
359 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT,
360 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,
361 ".amdhsa_user_sgpr_private_segment_buffer");
363 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_SHIFT,
364 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR,
365 ".amdhsa_user_sgpr_dispatch_ptr");
367 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_SHIFT,
368 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR,
369 ".amdhsa_user_sgpr_queue_ptr");
371 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT,
372 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR,
373 ".amdhsa_user_sgpr_kernarg_segment_ptr");
375 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_SHIFT,
376 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID,
377 ".amdhsa_user_sgpr_dispatch_id");
380 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT,
381 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT,
382 ".amdhsa_user_sgpr_flat_scratch_init");
384 PrintField(KD.
kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_LENGTH_SHIFT,
385 amdhsa::KERNARG_PRELOAD_SPEC_LENGTH,
386 ".amdhsa_user_sgpr_kernarg_preload_length");
387 PrintField(KD.
kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_OFFSET_SHIFT,
388 amdhsa::KERNARG_PRELOAD_SPEC_OFFSET,
389 ".amdhsa_user_sgpr_kernarg_preload_offset");
393 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT,
394 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE,
395 ".amdhsa_user_sgpr_private_segment_size");
396 if (IVersion.
Major >= 10)
398 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT,
399 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
400 ".amdhsa_wavefront_size32");
403 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK_SHIFT,
404 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK,
405 ".amdhsa_uses_dynamic_stack");
407 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT_SHIFT,
408 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT,
410 ?
".amdhsa_enable_private_segment"
411 :
".amdhsa_system_sgpr_private_segment_wavefront_offset"));
413 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT,
414 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X,
415 ".amdhsa_system_sgpr_workgroup_id_x");
417 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT,
418 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y,
419 ".amdhsa_system_sgpr_workgroup_id_y");
421 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT,
422 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z,
423 ".amdhsa_system_sgpr_workgroup_id_z");
425 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO_SHIFT,
426 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO,
427 ".amdhsa_system_sgpr_workgroup_info");
429 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID_SHIFT,
430 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID,
431 ".amdhsa_system_vgpr_workitem_id");
434 OS <<
"\t\t.amdhsa_next_free_vgpr " << NextVGPR <<
'\n';
435 OS <<
"\t\t.amdhsa_next_free_sgpr " << NextSGPR <<
'\n';
441 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET_SHIFT,
442 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET,
getContext());
447 OS <<
"\t\t.amdhsa_accum_offset ";
449 if (accum_bits->evaluateAsAbsolute(IVal)) {
450 OS << static_cast<uint64_t>(IVal);
452 accum_bits->
print(OS, MAI);
458 OS <<
"\t\t.amdhsa_reserve_vcc " << ReserveVCC <<
'\n';
460 OS <<
"\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr <<
'\n';
468 OS <<
"\t\t.amdhsa_reserve_xnack_mask " <<
getTargetID()->isXnackOnOrAny() <<
'\n';
473 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32_SHIFT,
474 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32,
475 ".amdhsa_float_round_mode_32");
477 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64_SHIFT,
478 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64,
479 ".amdhsa_float_round_mode_16_64");
481 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32_SHIFT,
482 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32,
483 ".amdhsa_float_denorm_mode_32");
485 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64_SHIFT,
486 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
487 ".amdhsa_float_denorm_mode_16_64");
488 if (IVersion.
Major < 12) {
490 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP_SHIFT,
491 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP,
492 ".amdhsa_dx10_clamp");
494 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE_SHIFT,
495 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE,
496 ".amdhsa_ieee_mode");
498 if (IVersion.
Major >= 9) {
500 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL_SHIFT,
501 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL,
502 ".amdhsa_fp16_overflow");
506 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,
507 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT,
".amdhsa_tg_split");
508 if (IVersion.
Major >= 10) {
510 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE_SHIFT,
511 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE,
512 ".amdhsa_workgroup_processor_mode");
514 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED_SHIFT,
515 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED,
516 ".amdhsa_memory_ordered");
518 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS_SHIFT,
519 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS,
520 ".amdhsa_forward_progress");
522 if (IVersion.
Major >= 10 && IVersion.
Major < 12) {
524 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT_SHIFT,
525 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT,
526 ".amdhsa_shared_vgpr_count");
528 if (IVersion.
Major >= 12) {
530 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN_SHIFT,
531 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN,
532 ".amdhsa_round_robin_scheduling");
537 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT,
538 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION,
539 ".amdhsa_exception_fp_ieee_invalid_op");
542 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT,
543 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE,
544 ".amdhsa_exception_fp_denorm_src");
548 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT,
549 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO,
550 ".amdhsa_exception_fp_ieee_div_zero");
553 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT,
554 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW,
555 ".amdhsa_exception_fp_ieee_overflow");
558 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT,
559 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW,
560 ".amdhsa_exception_fp_ieee_underflow");
563 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT,
564 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT,
565 ".amdhsa_exception_fp_ieee_inexact");
568 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO_SHIFT,
569 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,
570 ".amdhsa_exception_int_div_zero");
572 OS <<
"\t.end_amdhsa_kernel\n";
610void AMDGPUTargetELFStreamer::EmitNote(
614 auto &
Context = S.getContext();
616 auto NameSZ =
Name.size() + 1;
618 unsigned NoteFlags = 0;
628 S.emitValue(DescSZ, 4);
629 S.emitInt32(NoteType);
631 S.emitValueToAlignment(
Align(4), 0, 1, 0);
633 S.emitValueToAlignment(
Align(4), 0, 1, 0);
637unsigned AMDGPUTargetELFStreamer::getEFlags() {
642 return getEFlagsR600();
644 return getEFlagsAMDGCN();
648unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
654unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
662 return getEFlagsUnknownOS();
664 return getEFlagsAMDHSA();
666 return getEFlagsAMDPAL();
668 return getEFlagsMesa3D();
672unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
676 return getEFlagsV3();
679unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
683 return getEFlagsV6();
684 return getEFlagsV4();
687unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
690 return getEFlagsV3();
693unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
696 return getEFlagsV3();
699unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
700 unsigned EFlagsV3 = 0;
715unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
716 unsigned EFlagsV4 = 0;
755unsigned AMDGPUTargetELFStreamer::getEFlagsV6() {
756 unsigned Flags = getEFlagsV4();
783 " - no ELF flag can represent this version!");
797 OS.emitBytes(
StringRef((
const char*)&Header,
sizeof(Header)));
805 Symbol->setType(
Type);
810 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol);
820 " redeclared as different type");
831 auto *DescBegin =
Context.createTempSymbol();
832 auto *DescEnd =
Context.createTempSymbol();
839 OS.emitLabel(DescBegin);
841 OS.emitLabel(DescEnd);
852 std::string HSAMetadataString;
858 auto *DescBegin =
Context.createTempSymbol();
859 auto *DescEnd =
Context.createTempSymbol();
866 OS.emitLabel(DescBegin);
867 OS.emitBytes(HSAMetadataString);
868 OS.emitLabel(DescEnd);
875 const uint32_t Encoded_s_nop = 0xbf800000;
876 const uint32_t Encoded_s_trap = 0xbf920002;
877 const uint32_t Encoded_s_endpgm = 0xbf810000;
878 const uint32_t TrapInstr = TrapEnabled ? Encoded_s_trap : Encoded_s_endpgm;
880 OS.emitInt32(TrapInstr);
881 for (
int i = 0; i < 63; ++i) {
882 OS.emitInt32(Encoded_s_nop);
888 const uint32_t Encoded_s_code_end = 0xbf9f0000;
889 const uint32_t Encoded_s_nop = 0xbf800000;
890 uint32_t Encoded_pad = Encoded_s_code_end;
900 Encoded_pad = Encoded_s_nop;
907 for (
unsigned I = 0;
I < FillSize;
I += 4)
908 OS.emitInt32(Encoded_pad);
916 uint64_t NextSGPR,
bool ReserveVCC,
bool ReserveFlatScr) {
922 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
932 KernelDescriptorSymbol->
setSize(
940 Streamer.
emitLabel(KernelDescriptorSymbol);
AMDHSA kernel descriptor MCExpr struct for use in MC layer.
Enums and constants for AMDGPU PT_NOTE sections.
static cl::opt< unsigned > ForceGenericVersion("amdgpu-force-generic-version", cl::desc("Force a specific generic_v<N> flag to be " "added. For testing purposes only."), cl::ReallyHidden, cl::init(0))
AMDHSA kernel descriptor definitions.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
verify safepoint Safepoint IR Verifier
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
bool EmitISAVersion() override
void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV) override
void EmitDirectiveAMDGCNTarget() override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI, bool TrapEnabled) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
void EmitDirectiveAMDGCNTarget() override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override
MCELFStreamer & getStreamer()
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI, bool TrapEnabled) override
bool EmitISAVersion() override
virtual bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict)
Emit HSA Metadata.
AMDGPUPALMetadata * getPALMetadata()
virtual void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV)
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
static unsigned getElfMach(StringRef GPU)
MCContext & getContext() const
static StringRef getArchNameFromElfMach(unsigned ElfMach)
const std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > & getTargetID() const
unsigned CodeObjectVersion
This class is intended to be used as a base class for asm properties and features specific to the tar...
MCObjectWriter & getWriter() const
void setELFHeaderEFlags(unsigned Flags)
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createMul(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
const MCAsmInfo * getAsmInfo() const
Base class for the full range of assembler expressions which are needed for parsing.
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
MCAssembler & getAssembler()
virtual void setOverrideABIVersion(uint8_t ABIVersion)
ELF only, override the default ABIVersion in the ELF header.
Streaming machine code generation interface.
MCContext & getContext() const
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
void emitInt8(uint64_t Value)
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
unsigned getOther() const
void setVisibility(unsigned Visibility)
void setSize(const MCExpr *SS)
bool isBindingSet() const
void setBinding(unsigned Binding) const
unsigned getVisibility() const
unsigned getBinding() const
void setType(unsigned Type) const
void setOther(unsigned Other)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
void setExternal(bool Value) const
void setIndex(uint32_t Value) const
Set the (implementation defined) index.
bool declareCommon(uint64_t Size, Align Alignment, bool Target=false)
Declare this symbol as being 'common'.
StringRef - Represent a constant reference to a string, i.e.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
An efficient, type-erasing, non-owning reference to a callable.
Simple in-memory representation of a document of msgpack objects with ability to find and create arra...
DocNode & getRoot()
Get ref to the document's root element.
void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static constexpr unsigned GFX10_1
static constexpr unsigned GFX10_3
static constexpr unsigned GFX11
static constexpr unsigned GFX9
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
StringRef getArchNameR600(GPUKind AK)
GPUKind
GPU kinds supported by the AMDGPU target.
bool isHsaAbi(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
bool isGFX90A(const MCSubtargetInfo &STI)
GPUKind parseArchAMDGCN(StringRef CPU)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
StringRef getArchNameAMDGCN(GPUKind AK)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
GPUKind parseArchR600(StringRef CPU)
@ EF_AMDGPU_GENERIC_VERSION_MAX
@ EF_AMDGPU_FEATURE_XNACK_ANY_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX703
@ EF_AMDGPU_MACH_AMDGCN_GFX1035
@ EF_AMDGPU_FEATURE_SRAMECC_V3
@ EF_AMDGPU_MACH_AMDGCN_GFX1031
@ EF_AMDGPU_GENERIC_VERSION_OFFSET
@ EF_AMDGPU_MACH_R600_CAYMAN
@ EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX704
@ EF_AMDGPU_MACH_AMDGCN_GFX902
@ EF_AMDGPU_MACH_AMDGCN_GFX810
@ EF_AMDGPU_MACH_AMDGCN_GFX1036
@ EF_AMDGPU_MACH_AMDGCN_GFX1102
@ EF_AMDGPU_MACH_R600_RV730
@ EF_AMDGPU_MACH_R600_RV710
@ EF_AMDGPU_MACH_AMDGCN_GFX908
@ EF_AMDGPU_MACH_AMDGCN_GFX1011
@ EF_AMDGPU_MACH_R600_CYPRESS
@ EF_AMDGPU_MACH_AMDGCN_GFX1032
@ EF_AMDGPU_MACH_R600_R600
@ EF_AMDGPU_MACH_AMDGCN_GFX940
@ EF_AMDGPU_MACH_AMDGCN_GFX941
@ EF_AMDGPU_MACH_R600_TURKS
@ EF_AMDGPU_MACH_R600_JUNIPER
@ EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
@ EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX601
@ EF_AMDGPU_MACH_AMDGCN_GFX942
@ EF_AMDGPU_MACH_R600_R630
@ EF_AMDGPU_MACH_R600_REDWOOD
@ EF_AMDGPU_MACH_R600_RV770
@ EF_AMDGPU_FEATURE_XNACK_OFF_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX600
@ EF_AMDGPU_FEATURE_XNACK_V3
@ EF_AMDGPU_MACH_AMDGCN_GFX602
@ EF_AMDGPU_MACH_AMDGCN_GFX1101
@ EF_AMDGPU_MACH_AMDGCN_GFX1100
@ EF_AMDGPU_MACH_AMDGCN_GFX1033
@ EF_AMDGPU_MACH_AMDGCN_GFX801
@ EF_AMDGPU_MACH_AMDGCN_GFX705
@ EF_AMDGPU_MACH_AMDGCN_GFX1010
@ EF_AMDGPU_MACH_R600_RV670
@ EF_AMDGPU_MACH_AMDGCN_GFX701
@ EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC
@ EF_AMDGPU_MACH_AMDGCN_GFX1012
@ EF_AMDGPU_MACH_AMDGCN_GFX1151
@ EF_AMDGPU_MACH_AMDGCN_GFX1030
@ EF_AMDGPU_MACH_R600_CEDAR
@ EF_AMDGPU_MACH_AMDGCN_GFX1200
@ EF_AMDGPU_MACH_AMDGCN_GFX700
@ EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC
@ EF_AMDGPU_MACH_AMDGCN_GFX803
@ EF_AMDGPU_MACH_AMDGCN_GFX802
@ EF_AMDGPU_MACH_AMDGCN_GFX90C
@ EF_AMDGPU_FEATURE_XNACK_ON_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX900
@ EF_AMDGPU_MACH_AMDGCN_GFX909
@ EF_AMDGPU_MACH_AMDGCN_GFX906
@ EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC
@ EF_AMDGPU_MACH_AMDGCN_GFX1103
@ EF_AMDGPU_MACH_R600_CAICOS
@ EF_AMDGPU_MACH_AMDGCN_GFX90A
@ EF_AMDGPU_MACH_AMDGCN_GFX1034
@ EF_AMDGPU_MACH_AMDGCN_GFX1013
@ EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC
@ EF_AMDGPU_MACH_AMDGCN_GFX904
@ EF_AMDGPU_MACH_R600_RS880
@ EF_AMDGPU_MACH_AMDGCN_GFX805
@ EF_AMDGPU_MACH_AMDGCN_GFX1201
@ EF_AMDGPU_MACH_AMDGCN_GFX1150
@ EF_AMDGPU_MACH_R600_SUMO
@ EF_AMDGPU_MACH_R600_BARTS
@ EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
@ EF_AMDGPU_FEATURE_SRAMECC_ON_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX702
initializer< Ty > init(const Ty &Val)
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
This is an optimization pass for GlobalISel generic memory operations.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
void dumpAmdKernelCode(const amd_kernel_code_t *C, raw_ostream &OS, const char *tab)
AMD Kernel Code Object (amd_kernel_code_t).
Instruction set architecture version.
const MCExpr * compute_pgm_rsrc2
const MCExpr * kernarg_size
const MCExpr * kernarg_preload
const MCExpr * compute_pgm_rsrc3
const MCExpr * private_segment_fixed_size
static const MCExpr * bits_get(const MCExpr *Src, uint32_t Shift, uint32_t Mask, MCContext &Ctx)
const MCExpr * compute_pgm_rsrc1
const MCExpr * group_segment_fixed_size
const MCExpr * kernel_code_properties
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
uint32_t group_segment_fixed_size
uint32_t compute_pgm_rsrc1
uint32_t private_segment_fixed_size
uint32_t compute_pgm_rsrc2
uint16_t kernel_code_properties
uint32_t compute_pgm_rsrc3
int64_t kernel_code_entry_byte_offset