LLVM  14.0.0git
AVRExpandPseudoInsts.cpp
Go to the documentation of this file.
1 //===-- AVRExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass that expands pseudo instructions into target
10 // instructions. This pass should be run after register allocation but before
11 // the post-regalloc scheduling pass.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AVR.h"
16 #include "AVRInstrInfo.h"
17 #include "AVRTargetMachine.h"
19 
25 
26 using namespace llvm;
27 
28 #define AVR_EXPAND_PSEUDO_NAME "AVR pseudo instruction expansion pass"
29 
30 namespace {
31 
32 /// Expands "placeholder" instructions marked as pseudo into
33 /// actual AVR instructions.
34 class AVRExpandPseudo : public MachineFunctionPass {
35 public:
36  static char ID;
37 
38  AVRExpandPseudo() : MachineFunctionPass(ID) {
40  }
41 
42  bool runOnMachineFunction(MachineFunction &MF) override;
43 
44  StringRef getPassName() const override { return AVR_EXPAND_PSEUDO_NAME; }
45 
46 private:
47  typedef MachineBasicBlock Block;
48  typedef Block::iterator BlockIt;
49 
50  const AVRRegisterInfo *TRI;
51  const TargetInstrInfo *TII;
52 
53  /// The register to be used for temporary storage.
54  const Register SCRATCH_REGISTER = AVR::R0;
55  /// The register that will always contain zero.
56  const Register ZERO_REGISTER = AVR::R1;
57  /// The IO address of the status register.
58  const unsigned SREG_ADDR = 0x3f;
59 
60  bool expandMBB(Block &MBB);
61  bool expandMI(Block &MBB, BlockIt MBBI);
62  template <unsigned OP> bool expand(Block &MBB, BlockIt MBBI);
63 
64  MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
65  return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
66  }
67 
68  MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode,
69  Register DstReg) {
70  return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
71  }
72 
73  MachineRegisterInfo &getRegInfo(Block &MBB) {
74  return MBB.getParent()->getRegInfo();
75  }
76 
77  bool expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI);
78  bool expandLogic(unsigned Op, Block &MBB, BlockIt MBBI);
79  bool expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI);
80  bool isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const;
81 
82  template <typename Func> bool expandAtomic(Block &MBB, BlockIt MBBI, Func f);
83 
84  template <typename Func>
85  bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI, Func f);
86 
87  bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI);
88 
89  bool expandAtomicArithmeticOp(unsigned MemOpcode, unsigned ArithOpcode,
90  Block &MBB, BlockIt MBBI);
91 
92  /// Specific shift implementation.
93  bool expandLSLB7Rd(Block &MBB, BlockIt MBBI);
94  bool expandLSRB7Rd(Block &MBB, BlockIt MBBI);
95  bool expandASRB7Rd(Block &MBB, BlockIt MBBI);
96  bool expandLSLW4Rd(Block &MBB, BlockIt MBBI);
97  bool expandLSRW4Rd(Block &MBB, BlockIt MBBI);
98  bool expandLSLW8Rd(Block &MBB, BlockIt MBBI);
99  bool expandLSRW8Rd(Block &MBB, BlockIt MBBI);
100  bool expandASRW8Rd(Block &MBB, BlockIt MBBI);
101  bool expandLSLW12Rd(Block &MBB, BlockIt MBBI);
102  bool expandLSRW12Rd(Block &MBB, BlockIt MBBI);
103 
104  /// Scavenges a free GPR8 register for use.
105  Register scavengeGPR8(MachineInstr &MI);
106 };
107 
108 char AVRExpandPseudo::ID = 0;
109 
110 bool AVRExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
111  bool Modified = false;
112 
113  BlockIt MBBI = MBB.begin(), E = MBB.end();
114  while (MBBI != E) {
115  BlockIt NMBBI = std::next(MBBI);
116  Modified |= expandMI(MBB, MBBI);
117  MBBI = NMBBI;
118  }
119 
120  return Modified;
121 }
122 
123 bool AVRExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
124  bool Modified = false;
125 
126  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
127  TRI = STI.getRegisterInfo();
128  TII = STI.getInstrInfo();
129 
130  // We need to track liveness in order to use register scavenging.
132 
133  for (Block &MBB : MF) {
134  bool ContinueExpanding = true;
135  unsigned ExpandCount = 0;
136 
137  // Continue expanding the block until all pseudos are expanded.
138  do {
139  assert(ExpandCount < 10 && "pseudo expand limit reached");
140 
141  bool BlockModified = expandMBB(MBB);
142  Modified |= BlockModified;
143  ExpandCount++;
144 
145  ContinueExpanding = BlockModified;
146  } while (ContinueExpanding);
147  }
148 
149  return Modified;
150 }
151 
152 bool AVRExpandPseudo::expandArith(unsigned OpLo, unsigned OpHi, Block &MBB,
153  BlockIt MBBI) {
154  MachineInstr &MI = *MBBI;
155  Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
156  Register DstReg = MI.getOperand(0).getReg();
157  Register SrcReg = MI.getOperand(2).getReg();
158  bool DstIsDead = MI.getOperand(0).isDead();
159  bool DstIsKill = MI.getOperand(1).isKill();
160  bool SrcIsKill = MI.getOperand(2).isKill();
161  bool ImpIsDead = MI.getOperand(3).isDead();
162  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
163  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
164 
165  buildMI(MBB, MBBI, OpLo)
166  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
167  .addReg(DstLoReg, getKillRegState(DstIsKill))
168  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
169 
170  auto MIBHI =
171  buildMI(MBB, MBBI, OpHi)
172  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
173  .addReg(DstHiReg, getKillRegState(DstIsKill))
174  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
175 
176  if (ImpIsDead)
177  MIBHI->getOperand(3).setIsDead();
178 
179  // SREG is always implicitly killed
180  MIBHI->getOperand(4).setIsKill();
181 
182  MI.eraseFromParent();
183  return true;
184 }
185 
186 bool AVRExpandPseudo::expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
187  MachineInstr &MI = *MBBI;
188  Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
189  Register DstReg = MI.getOperand(0).getReg();
190  Register SrcReg = MI.getOperand(2).getReg();
191  bool DstIsDead = MI.getOperand(0).isDead();
192  bool DstIsKill = MI.getOperand(1).isKill();
193  bool SrcIsKill = MI.getOperand(2).isKill();
194  bool ImpIsDead = MI.getOperand(3).isDead();
195  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
196  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
197 
198  auto MIBLO =
199  buildMI(MBB, MBBI, Op)
200  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
201  .addReg(DstLoReg, getKillRegState(DstIsKill))
202  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
203 
204  // SREG is always implicitly dead
205  MIBLO->getOperand(3).setIsDead();
206 
207  auto MIBHI =
208  buildMI(MBB, MBBI, Op)
209  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
210  .addReg(DstHiReg, getKillRegState(DstIsKill))
211  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
212 
213  if (ImpIsDead)
214  MIBHI->getOperand(3).setIsDead();
215 
216  MI.eraseFromParent();
217  return true;
218 }
219 
220 bool AVRExpandPseudo::isLogicImmOpRedundant(unsigned Op,
221  unsigned ImmVal) const {
222 
223  // ANDI Rd, 0xff is redundant.
224  if (Op == AVR::ANDIRdK && ImmVal == 0xff)
225  return true;
226 
227  // ORI Rd, 0x0 is redundant.
228  if (Op == AVR::ORIRdK && ImmVal == 0x0)
229  return true;
230 
231  return false;
232 }
233 
234 bool AVRExpandPseudo::expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI) {
235  MachineInstr &MI = *MBBI;
236  Register DstLoReg, DstHiReg;
237  Register DstReg = MI.getOperand(0).getReg();
238  bool DstIsDead = MI.getOperand(0).isDead();
239  bool SrcIsKill = MI.getOperand(1).isKill();
240  bool ImpIsDead = MI.getOperand(3).isDead();
241  unsigned Imm = MI.getOperand(2).getImm();
242  unsigned Lo8 = Imm & 0xff;
243  unsigned Hi8 = (Imm >> 8) & 0xff;
244  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
245 
246  if (!isLogicImmOpRedundant(Op, Lo8)) {
247  auto MIBLO =
248  buildMI(MBB, MBBI, Op)
249  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
250  .addReg(DstLoReg, getKillRegState(SrcIsKill))
251  .addImm(Lo8);
252 
253  // SREG is always implicitly dead
254  MIBLO->getOperand(3).setIsDead();
255  }
256 
257  if (!isLogicImmOpRedundant(Op, Hi8)) {
258  auto MIBHI =
259  buildMI(MBB, MBBI, Op)
260  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
261  .addReg(DstHiReg, getKillRegState(SrcIsKill))
262  .addImm(Hi8);
263 
264  if (ImpIsDead)
265  MIBHI->getOperand(3).setIsDead();
266  }
267 
268  MI.eraseFromParent();
269  return true;
270 }
271 
272 template <>
273 bool AVRExpandPseudo::expand<AVR::ADDWRdRr>(Block &MBB, BlockIt MBBI) {
274  return expandArith(AVR::ADDRdRr, AVR::ADCRdRr, MBB, MBBI);
275 }
276 
277 template <>
278 bool AVRExpandPseudo::expand<AVR::ADCWRdRr>(Block &MBB, BlockIt MBBI) {
279  return expandArith(AVR::ADCRdRr, AVR::ADCRdRr, MBB, MBBI);
280 }
281 
282 template <>
283 bool AVRExpandPseudo::expand<AVR::SUBWRdRr>(Block &MBB, BlockIt MBBI) {
284  return expandArith(AVR::SUBRdRr, AVR::SBCRdRr, MBB, MBBI);
285 }
286 
287 template <>
288 bool AVRExpandPseudo::expand<AVR::SUBIWRdK>(Block &MBB, BlockIt MBBI) {
289  MachineInstr &MI = *MBBI;
290  Register DstLoReg, DstHiReg;
291  Register DstReg = MI.getOperand(0).getReg();
292  bool DstIsDead = MI.getOperand(0).isDead();
293  bool SrcIsKill = MI.getOperand(1).isKill();
294  bool ImpIsDead = MI.getOperand(3).isDead();
295  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
296 
297  auto MIBLO =
298  buildMI(MBB, MBBI, AVR::SUBIRdK)
299  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
300  .addReg(DstLoReg, getKillRegState(SrcIsKill));
301 
302  auto MIBHI =
303  buildMI(MBB, MBBI, AVR::SBCIRdK)
304  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
305  .addReg(DstHiReg, getKillRegState(SrcIsKill));
306 
307  switch (MI.getOperand(2).getType()) {
309  const GlobalValue *GV = MI.getOperand(2).getGlobal();
310  int64_t Offs = MI.getOperand(2).getOffset();
311  unsigned TF = MI.getOperand(2).getTargetFlags();
312  MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_LO);
313  MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_HI);
314  break;
315  }
317  unsigned Imm = MI.getOperand(2).getImm();
318  MIBLO.addImm(Imm & 0xff);
319  MIBHI.addImm((Imm >> 8) & 0xff);
320  break;
321  }
322  default:
323  llvm_unreachable("Unknown operand type!");
324  }
325 
326  if (ImpIsDead)
327  MIBHI->getOperand(3).setIsDead();
328 
329  // SREG is always implicitly killed
330  MIBHI->getOperand(4).setIsKill();
331 
332  MI.eraseFromParent();
333  return true;
334 }
335 
336 template <>
337 bool AVRExpandPseudo::expand<AVR::SBCWRdRr>(Block &MBB, BlockIt MBBI) {
338  return expandArith(AVR::SBCRdRr, AVR::SBCRdRr, MBB, MBBI);
339 }
340 
341 template <>
342 bool AVRExpandPseudo::expand<AVR::SBCIWRdK>(Block &MBB, BlockIt MBBI) {
343  MachineInstr &MI = *MBBI;
344  Register DstLoReg, DstHiReg;
345  Register DstReg = MI.getOperand(0).getReg();
346  bool DstIsDead = MI.getOperand(0).isDead();
347  bool SrcIsKill = MI.getOperand(1).isKill();
348  bool ImpIsDead = MI.getOperand(3).isDead();
349  unsigned Imm = MI.getOperand(2).getImm();
350  unsigned Lo8 = Imm & 0xff;
351  unsigned Hi8 = (Imm >> 8) & 0xff;
352  unsigned OpLo = AVR::SBCIRdK;
353  unsigned OpHi = AVR::SBCIRdK;
354  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
355 
356  auto MIBLO =
357  buildMI(MBB, MBBI, OpLo)
358  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
359  .addReg(DstLoReg, getKillRegState(SrcIsKill))
360  .addImm(Lo8);
361 
362  // SREG is always implicitly killed
363  MIBLO->getOperand(4).setIsKill();
364 
365  auto MIBHI =
366  buildMI(MBB, MBBI, OpHi)
367  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
368  .addReg(DstHiReg, getKillRegState(SrcIsKill))
369  .addImm(Hi8);
370 
371  if (ImpIsDead)
372  MIBHI->getOperand(3).setIsDead();
373 
374  // SREG is always implicitly killed
375  MIBHI->getOperand(4).setIsKill();
376 
377  MI.eraseFromParent();
378  return true;
379 }
380 
381 template <>
382 bool AVRExpandPseudo::expand<AVR::ANDWRdRr>(Block &MBB, BlockIt MBBI) {
383  return expandLogic(AVR::ANDRdRr, MBB, MBBI);
384 }
385 
386 template <>
387 bool AVRExpandPseudo::expand<AVR::ANDIWRdK>(Block &MBB, BlockIt MBBI) {
388  return expandLogicImm(AVR::ANDIRdK, MBB, MBBI);
389 }
390 
391 template <>
392 bool AVRExpandPseudo::expand<AVR::ORWRdRr>(Block &MBB, BlockIt MBBI) {
393  return expandLogic(AVR::ORRdRr, MBB, MBBI);
394 }
395 
396 template <>
397 bool AVRExpandPseudo::expand<AVR::ORIWRdK>(Block &MBB, BlockIt MBBI) {
398  return expandLogicImm(AVR::ORIRdK, MBB, MBBI);
399 }
400 
401 template <>
402 bool AVRExpandPseudo::expand<AVR::EORWRdRr>(Block &MBB, BlockIt MBBI) {
403  return expandLogic(AVR::EORRdRr, MBB, MBBI);
404 }
405 
406 template <>
407 bool AVRExpandPseudo::expand<AVR::COMWRd>(Block &MBB, BlockIt MBBI) {
408  MachineInstr &MI = *MBBI;
409  Register DstLoReg, DstHiReg;
410  Register DstReg = MI.getOperand(0).getReg();
411  bool DstIsDead = MI.getOperand(0).isDead();
412  bool DstIsKill = MI.getOperand(1).isKill();
413  bool ImpIsDead = MI.getOperand(2).isDead();
414  unsigned OpLo = AVR::COMRd;
415  unsigned OpHi = AVR::COMRd;
416  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
417 
418  auto MIBLO =
419  buildMI(MBB, MBBI, OpLo)
420  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
421  .addReg(DstLoReg, getKillRegState(DstIsKill));
422 
423  // SREG is always implicitly dead
424  MIBLO->getOperand(2).setIsDead();
425 
426  auto MIBHI =
427  buildMI(MBB, MBBI, OpHi)
428  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
429  .addReg(DstHiReg, getKillRegState(DstIsKill));
430 
431  if (ImpIsDead)
432  MIBHI->getOperand(2).setIsDead();
433 
434  MI.eraseFromParent();
435  return true;
436 }
437 
438 template <>
439 bool AVRExpandPseudo::expand<AVR::NEGWRd>(Block &MBB, BlockIt MBBI) {
440  MachineInstr &MI = *MBBI;
441  Register DstLoReg, DstHiReg;
442  Register DstReg = MI.getOperand(0).getReg();
443  bool DstIsDead = MI.getOperand(0).isDead();
444  bool DstIsKill = MI.getOperand(1).isKill();
445  bool ImpIsDead = MI.getOperand(2).isDead();
446  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
447 
448  // Do NEG on the upper byte.
449  auto MIBHI =
450  buildMI(MBB, MBBI, AVR::NEGRd)
451  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
452  .addReg(DstHiReg, getKillRegState(DstIsKill));
453  // SREG is always implicitly dead
454  MIBHI->getOperand(2).setIsDead();
455 
456  // Do NEG on the lower byte.
457  buildMI(MBB, MBBI, AVR::NEGRd)
458  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
459  .addReg(DstLoReg, getKillRegState(DstIsKill));
460 
461  // Do an extra SBC.
462  auto MISBCI =
463  buildMI(MBB, MBBI, AVR::SBCRdRr)
464  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
465  .addReg(DstHiReg, getKillRegState(DstIsKill))
466  .addReg(ZERO_REGISTER);
467  if (ImpIsDead)
468  MISBCI->getOperand(3).setIsDead();
469  // SREG is always implicitly killed
470  MISBCI->getOperand(4).setIsKill();
471 
472  MI.eraseFromParent();
473  return true;
474 }
475 
476 template <>
477 bool AVRExpandPseudo::expand<AVR::CPWRdRr>(Block &MBB, BlockIt MBBI) {
478  MachineInstr &MI = *MBBI;
479  Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
480  Register DstReg = MI.getOperand(0).getReg();
481  Register SrcReg = MI.getOperand(1).getReg();
482  bool DstIsKill = MI.getOperand(0).isKill();
483  bool SrcIsKill = MI.getOperand(1).isKill();
484  bool ImpIsDead = MI.getOperand(2).isDead();
485  unsigned OpLo = AVR::CPRdRr;
486  unsigned OpHi = AVR::CPCRdRr;
487  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
488  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
489 
490  // Low part
491  buildMI(MBB, MBBI, OpLo)
492  .addReg(DstLoReg, getKillRegState(DstIsKill))
493  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
494 
495  auto MIBHI = buildMI(MBB, MBBI, OpHi)
496  .addReg(DstHiReg, getKillRegState(DstIsKill))
497  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
498 
499  if (ImpIsDead)
500  MIBHI->getOperand(2).setIsDead();
501 
502  // SREG is always implicitly killed
503  MIBHI->getOperand(3).setIsKill();
504 
505  MI.eraseFromParent();
506  return true;
507 }
508 
509 template <>
510 bool AVRExpandPseudo::expand<AVR::CPCWRdRr>(Block &MBB, BlockIt MBBI) {
511  MachineInstr &MI = *MBBI;
512  Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
513  Register DstReg = MI.getOperand(0).getReg();
514  Register SrcReg = MI.getOperand(1).getReg();
515  bool DstIsKill = MI.getOperand(0).isKill();
516  bool SrcIsKill = MI.getOperand(1).isKill();
517  bool ImpIsDead = MI.getOperand(2).isDead();
518  unsigned OpLo = AVR::CPCRdRr;
519  unsigned OpHi = AVR::CPCRdRr;
520  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
521  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
522 
523  auto MIBLO = buildMI(MBB, MBBI, OpLo)
524  .addReg(DstLoReg, getKillRegState(DstIsKill))
525  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
526 
527  // SREG is always implicitly killed
528  MIBLO->getOperand(3).setIsKill();
529 
530  auto MIBHI = buildMI(MBB, MBBI, OpHi)
531  .addReg(DstHiReg, getKillRegState(DstIsKill))
532  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
533 
534  if (ImpIsDead)
535  MIBHI->getOperand(2).setIsDead();
536 
537  // SREG is always implicitly killed
538  MIBHI->getOperand(3).setIsKill();
539 
540  MI.eraseFromParent();
541  return true;
542 }
543 
544 template <>
545 bool AVRExpandPseudo::expand<AVR::LDIWRdK>(Block &MBB, BlockIt MBBI) {
546  MachineInstr &MI = *MBBI;
547  Register DstLoReg, DstHiReg;
548  Register DstReg = MI.getOperand(0).getReg();
549  bool DstIsDead = MI.getOperand(0).isDead();
550  unsigned OpLo = AVR::LDIRdK;
551  unsigned OpHi = AVR::LDIRdK;
552  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
553 
554  auto MIBLO =
555  buildMI(MBB, MBBI, OpLo)
556  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
557 
558  auto MIBHI =
559  buildMI(MBB, MBBI, OpHi)
560  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
561 
562  switch (MI.getOperand(1).getType()) {
564  const GlobalValue *GV = MI.getOperand(1).getGlobal();
565  int64_t Offs = MI.getOperand(1).getOffset();
566  unsigned TF = MI.getOperand(1).getTargetFlags();
567 
568  MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_LO);
569  MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_HI);
570  break;
571  }
573  const BlockAddress *BA = MI.getOperand(1).getBlockAddress();
574  unsigned TF = MI.getOperand(1).getTargetFlags();
575 
576  MIBLO.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_LO));
577  MIBHI.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_HI));
578  break;
579  }
581  unsigned Imm = MI.getOperand(1).getImm();
582 
583  MIBLO.addImm(Imm & 0xff);
584  MIBHI.addImm((Imm >> 8) & 0xff);
585  break;
586  }
587  default:
588  llvm_unreachable("Unknown operand type!");
589  }
590 
591  MI.eraseFromParent();
592  return true;
593 }
594 
595 template <>
596 bool AVRExpandPseudo::expand<AVR::LDSWRdK>(Block &MBB, BlockIt MBBI) {
597  MachineInstr &MI = *MBBI;
598  Register DstLoReg, DstHiReg;
599  Register DstReg = MI.getOperand(0).getReg();
600  bool DstIsDead = MI.getOperand(0).isDead();
601  unsigned OpLo = AVR::LDSRdK;
602  unsigned OpHi = AVR::LDSRdK;
603  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
604 
605  auto MIBLO =
606  buildMI(MBB, MBBI, OpLo)
607  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
608 
609  auto MIBHI =
610  buildMI(MBB, MBBI, OpHi)
611  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
612 
613  switch (MI.getOperand(1).getType()) {
615  const GlobalValue *GV = MI.getOperand(1).getGlobal();
616  int64_t Offs = MI.getOperand(1).getOffset();
617  unsigned TF = MI.getOperand(1).getTargetFlags();
618 
619  MIBLO.addGlobalAddress(GV, Offs, TF);
620  MIBHI.addGlobalAddress(GV, Offs + 1, TF);
621  break;
622  }
624  unsigned Imm = MI.getOperand(1).getImm();
625 
626  MIBLO.addImm(Imm);
627  MIBHI.addImm(Imm + 1);
628  break;
629  }
630  default:
631  llvm_unreachable("Unknown operand type!");
632  }
633 
634  MIBLO.setMemRefs(MI.memoperands());
635  MIBHI.setMemRefs(MI.memoperands());
636 
637  MI.eraseFromParent();
638  return true;
639 }
640 
641 template <>
642 bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
643  MachineInstr &MI = *MBBI;
644  Register DstLoReg, DstHiReg;
645  Register DstReg = MI.getOperand(0).getReg();
646  Register TmpReg = 0; // 0 for no temporary register
647  Register SrcReg = MI.getOperand(1).getReg();
648  bool SrcIsKill = MI.getOperand(1).isKill();
649  unsigned OpLo = AVR::LDRdPtr;
650  unsigned OpHi = AVR::LDDRdPtrQ;
651  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
652 
653  // Use a temporary register if src and dst registers are the same.
654  if (DstReg == SrcReg)
655  TmpReg = scavengeGPR8(MI);
656 
657  Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
658  Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
659 
660  // Load low byte.
661  auto MIBLO = buildMI(MBB, MBBI, OpLo)
662  .addReg(CurDstLoReg, RegState::Define)
663  .addReg(SrcReg);
664 
665  // Push low byte onto stack if necessary.
666  if (TmpReg)
667  buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
668 
669  // Load high byte.
670  auto MIBHI = buildMI(MBB, MBBI, OpHi)
671  .addReg(CurDstHiReg, RegState::Define)
672  .addReg(SrcReg, getKillRegState(SrcIsKill))
673  .addImm(1);
674 
675  if (TmpReg) {
676  // Move the high byte into the final destination.
677  buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg);
678 
679  // Move the low byte from the scratch space into the final destination.
680  buildMI(MBB, MBBI, AVR::POPRd, DstLoReg);
681  }
682 
683  MIBLO.setMemRefs(MI.memoperands());
684  MIBHI.setMemRefs(MI.memoperands());
685 
686  MI.eraseFromParent();
687  return true;
688 }
689 
690 template <>
691 bool AVRExpandPseudo::expand<AVR::LDWRdPtrPi>(Block &MBB, BlockIt MBBI) {
692  MachineInstr &MI = *MBBI;
693  Register DstLoReg, DstHiReg;
694  Register DstReg = MI.getOperand(0).getReg();
695  Register SrcReg = MI.getOperand(1).getReg();
696  bool DstIsDead = MI.getOperand(0).isDead();
697  bool SrcIsDead = MI.getOperand(1).isKill();
698  unsigned OpLo = AVR::LDRdPtrPi;
699  unsigned OpHi = AVR::LDRdPtrPi;
700  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
701 
702  assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
703 
704  auto MIBLO =
705  buildMI(MBB, MBBI, OpLo)
706  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
707  .addReg(SrcReg, RegState::Define)
708  .addReg(SrcReg, RegState::Kill);
709 
710  auto MIBHI =
711  buildMI(MBB, MBBI, OpHi)
712  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
713  .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
714  .addReg(SrcReg, RegState::Kill);
715 
716  MIBLO.setMemRefs(MI.memoperands());
717  MIBHI.setMemRefs(MI.memoperands());
718 
719  MI.eraseFromParent();
720  return true;
721 }
722 
723 template <>
724 bool AVRExpandPseudo::expand<AVR::LDWRdPtrPd>(Block &MBB, BlockIt MBBI) {
725  MachineInstr &MI = *MBBI;
726  Register DstLoReg, DstHiReg;
727  Register DstReg = MI.getOperand(0).getReg();
728  Register SrcReg = MI.getOperand(1).getReg();
729  bool DstIsDead = MI.getOperand(0).isDead();
730  bool SrcIsDead = MI.getOperand(1).isKill();
731  unsigned OpLo = AVR::LDRdPtrPd;
732  unsigned OpHi = AVR::LDRdPtrPd;
733  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
734 
735  assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
736 
737  auto MIBHI =
738  buildMI(MBB, MBBI, OpHi)
739  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
740  .addReg(SrcReg, RegState::Define)
741  .addReg(SrcReg, RegState::Kill);
742 
743  auto MIBLO =
744  buildMI(MBB, MBBI, OpLo)
745  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
746  .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
747  .addReg(SrcReg, RegState::Kill);
748 
749  MIBLO.setMemRefs(MI.memoperands());
750  MIBHI.setMemRefs(MI.memoperands());
751 
752  MI.eraseFromParent();
753  return true;
754 }
755 
756 template <>
757 bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
758  MachineInstr &MI = *MBBI;
759  Register DstLoReg, DstHiReg;
760  Register DstReg = MI.getOperand(0).getReg();
761  Register TmpReg = 0; // 0 for no temporary register
762  Register SrcReg = MI.getOperand(1).getReg();
763  unsigned Imm = MI.getOperand(2).getImm();
764  bool SrcIsKill = MI.getOperand(1).isKill();
765  unsigned OpLo = AVR::LDDRdPtrQ;
766  unsigned OpHi = AVR::LDDRdPtrQ;
767  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
768 
769  // Since we add 1 to the Imm value for the high byte below, and 63 is the
770  // highest Imm value allowed for the instruction, 62 is the limit here.
771  assert(Imm <= 62 && "Offset is out of range");
772 
773  // Use a temporary register if src and dst registers are the same.
774  if (DstReg == SrcReg)
775  TmpReg = scavengeGPR8(MI);
776 
777  Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
778  Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
779 
780  // Load low byte.
781  auto MIBLO = buildMI(MBB, MBBI, OpLo)
782  .addReg(CurDstLoReg, RegState::Define)
783  .addReg(SrcReg)
784  .addImm(Imm);
785 
786  // Push low byte onto stack if necessary.
787  if (TmpReg)
788  buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
789 
790  // Load high byte.
791  auto MIBHI = buildMI(MBB, MBBI, OpHi)
792  .addReg(CurDstHiReg, RegState::Define)
793  .addReg(SrcReg, getKillRegState(SrcIsKill))
794  .addImm(Imm + 1);
795 
796  if (TmpReg) {
797  // Move the high byte into the final destination.
798  buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg);
799 
800  // Move the low byte from the scratch space into the final destination.
801  buildMI(MBB, MBBI, AVR::POPRd, DstLoReg);
802  }
803 
804  MIBLO.setMemRefs(MI.memoperands());
805  MIBHI.setMemRefs(MI.memoperands());
806 
807  MI.eraseFromParent();
808  return true;
809 }
810 
811 template <>
812 bool AVRExpandPseudo::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {
813  MachineInstr &MI = *MBBI;
814  Register DstLoReg, DstHiReg;
815  Register DstReg = MI.getOperand(0).getReg();
816  Register TmpReg = 0; // 0 for no temporary register
817  Register SrcReg = MI.getOperand(1).getReg();
818  bool SrcIsKill = MI.getOperand(1).isKill();
819  unsigned OpLo = AVR::LPMRdZPi;
820  unsigned OpHi = AVR::LPMRdZ;
821  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
822 
823  // Use a temporary register if src and dst registers are the same.
824  if (DstReg == SrcReg)
825  TmpReg = scavengeGPR8(MI);
826 
827  Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
828  Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
829 
830  // Load low byte.
831  auto MIBLO = buildMI(MBB, MBBI, OpLo)
832  .addReg(CurDstLoReg, RegState::Define)
833  .addReg(SrcReg);
834 
835  // Push low byte onto stack if necessary.
836  if (TmpReg)
837  buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
838 
839  // Load high byte.
840  auto MIBHI = buildMI(MBB, MBBI, OpHi)
841  .addReg(CurDstHiReg, RegState::Define)
842  .addReg(SrcReg, getKillRegState(SrcIsKill));
843 
844  if (TmpReg) {
845  // Move the high byte into the final destination.
846  buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg);
847 
848  // Move the low byte from the scratch space into the final destination.
849  buildMI(MBB, MBBI, AVR::POPRd, DstLoReg);
850  }
851 
852  MIBLO.setMemRefs(MI.memoperands());
853  MIBHI.setMemRefs(MI.memoperands());
854 
855  MI.eraseFromParent();
856  return true;
857 }
858 
859 template <>
860 bool AVRExpandPseudo::expand<AVR::LPMWRdZPi>(Block &MBB, BlockIt MBBI) {
861  llvm_unreachable("wide LPMPi is unimplemented");
862 }
863 
864 template <typename Func>
865 bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
866  // Remove the pseudo instruction.
867  MachineInstr &MI = *MBBI;
868 
869  // Store the SREG.
870  buildMI(MBB, MBBI, AVR::INRdA)
871  .addReg(SCRATCH_REGISTER, RegState::Define)
872  .addImm(SREG_ADDR);
873 
874  // Disable exceptions.
875  buildMI(MBB, MBBI, AVR::BCLRs).addImm(7); // CLI
876 
877  f(MI);
878 
879  // Restore the status reg.
880  buildMI(MBB, MBBI, AVR::OUTARr).addImm(SREG_ADDR).addReg(SCRATCH_REGISTER);
881 
882  MI.eraseFromParent();
883  return true;
884 }
885 
886 template <typename Func>
887 bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode, Block &MBB,
888  BlockIt MBBI, Func f) {
889  return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
890  auto Op1 = MI.getOperand(0);
891  auto Op2 = MI.getOperand(1);
892 
893  MachineInstr &NewInst =
894  *buildMI(MBB, MBBI, Opcode).add(Op1).add(Op2).getInstr();
895  f(NewInst);
896  });
897 }
898 
899 bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode, Block &MBB,
900  BlockIt MBBI) {
901  return expandAtomicBinaryOp(Opcode, MBB, MBBI, [](MachineInstr &MI) {});
902 }
903 
904 bool AVRExpandPseudo::expandAtomicArithmeticOp(unsigned Width,
905  unsigned ArithOpcode, Block &MBB,
906  BlockIt MBBI) {
907  return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
908  auto DstReg = MI.getOperand(0).getReg();
909  auto PtrOp = MI.getOperand(1);
910  auto SrcReg = MI.getOperand(2).getReg();
911 
912  unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
913  unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
914 
915  // FIXME: this returns the new value (after the operation), not the old
916  // value as the atomicrmw instruction is supposed to do!
917 
918  // Create the load
919  buildMI(MBB, MBBI, LoadOpcode, DstReg).addReg(PtrOp.getReg());
920 
921  // Create the arithmetic op
922  buildMI(MBB, MBBI, ArithOpcode, DstReg).addReg(DstReg).addReg(SrcReg);
923 
924  // Create the store
925  buildMI(MBB, MBBI, StoreOpcode).add(PtrOp).addReg(DstReg);
926  });
927 }
928 
929 Register AVRExpandPseudo::scavengeGPR8(MachineInstr &MI) {
930  MachineBasicBlock &MBB = *MI.getParent();
931  RegScavenger RS;
932 
933  RS.enterBasicBlock(MBB);
934  RS.forward(MI);
935 
936  BitVector Candidates =
937  TRI->getAllocatableSet(*MBB.getParent(), &AVR::GPR8RegClass);
938 
939  // Exclude all the registers being used by the instruction.
940  for (MachineOperand &MO : MI.operands()) {
941  if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
942  !Register::isVirtualRegister(MO.getReg()))
943  Candidates.reset(MO.getReg());
944  }
945 
946  BitVector Available = RS.getRegsAvailable(&AVR::GPR8RegClass);
947  Available &= Candidates;
948 
949  signed Reg = Available.find_first();
950  assert(Reg != -1 && "ran out of registers");
951  return Reg;
952 }
953 
954 template <>
955 bool AVRExpandPseudo::expand<AVR::AtomicLoad8>(Block &MBB, BlockIt MBBI) {
956  return expandAtomicBinaryOp(AVR::LDRdPtr, MBB, MBBI);
957 }
958 
959 template <>
960 bool AVRExpandPseudo::expand<AVR::AtomicLoad16>(Block &MBB, BlockIt MBBI) {
961  return expandAtomicBinaryOp(AVR::LDWRdPtr, MBB, MBBI);
962 }
963 
964 template <>
965 bool AVRExpandPseudo::expand<AVR::AtomicStore8>(Block &MBB, BlockIt MBBI) {
966  return expandAtomicBinaryOp(AVR::STPtrRr, MBB, MBBI);
967 }
968 
969 template <>
970 bool AVRExpandPseudo::expand<AVR::AtomicStore16>(Block &MBB, BlockIt MBBI) {
971  return expandAtomicBinaryOp(AVR::STWPtrRr, MBB, MBBI);
972 }
973 
974 template <>
975 bool AVRExpandPseudo::expand<AVR::AtomicLoadAdd8>(Block &MBB, BlockIt MBBI) {
976  return expandAtomicArithmeticOp(8, AVR::ADDRdRr, MBB, MBBI);
977 }
978 
979 template <>
980 bool AVRExpandPseudo::expand<AVR::AtomicLoadAdd16>(Block &MBB, BlockIt MBBI) {
981  return expandAtomicArithmeticOp(16, AVR::ADDWRdRr, MBB, MBBI);
982 }
983 
984 template <>
985 bool AVRExpandPseudo::expand<AVR::AtomicLoadSub8>(Block &MBB, BlockIt MBBI) {
986  return expandAtomicArithmeticOp(8, AVR::SUBRdRr, MBB, MBBI);
987 }
988 
989 template <>
990 bool AVRExpandPseudo::expand<AVR::AtomicLoadSub16>(Block &MBB, BlockIt MBBI) {
991  return expandAtomicArithmeticOp(16, AVR::SUBWRdRr, MBB, MBBI);
992 }
993 
994 template <>
995 bool AVRExpandPseudo::expand<AVR::AtomicLoadAnd8>(Block &MBB, BlockIt MBBI) {
996  return expandAtomicArithmeticOp(8, AVR::ANDRdRr, MBB, MBBI);
997 }
998 
999 template <>
1000 bool AVRExpandPseudo::expand<AVR::AtomicLoadAnd16>(Block &MBB, BlockIt MBBI) {
1001  return expandAtomicArithmeticOp(16, AVR::ANDWRdRr, MBB, MBBI);
1002 }
1003 
1004 template <>
1005 bool AVRExpandPseudo::expand<AVR::AtomicLoadOr8>(Block &MBB, BlockIt MBBI) {
1006  return expandAtomicArithmeticOp(8, AVR::ORRdRr, MBB, MBBI);
1007 }
1008 
1009 template <>
1010 bool AVRExpandPseudo::expand<AVR::AtomicLoadOr16>(Block &MBB, BlockIt MBBI) {
1011  return expandAtomicArithmeticOp(16, AVR::ORWRdRr, MBB, MBBI);
1012 }
1013 
1014 template <>
1015 bool AVRExpandPseudo::expand<AVR::AtomicLoadXor8>(Block &MBB, BlockIt MBBI) {
1016  return expandAtomicArithmeticOp(8, AVR::EORRdRr, MBB, MBBI);
1017 }
1018 
1019 template <>
1020 bool AVRExpandPseudo::expand<AVR::AtomicLoadXor16>(Block &MBB, BlockIt MBBI) {
1021  return expandAtomicArithmeticOp(16, AVR::EORWRdRr, MBB, MBBI);
1022 }
1023 
1024 template <>
1025 bool AVRExpandPseudo::expand<AVR::AtomicFence>(Block &MBB, BlockIt MBBI) {
1026  // On AVR, there is only one core and so atomic fences do nothing.
1027  MBBI->eraseFromParent();
1028  return true;
1029 }
1030 
1031 template <>
1032 bool AVRExpandPseudo::expand<AVR::STSWKRr>(Block &MBB, BlockIt MBBI) {
1033  MachineInstr &MI = *MBBI;
1034  Register SrcLoReg, SrcHiReg;
1035  Register SrcReg = MI.getOperand(1).getReg();
1036  bool SrcIsKill = MI.getOperand(1).isKill();
1037  unsigned OpLo = AVR::STSKRr;
1038  unsigned OpHi = AVR::STSKRr;
1039  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1040 
1041  // Write the high byte first in case this address belongs to a special
1042  // I/O address with a special temporary register.
1043  auto MIBHI = buildMI(MBB, MBBI, OpHi);
1044  auto MIBLO = buildMI(MBB, MBBI, OpLo);
1045 
1046  switch (MI.getOperand(0).getType()) {
1048  const GlobalValue *GV = MI.getOperand(0).getGlobal();
1049  int64_t Offs = MI.getOperand(0).getOffset();
1050  unsigned TF = MI.getOperand(0).getTargetFlags();
1051 
1052  MIBLO.addGlobalAddress(GV, Offs, TF);
1053  MIBHI.addGlobalAddress(GV, Offs + 1, TF);
1054  break;
1055  }
1057  unsigned Imm = MI.getOperand(0).getImm();
1058 
1059  MIBLO.addImm(Imm);
1060  MIBHI.addImm(Imm + 1);
1061  break;
1062  }
1063  default:
1064  llvm_unreachable("Unknown operand type!");
1065  }
1066 
1067  MIBLO.addReg(SrcLoReg, getKillRegState(SrcIsKill));
1068  MIBHI.addReg(SrcHiReg, getKillRegState(SrcIsKill));
1069 
1070  MIBLO.setMemRefs(MI.memoperands());
1071  MIBHI.setMemRefs(MI.memoperands());
1072 
1073  MI.eraseFromParent();
1074  return true;
1075 }
1076 
1077 template <>
1078 bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
1079  MachineInstr &MI = *MBBI;
1080  Register SrcLoReg, SrcHiReg;
1081  Register DstReg = MI.getOperand(0).getReg();
1082  Register SrcReg = MI.getOperand(1).getReg();
1083  bool DstIsUndef = MI.getOperand(0).isUndef();
1084  bool SrcIsKill = MI.getOperand(1).isKill();
1085  unsigned OpLo = AVR::STPtrRr;
1086  unsigned OpHi = AVR::STDPtrQRr;
1087  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1088 
1089  //: TODO: need to reverse this order like inw and stsw?
1090  auto MIBLO = buildMI(MBB, MBBI, OpLo)
1091  .addReg(DstReg, getUndefRegState(DstIsUndef))
1092  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1093 
1094  auto MIBHI = buildMI(MBB, MBBI, OpHi)
1095  .addReg(DstReg, getUndefRegState(DstIsUndef))
1096  .addImm(1)
1097  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1098 
1099  MIBLO.setMemRefs(MI.memoperands());
1100  MIBHI.setMemRefs(MI.memoperands());
1101 
1102  MI.eraseFromParent();
1103  return true;
1104 }
1105 
1106 template <>
1107 bool AVRExpandPseudo::expand<AVR::STWPtrPiRr>(Block &MBB, BlockIt MBBI) {
1108  MachineInstr &MI = *MBBI;
1109  Register SrcLoReg, SrcHiReg;
1110  Register DstReg = MI.getOperand(0).getReg();
1111  Register SrcReg = MI.getOperand(2).getReg();
1112  unsigned Imm = MI.getOperand(3).getImm();
1113  bool DstIsDead = MI.getOperand(0).isDead();
1114  bool SrcIsKill = MI.getOperand(2).isKill();
1115  unsigned OpLo = AVR::STPtrPiRr;
1116  unsigned OpHi = AVR::STPtrPiRr;
1117  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1118 
1119  assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1120 
1121  auto MIBLO = buildMI(MBB, MBBI, OpLo)
1122  .addReg(DstReg, RegState::Define)
1123  .addReg(DstReg, RegState::Kill)
1124  .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1125  .addImm(Imm);
1126 
1127  auto MIBHI =
1128  buildMI(MBB, MBBI, OpHi)
1129  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1130  .addReg(DstReg, RegState::Kill)
1131  .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1132  .addImm(Imm);
1133 
1134  MIBLO.setMemRefs(MI.memoperands());
1135  MIBHI.setMemRefs(MI.memoperands());
1136 
1137  MI.eraseFromParent();
1138  return true;
1139 }
1140 
1141 template <>
1142 bool AVRExpandPseudo::expand<AVR::STWPtrPdRr>(Block &MBB, BlockIt MBBI) {
1143  MachineInstr &MI = *MBBI;
1144  Register SrcLoReg, SrcHiReg;
1145  Register DstReg = MI.getOperand(0).getReg();
1146  Register SrcReg = MI.getOperand(2).getReg();
1147  unsigned Imm = MI.getOperand(3).getImm();
1148  bool DstIsDead = MI.getOperand(0).isDead();
1149  bool SrcIsKill = MI.getOperand(2).isKill();
1150  unsigned OpLo = AVR::STPtrPdRr;
1151  unsigned OpHi = AVR::STPtrPdRr;
1152  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1153 
1154  assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1155 
1156  auto MIBHI = buildMI(MBB, MBBI, OpHi)
1157  .addReg(DstReg, RegState::Define)
1158  .addReg(DstReg, RegState::Kill)
1159  .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1160  .addImm(Imm);
1161 
1162  auto MIBLO =
1163  buildMI(MBB, MBBI, OpLo)
1164  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1165  .addReg(DstReg, RegState::Kill)
1166  .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1167  .addImm(Imm);
1168 
1169  MIBLO.setMemRefs(MI.memoperands());
1170  MIBHI.setMemRefs(MI.memoperands());
1171 
1172  MI.eraseFromParent();
1173  return true;
1174 }
1175 
1176 template <>
1177 bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
1178  MachineInstr &MI = *MBBI;
1179  Register SrcLoReg, SrcHiReg;
1180  Register DstReg = MI.getOperand(0).getReg();
1181  Register SrcReg = MI.getOperand(2).getReg();
1182  unsigned Imm = MI.getOperand(1).getImm();
1183  bool DstIsKill = MI.getOperand(0).isKill();
1184  bool SrcIsKill = MI.getOperand(2).isKill();
1185  unsigned OpLo = AVR::STDPtrQRr;
1186  unsigned OpHi = AVR::STDPtrQRr;
1187  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1188 
1189  // Since we add 1 to the Imm value for the high byte below, and 63 is the
1190  // highest Imm value allowed for the instruction, 62 is the limit here.
1191  assert(Imm <= 62 && "Offset is out of range");
1192 
1193  auto MIBLO = buildMI(MBB, MBBI, OpLo)
1194  .addReg(DstReg)
1195  .addImm(Imm)
1196  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1197 
1198  auto MIBHI = buildMI(MBB, MBBI, OpHi)
1199  .addReg(DstReg, getKillRegState(DstIsKill))
1200  .addImm(Imm + 1)
1201  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1202 
1203  MIBLO.setMemRefs(MI.memoperands());
1204  MIBHI.setMemRefs(MI.memoperands());
1205 
1206  MI.eraseFromParent();
1207  return true;
1208 }
1209 
1210 template <>
1211 bool AVRExpandPseudo::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) {
1212  MachineInstr &MI = *MBBI;
1213  Register DstLoReg, DstHiReg;
1214  unsigned Imm = MI.getOperand(1).getImm();
1215  Register DstReg = MI.getOperand(0).getReg();
1216  bool DstIsDead = MI.getOperand(0).isDead();
1217  unsigned OpLo = AVR::INRdA;
1218  unsigned OpHi = AVR::INRdA;
1219  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1220 
1221  // Since we add 1 to the Imm value for the high byte below, and 63 is the
1222  // highest Imm value allowed for the instruction, 62 is the limit here.
1223  assert(Imm <= 62 && "Address is out of range");
1224 
1225  auto MIBLO =
1226  buildMI(MBB, MBBI, OpLo)
1227  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1228  .addImm(Imm);
1229 
1230  auto MIBHI =
1231  buildMI(MBB, MBBI, OpHi)
1232  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1233  .addImm(Imm + 1);
1234 
1235  MIBLO.setMemRefs(MI.memoperands());
1236  MIBHI.setMemRefs(MI.memoperands());
1237 
1238  MI.eraseFromParent();
1239  return true;
1240 }
1241 
1242 template <>
1243 bool AVRExpandPseudo::expand<AVR::OUTWARr>(Block &MBB, BlockIt MBBI) {
1244  MachineInstr &MI = *MBBI;
1245  Register SrcLoReg, SrcHiReg;
1246  unsigned Imm = MI.getOperand(0).getImm();
1247  Register SrcReg = MI.getOperand(1).getReg();
1248  bool SrcIsKill = MI.getOperand(1).isKill();
1249  unsigned OpLo = AVR::OUTARr;
1250  unsigned OpHi = AVR::OUTARr;
1251  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1252 
1253  // Since we add 1 to the Imm value for the high byte below, and 63 is the
1254  // highest Imm value allowed for the instruction, 62 is the limit here.
1255  assert(Imm <= 62 && "Address is out of range");
1256 
1257  // 16 bit I/O writes need the high byte first
1258  auto MIBHI = buildMI(MBB, MBBI, OpHi)
1259  .addImm(Imm + 1)
1260  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1261 
1262  auto MIBLO = buildMI(MBB, MBBI, OpLo)
1263  .addImm(Imm)
1264  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1265 
1266  MIBLO.setMemRefs(MI.memoperands());
1267  MIBHI.setMemRefs(MI.memoperands());
1268 
1269  MI.eraseFromParent();
1270  return true;
1271 }
1272 
1273 template <>
1274 bool AVRExpandPseudo::expand<AVR::PUSHWRr>(Block &MBB, BlockIt MBBI) {
1275  MachineInstr &MI = *MBBI;
1276  Register SrcLoReg, SrcHiReg;
1277  Register SrcReg = MI.getOperand(0).getReg();
1278  bool SrcIsKill = MI.getOperand(0).isKill();
1279  unsigned Flags = MI.getFlags();
1280  unsigned OpLo = AVR::PUSHRr;
1281  unsigned OpHi = AVR::PUSHRr;
1282  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1283 
1284  // Low part
1285  buildMI(MBB, MBBI, OpLo)
1286  .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1287  .setMIFlags(Flags);
1288 
1289  // High part
1290  buildMI(MBB, MBBI, OpHi)
1291  .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1292  .setMIFlags(Flags);
1293 
1294  MI.eraseFromParent();
1295  return true;
1296 }
1297 
1298 template <>
1299 bool AVRExpandPseudo::expand<AVR::POPWRd>(Block &MBB, BlockIt MBBI) {
1300  MachineInstr &MI = *MBBI;
1301  Register DstLoReg, DstHiReg;
1302  Register DstReg = MI.getOperand(0).getReg();
1303  unsigned Flags = MI.getFlags();
1304  unsigned OpLo = AVR::POPRd;
1305  unsigned OpHi = AVR::POPRd;
1306  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1307 
1308  buildMI(MBB, MBBI, OpHi, DstHiReg).setMIFlags(Flags); // High
1309  buildMI(MBB, MBBI, OpLo, DstLoReg).setMIFlags(Flags); // Low
1310 
1311  MI.eraseFromParent();
1312  return true;
1313 }
1314 
1315 template <>
1316 bool AVRExpandPseudo::expand<AVR::ROLBRd>(Block &MBB, BlockIt MBBI) {
1317  // In AVR, the rotate instructions behave quite unintuitively. They rotate
1318  // bits through the carry bit in SREG, effectively rotating over 9 bits,
1319  // instead of 8. This is useful when we are dealing with numbers over
1320  // multiple registers, but when we actually need to rotate stuff, we have
1321  // to explicitly add the carry bit.
1322 
1323  MachineInstr &MI = *MBBI;
1324  unsigned OpShift, OpCarry;
1325  Register DstReg = MI.getOperand(0).getReg();
1326  bool DstIsDead = MI.getOperand(0).isDead();
1327  OpShift = AVR::ADDRdRr;
1328  OpCarry = AVR::ADCRdRr;
1329 
1330  // add r16, r16
1331  // adc r16, r1
1332 
1333  // Shift part
1334  buildMI(MBB, MBBI, OpShift)
1335  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1336  .addReg(DstReg)
1337  .addReg(DstReg);
1338 
1339  // Add the carry bit
1340  auto MIB = buildMI(MBB, MBBI, OpCarry)
1341  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1342  .addReg(DstReg)
1343  .addReg(ZERO_REGISTER);
1344 
1345  // SREG is always implicitly killed
1346  MIB->getOperand(2).setIsKill();
1347 
1348  MI.eraseFromParent();
1349  return true;
1350 }
1351 
1352 template <>
1353 bool AVRExpandPseudo::expand<AVR::RORBRd>(Block &MBB, BlockIt MBBI) {
1354  // In AVR, the rotate instructions behave quite unintuitively. They rotate
1355  // bits through the carry bit in SREG, effectively rotating over 9 bits,
1356  // instead of 8. This is useful when we are dealing with numbers over
1357  // multiple registers, but when we actually need to rotate stuff, we have
1358  // to explicitly add the carry bit.
1359 
1360  MachineInstr &MI = *MBBI;
1361  Register DstReg = MI.getOperand(0).getReg();
1362 
1363  // bst r16, 0
1364  // ror r16
1365  // bld r16, 7
1366 
1367  // Move the lowest bit from DstReg into the T bit
1368  buildMI(MBB, MBBI, AVR::BST).addReg(DstReg).addImm(0);
1369 
1370  // Rotate to the right
1371  buildMI(MBB, MBBI, AVR::RORRd, DstReg).addReg(DstReg);
1372 
1373  // Move the T bit into the highest bit of DstReg.
1374  buildMI(MBB, MBBI, AVR::BLD, DstReg).addReg(DstReg).addImm(7);
1375 
1376  MI.eraseFromParent();
1377  return true;
1378 }
1379 
1380 template <>
1381 bool AVRExpandPseudo::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) {
1382  MachineInstr &MI = *MBBI;
1383  Register DstLoReg, DstHiReg;
1384  Register DstReg = MI.getOperand(0).getReg();
1385  bool DstIsDead = MI.getOperand(0).isDead();
1386  bool DstIsKill = MI.getOperand(1).isKill();
1387  bool ImpIsDead = MI.getOperand(2).isDead();
1388  unsigned OpLo = AVR::ADDRdRr; // ADD Rd, Rd <==> LSL Rd
1389  unsigned OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd
1390  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1391 
1392  // Low part
1393  buildMI(MBB, MBBI, OpLo)
1394  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1395  .addReg(DstLoReg)
1396  .addReg(DstLoReg, getKillRegState(DstIsKill));
1397 
1398  auto MIBHI =
1399  buildMI(MBB, MBBI, OpHi)
1400  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1401  .addReg(DstHiReg)
1402  .addReg(DstHiReg, getKillRegState(DstIsKill));
1403 
1404  if (ImpIsDead)
1405  MIBHI->getOperand(3).setIsDead();
1406 
1407  // SREG is always implicitly killed
1408  MIBHI->getOperand(4).setIsKill();
1409 
1410  MI.eraseFromParent();
1411  return true;
1412 }
1413 
1414 bool AVRExpandPseudo::expandLSLW4Rd(Block &MBB, BlockIt MBBI) {
1415  MachineInstr &MI = *MBBI;
1416  Register DstLoReg, DstHiReg;
1417  Register DstReg = MI.getOperand(0).getReg();
1418  bool DstIsDead = MI.getOperand(0).isDead();
1419  bool DstIsKill = MI.getOperand(1).isKill();
1420  bool ImpIsDead = MI.getOperand(3).isDead();
1421  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1422 
1423  // swap Rh
1424  // swap Rl
1425  buildMI(MBB, MBBI, AVR::SWAPRd)
1426  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1427  .addReg(DstHiReg, getKillRegState(DstIsKill));
1428  buildMI(MBB, MBBI, AVR::SWAPRd)
1429  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1430  .addReg(DstLoReg, getKillRegState(DstIsKill));
1431 
1432  // andi Rh, 0xf0
1433  auto MI0 =
1434  buildMI(MBB, MBBI, AVR::ANDIRdK)
1435  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1436  .addReg(DstHiReg, getKillRegState(DstIsKill))
1437  .addImm(0xf0);
1438  // SREG is implicitly dead.
1439  MI0->getOperand(3).setIsDead();
1440 
1441  // eor Rh, Rl
1442  auto MI1 =
1443  buildMI(MBB, MBBI, AVR::EORRdRr)
1444  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1445  .addReg(DstHiReg, getKillRegState(DstIsKill))
1446  .addReg(DstLoReg);
1447  // SREG is implicitly dead.
1448  MI1->getOperand(3).setIsDead();
1449 
1450  // andi Rl, 0xf0
1451  auto MI2 =
1452  buildMI(MBB, MBBI, AVR::ANDIRdK)
1453  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1454  .addReg(DstLoReg, getKillRegState(DstIsKill))
1455  .addImm(0xf0);
1456  // SREG is implicitly dead.
1457  MI2->getOperand(3).setIsDead();
1458 
1459  // eor Rh, Rl
1460  auto MI3 =
1461  buildMI(MBB, MBBI, AVR::EORRdRr)
1462  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1463  .addReg(DstHiReg, getKillRegState(DstIsKill))
1464  .addReg(DstLoReg);
1465  if (ImpIsDead)
1466  MI3->getOperand(3).setIsDead();
1467 
1468  MI.eraseFromParent();
1469  return true;
1470 }
1471 
1472 bool AVRExpandPseudo::expandLSLW8Rd(Block &MBB, BlockIt MBBI) {
1473  MachineInstr &MI = *MBBI;
1474  Register DstLoReg, DstHiReg;
1475  Register DstReg = MI.getOperand(0).getReg();
1476  bool DstIsDead = MI.getOperand(0).isDead();
1477  bool DstIsKill = MI.getOperand(1).isKill();
1478  bool ImpIsDead = MI.getOperand(3).isDead();
1479  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1480 
1481  // mov Rh, Rl
1482  buildMI(MBB, MBBI, AVR::MOVRdRr)
1483  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1484  .addReg(DstLoReg);
1485 
1486  // clr Rl
1487  auto MIBLO =
1488  buildMI(MBB, MBBI, AVR::EORRdRr)
1489  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1490  .addReg(DstLoReg, getKillRegState(DstIsKill))
1491  .addReg(DstLoReg, getKillRegState(DstIsKill));
1492  if (ImpIsDead)
1493  MIBLO->getOperand(3).setIsDead();
1494 
1495  MI.eraseFromParent();
1496  return true;
1497 }
1498 
1499 bool AVRExpandPseudo::expandLSLW12Rd(Block &MBB, BlockIt MBBI) {
1500  MachineInstr &MI = *MBBI;
1501  Register DstLoReg, DstHiReg;
1502  Register DstReg = MI.getOperand(0).getReg();
1503  bool DstIsDead = MI.getOperand(0).isDead();
1504  bool DstIsKill = MI.getOperand(1).isKill();
1505  bool ImpIsDead = MI.getOperand(3).isDead();
1506  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1507 
1508  // mov Rh, Rl
1509  buildMI(MBB, MBBI, AVR::MOVRdRr)
1510  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1511  .addReg(DstLoReg);
1512 
1513  // swap Rh
1514  buildMI(MBB, MBBI, AVR::SWAPRd)
1515  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1516  .addReg(DstHiReg, getKillRegState(DstIsKill));
1517 
1518  // andi Rh, 0xf0
1519  auto MI0 =
1520  buildMI(MBB, MBBI, AVR::ANDIRdK)
1521  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1522  .addReg(DstHiReg, getKillRegState(DstIsKill))
1523  .addImm(0xf0);
1524  // SREG is implicitly dead.
1525  MI0->getOperand(3).setIsDead();
1526 
1527  // clr Rl
1528  auto MI1 =
1529  buildMI(MBB, MBBI, AVR::EORRdRr)
1530  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1531  .addReg(DstLoReg, getKillRegState(DstIsKill))
1532  .addReg(DstLoReg, getKillRegState(DstIsKill));
1533  if (ImpIsDead)
1534  MI1->getOperand(3).setIsDead();
1535 
1536  MI.eraseFromParent();
1537  return true;
1538 }
1539 
1540 template <>
1541 bool AVRExpandPseudo::expand<AVR::LSLWNRd>(Block &MBB, BlockIt MBBI) {
1542  MachineInstr &MI = *MBBI;
1543  unsigned Imm = MI.getOperand(2).getImm();
1544  switch (Imm) {
1545  case 4:
1546  return expandLSLW4Rd(MBB, MBBI);
1547  case 8:
1548  return expandLSLW8Rd(MBB, MBBI);
1549  case 12:
1550  return expandLSLW12Rd(MBB, MBBI);
1551  default:
1552  llvm_unreachable("unimplemented lslwn");
1553  return false;
1554  }
1555 }
1556 
1557 template <>
1558 bool AVRExpandPseudo::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {
1559  MachineInstr &MI = *MBBI;
1560  Register DstLoReg, DstHiReg;
1561  Register DstReg = MI.getOperand(0).getReg();
1562  bool DstIsDead = MI.getOperand(0).isDead();
1563  bool DstIsKill = MI.getOperand(1).isKill();
1564  bool ImpIsDead = MI.getOperand(2).isDead();
1565  unsigned OpLo = AVR::RORRd;
1566  unsigned OpHi = AVR::LSRRd;
1567  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1568 
1569  // High part
1570  buildMI(MBB, MBBI, OpHi)
1571  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1572  .addReg(DstHiReg, getKillRegState(DstIsKill));
1573 
1574  auto MIBLO =
1575  buildMI(MBB, MBBI, OpLo)
1576  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1577  .addReg(DstLoReg, getKillRegState(DstIsKill));
1578 
1579  if (ImpIsDead)
1580  MIBLO->getOperand(2).setIsDead();
1581 
1582  // SREG is always implicitly killed
1583  MIBLO->getOperand(3).setIsKill();
1584 
1585  MI.eraseFromParent();
1586  return true;
1587 }
1588 
1589 bool AVRExpandPseudo::expandLSRW4Rd(Block &MBB, BlockIt MBBI) {
1590  MachineInstr &MI = *MBBI;
1591  Register DstLoReg, DstHiReg;
1592  Register DstReg = MI.getOperand(0).getReg();
1593  bool DstIsDead = MI.getOperand(0).isDead();
1594  bool DstIsKill = MI.getOperand(1).isKill();
1595  bool ImpIsDead = MI.getOperand(3).isDead();
1596  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1597 
1598  // swap Rh
1599  // swap Rl
1600  buildMI(MBB, MBBI, AVR::SWAPRd)
1601  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1602  .addReg(DstHiReg, getKillRegState(DstIsKill));
1603  buildMI(MBB, MBBI, AVR::SWAPRd)
1604  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1605  .addReg(DstLoReg, getKillRegState(DstIsKill));
1606 
1607  // andi Rl, 0xf
1608  auto MI0 =
1609  buildMI(MBB, MBBI, AVR::ANDIRdK)
1610  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1611  .addReg(DstLoReg, getKillRegState(DstIsKill))
1612  .addImm(0xf);
1613  // SREG is implicitly dead.
1614  MI0->getOperand(3).setIsDead();
1615 
1616  // eor Rl, Rh
1617  auto MI1 =
1618  buildMI(MBB, MBBI, AVR::EORRdRr)
1619  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1620  .addReg(DstLoReg, getKillRegState(DstIsKill))
1621  .addReg(DstHiReg);
1622  // SREG is implicitly dead.
1623  MI1->getOperand(3).setIsDead();
1624 
1625  // andi Rh, 0xf
1626  auto MI2 =
1627  buildMI(MBB, MBBI, AVR::ANDIRdK)
1628  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1629  .addReg(DstHiReg, getKillRegState(DstIsKill))
1630  .addImm(0xf);
1631  // SREG is implicitly dead.
1632  MI2->getOperand(3).setIsDead();
1633 
1634  // eor Rl, Rh
1635  auto MI3 =
1636  buildMI(MBB, MBBI, AVR::EORRdRr)
1637  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1638  .addReg(DstLoReg, getKillRegState(DstIsKill))
1639  .addReg(DstHiReg);
1640  if (ImpIsDead)
1641  MI3->getOperand(3).setIsDead();
1642 
1643  MI.eraseFromParent();
1644  return true;
1645 }
1646 
1647 bool AVRExpandPseudo::expandLSRW8Rd(Block &MBB, BlockIt MBBI) {
1648  MachineInstr &MI = *MBBI;
1649  Register DstLoReg, DstHiReg;
1650  Register DstReg = MI.getOperand(0).getReg();
1651  bool DstIsDead = MI.getOperand(0).isDead();
1652  bool DstIsKill = MI.getOperand(1).isKill();
1653  bool ImpIsDead = MI.getOperand(3).isDead();
1654  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1655 
1656  // Move upper byte to lower byte.
1657  buildMI(MBB, MBBI, AVR::MOVRdRr)
1658  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1659  .addReg(DstHiReg);
1660 
1661  // Clear upper byte.
1662  auto MIBHI =
1663  buildMI(MBB, MBBI, AVR::EORRdRr)
1664  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1665  .addReg(DstHiReg, getKillRegState(DstIsKill))
1666  .addReg(DstHiReg, getKillRegState(DstIsKill));
1667  if (ImpIsDead)
1668  MIBHI->getOperand(3).setIsDead();
1669 
1670  MI.eraseFromParent();
1671  return true;
1672 }
1673 
1674 bool AVRExpandPseudo::expandLSRW12Rd(Block &MBB, BlockIt MBBI) {
1675  MachineInstr &MI = *MBBI;
1676  Register DstLoReg, DstHiReg;
1677  Register DstReg = MI.getOperand(0).getReg();
1678  bool DstIsDead = MI.getOperand(0).isDead();
1679  bool DstIsKill = MI.getOperand(1).isKill();
1680  bool ImpIsDead = MI.getOperand(3).isDead();
1681  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1682 
1683  // Move upper byte to lower byte.
1684  buildMI(MBB, MBBI, AVR::MOVRdRr)
1685  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1686  .addReg(DstHiReg);
1687 
1688  // swap Rl
1689  buildMI(MBB, MBBI, AVR::SWAPRd)
1690  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1691  .addReg(DstLoReg, getKillRegState(DstIsKill));
1692 
1693  // andi Rl, 0xf
1694  auto MI0 =
1695  buildMI(MBB, MBBI, AVR::ANDIRdK)
1696  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1697  .addReg(DstLoReg, getKillRegState(DstIsKill))
1698  .addImm(0xf);
1699  // SREG is implicitly dead.
1700  MI0->getOperand(3).setIsDead();
1701 
1702  // Clear upper byte.
1703  auto MIBHI =
1704  buildMI(MBB, MBBI, AVR::EORRdRr)
1705  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1706  .addReg(DstHiReg, getKillRegState(DstIsKill))
1707  .addReg(DstHiReg, getKillRegState(DstIsKill));
1708  if (ImpIsDead)
1709  MIBHI->getOperand(3).setIsDead();
1710 
1711  MI.eraseFromParent();
1712  return true;
1713 }
1714 
1715 template <>
1716 bool AVRExpandPseudo::expand<AVR::LSRWNRd>(Block &MBB, BlockIt MBBI) {
1717  MachineInstr &MI = *MBBI;
1718  unsigned Imm = MI.getOperand(2).getImm();
1719  switch (Imm) {
1720  case 4:
1721  return expandLSRW4Rd(MBB, MBBI);
1722  case 8:
1723  return expandLSRW8Rd(MBB, MBBI);
1724  case 12:
1725  return expandLSRW12Rd(MBB, MBBI);
1726  default:
1727  llvm_unreachable("unimplemented lsrwn");
1728  return false;
1729  }
1730 }
1731 
1732 template <>
1733 bool AVRExpandPseudo::expand<AVR::RORWRd>(Block &MBB, BlockIt MBBI) {
1734  llvm_unreachable("RORW unimplemented");
1735  return false;
1736 }
1737 
1738 template <>
1739 bool AVRExpandPseudo::expand<AVR::ROLWRd>(Block &MBB, BlockIt MBBI) {
1740  llvm_unreachable("ROLW unimplemented");
1741  return false;
1742 }
1743 
1744 template <>
1745 bool AVRExpandPseudo::expand<AVR::ASRWRd>(Block &MBB, BlockIt MBBI) {
1746  MachineInstr &MI = *MBBI;
1747  Register DstLoReg, DstHiReg;
1748  Register DstReg = MI.getOperand(0).getReg();
1749  bool DstIsDead = MI.getOperand(0).isDead();
1750  bool DstIsKill = MI.getOperand(1).isKill();
1751  bool ImpIsDead = MI.getOperand(2).isDead();
1752  unsigned OpLo = AVR::RORRd;
1753  unsigned OpHi = AVR::ASRRd;
1754  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1755 
1756  // High part
1757  buildMI(MBB, MBBI, OpHi)
1758  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1759  .addReg(DstHiReg, getKillRegState(DstIsKill));
1760 
1761  auto MIBLO =
1762  buildMI(MBB, MBBI, OpLo)
1763  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1764  .addReg(DstLoReg, getKillRegState(DstIsKill));
1765 
1766  if (ImpIsDead)
1767  MIBLO->getOperand(2).setIsDead();
1768 
1769  // SREG is always implicitly killed
1770  MIBLO->getOperand(3).setIsKill();
1771 
1772  MI.eraseFromParent();
1773  return true;
1774 }
1775 
1776 bool AVRExpandPseudo::expandASRW8Rd(Block &MBB, BlockIt MBBI) {
1777  MachineInstr &MI = *MBBI;
1778  Register DstLoReg, DstHiReg;
1779  Register DstReg = MI.getOperand(0).getReg();
1780  bool DstIsDead = MI.getOperand(0).isDead();
1781  bool DstIsKill = MI.getOperand(1).isKill();
1782  bool ImpIsDead = MI.getOperand(3).isDead();
1783  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1784 
1785  // Move upper byte to lower byte.
1786  buildMI(MBB, MBBI, AVR::MOVRdRr)
1787  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1788  .addReg(DstHiReg);
1789 
1790  // Move the sign bit to the C flag.
1791  buildMI(MBB, MBBI, AVR::ADDRdRr)
1792  .addReg(DstHiReg, RegState::Define, getDeadRegState(DstIsDead))
1793  .addReg(DstHiReg, getKillRegState(DstIsKill) | getDeadRegState(DstIsDead))
1794  .addReg(DstHiReg, getKillRegState(DstIsKill));
1795 
1796  // Set upper byte to 0 or -1.
1797  auto MIBHI =
1798  buildMI(MBB, MBBI, AVR::SBCRdRr)
1799  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1800  .addReg(DstHiReg, getKillRegState(DstIsKill))
1801  .addReg(DstHiReg, getKillRegState(DstIsKill));
1802  if (ImpIsDead)
1803  MIBHI->getOperand(3).setIsDead();
1804 
1805  MI.eraseFromParent();
1806  return true;
1807 }
1808 
1809 template <>
1810 bool AVRExpandPseudo::expand<AVR::ASRWNRd>(Block &MBB, BlockIt MBBI) {
1811  MachineInstr &MI = *MBBI;
1812  unsigned Imm = MI.getOperand(2).getImm();
1813  switch (Imm) {
1814  case 8:
1815  return expandASRW8Rd(MBB, MBBI);
1816  default:
1817  llvm_unreachable("unimplemented asrwn");
1818  return false;
1819  }
1820 }
1821 
1822 bool AVRExpandPseudo::expandLSLB7Rd(Block &MBB, BlockIt MBBI) {
1823  MachineInstr &MI = *MBBI;
1824  Register DstReg = MI.getOperand(0).getReg();
1825  bool DstIsDead = MI.getOperand(0).isDead();
1826  bool DstIsKill = MI.getOperand(1).isKill();
1827  bool ImpIsDead = MI.getOperand(3).isDead();
1828 
1829  // ror r24
1830  // clr r24
1831  // ror r24
1832 
1833  buildMI(MBB, MBBI, AVR::RORRd)
1834  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1835  .addReg(DstReg, getKillRegState(DstIsKill))
1836  ->getOperand(3)
1837  .setIsUndef(true);
1838 
1839  buildMI(MBB, MBBI, AVR::EORRdRr)
1840  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1841  .addReg(DstReg, getKillRegState(DstIsKill))
1842  .addReg(DstReg, getKillRegState(DstIsKill));
1843 
1844  auto MIRRC =
1845  buildMI(MBB, MBBI, AVR::RORRd)
1846  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1847  .addReg(DstReg, getKillRegState(DstIsKill));
1848 
1849  if (ImpIsDead)
1850  MIRRC->getOperand(2).setIsDead();
1851 
1852  // SREG is always implicitly killed
1853  MIRRC->getOperand(3).setIsKill();
1854 
1855  MI.eraseFromParent();
1856  return true;
1857 }
1858 
1859 template <>
1860 bool AVRExpandPseudo::expand<AVR::LSLBNRd>(Block &MBB, BlockIt MBBI) {
1861  MachineInstr &MI = *MBBI;
1862  unsigned Imm = MI.getOperand(2).getImm();
1863  switch (Imm) {
1864  case 7:
1865  return expandLSLB7Rd(MBB, MBBI);
1866  default:
1867  llvm_unreachable("unimplemented lslbn");
1868  return false;
1869  }
1870 }
1871 
1872 bool AVRExpandPseudo::expandLSRB7Rd(Block &MBB, BlockIt MBBI) {
1873  MachineInstr &MI = *MBBI;
1874  Register DstReg = MI.getOperand(0).getReg();
1875  bool DstIsDead = MI.getOperand(0).isDead();
1876  bool DstIsKill = MI.getOperand(1).isKill();
1877  bool ImpIsDead = MI.getOperand(3).isDead();
1878 
1879  // rol r24
1880  // clr r24
1881  // rol r24
1882 
1883  buildMI(MBB, MBBI, AVR::ADCRdRr)
1884  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1885  .addReg(DstReg, getKillRegState(DstIsKill))
1886  .addReg(DstReg, getKillRegState(DstIsKill))
1887  ->getOperand(4)
1888  .setIsUndef(true);
1889 
1890  buildMI(MBB, MBBI, AVR::EORRdRr)
1891  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1892  .addReg(DstReg, getKillRegState(DstIsKill))
1893  .addReg(DstReg, getKillRegState(DstIsKill));
1894 
1895  auto MIRRC =
1896  buildMI(MBB, MBBI, AVR::ADCRdRr)
1897  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1898  .addReg(DstReg, getKillRegState(DstIsKill))
1899  .addReg(DstReg, getKillRegState(DstIsKill));
1900 
1901  if (ImpIsDead)
1902  MIRRC->getOperand(3).setIsDead();
1903 
1904  // SREG is always implicitly killed
1905  MIRRC->getOperand(4).setIsKill();
1906 
1907  MI.eraseFromParent();
1908  return true;
1909 }
1910 
1911 template <>
1912 bool AVRExpandPseudo::expand<AVR::LSRBNRd>(Block &MBB, BlockIt MBBI) {
1913  MachineInstr &MI = *MBBI;
1914  unsigned Imm = MI.getOperand(2).getImm();
1915  switch (Imm) {
1916  case 7:
1917  return expandLSRB7Rd(MBB, MBBI);
1918  default:
1919  llvm_unreachable("unimplemented lsrbn");
1920  return false;
1921  }
1922 }
1923 
1924 bool AVRExpandPseudo::expandASRB7Rd(Block &MBB, BlockIt MBBI) {
1925  MachineInstr &MI = *MBBI;
1926  Register DstReg = MI.getOperand(0).getReg();
1927  bool DstIsDead = MI.getOperand(0).isDead();
1928  bool DstIsKill = MI.getOperand(1).isKill();
1929  bool ImpIsDead = MI.getOperand(3).isDead();
1930 
1931  // lsl r24
1932  // sbc r24, r24
1933 
1934  buildMI(MBB, MBBI, AVR::ADDRdRr)
1935  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1936  .addReg(DstReg, getKillRegState(DstIsKill))
1937  .addReg(DstReg, getKillRegState(DstIsKill));
1938 
1939  auto MIRRC =
1940  buildMI(MBB, MBBI, AVR::SBCRdRr)
1941  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1942  .addReg(DstReg, getKillRegState(DstIsKill))
1943  .addReg(DstReg, getKillRegState(DstIsKill));
1944 
1945  if (ImpIsDead)
1946  MIRRC->getOperand(3).setIsDead();
1947 
1948  // SREG is always implicitly killed
1949  MIRRC->getOperand(4).setIsKill();
1950 
1951  MI.eraseFromParent();
1952  return true;
1953 }
1954 
1955 template <>
1956 bool AVRExpandPseudo::expand<AVR::ASRBNRd>(Block &MBB, BlockIt MBBI) {
1957  MachineInstr &MI = *MBBI;
1958  unsigned Imm = MI.getOperand(2).getImm();
1959  switch (Imm) {
1960  case 7:
1961  return expandASRB7Rd(MBB, MBBI);
1962  default:
1963  llvm_unreachable("unimplemented asrbn");
1964  return false;
1965  }
1966 }
1967 
1968 template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {
1969  MachineInstr &MI = *MBBI;
1970  Register DstLoReg, DstHiReg;
1971  // sext R17:R16, R17
1972  // mov r16, r17
1973  // lsl r17
1974  // sbc r17, r17
1975  // sext R17:R16, R13
1976  // mov r16, r13
1977  // mov r17, r13
1978  // lsl r17
1979  // sbc r17, r17
1980  // sext R17:R16, R16
1981  // mov r17, r16
1982  // lsl r17
1983  // sbc r17, r17
1984  Register DstReg = MI.getOperand(0).getReg();
1985  Register SrcReg = MI.getOperand(1).getReg();
1986  bool DstIsDead = MI.getOperand(0).isDead();
1987  bool SrcIsKill = MI.getOperand(1).isKill();
1988  bool ImpIsDead = MI.getOperand(2).isDead();
1989  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1990 
1991  if (SrcReg != DstLoReg) {
1992  auto MOV =
1993  buildMI(MBB, MBBI, AVR::MOVRdRr)
1994  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1995  .addReg(SrcReg);
1996 
1997  if (SrcReg == DstHiReg) {
1998  MOV->getOperand(1).setIsKill();
1999  }
2000  }
2001 
2002  if (SrcReg != DstHiReg) {
2003  buildMI(MBB, MBBI, AVR::MOVRdRr)
2004  .addReg(DstHiReg, RegState::Define)
2005  .addReg(SrcReg, getKillRegState(SrcIsKill));
2006  }
2007 
2008  buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr
2009  .addReg(DstHiReg, RegState::Define)
2010  .addReg(DstHiReg)
2011  .addReg(DstHiReg, RegState::Kill);
2012 
2013  auto SBC =
2014  buildMI(MBB, MBBI, AVR::SBCRdRr)
2015  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2016  .addReg(DstHiReg, RegState::Kill)
2017  .addReg(DstHiReg, RegState::Kill);
2018 
2019  if (ImpIsDead)
2020  SBC->getOperand(3).setIsDead();
2021 
2022  // SREG is always implicitly killed
2023  SBC->getOperand(4).setIsKill();
2024 
2025  MI.eraseFromParent();
2026  return true;
2027 }
2028 
2029 template <> bool AVRExpandPseudo::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) {
2030  MachineInstr &MI = *MBBI;
2031  Register DstLoReg, DstHiReg;
2032  // zext R25:R24, R20
2033  // mov R24, R20
2034  // eor R25, R25
2035  // zext R25:R24, R24
2036  // eor R25, R25
2037  // zext R25:R24, R25
2038  // mov R24, R25
2039  // eor R25, R25
2040  Register DstReg = MI.getOperand(0).getReg();
2041  Register SrcReg = MI.getOperand(1).getReg();
2042  bool DstIsDead = MI.getOperand(0).isDead();
2043  bool SrcIsKill = MI.getOperand(1).isKill();
2044  bool ImpIsDead = MI.getOperand(2).isDead();
2045  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2046 
2047  if (SrcReg != DstLoReg) {
2048  buildMI(MBB, MBBI, AVR::MOVRdRr)
2049  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2050  .addReg(SrcReg, getKillRegState(SrcIsKill));
2051  }
2052 
2053  auto EOR =
2054  buildMI(MBB, MBBI, AVR::EORRdRr)
2055  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2056  .addReg(DstHiReg, RegState::Kill | RegState::Undef)
2057  .addReg(DstHiReg, RegState::Kill | RegState::Undef);
2058 
2059  if (ImpIsDead)
2060  EOR->getOperand(3).setIsDead();
2061 
2062  MI.eraseFromParent();
2063  return true;
2064 }
2065 
2066 template <>
2067 bool AVRExpandPseudo::expand<AVR::SPREAD>(Block &MBB, BlockIt MBBI) {
2068  MachineInstr &MI = *MBBI;
2069  Register DstLoReg, DstHiReg;
2070  Register DstReg = MI.getOperand(0).getReg();
2071  bool DstIsDead = MI.getOperand(0).isDead();
2072  unsigned Flags = MI.getFlags();
2073  unsigned OpLo = AVR::INRdA;
2074  unsigned OpHi = AVR::INRdA;
2075  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2076 
2077  // Low part
2078  buildMI(MBB, MBBI, OpLo)
2079  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2080  .addImm(0x3d)
2081  .setMIFlags(Flags);
2082 
2083  // High part
2084  buildMI(MBB, MBBI, OpHi)
2085  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2086  .addImm(0x3e)
2087  .setMIFlags(Flags);
2088 
2089  MI.eraseFromParent();
2090  return true;
2091 }
2092 
2093 template <>
2094 bool AVRExpandPseudo::expand<AVR::SPWRITE>(Block &MBB, BlockIt MBBI) {
2095  MachineInstr &MI = *MBBI;
2096  Register SrcLoReg, SrcHiReg;
2097  Register SrcReg = MI.getOperand(1).getReg();
2098  bool SrcIsKill = MI.getOperand(1).isKill();
2099  unsigned Flags = MI.getFlags();
2100  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
2101 
2102  buildMI(MBB, MBBI, AVR::INRdA)
2103  .addReg(AVR::R0, RegState::Define)
2104  .addImm(SREG_ADDR)
2105  .setMIFlags(Flags);
2106 
2107  buildMI(MBB, MBBI, AVR::BCLRs).addImm(0x07).setMIFlags(Flags);
2108 
2109  buildMI(MBB, MBBI, AVR::OUTARr)
2110  .addImm(0x3e)
2111  .addReg(SrcHiReg, getKillRegState(SrcIsKill))
2112  .setMIFlags(Flags);
2113 
2114  buildMI(MBB, MBBI, AVR::OUTARr)
2115  .addImm(SREG_ADDR)
2116  .addReg(AVR::R0, RegState::Kill)
2117  .setMIFlags(Flags);
2118 
2119  buildMI(MBB, MBBI, AVR::OUTARr)
2120  .addImm(0x3d)
2121  .addReg(SrcLoReg, getKillRegState(SrcIsKill))
2122  .setMIFlags(Flags);
2123 
2124  MI.eraseFromParent();
2125  return true;
2126 }
2127 
2128 bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
2129  MachineInstr &MI = *MBBI;
2130  int Opcode = MBBI->getOpcode();
2131 
2132 #define EXPAND(Op) \
2133  case Op: \
2134  return expand<Op>(MBB, MI)
2135 
2136  switch (Opcode) {
2137  EXPAND(AVR::ADDWRdRr);
2138  EXPAND(AVR::ADCWRdRr);
2139  EXPAND(AVR::SUBWRdRr);
2140  EXPAND(AVR::SUBIWRdK);
2141  EXPAND(AVR::SBCWRdRr);
2142  EXPAND(AVR::SBCIWRdK);
2143  EXPAND(AVR::ANDWRdRr);
2144  EXPAND(AVR::ANDIWRdK);
2145  EXPAND(AVR::ORWRdRr);
2146  EXPAND(AVR::ORIWRdK);
2147  EXPAND(AVR::EORWRdRr);
2148  EXPAND(AVR::COMWRd);
2149  EXPAND(AVR::NEGWRd);
2150  EXPAND(AVR::CPWRdRr);
2151  EXPAND(AVR::CPCWRdRr);
2152  EXPAND(AVR::LDIWRdK);
2153  EXPAND(AVR::LDSWRdK);
2154  EXPAND(AVR::LDWRdPtr);
2155  EXPAND(AVR::LDWRdPtrPi);
2156  EXPAND(AVR::LDWRdPtrPd);
2157  case AVR::LDDWRdYQ: //: FIXME: remove this once PR13375 gets fixed
2158  EXPAND(AVR::LDDWRdPtrQ);
2159  EXPAND(AVR::LPMWRdZ);
2160  EXPAND(AVR::LPMWRdZPi);
2161  EXPAND(AVR::AtomicLoad8);
2162  EXPAND(AVR::AtomicLoad16);
2163  EXPAND(AVR::AtomicStore8);
2164  EXPAND(AVR::AtomicStore16);
2165  EXPAND(AVR::AtomicLoadAdd8);
2166  EXPAND(AVR::AtomicLoadAdd16);
2167  EXPAND(AVR::AtomicLoadSub8);
2168  EXPAND(AVR::AtomicLoadSub16);
2169  EXPAND(AVR::AtomicLoadAnd8);
2170  EXPAND(AVR::AtomicLoadAnd16);
2171  EXPAND(AVR::AtomicLoadOr8);
2172  EXPAND(AVR::AtomicLoadOr16);
2173  EXPAND(AVR::AtomicLoadXor8);
2174  EXPAND(AVR::AtomicLoadXor16);
2175  EXPAND(AVR::AtomicFence);
2176  EXPAND(AVR::STSWKRr);
2177  EXPAND(AVR::STWPtrRr);
2178  EXPAND(AVR::STWPtrPiRr);
2179  EXPAND(AVR::STWPtrPdRr);
2180  EXPAND(AVR::STDWPtrQRr);
2181  EXPAND(AVR::INWRdA);
2182  EXPAND(AVR::OUTWARr);
2183  EXPAND(AVR::PUSHWRr);
2184  EXPAND(AVR::POPWRd);
2185  EXPAND(AVR::ROLBRd);
2186  EXPAND(AVR::RORBRd);
2187  EXPAND(AVR::LSLWRd);
2188  EXPAND(AVR::LSRWRd);
2189  EXPAND(AVR::RORWRd);
2190  EXPAND(AVR::ROLWRd);
2191  EXPAND(AVR::ASRWRd);
2192  EXPAND(AVR::LSLWNRd);
2193  EXPAND(AVR::LSRWNRd);
2194  EXPAND(AVR::ASRWNRd);
2195  EXPAND(AVR::LSLBNRd);
2196  EXPAND(AVR::LSRBNRd);
2197  EXPAND(AVR::ASRBNRd);
2198  EXPAND(AVR::SEXT);
2199  EXPAND(AVR::ZEXT);
2200  EXPAND(AVR::SPREAD);
2201  EXPAND(AVR::SPWRITE);
2202  }
2203 #undef EXPAND
2204  return false;
2205 }
2206 
2207 } // end of anonymous namespace
2208 
2209 INITIALIZE_PASS(AVRExpandPseudo, "avr-expand-pseudo", AVR_EXPAND_PSEUDO_NAME,
2210  false, false)
2211 namespace llvm {
2212 
2213 FunctionPass *createAVRExpandPseudoPass() { return new AVRExpandPseudo(); }
2214 
2215 } // end of namespace llvm
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:63
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:53
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
EXPAND
#define EXPAND(Op)
llvm::TargetRegisterInfo::getAllocatableSet
BitVector getAllocatableSet(const MachineFunction &MF, const TargetRegisterClass *RC=nullptr) const
Returns a bitset indexed by register number indicating if a register is allocatable or not.
Definition: TargetRegisterInfo.cpp:255
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
INITIALIZE_PASS
INITIALIZE_PASS(AVRExpandPseudo, "avr-expand-pseudo", AVR_EXPAND_PSEUDO_NAME, false, false) namespace llvm
Definition: AVRExpandPseudoInsts.cpp:2209
llvm::getDeadRegState
unsigned getDeadRegState(bool B)
Definition: MachineInstrBuilder.h:511
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::getUndefRegState
unsigned getUndefRegState(bool B)
Definition: MachineInstrBuilder.h:514
MachineRegisterInfo.h
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:636
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:62
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
AvailabilityState::Available
@ Available
We know the block is fully available. This is a fixpoint.
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::AVRSubtarget
A specific AVR target MCU.
Definition: AVRSubtarget.h:31
llvm::MachineBasicBlock::eraseFromParent
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition: MachineBasicBlock.cpp:1332
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:717
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:169
LoopDeletionResult::Modified
@ Modified
llvm::AVRSubtarget::getInstrInfo
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:41
llvm::initializeAVRExpandPseudoPass
void initializeAVRExpandPseudoPass(PassRegistry &)
AVR_EXPAND_PSEUDO_NAME
#define AVR_EXPAND_PSEUDO_NAME
Definition: AVRExpandPseudoInsts.cpp:28
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
llvm::BitVector
Definition: BitVector.h:74
llvm::AArch64ISD::SBC
@ SBC
Definition: AArch64ISelLowering.h:77
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:626
llvm::GlobalValue
Definition: GlobalValue.h:44
expand
static Expected< BitVector > expand(StringRef S, StringRef Original)
Definition: GlobPattern.cpp:27
llvm::MachineFunctionProperties::Property::TracksLiveness
@ TracksLiveness
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::AVRRegisterInfo
Utilities relating to AVR registers.
Definition: AVRRegisterInfo.h:24
llvm::RegScavenger
Definition: RegisterScavenging.h:34
MachineFunctionPass.h
AVRTargetMachine.h
llvm::Register::isVirtualRegister
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:71
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineOperand::CreateBA
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:866
AVRMCTargetDesc.h
llvm::AVRII::MO_NEG
@ MO_NEG
On a symbol operand, this represents it has to be negated.
Definition: AVRInstrInfo.h:58
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:848
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::RegScavenger::enterBasicBlock
void enterBasicBlock(MachineBasicBlock &MBB)
Start tracking liveness from the begin of basic block MBB.
Definition: RegisterScavenging.cpp:84
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
AVR.h
llvm::RegScavenger::forward
void forward()
Move the internal MBB iterator and update register states.
Definition: RegisterScavenging.cpp:157
llvm::BitVector::reset
BitVector & reset()
Definition: BitVector.h:384
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:410
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:508
llvm::RegScavenger::getRegsAvailable
BitVector getRegsAvailable(const TargetRegisterClass *RC)
Return all available registers in the register class in Mask.
Definition: RegisterScavenging.cpp:279
llvm::AVRSubtarget::getRegisterInfo
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:51
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
AVRInstrInfo.h
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
RegisterScavenging.h
llvm::AVRII::MO_LO
@ MO_LO
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:52
TargetRegisterInfo.h
llvm::createAVRExpandPseudoPass
FunctionPass * createAVRExpandPseudoPass()
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::SISrcMods::SEXT
@ SEXT
Definition: SIDefines.h:208
getReg
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Definition: MipsDisassembler.cpp:580
llvm::AVRII::MO_HI
@ MO_HI
On a symbol operand, this represents the hi part.
Definition: AVRInstrInfo.h:55
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37