LLVM  16.0.0git
AVRExpandPseudoInsts.cpp
Go to the documentation of this file.
1 //===-- AVRExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass that expands pseudo instructions into target
10 // instructions. This pass should be run after register allocation but before
11 // the post-regalloc scheduling pass.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "AVR.h"
16 #include "AVRInstrInfo.h"
17 #include "AVRTargetMachine.h"
19 
24 
25 using namespace llvm;
26 
27 #define AVR_EXPAND_PSEUDO_NAME "AVR pseudo instruction expansion pass"
28 
29 namespace {
30 
31 /// Expands "placeholder" instructions marked as pseudo into
32 /// actual AVR instructions.
33 class AVRExpandPseudo : public MachineFunctionPass {
34 public:
35  static char ID;
36 
37  AVRExpandPseudo() : MachineFunctionPass(ID) {
39  }
40 
41  bool runOnMachineFunction(MachineFunction &MF) override;
42 
43  StringRef getPassName() const override { return AVR_EXPAND_PSEUDO_NAME; }
44 
45 private:
46  typedef MachineBasicBlock Block;
47  typedef Block::iterator BlockIt;
48 
49  const AVRRegisterInfo *TRI;
50  const TargetInstrInfo *TII;
51 
52  bool expandMBB(Block &MBB);
53  bool expandMI(Block &MBB, BlockIt MBBI);
54  template <unsigned OP> bool expand(Block &MBB, BlockIt MBBI);
55 
56  MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
57  return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
58  }
59 
60  MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode,
61  Register DstReg) {
62  return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
63  }
64 
65  MachineRegisterInfo &getRegInfo(Block &MBB) {
66  return MBB.getParent()->getRegInfo();
67  }
68 
69  bool expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI);
70  bool expandLogic(unsigned Op, Block &MBB, BlockIt MBBI);
71  bool expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI);
72  bool isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const;
73 
74  template <typename Func> bool expandAtomic(Block &MBB, BlockIt MBBI, Func f);
75 
76  template <typename Func>
77  bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI, Func f);
78 
79  bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI);
80 
81  /// Specific shift implementation for int8.
82  bool expandLSLB7Rd(Block &MBB, BlockIt MBBI);
83  bool expandLSRB7Rd(Block &MBB, BlockIt MBBI);
84  bool expandASRB6Rd(Block &MBB, BlockIt MBBI);
85  bool expandASRB7Rd(Block &MBB, BlockIt MBBI);
86 
87  /// Specific shift implementation for int16.
88  bool expandLSLW4Rd(Block &MBB, BlockIt MBBI);
89  bool expandLSRW4Rd(Block &MBB, BlockIt MBBI);
90  bool expandASRW7Rd(Block &MBB, BlockIt MBBI);
91  bool expandLSLW8Rd(Block &MBB, BlockIt MBBI);
92  bool expandLSRW8Rd(Block &MBB, BlockIt MBBI);
93  bool expandASRW8Rd(Block &MBB, BlockIt MBBI);
94  bool expandLSLW12Rd(Block &MBB, BlockIt MBBI);
95  bool expandLSRW12Rd(Block &MBB, BlockIt MBBI);
96  bool expandASRW14Rd(Block &MBB, BlockIt MBBI);
97  bool expandASRW15Rd(Block &MBB, BlockIt MBBI);
98 
99  // Common implementation of LPMWRdZ and ELPMWRdZ.
100  bool expandLPMWELPMW(Block &MBB, BlockIt MBBI, bool IsExt);
101 };
102 
103 char AVRExpandPseudo::ID = 0;
104 
105 bool AVRExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
106  bool Modified = false;
107 
108  BlockIt MBBI = MBB.begin(), E = MBB.end();
109  while (MBBI != E) {
110  BlockIt NMBBI = std::next(MBBI);
111  Modified |= expandMI(MBB, MBBI);
112  MBBI = NMBBI;
113  }
114 
115  return Modified;
116 }
117 
118 bool AVRExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
119  bool Modified = false;
120 
121  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
122  TRI = STI.getRegisterInfo();
123  TII = STI.getInstrInfo();
124 
125  for (Block &MBB : MF) {
126  bool ContinueExpanding = true;
127  unsigned ExpandCount = 0;
128 
129  // Continue expanding the block until all pseudos are expanded.
130  do {
131  assert(ExpandCount < 10 && "pseudo expand limit reached");
132  (void)ExpandCount;
133 
134  bool BlockModified = expandMBB(MBB);
135  Modified |= BlockModified;
136  ExpandCount++;
137 
138  ContinueExpanding = BlockModified;
139  } while (ContinueExpanding);
140  }
141 
142  return Modified;
143 }
144 
145 bool AVRExpandPseudo::expandArith(unsigned OpLo, unsigned OpHi, Block &MBB,
146  BlockIt MBBI) {
147  MachineInstr &MI = *MBBI;
148  Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
149  Register DstReg = MI.getOperand(0).getReg();
150  Register SrcReg = MI.getOperand(2).getReg();
151  bool DstIsDead = MI.getOperand(0).isDead();
152  bool DstIsKill = MI.getOperand(1).isKill();
153  bool SrcIsKill = MI.getOperand(2).isKill();
154  bool ImpIsDead = MI.getOperand(3).isDead();
155  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
156  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
157 
158  buildMI(MBB, MBBI, OpLo)
159  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
160  .addReg(DstLoReg, getKillRegState(DstIsKill))
161  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
162 
163  auto MIBHI =
164  buildMI(MBB, MBBI, OpHi)
165  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
166  .addReg(DstHiReg, getKillRegState(DstIsKill))
167  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
168 
169  if (ImpIsDead)
170  MIBHI->getOperand(3).setIsDead();
171 
172  // SREG is always implicitly killed
173  MIBHI->getOperand(4).setIsKill();
174 
175  MI.eraseFromParent();
176  return true;
177 }
178 
179 bool AVRExpandPseudo::expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
180  MachineInstr &MI = *MBBI;
181  Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
182  Register DstReg = MI.getOperand(0).getReg();
183  Register SrcReg = MI.getOperand(2).getReg();
184  bool DstIsDead = MI.getOperand(0).isDead();
185  bool DstIsKill = MI.getOperand(1).isKill();
186  bool SrcIsKill = MI.getOperand(2).isKill();
187  bool ImpIsDead = MI.getOperand(3).isDead();
188  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
189  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
190 
191  auto MIBLO =
192  buildMI(MBB, MBBI, Op)
193  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
194  .addReg(DstLoReg, getKillRegState(DstIsKill))
195  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
196 
197  // SREG is always implicitly dead
198  MIBLO->getOperand(3).setIsDead();
199 
200  auto MIBHI =
201  buildMI(MBB, MBBI, Op)
202  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
203  .addReg(DstHiReg, getKillRegState(DstIsKill))
204  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
205 
206  if (ImpIsDead)
207  MIBHI->getOperand(3).setIsDead();
208 
209  MI.eraseFromParent();
210  return true;
211 }
212 
213 bool AVRExpandPseudo::isLogicImmOpRedundant(unsigned Op,
214  unsigned ImmVal) const {
215 
216  // ANDI Rd, 0xff is redundant.
217  if (Op == AVR::ANDIRdK && ImmVal == 0xff)
218  return true;
219 
220  // ORI Rd, 0x0 is redundant.
221  if (Op == AVR::ORIRdK && ImmVal == 0x0)
222  return true;
223 
224  return false;
225 }
226 
227 bool AVRExpandPseudo::expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI) {
228  MachineInstr &MI = *MBBI;
229  Register DstLoReg, DstHiReg;
230  Register DstReg = MI.getOperand(0).getReg();
231  bool DstIsDead = MI.getOperand(0).isDead();
232  bool SrcIsKill = MI.getOperand(1).isKill();
233  bool ImpIsDead = MI.getOperand(3).isDead();
234  unsigned Imm = MI.getOperand(2).getImm();
235  unsigned Lo8 = Imm & 0xff;
236  unsigned Hi8 = (Imm >> 8) & 0xff;
237  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
238 
239  if (!isLogicImmOpRedundant(Op, Lo8)) {
240  auto MIBLO =
241  buildMI(MBB, MBBI, Op)
242  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
243  .addReg(DstLoReg, getKillRegState(SrcIsKill))
244  .addImm(Lo8);
245 
246  // SREG is always implicitly dead
247  MIBLO->getOperand(3).setIsDead();
248  }
249 
250  if (!isLogicImmOpRedundant(Op, Hi8)) {
251  auto MIBHI =
252  buildMI(MBB, MBBI, Op)
253  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
254  .addReg(DstHiReg, getKillRegState(SrcIsKill))
255  .addImm(Hi8);
256 
257  if (ImpIsDead)
258  MIBHI->getOperand(3).setIsDead();
259  }
260 
261  MI.eraseFromParent();
262  return true;
263 }
264 
265 template <>
266 bool AVRExpandPseudo::expand<AVR::ADDWRdRr>(Block &MBB, BlockIt MBBI) {
267  return expandArith(AVR::ADDRdRr, AVR::ADCRdRr, MBB, MBBI);
268 }
269 
270 template <>
271 bool AVRExpandPseudo::expand<AVR::ADCWRdRr>(Block &MBB, BlockIt MBBI) {
272  return expandArith(AVR::ADCRdRr, AVR::ADCRdRr, MBB, MBBI);
273 }
274 
275 template <>
276 bool AVRExpandPseudo::expand<AVR::SUBWRdRr>(Block &MBB, BlockIt MBBI) {
277  return expandArith(AVR::SUBRdRr, AVR::SBCRdRr, MBB, MBBI);
278 }
279 
280 template <>
281 bool AVRExpandPseudo::expand<AVR::SUBIWRdK>(Block &MBB, BlockIt MBBI) {
282  MachineInstr &MI = *MBBI;
283  Register DstLoReg, DstHiReg;
284  Register DstReg = MI.getOperand(0).getReg();
285  bool DstIsDead = MI.getOperand(0).isDead();
286  bool SrcIsKill = MI.getOperand(1).isKill();
287  bool ImpIsDead = MI.getOperand(3).isDead();
288  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
289 
290  auto MIBLO =
291  buildMI(MBB, MBBI, AVR::SUBIRdK)
292  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
293  .addReg(DstLoReg, getKillRegState(SrcIsKill));
294 
295  auto MIBHI =
296  buildMI(MBB, MBBI, AVR::SBCIRdK)
297  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
298  .addReg(DstHiReg, getKillRegState(SrcIsKill));
299 
300  switch (MI.getOperand(2).getType()) {
302  const GlobalValue *GV = MI.getOperand(2).getGlobal();
303  int64_t Offs = MI.getOperand(2).getOffset();
304  unsigned TF = MI.getOperand(2).getTargetFlags();
305  MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_LO);
306  MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_HI);
307  break;
308  }
310  unsigned Imm = MI.getOperand(2).getImm();
311  MIBLO.addImm(Imm & 0xff);
312  MIBHI.addImm((Imm >> 8) & 0xff);
313  break;
314  }
315  default:
316  llvm_unreachable("Unknown operand type!");
317  }
318 
319  if (ImpIsDead)
320  MIBHI->getOperand(3).setIsDead();
321 
322  // SREG is always implicitly killed
323  MIBHI->getOperand(4).setIsKill();
324 
325  MI.eraseFromParent();
326  return true;
327 }
328 
329 template <>
330 bool AVRExpandPseudo::expand<AVR::SBCWRdRr>(Block &MBB, BlockIt MBBI) {
331  return expandArith(AVR::SBCRdRr, AVR::SBCRdRr, MBB, MBBI);
332 }
333 
334 template <>
335 bool AVRExpandPseudo::expand<AVR::SBCIWRdK>(Block &MBB, BlockIt MBBI) {
336  MachineInstr &MI = *MBBI;
337  Register DstLoReg, DstHiReg;
338  Register DstReg = MI.getOperand(0).getReg();
339  bool DstIsDead = MI.getOperand(0).isDead();
340  bool SrcIsKill = MI.getOperand(1).isKill();
341  bool ImpIsDead = MI.getOperand(3).isDead();
342  unsigned Imm = MI.getOperand(2).getImm();
343  unsigned Lo8 = Imm & 0xff;
344  unsigned Hi8 = (Imm >> 8) & 0xff;
345  unsigned OpLo = AVR::SBCIRdK;
346  unsigned OpHi = AVR::SBCIRdK;
347  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
348 
349  auto MIBLO =
350  buildMI(MBB, MBBI, OpLo)
351  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
352  .addReg(DstLoReg, getKillRegState(SrcIsKill))
353  .addImm(Lo8);
354 
355  // SREG is always implicitly killed
356  MIBLO->getOperand(4).setIsKill();
357 
358  auto MIBHI =
359  buildMI(MBB, MBBI, OpHi)
360  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
361  .addReg(DstHiReg, getKillRegState(SrcIsKill))
362  .addImm(Hi8);
363 
364  if (ImpIsDead)
365  MIBHI->getOperand(3).setIsDead();
366 
367  // SREG is always implicitly killed
368  MIBHI->getOperand(4).setIsKill();
369 
370  MI.eraseFromParent();
371  return true;
372 }
373 
374 template <>
375 bool AVRExpandPseudo::expand<AVR::ANDWRdRr>(Block &MBB, BlockIt MBBI) {
376  return expandLogic(AVR::ANDRdRr, MBB, MBBI);
377 }
378 
379 template <>
380 bool AVRExpandPseudo::expand<AVR::ANDIWRdK>(Block &MBB, BlockIt MBBI) {
381  return expandLogicImm(AVR::ANDIRdK, MBB, MBBI);
382 }
383 
384 template <>
385 bool AVRExpandPseudo::expand<AVR::ORWRdRr>(Block &MBB, BlockIt MBBI) {
386  return expandLogic(AVR::ORRdRr, MBB, MBBI);
387 }
388 
389 template <>
390 bool AVRExpandPseudo::expand<AVR::ORIWRdK>(Block &MBB, BlockIt MBBI) {
391  return expandLogicImm(AVR::ORIRdK, MBB, MBBI);
392 }
393 
394 template <>
395 bool AVRExpandPseudo::expand<AVR::EORWRdRr>(Block &MBB, BlockIt MBBI) {
396  return expandLogic(AVR::EORRdRr, MBB, MBBI);
397 }
398 
399 template <>
400 bool AVRExpandPseudo::expand<AVR::COMWRd>(Block &MBB, BlockIt MBBI) {
401  MachineInstr &MI = *MBBI;
402  Register DstLoReg, DstHiReg;
403  Register DstReg = MI.getOperand(0).getReg();
404  bool DstIsDead = MI.getOperand(0).isDead();
405  bool DstIsKill = MI.getOperand(1).isKill();
406  bool ImpIsDead = MI.getOperand(2).isDead();
407  unsigned OpLo = AVR::COMRd;
408  unsigned OpHi = AVR::COMRd;
409  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
410 
411  auto MIBLO =
412  buildMI(MBB, MBBI, OpLo)
413  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
414  .addReg(DstLoReg, getKillRegState(DstIsKill));
415 
416  // SREG is always implicitly dead
417  MIBLO->getOperand(2).setIsDead();
418 
419  auto MIBHI =
420  buildMI(MBB, MBBI, OpHi)
421  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
422  .addReg(DstHiReg, getKillRegState(DstIsKill));
423 
424  if (ImpIsDead)
425  MIBHI->getOperand(2).setIsDead();
426 
427  MI.eraseFromParent();
428  return true;
429 }
430 
431 template <>
432 bool AVRExpandPseudo::expand<AVR::NEGWRd>(Block &MBB, BlockIt MBBI) {
433  MachineInstr &MI = *MBBI;
434  Register DstLoReg, DstHiReg;
435  Register DstReg = MI.getOperand(0).getReg();
436  Register ZeroReg = MI.getOperand(2).getReg();
437  bool DstIsDead = MI.getOperand(0).isDead();
438  bool DstIsKill = MI.getOperand(1).isKill();
439  bool ImpIsDead = MI.getOperand(2).isDead();
440  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
441 
442  // Do NEG on the upper byte.
443  auto MIBHI =
444  buildMI(MBB, MBBI, AVR::NEGRd)
445  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
446  .addReg(DstHiReg, RegState::Kill);
447  // SREG is always implicitly dead
448  MIBHI->getOperand(2).setIsDead();
449 
450  // Do NEG on the lower byte.
451  buildMI(MBB, MBBI, AVR::NEGRd)
452  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
453  .addReg(DstLoReg, getKillRegState(DstIsKill));
454 
455  // Do an extra SBC.
456  auto MISBCI =
457  buildMI(MBB, MBBI, AVR::SBCRdRr)
458  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
459  .addReg(DstHiReg, getKillRegState(DstIsKill))
460  .addReg(ZeroReg);
461  if (ImpIsDead)
462  MISBCI->getOperand(3).setIsDead();
463  // SREG is always implicitly killed
464  MISBCI->getOperand(4).setIsKill();
465 
466  MI.eraseFromParent();
467  return true;
468 }
469 
470 template <>
471 bool AVRExpandPseudo::expand<AVR::CPWRdRr>(Block &MBB, BlockIt MBBI) {
472  MachineInstr &MI = *MBBI;
473  Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
474  Register DstReg = MI.getOperand(0).getReg();
475  Register SrcReg = MI.getOperand(1).getReg();
476  bool DstIsKill = MI.getOperand(0).isKill();
477  bool SrcIsKill = MI.getOperand(1).isKill();
478  bool ImpIsDead = MI.getOperand(2).isDead();
479  unsigned OpLo = AVR::CPRdRr;
480  unsigned OpHi = AVR::CPCRdRr;
481  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
482  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
483 
484  // Low part
485  buildMI(MBB, MBBI, OpLo)
486  .addReg(DstLoReg, getKillRegState(DstIsKill))
487  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
488 
489  auto MIBHI = buildMI(MBB, MBBI, OpHi)
490  .addReg(DstHiReg, getKillRegState(DstIsKill))
491  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
492 
493  if (ImpIsDead)
494  MIBHI->getOperand(2).setIsDead();
495 
496  // SREG is always implicitly killed
497  MIBHI->getOperand(3).setIsKill();
498 
499  MI.eraseFromParent();
500  return true;
501 }
502 
503 template <>
504 bool AVRExpandPseudo::expand<AVR::CPCWRdRr>(Block &MBB, BlockIt MBBI) {
505  MachineInstr &MI = *MBBI;
506  Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
507  Register DstReg = MI.getOperand(0).getReg();
508  Register SrcReg = MI.getOperand(1).getReg();
509  bool DstIsKill = MI.getOperand(0).isKill();
510  bool SrcIsKill = MI.getOperand(1).isKill();
511  bool ImpIsDead = MI.getOperand(2).isDead();
512  unsigned OpLo = AVR::CPCRdRr;
513  unsigned OpHi = AVR::CPCRdRr;
514  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
515  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
516 
517  auto MIBLO = buildMI(MBB, MBBI, OpLo)
518  .addReg(DstLoReg, getKillRegState(DstIsKill))
519  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
520 
521  // SREG is always implicitly killed
522  MIBLO->getOperand(3).setIsKill();
523 
524  auto MIBHI = buildMI(MBB, MBBI, OpHi)
525  .addReg(DstHiReg, getKillRegState(DstIsKill))
526  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
527 
528  if (ImpIsDead)
529  MIBHI->getOperand(2).setIsDead();
530 
531  // SREG is always implicitly killed
532  MIBHI->getOperand(3).setIsKill();
533 
534  MI.eraseFromParent();
535  return true;
536 }
537 
538 template <>
539 bool AVRExpandPseudo::expand<AVR::LDIWRdK>(Block &MBB, BlockIt MBBI) {
540  MachineInstr &MI = *MBBI;
541  Register DstLoReg, DstHiReg;
542  Register DstReg = MI.getOperand(0).getReg();
543  bool DstIsDead = MI.getOperand(0).isDead();
544  unsigned OpLo = AVR::LDIRdK;
545  unsigned OpHi = AVR::LDIRdK;
546  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
547 
548  auto MIBLO =
549  buildMI(MBB, MBBI, OpLo)
550  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
551 
552  auto MIBHI =
553  buildMI(MBB, MBBI, OpHi)
554  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
555 
556  switch (MI.getOperand(1).getType()) {
558  const GlobalValue *GV = MI.getOperand(1).getGlobal();
559  int64_t Offs = MI.getOperand(1).getOffset();
560  unsigned TF = MI.getOperand(1).getTargetFlags();
561 
562  MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_LO);
563  MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_HI);
564  break;
565  }
567  const BlockAddress *BA = MI.getOperand(1).getBlockAddress();
568  unsigned TF = MI.getOperand(1).getTargetFlags();
569 
570  MIBLO.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_LO));
571  MIBHI.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_HI));
572  break;
573  }
575  unsigned Imm = MI.getOperand(1).getImm();
576 
577  MIBLO.addImm(Imm & 0xff);
578  MIBHI.addImm((Imm >> 8) & 0xff);
579  break;
580  }
581  default:
582  llvm_unreachable("Unknown operand type!");
583  }
584 
585  MI.eraseFromParent();
586  return true;
587 }
588 
589 template <>
590 bool AVRExpandPseudo::expand<AVR::LDSWRdK>(Block &MBB, BlockIt MBBI) {
591  MachineInstr &MI = *MBBI;
592  Register DstLoReg, DstHiReg;
593  Register DstReg = MI.getOperand(0).getReg();
594  bool DstIsDead = MI.getOperand(0).isDead();
595  unsigned OpLo = AVR::LDSRdK;
596  unsigned OpHi = AVR::LDSRdK;
597  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
598 
599  auto MIBLO =
600  buildMI(MBB, MBBI, OpLo)
601  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
602 
603  auto MIBHI =
604  buildMI(MBB, MBBI, OpHi)
605  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
606 
607  switch (MI.getOperand(1).getType()) {
609  const GlobalValue *GV = MI.getOperand(1).getGlobal();
610  int64_t Offs = MI.getOperand(1).getOffset();
611  unsigned TF = MI.getOperand(1).getTargetFlags();
612 
613  MIBLO.addGlobalAddress(GV, Offs, TF);
614  MIBHI.addGlobalAddress(GV, Offs + 1, TF);
615  break;
616  }
618  unsigned Imm = MI.getOperand(1).getImm();
619 
620  MIBLO.addImm(Imm);
621  MIBHI.addImm(Imm + 1);
622  break;
623  }
624  default:
625  llvm_unreachable("Unknown operand type!");
626  }
627 
628  MIBLO.setMemRefs(MI.memoperands());
629  MIBHI.setMemRefs(MI.memoperands());
630 
631  MI.eraseFromParent();
632  return true;
633 }
634 
635 template <>
636 bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
637  MachineInstr &MI = *MBBI;
638  Register DstLoReg, DstHiReg;
639  Register DstReg = MI.getOperand(0).getReg();
640  Register SrcReg = MI.getOperand(1).getReg();
641  bool SrcIsKill = MI.getOperand(1).isKill();
642  unsigned OpLo = AVR::LDRdPtr;
643  unsigned OpHi = AVR::LDDRdPtrQ;
644  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
645 
646  // DstReg has an earlyclobber so the register allocator will allocate them in
647  // separate registers.
648  assert(DstReg != SrcReg && "Dst and Src registers are the same!");
649 
650  // Load low byte.
651  buildMI(MBB, MBBI, OpLo)
652  .addReg(DstLoReg, RegState::Define)
653  .addReg(SrcReg)
654  .setMemRefs(MI.memoperands());
655 
656  // Load high byte.
657  buildMI(MBB, MBBI, OpHi)
658  .addReg(DstHiReg, RegState::Define)
659  .addReg(SrcReg, getKillRegState(SrcIsKill))
660  .addImm(1)
661  .setMemRefs(MI.memoperands());
662 
663  MI.eraseFromParent();
664  return true;
665 }
666 
667 template <>
668 bool AVRExpandPseudo::expand<AVR::LDWRdPtrPi>(Block &MBB, BlockIt MBBI) {
669  MachineInstr &MI = *MBBI;
670  Register DstLoReg, DstHiReg;
671  Register DstReg = MI.getOperand(0).getReg();
672  Register SrcReg = MI.getOperand(1).getReg();
673  bool DstIsDead = MI.getOperand(0).isDead();
674  bool SrcIsDead = MI.getOperand(1).isKill();
675  unsigned OpLo = AVR::LDRdPtrPi;
676  unsigned OpHi = AVR::LDRdPtrPi;
677  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
678 
679  assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
680 
681  auto MIBLO =
682  buildMI(MBB, MBBI, OpLo)
683  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
684  .addReg(SrcReg, RegState::Define)
685  .addReg(SrcReg, RegState::Kill);
686 
687  auto MIBHI =
688  buildMI(MBB, MBBI, OpHi)
689  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
690  .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
691  .addReg(SrcReg, RegState::Kill);
692 
693  MIBLO.setMemRefs(MI.memoperands());
694  MIBHI.setMemRefs(MI.memoperands());
695 
696  MI.eraseFromParent();
697  return true;
698 }
699 
700 template <>
701 bool AVRExpandPseudo::expand<AVR::LDWRdPtrPd>(Block &MBB, BlockIt MBBI) {
702  MachineInstr &MI = *MBBI;
703  Register DstLoReg, DstHiReg;
704  Register DstReg = MI.getOperand(0).getReg();
705  Register SrcReg = MI.getOperand(1).getReg();
706  bool DstIsDead = MI.getOperand(0).isDead();
707  bool SrcIsDead = MI.getOperand(1).isKill();
708  unsigned OpLo = AVR::LDRdPtrPd;
709  unsigned OpHi = AVR::LDRdPtrPd;
710  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
711 
712  assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
713 
714  auto MIBHI =
715  buildMI(MBB, MBBI, OpHi)
716  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
717  .addReg(SrcReg, RegState::Define)
718  .addReg(SrcReg, RegState::Kill);
719 
720  auto MIBLO =
721  buildMI(MBB, MBBI, OpLo)
722  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
723  .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
724  .addReg(SrcReg, RegState::Kill);
725 
726  MIBLO.setMemRefs(MI.memoperands());
727  MIBHI.setMemRefs(MI.memoperands());
728 
729  MI.eraseFromParent();
730  return true;
731 }
732 
733 template <>
734 bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
735  MachineInstr &MI = *MBBI;
736  Register DstLoReg, DstHiReg;
737  Register DstReg = MI.getOperand(0).getReg();
738  Register SrcReg = MI.getOperand(1).getReg();
739  unsigned Imm = MI.getOperand(2).getImm();
740  bool SrcIsKill = MI.getOperand(1).isKill();
741  unsigned OpLo = AVR::LDDRdPtrQ;
742  unsigned OpHi = AVR::LDDRdPtrQ;
743  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
744 
745  // Since we add 1 to the Imm value for the high byte below, and 63 is the
746  // highest Imm value allowed for the instruction, 62 is the limit here.
747  assert(Imm <= 62 && "Offset is out of range");
748 
749  // DstReg has an earlyclobber so the register allocator will allocate them in
750  // separate registers.
751  assert(DstReg != SrcReg && "Dst and Src registers are the same!");
752 
753  // Load low byte.
754  buildMI(MBB, MBBI, OpLo)
755  .addReg(DstLoReg, RegState::Define)
756  .addReg(SrcReg)
757  .addImm(Imm)
758  .setMemRefs(MI.memoperands());
759 
760  // Load high byte.
761  buildMI(MBB, MBBI, OpHi)
762  .addReg(DstHiReg, RegState::Define)
763  .addReg(SrcReg, getKillRegState(SrcIsKill))
764  .addImm(Imm + 1)
765  .setMemRefs(MI.memoperands());
766 
767  MI.eraseFromParent();
768  return true;
769 }
770 
771 bool AVRExpandPseudo::expandLPMWELPMW(Block &MBB, BlockIt MBBI, bool IsExt) {
772  MachineInstr &MI = *MBBI;
773  Register DstLoReg, DstHiReg;
774  Register DstReg = MI.getOperand(0).getReg();
775  Register SrcReg = MI.getOperand(1).getReg();
776  bool SrcIsKill = MI.getOperand(1).isKill();
777  unsigned OpLo = IsExt ? AVR::ELPMRdZPi : AVR::LPMRdZPi;
778  unsigned OpHi = IsExt ? AVR::ELPMRdZ : AVR::LPMRdZ;
779  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
780 
781  // Set the I/O register RAMPZ for ELPM.
782  if (IsExt) {
784  Register Bank = MI.getOperand(2).getReg();
785  // out RAMPZ, rtmp
786  buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(Bank);
787  }
788 
789  // This is enforced by the @earlyclobber constraint.
790  assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
791 
792  // Load low byte.
793  auto MIBLO = buildMI(MBB, MBBI, OpLo)
794  .addReg(DstLoReg, RegState::Define)
795  .addReg(SrcReg);
796 
797  // Load high byte.
798  auto MIBHI = buildMI(MBB, MBBI, OpHi)
799  .addReg(DstHiReg, RegState::Define)
800  .addReg(SrcReg, getKillRegState(SrcIsKill));
801 
802  MIBLO.setMemRefs(MI.memoperands());
803  MIBHI.setMemRefs(MI.memoperands());
804 
805  MI.eraseFromParent();
806  return true;
807 }
808 
809 template <>
810 bool AVRExpandPseudo::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {
811  return expandLPMWELPMW(MBB, MBBI, false);
812 }
813 
814 template <>
815 bool AVRExpandPseudo::expand<AVR::ELPMWRdZ>(Block &MBB, BlockIt MBBI) {
816  return expandLPMWELPMW(MBB, MBBI, true);
817 }
818 
819 template <>
820 bool AVRExpandPseudo::expand<AVR::ELPMBRdZ>(Block &MBB, BlockIt MBBI) {
821  MachineInstr &MI = *MBBI;
822  Register DstReg = MI.getOperand(0).getReg();
823  Register SrcReg = MI.getOperand(1).getReg();
824  Register BankReg = MI.getOperand(2).getReg();
825  bool SrcIsKill = MI.getOperand(1).isKill();
827 
828  // Set the I/O register RAMPZ for ELPM (out RAMPZ, rtmp).
829  buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(BankReg);
830 
831  // Load byte.
832  auto MILB = buildMI(MBB, MBBI, AVR::ELPMRdZ)
833  .addReg(DstReg, RegState::Define)
834  .addReg(SrcReg, getKillRegState(SrcIsKill));
835 
836  MILB.setMemRefs(MI.memoperands());
837 
838  MI.eraseFromParent();
839  return true;
840 }
841 
842 template <>
843 bool AVRExpandPseudo::expand<AVR::LPMWRdZPi>(Block &MBB, BlockIt MBBI) {
844  llvm_unreachable("16-bit LPMPi is unimplemented");
845 }
846 
847 template <>
848 bool AVRExpandPseudo::expand<AVR::ELPMBRdZPi>(Block &MBB, BlockIt MBBI) {
849  llvm_unreachable("byte ELPMPi is unimplemented");
850 }
851 
852 template <>
853 bool AVRExpandPseudo::expand<AVR::ELPMWRdZPi>(Block &MBB, BlockIt MBBI) {
854  llvm_unreachable("16-bit ELPMPi is unimplemented");
855 }
856 
857 template <typename Func>
858 bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
859  MachineInstr &MI = *MBBI;
861 
862  // Store the SREG.
863  buildMI(MBB, MBBI, AVR::INRdA)
864  .addReg(STI.getTmpRegister(), RegState::Define)
865  .addImm(STI.getIORegSREG());
866 
867  // Disable exceptions.
868  buildMI(MBB, MBBI, AVR::BCLRs).addImm(7); // CLI
869 
870  f(MI);
871 
872  // Restore the status reg.
873  buildMI(MBB, MBBI, AVR::OUTARr)
874  .addImm(STI.getIORegSREG())
875  .addReg(STI.getTmpRegister());
876 
877  MI.eraseFromParent();
878  return true;
879 }
880 
881 template <typename Func>
882 bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode, Block &MBB,
883  BlockIt MBBI, Func f) {
884  return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
885  auto Op1 = MI.getOperand(0);
886  auto Op2 = MI.getOperand(1);
887 
888  MachineInstr &NewInst =
889  *buildMI(MBB, MBBI, Opcode).add(Op1).add(Op2).getInstr();
890  f(NewInst);
891  });
892 }
893 
894 bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode, Block &MBB,
895  BlockIt MBBI) {
896  return expandAtomicBinaryOp(Opcode, MBB, MBBI, [](MachineInstr &MI) {});
897 }
898 
899 template <>
900 bool AVRExpandPseudo::expand<AVR::AtomicLoad8>(Block &MBB, BlockIt MBBI) {
901  return expandAtomicBinaryOp(AVR::LDRdPtr, MBB, MBBI);
902 }
903 
904 template <>
905 bool AVRExpandPseudo::expand<AVR::AtomicLoad16>(Block &MBB, BlockIt MBBI) {
906  return expandAtomicBinaryOp(AVR::LDWRdPtr, MBB, MBBI);
907 }
908 
909 template <>
910 bool AVRExpandPseudo::expand<AVR::AtomicStore8>(Block &MBB, BlockIt MBBI) {
911  return expandAtomicBinaryOp(AVR::STPtrRr, MBB, MBBI);
912 }
913 
914 template <>
915 bool AVRExpandPseudo::expand<AVR::AtomicStore16>(Block &MBB, BlockIt MBBI) {
916  return expandAtomicBinaryOp(AVR::STWPtrRr, MBB, MBBI);
917 }
918 
919 template <>
920 bool AVRExpandPseudo::expand<AVR::AtomicFence>(Block &MBB, BlockIt MBBI) {
921  // On AVR, there is only one core and so atomic fences do nothing.
923  return true;
924 }
925 
926 template <>
927 bool AVRExpandPseudo::expand<AVR::STSWKRr>(Block &MBB, BlockIt MBBI) {
928  MachineInstr &MI = *MBBI;
929  Register SrcLoReg, SrcHiReg;
930  Register SrcReg = MI.getOperand(1).getReg();
931  bool SrcIsKill = MI.getOperand(1).isKill();
932  unsigned OpLo = AVR::STSKRr;
933  unsigned OpHi = AVR::STSKRr;
934  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
935 
936  // Write the high byte first in case this address belongs to a special
937  // I/O address with a special temporary register.
938  auto MIBHI = buildMI(MBB, MBBI, OpHi);
939  auto MIBLO = buildMI(MBB, MBBI, OpLo);
940 
941  switch (MI.getOperand(0).getType()) {
943  const GlobalValue *GV = MI.getOperand(0).getGlobal();
944  int64_t Offs = MI.getOperand(0).getOffset();
945  unsigned TF = MI.getOperand(0).getTargetFlags();
946 
947  MIBLO.addGlobalAddress(GV, Offs, TF);
948  MIBHI.addGlobalAddress(GV, Offs + 1, TF);
949  break;
950  }
952  unsigned Imm = MI.getOperand(0).getImm();
953 
954  MIBLO.addImm(Imm);
955  MIBHI.addImm(Imm + 1);
956  break;
957  }
958  default:
959  llvm_unreachable("Unknown operand type!");
960  }
961 
962  MIBLO.addReg(SrcLoReg, getKillRegState(SrcIsKill));
963  MIBHI.addReg(SrcHiReg, getKillRegState(SrcIsKill));
964 
965  MIBLO.setMemRefs(MI.memoperands());
966  MIBHI.setMemRefs(MI.memoperands());
967 
968  MI.eraseFromParent();
969  return true;
970 }
971 
972 template <>
973 bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
974  MachineInstr &MI = *MBBI;
975  Register SrcLoReg, SrcHiReg;
976  Register DstReg = MI.getOperand(0).getReg();
977  Register SrcReg = MI.getOperand(1).getReg();
978  bool DstIsUndef = MI.getOperand(0).isUndef();
979  bool SrcIsKill = MI.getOperand(1).isKill();
980  unsigned OpLo = AVR::STPtrRr;
981  unsigned OpHi = AVR::STDPtrQRr;
982  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
983 
984  //: TODO: need to reverse this order like inw and stsw?
985  auto MIBLO = buildMI(MBB, MBBI, OpLo)
986  .addReg(DstReg, getUndefRegState(DstIsUndef))
987  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
988 
989  auto MIBHI = buildMI(MBB, MBBI, OpHi)
990  .addReg(DstReg, getUndefRegState(DstIsUndef))
991  .addImm(1)
992  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
993 
994  MIBLO.setMemRefs(MI.memoperands());
995  MIBHI.setMemRefs(MI.memoperands());
996 
997  MI.eraseFromParent();
998  return true;
999 }
1000 
1001 template <>
1002 bool AVRExpandPseudo::expand<AVR::STWPtrPiRr>(Block &MBB, BlockIt MBBI) {
1003  MachineInstr &MI = *MBBI;
1004  Register SrcLoReg, SrcHiReg;
1005  Register DstReg = MI.getOperand(0).getReg();
1006  Register SrcReg = MI.getOperand(2).getReg();
1007  unsigned Imm = MI.getOperand(3).getImm();
1008  bool DstIsDead = MI.getOperand(0).isDead();
1009  bool SrcIsKill = MI.getOperand(2).isKill();
1010  unsigned OpLo = AVR::STPtrPiRr;
1011  unsigned OpHi = AVR::STPtrPiRr;
1012  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1013 
1014  assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1015 
1016  auto MIBLO = buildMI(MBB, MBBI, OpLo)
1017  .addReg(DstReg, RegState::Define)
1018  .addReg(DstReg, RegState::Kill)
1019  .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1020  .addImm(Imm);
1021 
1022  auto MIBHI =
1023  buildMI(MBB, MBBI, OpHi)
1024  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1025  .addReg(DstReg, RegState::Kill)
1026  .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1027  .addImm(Imm);
1028 
1029  MIBLO.setMemRefs(MI.memoperands());
1030  MIBHI.setMemRefs(MI.memoperands());
1031 
1032  MI.eraseFromParent();
1033  return true;
1034 }
1035 
1036 template <>
1037 bool AVRExpandPseudo::expand<AVR::STWPtrPdRr>(Block &MBB, BlockIt MBBI) {
1038  MachineInstr &MI = *MBBI;
1039  Register SrcLoReg, SrcHiReg;
1040  Register DstReg = MI.getOperand(0).getReg();
1041  Register SrcReg = MI.getOperand(2).getReg();
1042  unsigned Imm = MI.getOperand(3).getImm();
1043  bool DstIsDead = MI.getOperand(0).isDead();
1044  bool SrcIsKill = MI.getOperand(2).isKill();
1045  unsigned OpLo = AVR::STPtrPdRr;
1046  unsigned OpHi = AVR::STPtrPdRr;
1047  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1048 
1049  assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1050 
1051  auto MIBHI = buildMI(MBB, MBBI, OpHi)
1052  .addReg(DstReg, RegState::Define)
1053  .addReg(DstReg, RegState::Kill)
1054  .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1055  .addImm(Imm);
1056 
1057  auto MIBLO =
1058  buildMI(MBB, MBBI, OpLo)
1059  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1060  .addReg(DstReg, RegState::Kill)
1061  .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1062  .addImm(Imm);
1063 
1064  MIBLO.setMemRefs(MI.memoperands());
1065  MIBHI.setMemRefs(MI.memoperands());
1066 
1067  MI.eraseFromParent();
1068  return true;
1069 }
1070 
1071 template <>
1072 bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
1073  MachineInstr &MI = *MBBI;
1074 
1075  Register DstReg = MI.getOperand(0).getReg();
1076  bool DstIsKill = MI.getOperand(0).isKill();
1077  unsigned Imm = MI.getOperand(1).getImm();
1078  Register SrcReg = MI.getOperand(2).getReg();
1079  bool SrcIsKill = MI.getOperand(2).isKill();
1080 
1081  // STD's maximum displacement is 63, so larger stores have to be split into a
1082  // set of operations
1083  if (Imm >= 63) {
1084  if (!DstIsKill) {
1085  buildMI(MBB, MBBI, AVR::PUSHWRr).addReg(DstReg);
1086  }
1087 
1088  buildMI(MBB, MBBI, AVR::SUBIWRdK)
1089  .addReg(DstReg, RegState::Define)
1090  .addReg(DstReg, RegState::Kill)
1091  .addImm(-Imm);
1092 
1093  buildMI(MBB, MBBI, AVR::STWPtrRr)
1094  .addReg(DstReg, RegState::Kill)
1095  .addReg(SrcReg, getKillRegState(SrcIsKill));
1096 
1097  if (!DstIsKill) {
1098  buildMI(MBB, MBBI, AVR::POPWRd).addDef(DstReg, RegState::Define);
1099  }
1100  } else {
1101  unsigned OpLo = AVR::STDPtrQRr;
1102  unsigned OpHi = AVR::STDPtrQRr;
1103  Register SrcLoReg, SrcHiReg;
1104  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1105 
1106  auto MIBLO = buildMI(MBB, MBBI, OpLo)
1107  .addReg(DstReg)
1108  .addImm(Imm)
1109  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1110 
1111  auto MIBHI = buildMI(MBB, MBBI, OpHi)
1112  .addReg(DstReg, getKillRegState(DstIsKill))
1113  .addImm(Imm + 1)
1114  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1115 
1116  MIBLO.setMemRefs(MI.memoperands());
1117  MIBHI.setMemRefs(MI.memoperands());
1118  }
1119 
1120  MI.eraseFromParent();
1121  return true;
1122 }
1123 
1124 template <>
1125 bool AVRExpandPseudo::expand<AVR::STDSPQRr>(Block &MBB, BlockIt MBBI) {
1126  MachineInstr &MI = *MBBI;
1127  const MachineFunction &MF = *MBB.getParent();
1128  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
1129 
1130  assert(MI.getOperand(0).getReg() == AVR::SP &&
1131  "SP is expected as base pointer");
1132 
1134  "unexpected STDSPQRr pseudo instruction");
1135  (void)STI;
1136 
1137  MI.setDesc(TII->get(AVR::STDPtrQRr));
1138  MI.getOperand(0).setReg(AVR::R29R28);
1139 
1140  return true;
1141 }
1142 
1143 template <>
1144 bool AVRExpandPseudo::expand<AVR::STDWSPQRr>(Block &MBB, BlockIt MBBI) {
1145  MachineInstr &MI = *MBBI;
1146  const MachineFunction &MF = *MBB.getParent();
1147  const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
1148 
1149  assert(MI.getOperand(0).getReg() == AVR::SP &&
1150  "SP is expected as base pointer");
1151 
1153  "unexpected STDWSPQRr pseudo instruction");
1154  (void)STI;
1155 
1156  MI.setDesc(TII->get(AVR::STDWPtrQRr));
1157  MI.getOperand(0).setReg(AVR::R29R28);
1158 
1159  return true;
1160 }
1161 
1162 template <>
1163 bool AVRExpandPseudo::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) {
1164  MachineInstr &MI = *MBBI;
1165  Register DstLoReg, DstHiReg;
1166  unsigned Imm = MI.getOperand(1).getImm();
1167  Register DstReg = MI.getOperand(0).getReg();
1168  bool DstIsDead = MI.getOperand(0).isDead();
1169  unsigned OpLo = AVR::INRdA;
1170  unsigned OpHi = AVR::INRdA;
1171  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1172 
1173  // Since we add 1 to the Imm value for the high byte below, and 63 is the
1174  // highest Imm value allowed for the instruction, 62 is the limit here.
1175  assert(Imm <= 62 && "Address is out of range");
1176 
1177  auto MIBLO =
1178  buildMI(MBB, MBBI, OpLo)
1179  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1180  .addImm(Imm);
1181 
1182  auto MIBHI =
1183  buildMI(MBB, MBBI, OpHi)
1184  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1185  .addImm(Imm + 1);
1186 
1187  MIBLO.setMemRefs(MI.memoperands());
1188  MIBHI.setMemRefs(MI.memoperands());
1189 
1190  MI.eraseFromParent();
1191  return true;
1192 }
1193 
1194 template <>
1195 bool AVRExpandPseudo::expand<AVR::OUTWARr>(Block &MBB, BlockIt MBBI) {
1196  MachineInstr &MI = *MBBI;
1197  Register SrcLoReg, SrcHiReg;
1198  unsigned Imm = MI.getOperand(0).getImm();
1199  Register SrcReg = MI.getOperand(1).getReg();
1200  bool SrcIsKill = MI.getOperand(1).isKill();
1201  unsigned OpLo = AVR::OUTARr;
1202  unsigned OpHi = AVR::OUTARr;
1203  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1204 
1205  // Since we add 1 to the Imm value for the high byte below, and 63 is the
1206  // highest Imm value allowed for the instruction, 62 is the limit here.
1207  assert(Imm <= 62 && "Address is out of range");
1208 
1209  // 16 bit I/O writes need the high byte first
1210  auto MIBHI = buildMI(MBB, MBBI, OpHi)
1211  .addImm(Imm + 1)
1212  .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1213 
1214  auto MIBLO = buildMI(MBB, MBBI, OpLo)
1215  .addImm(Imm)
1216  .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1217 
1218  MIBLO.setMemRefs(MI.memoperands());
1219  MIBHI.setMemRefs(MI.memoperands());
1220 
1221  MI.eraseFromParent();
1222  return true;
1223 }
1224 
1225 template <>
1226 bool AVRExpandPseudo::expand<AVR::PUSHWRr>(Block &MBB, BlockIt MBBI) {
1227  MachineInstr &MI = *MBBI;
1228  Register SrcLoReg, SrcHiReg;
1229  Register SrcReg = MI.getOperand(0).getReg();
1230  bool SrcIsKill = MI.getOperand(0).isKill();
1231  unsigned Flags = MI.getFlags();
1232  unsigned OpLo = AVR::PUSHRr;
1233  unsigned OpHi = AVR::PUSHRr;
1234  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1235 
1236  // Low part
1237  buildMI(MBB, MBBI, OpLo)
1238  .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1239  .setMIFlags(Flags);
1240 
1241  // High part
1242  buildMI(MBB, MBBI, OpHi)
1243  .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1244  .setMIFlags(Flags);
1245 
1246  MI.eraseFromParent();
1247  return true;
1248 }
1249 
1250 template <>
1251 bool AVRExpandPseudo::expand<AVR::POPWRd>(Block &MBB, BlockIt MBBI) {
1252  MachineInstr &MI = *MBBI;
1253  Register DstLoReg, DstHiReg;
1254  Register DstReg = MI.getOperand(0).getReg();
1255  unsigned Flags = MI.getFlags();
1256  unsigned OpLo = AVR::POPRd;
1257  unsigned OpHi = AVR::POPRd;
1258  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1259 
1260  buildMI(MBB, MBBI, OpHi, DstHiReg).setMIFlags(Flags); // High
1261  buildMI(MBB, MBBI, OpLo, DstLoReg).setMIFlags(Flags); // Low
1262 
1263  MI.eraseFromParent();
1264  return true;
1265 }
1266 
1267 template <>
1268 bool AVRExpandPseudo::expand<AVR::ROLBRd>(Block &MBB, BlockIt MBBI) {
1269  // In AVR, the rotate instructions behave quite unintuitively. They rotate
1270  // bits through the carry bit in SREG, effectively rotating over 9 bits,
1271  // instead of 8. This is useful when we are dealing with numbers over
1272  // multiple registers, but when we actually need to rotate stuff, we have
1273  // to explicitly add the carry bit.
1274 
1275  MachineInstr &MI = *MBBI;
1276  unsigned OpShift, OpCarry;
1277  Register DstReg = MI.getOperand(0).getReg();
1278  Register ZeroReg = MI.getOperand(2).getReg();
1279  bool DstIsDead = MI.getOperand(0).isDead();
1280  bool DstIsKill = MI.getOperand(1).isKill();
1281  OpShift = AVR::ADDRdRr;
1282  OpCarry = AVR::ADCRdRr;
1283 
1284  // add r16, r16
1285  // adc r16, r1
1286 
1287  // Shift part
1288  buildMI(MBB, MBBI, OpShift)
1289  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1290  .addReg(DstReg, RegState::Kill)
1291  .addReg(DstReg, RegState::Kill);
1292 
1293  // Add the carry bit
1294  auto MIB = buildMI(MBB, MBBI, OpCarry)
1295  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1296  .addReg(DstReg, getKillRegState(DstIsKill))
1297  .addReg(ZeroReg);
1298 
1299  MIB->getOperand(3).setIsDead(); // SREG is always dead
1300  MIB->getOperand(4).setIsKill(); // SREG is always implicitly killed
1301 
1302  MI.eraseFromParent();
1303  return true;
1304 }
1305 
1306 template <>
1307 bool AVRExpandPseudo::expand<AVR::RORBRd>(Block &MBB, BlockIt MBBI) {
1308  // In AVR, the rotate instructions behave quite unintuitively. They rotate
1309  // bits through the carry bit in SREG, effectively rotating over 9 bits,
1310  // instead of 8. This is useful when we are dealing with numbers over
1311  // multiple registers, but when we actually need to rotate stuff, we have
1312  // to explicitly add the carry bit.
1313 
1314  MachineInstr &MI = *MBBI;
1315  Register DstReg = MI.getOperand(0).getReg();
1316 
1317  // bst r16, 0
1318  // ror r16
1319  // bld r16, 7
1320 
1321  // Move the lowest bit from DstReg into the T bit
1322  buildMI(MBB, MBBI, AVR::BST).addReg(DstReg).addImm(0);
1323 
1324  // Rotate to the right
1325  buildMI(MBB, MBBI, AVR::RORRd, DstReg).addReg(DstReg);
1326 
1327  // Move the T bit into the highest bit of DstReg.
1328  buildMI(MBB, MBBI, AVR::BLD, DstReg).addReg(DstReg).addImm(7);
1329 
1330  MI.eraseFromParent();
1331  return true;
1332 }
1333 
1334 template <>
1335 bool AVRExpandPseudo::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) {
1336  MachineInstr &MI = *MBBI;
1337  Register DstLoReg, DstHiReg;
1338  Register DstReg = MI.getOperand(0).getReg();
1339  bool DstIsDead = MI.getOperand(0).isDead();
1340  bool DstIsKill = MI.getOperand(1).isKill();
1341  bool ImpIsDead = MI.getOperand(2).isDead();
1342  unsigned OpLo = AVR::ADDRdRr; // ADD Rd, Rd <==> LSL Rd
1343  unsigned OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd
1344  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1345 
1346  // Low part
1347  buildMI(MBB, MBBI, OpLo)
1348  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1349  .addReg(DstLoReg, getKillRegState(DstIsKill))
1350  .addReg(DstLoReg, getKillRegState(DstIsKill));
1351 
1352  auto MIBHI =
1353  buildMI(MBB, MBBI, OpHi)
1354  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1355  .addReg(DstHiReg, getKillRegState(DstIsKill))
1356  .addReg(DstHiReg, getKillRegState(DstIsKill));
1357 
1358  if (ImpIsDead)
1359  MIBHI->getOperand(3).setIsDead();
1360 
1361  // SREG is always implicitly killed
1362  MIBHI->getOperand(4).setIsKill();
1363 
1364  MI.eraseFromParent();
1365  return true;
1366 }
1367 
1368 template <>
1369 bool AVRExpandPseudo::expand<AVR::LSLWHiRd>(Block &MBB, BlockIt MBBI) {
1370  MachineInstr &MI = *MBBI;
1371  Register DstLoReg, DstHiReg;
1372  Register DstReg = MI.getOperand(0).getReg();
1373  bool DstIsDead = MI.getOperand(0).isDead();
1374  bool DstIsKill = MI.getOperand(1).isKill();
1375  bool ImpIsDead = MI.getOperand(2).isDead();
1376  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1377 
1378  // add hireg, hireg <==> lsl hireg
1379  auto MILSL =
1380  buildMI(MBB, MBBI, AVR::ADDRdRr)
1381  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1382  .addReg(DstHiReg, getKillRegState(DstIsKill))
1383  .addReg(DstHiReg, getKillRegState(DstIsKill));
1384 
1385  if (ImpIsDead)
1386  MILSL->getOperand(3).setIsDead();
1387 
1388  MI.eraseFromParent();
1389  return true;
1390 }
1391 
1392 bool AVRExpandPseudo::expandLSLW4Rd(Block &MBB, BlockIt MBBI) {
1393  MachineInstr &MI = *MBBI;
1394  Register DstLoReg, DstHiReg;
1395  Register DstReg = MI.getOperand(0).getReg();
1396  bool DstIsDead = MI.getOperand(0).isDead();
1397  bool DstIsKill = MI.getOperand(1).isKill();
1398  bool ImpIsDead = MI.getOperand(3).isDead();
1399  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1400 
1401  // swap Rh
1402  // swap Rl
1403  buildMI(MBB, MBBI, AVR::SWAPRd)
1404  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1405  .addReg(DstHiReg, RegState::Kill);
1406  buildMI(MBB, MBBI, AVR::SWAPRd)
1407  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1408  .addReg(DstLoReg, RegState::Kill);
1409 
1410  // andi Rh, 0xf0
1411  auto MI0 =
1412  buildMI(MBB, MBBI, AVR::ANDIRdK)
1413  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1414  .addReg(DstHiReg, RegState::Kill)
1415  .addImm(0xf0);
1416  // SREG is implicitly dead.
1417  MI0->getOperand(3).setIsDead();
1418 
1419  // eor Rh, Rl
1420  auto MI1 =
1421  buildMI(MBB, MBBI, AVR::EORRdRr)
1422  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1423  .addReg(DstHiReg, RegState::Kill)
1424  .addReg(DstLoReg);
1425  // SREG is implicitly dead.
1426  MI1->getOperand(3).setIsDead();
1427 
1428  // andi Rl, 0xf0
1429  auto MI2 =
1430  buildMI(MBB, MBBI, AVR::ANDIRdK)
1431  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1432  .addReg(DstLoReg, getKillRegState(DstIsKill))
1433  .addImm(0xf0);
1434  // SREG is implicitly dead.
1435  MI2->getOperand(3).setIsDead();
1436 
1437  // eor Rh, Rl
1438  auto MI3 =
1439  buildMI(MBB, MBBI, AVR::EORRdRr)
1440  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1441  .addReg(DstHiReg, getKillRegState(DstIsKill))
1442  .addReg(DstLoReg);
1443  if (ImpIsDead)
1444  MI3->getOperand(3).setIsDead();
1445 
1446  MI.eraseFromParent();
1447  return true;
1448 }
1449 
1450 bool AVRExpandPseudo::expandLSLW8Rd(Block &MBB, BlockIt MBBI) {
1451  MachineInstr &MI = *MBBI;
1452  Register DstLoReg, DstHiReg;
1453  Register DstReg = MI.getOperand(0).getReg();
1454  bool DstIsDead = MI.getOperand(0).isDead();
1455  bool DstIsKill = MI.getOperand(1).isKill();
1456  bool ImpIsDead = MI.getOperand(3).isDead();
1457  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1458 
1459  // mov Rh, Rl
1460  buildMI(MBB, MBBI, AVR::MOVRdRr)
1461  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1462  .addReg(DstLoReg);
1463 
1464  // clr Rl
1465  auto MIBLO =
1466  buildMI(MBB, MBBI, AVR::EORRdRr)
1467  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1468  .addReg(DstLoReg, getKillRegState(DstIsKill))
1469  .addReg(DstLoReg, getKillRegState(DstIsKill));
1470  if (ImpIsDead)
1471  MIBLO->getOperand(3).setIsDead();
1472 
1473  MI.eraseFromParent();
1474  return true;
1475 }
1476 
1477 bool AVRExpandPseudo::expandLSLW12Rd(Block &MBB, BlockIt MBBI) {
1478  MachineInstr &MI = *MBBI;
1479  Register DstLoReg, DstHiReg;
1480  Register DstReg = MI.getOperand(0).getReg();
1481  bool DstIsDead = MI.getOperand(0).isDead();
1482  bool DstIsKill = MI.getOperand(1).isKill();
1483  bool ImpIsDead = MI.getOperand(3).isDead();
1484  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1485 
1486  // mov Rh, Rl
1487  buildMI(MBB, MBBI, AVR::MOVRdRr)
1488  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1489  .addReg(DstLoReg);
1490 
1491  // swap Rh
1492  buildMI(MBB, MBBI, AVR::SWAPRd)
1493  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1494  .addReg(DstHiReg, RegState::Kill);
1495 
1496  // andi Rh, 0xf0
1497  auto MI0 =
1498  buildMI(MBB, MBBI, AVR::ANDIRdK)
1499  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1500  .addReg(DstHiReg, getKillRegState(DstIsKill))
1501  .addImm(0xf0);
1502  // SREG is implicitly dead.
1503  MI0->getOperand(3).setIsDead();
1504 
1505  // clr Rl
1506  auto MI1 =
1507  buildMI(MBB, MBBI, AVR::EORRdRr)
1508  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1509  .addReg(DstLoReg, getKillRegState(DstIsKill))
1510  .addReg(DstLoReg, getKillRegState(DstIsKill));
1511  if (ImpIsDead)
1512  MI1->getOperand(3).setIsDead();
1513 
1514  MI.eraseFromParent();
1515  return true;
1516 }
1517 
1518 template <>
1519 bool AVRExpandPseudo::expand<AVR::LSLWNRd>(Block &MBB, BlockIt MBBI) {
1520  MachineInstr &MI = *MBBI;
1521  unsigned Imm = MI.getOperand(2).getImm();
1522  switch (Imm) {
1523  case 4:
1524  return expandLSLW4Rd(MBB, MBBI);
1525  case 8:
1526  return expandLSLW8Rd(MBB, MBBI);
1527  case 12:
1528  return expandLSLW12Rd(MBB, MBBI);
1529  default:
1530  llvm_unreachable("unimplemented lslwn");
1531  return false;
1532  }
1533 }
1534 
1535 template <>
1536 bool AVRExpandPseudo::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {
1537  MachineInstr &MI = *MBBI;
1538  Register DstLoReg, DstHiReg;
1539  Register DstReg = MI.getOperand(0).getReg();
1540  bool DstIsDead = MI.getOperand(0).isDead();
1541  bool DstIsKill = MI.getOperand(1).isKill();
1542  bool ImpIsDead = MI.getOperand(2).isDead();
1543  unsigned OpLo = AVR::RORRd;
1544  unsigned OpHi = AVR::LSRRd;
1545  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1546 
1547  // High part
1548  buildMI(MBB, MBBI, OpHi)
1549  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1550  .addReg(DstHiReg, getKillRegState(DstIsKill));
1551 
1552  auto MIBLO =
1553  buildMI(MBB, MBBI, OpLo)
1554  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1555  .addReg(DstLoReg, getKillRegState(DstIsKill));
1556 
1557  if (ImpIsDead)
1558  MIBLO->getOperand(2).setIsDead();
1559 
1560  // SREG is always implicitly killed
1561  MIBLO->getOperand(3).setIsKill();
1562 
1563  MI.eraseFromParent();
1564  return true;
1565 }
1566 
1567 template <>
1568 bool AVRExpandPseudo::expand<AVR::LSRWLoRd>(Block &MBB, BlockIt MBBI) {
1569  MachineInstr &MI = *MBBI;
1570  Register DstLoReg, DstHiReg;
1571  Register DstReg = MI.getOperand(0).getReg();
1572  bool DstIsDead = MI.getOperand(0).isDead();
1573  bool DstIsKill = MI.getOperand(1).isKill();
1574  bool ImpIsDead = MI.getOperand(2).isDead();
1575  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1576 
1577  // lsr loreg
1578  auto MILSR =
1579  buildMI(MBB, MBBI, AVR::LSRRd)
1580  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1581  .addReg(DstLoReg, getKillRegState(DstIsKill));
1582 
1583  if (ImpIsDead)
1584  MILSR->getOperand(2).setIsDead();
1585 
1586  MI.eraseFromParent();
1587  return true;
1588 }
1589 
1590 bool AVRExpandPseudo::expandLSRW4Rd(Block &MBB, BlockIt MBBI) {
1591  MachineInstr &MI = *MBBI;
1592  Register DstLoReg, DstHiReg;
1593  Register DstReg = MI.getOperand(0).getReg();
1594  bool DstIsDead = MI.getOperand(0).isDead();
1595  bool DstIsKill = MI.getOperand(1).isKill();
1596  bool ImpIsDead = MI.getOperand(3).isDead();
1597  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1598 
1599  // swap Rh
1600  // swap Rl
1601  buildMI(MBB, MBBI, AVR::SWAPRd)
1602  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1603  .addReg(DstHiReg, RegState::Kill);
1604  buildMI(MBB, MBBI, AVR::SWAPRd)
1605  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1606  .addReg(DstLoReg, RegState::Kill);
1607 
1608  // andi Rl, 0xf
1609  auto MI0 =
1610  buildMI(MBB, MBBI, AVR::ANDIRdK)
1611  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1612  .addReg(DstLoReg, RegState::Kill)
1613  .addImm(0xf);
1614  // SREG is implicitly dead.
1615  MI0->getOperand(3).setIsDead();
1616 
1617  // eor Rl, Rh
1618  auto MI1 =
1619  buildMI(MBB, MBBI, AVR::EORRdRr)
1620  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1621  .addReg(DstLoReg, RegState::Kill)
1622  .addReg(DstHiReg);
1623  // SREG is implicitly dead.
1624  MI1->getOperand(3).setIsDead();
1625 
1626  // andi Rh, 0xf
1627  auto MI2 =
1628  buildMI(MBB, MBBI, AVR::ANDIRdK)
1629  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1630  .addReg(DstHiReg, getKillRegState(DstIsKill))
1631  .addImm(0xf);
1632  // SREG is implicitly dead.
1633  MI2->getOperand(3).setIsDead();
1634 
1635  // eor Rl, Rh
1636  auto MI3 =
1637  buildMI(MBB, MBBI, AVR::EORRdRr)
1638  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1639  .addReg(DstLoReg, getKillRegState(DstIsKill))
1640  .addReg(DstHiReg);
1641  if (ImpIsDead)
1642  MI3->getOperand(3).setIsDead();
1643 
1644  MI.eraseFromParent();
1645  return true;
1646 }
1647 
1648 bool AVRExpandPseudo::expandLSRW8Rd(Block &MBB, BlockIt MBBI) {
1649  MachineInstr &MI = *MBBI;
1650  Register DstLoReg, DstHiReg;
1651  Register DstReg = MI.getOperand(0).getReg();
1652  bool DstIsDead = MI.getOperand(0).isDead();
1653  bool DstIsKill = MI.getOperand(1).isKill();
1654  bool ImpIsDead = MI.getOperand(3).isDead();
1655  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1656 
1657  // Move upper byte to lower byte.
1658  buildMI(MBB, MBBI, AVR::MOVRdRr)
1659  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1660  .addReg(DstHiReg);
1661 
1662  // Clear upper byte.
1663  auto MIBHI =
1664  buildMI(MBB, MBBI, AVR::EORRdRr)
1665  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1666  .addReg(DstHiReg, getKillRegState(DstIsKill))
1667  .addReg(DstHiReg, getKillRegState(DstIsKill));
1668  if (ImpIsDead)
1669  MIBHI->getOperand(3).setIsDead();
1670 
1671  MI.eraseFromParent();
1672  return true;
1673 }
1674 
1675 bool AVRExpandPseudo::expandLSRW12Rd(Block &MBB, BlockIt MBBI) {
1676  MachineInstr &MI = *MBBI;
1677  Register DstLoReg, DstHiReg;
1678  Register DstReg = MI.getOperand(0).getReg();
1679  bool DstIsDead = MI.getOperand(0).isDead();
1680  bool DstIsKill = MI.getOperand(1).isKill();
1681  bool ImpIsDead = MI.getOperand(3).isDead();
1682  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1683 
1684  // Move upper byte to lower byte.
1685  buildMI(MBB, MBBI, AVR::MOVRdRr)
1686  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1687  .addReg(DstHiReg);
1688 
1689  // swap Rl
1690  buildMI(MBB, MBBI, AVR::SWAPRd)
1691  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1692  .addReg(DstLoReg, RegState::Kill);
1693 
1694  // andi Rl, 0xf
1695  auto MI0 =
1696  buildMI(MBB, MBBI, AVR::ANDIRdK)
1697  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1698  .addReg(DstLoReg, getKillRegState(DstIsKill))
1699  .addImm(0xf);
1700  // SREG is implicitly dead.
1701  MI0->getOperand(3).setIsDead();
1702 
1703  // Clear upper byte.
1704  auto MIBHI =
1705  buildMI(MBB, MBBI, AVR::EORRdRr)
1706  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1707  .addReg(DstHiReg, getKillRegState(DstIsKill))
1708  .addReg(DstHiReg, getKillRegState(DstIsKill));
1709  if (ImpIsDead)
1710  MIBHI->getOperand(3).setIsDead();
1711 
1712  MI.eraseFromParent();
1713  return true;
1714 }
1715 
1716 template <>
1717 bool AVRExpandPseudo::expand<AVR::LSRWNRd>(Block &MBB, BlockIt MBBI) {
1718  MachineInstr &MI = *MBBI;
1719  unsigned Imm = MI.getOperand(2).getImm();
1720  switch (Imm) {
1721  case 4:
1722  return expandLSRW4Rd(MBB, MBBI);
1723  case 8:
1724  return expandLSRW8Rd(MBB, MBBI);
1725  case 12:
1726  return expandLSRW12Rd(MBB, MBBI);
1727  default:
1728  llvm_unreachable("unimplemented lsrwn");
1729  return false;
1730  }
1731 }
1732 
1733 template <>
1734 bool AVRExpandPseudo::expand<AVR::RORWRd>(Block &MBB, BlockIt MBBI) {
1735  llvm_unreachable("RORW unimplemented");
1736  return false;
1737 }
1738 
1739 template <>
1740 bool AVRExpandPseudo::expand<AVR::ROLWRd>(Block &MBB, BlockIt MBBI) {
1741  llvm_unreachable("ROLW unimplemented");
1742  return false;
1743 }
1744 
1745 template <>
1746 bool AVRExpandPseudo::expand<AVR::ASRWRd>(Block &MBB, BlockIt MBBI) {
1747  MachineInstr &MI = *MBBI;
1748  Register DstLoReg, DstHiReg;
1749  Register DstReg = MI.getOperand(0).getReg();
1750  bool DstIsDead = MI.getOperand(0).isDead();
1751  bool DstIsKill = MI.getOperand(1).isKill();
1752  bool ImpIsDead = MI.getOperand(2).isDead();
1753  unsigned OpLo = AVR::RORRd;
1754  unsigned OpHi = AVR::ASRRd;
1755  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1756 
1757  // High part
1758  buildMI(MBB, MBBI, OpHi)
1759  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1760  .addReg(DstHiReg, getKillRegState(DstIsKill));
1761 
1762  auto MIBLO =
1763  buildMI(MBB, MBBI, OpLo)
1764  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1765  .addReg(DstLoReg, getKillRegState(DstIsKill));
1766 
1767  if (ImpIsDead)
1768  MIBLO->getOperand(2).setIsDead();
1769 
1770  // SREG is always implicitly killed
1771  MIBLO->getOperand(3).setIsKill();
1772 
1773  MI.eraseFromParent();
1774  return true;
1775 }
1776 
1777 template <>
1778 bool AVRExpandPseudo::expand<AVR::ASRWLoRd>(Block &MBB, BlockIt MBBI) {
1779  MachineInstr &MI = *MBBI;
1780  Register DstLoReg, DstHiReg;
1781  Register DstReg = MI.getOperand(0).getReg();
1782  bool DstIsDead = MI.getOperand(0).isDead();
1783  bool DstIsKill = MI.getOperand(1).isKill();
1784  bool ImpIsDead = MI.getOperand(2).isDead();
1785  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1786 
1787  // asr loreg
1788  auto MIASR =
1789  buildMI(MBB, MBBI, AVR::ASRRd)
1790  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1791  .addReg(DstLoReg, getKillRegState(DstIsKill));
1792 
1793  if (ImpIsDead)
1794  MIASR->getOperand(2).setIsDead();
1795 
1796  MI.eraseFromParent();
1797  return true;
1798 }
1799 
1800 bool AVRExpandPseudo::expandASRW7Rd(Block &MBB, BlockIt MBBI) {
1801  MachineInstr &MI = *MBBI;
1802  Register DstLoReg, DstHiReg;
1803  Register DstReg = MI.getOperand(0).getReg();
1804  bool DstIsDead = MI.getOperand(0).isDead();
1805  bool DstIsKill = MI.getOperand(1).isKill();
1806  bool ImpIsDead = MI.getOperand(3).isDead();
1807  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1808 
1809  // lsl r24
1810  // mov r24,r25
1811  // rol r24
1812  // sbc r25,r25
1813 
1814  // lsl r24 <=> add r24, r24
1815  buildMI(MBB, MBBI, AVR::ADDRdRr)
1816  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1817  .addReg(DstLoReg, RegState::Kill)
1818  .addReg(DstLoReg, RegState::Kill);
1819 
1820  // mov r24, r25
1821  buildMI(MBB, MBBI, AVR::MOVRdRr)
1822  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1823  .addReg(DstHiReg);
1824 
1825  // rol r24 <=> adc r24, r24
1826  buildMI(MBB, MBBI, AVR::ADCRdRr)
1827  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1828  .addReg(DstLoReg, getKillRegState(DstIsKill))
1829  .addReg(DstLoReg, getKillRegState(DstIsKill));
1830 
1831  // sbc r25, r25
1832  auto MISBC =
1833  buildMI(MBB, MBBI, AVR::SBCRdRr)
1834  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1835  .addReg(DstHiReg, getKillRegState(DstIsKill))
1836  .addReg(DstHiReg, getKillRegState(DstIsKill));
1837 
1838  if (ImpIsDead)
1839  MISBC->getOperand(3).setIsDead();
1840  // SREG is always implicitly killed
1841  MISBC->getOperand(4).setIsKill();
1842 
1843  MI.eraseFromParent();
1844  return true;
1845 }
1846 
1847 bool AVRExpandPseudo::expandASRW8Rd(Block &MBB, BlockIt MBBI) {
1848  MachineInstr &MI = *MBBI;
1849  Register DstLoReg, DstHiReg;
1850  Register DstReg = MI.getOperand(0).getReg();
1851  bool DstIsDead = MI.getOperand(0).isDead();
1852  bool DstIsKill = MI.getOperand(1).isKill();
1853  bool ImpIsDead = MI.getOperand(3).isDead();
1854  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1855 
1856  // Move upper byte to lower byte.
1857  buildMI(MBB, MBBI, AVR::MOVRdRr)
1858  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1859  .addReg(DstHiReg);
1860 
1861  // Move the sign bit to the C flag.
1862  buildMI(MBB, MBBI, AVR::ADDRdRr)
1863  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1864  .addReg(DstHiReg, RegState::Kill)
1865  .addReg(DstHiReg, RegState::Kill);
1866 
1867  // Set upper byte to 0 or -1.
1868  auto MIBHI =
1869  buildMI(MBB, MBBI, AVR::SBCRdRr)
1870  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1871  .addReg(DstHiReg, getKillRegState(DstIsKill))
1872  .addReg(DstHiReg, getKillRegState(DstIsKill));
1873 
1874  if (ImpIsDead)
1875  MIBHI->getOperand(3).setIsDead();
1876  // SREG is always implicitly killed
1877  MIBHI->getOperand(4).setIsKill();
1878 
1879  MI.eraseFromParent();
1880  return true;
1881 }
1882 bool AVRExpandPseudo::expandASRW14Rd(Block &MBB, BlockIt MBBI) {
1883  MachineInstr &MI = *MBBI;
1884  Register DstLoReg, DstHiReg;
1885  Register DstReg = MI.getOperand(0).getReg();
1886  bool DstIsDead = MI.getOperand(0).isDead();
1887  bool DstIsKill = MI.getOperand(1).isKill();
1888  bool ImpIsDead = MI.getOperand(3).isDead();
1889  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1890 
1891  // lsl r25
1892  // sbc r24, r24
1893  // lsl r25
1894  // mov r25, r24
1895  // rol r24
1896 
1897  // lsl r25 <=> add r25, r25
1898  buildMI(MBB, MBBI, AVR::ADDRdRr)
1899  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1900  .addReg(DstHiReg, RegState::Kill)
1901  .addReg(DstHiReg, RegState::Kill);
1902 
1903  // sbc r24, r24
1904  buildMI(MBB, MBBI, AVR::SBCRdRr)
1905  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1906  .addReg(DstLoReg, RegState::Kill)
1907  .addReg(DstLoReg, RegState::Kill);
1908 
1909  // lsl r25 <=> add r25, r25
1910  buildMI(MBB, MBBI, AVR::ADDRdRr)
1911  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1912  .addReg(DstHiReg, RegState::Kill)
1913  .addReg(DstHiReg, RegState::Kill);
1914 
1915  // mov r25, r24
1916  buildMI(MBB, MBBI, AVR::MOVRdRr)
1917  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1918  .addReg(DstLoReg);
1919 
1920  // rol r24 <=> adc r24, r24
1921  auto MIROL =
1922  buildMI(MBB, MBBI, AVR::ADCRdRr)
1923  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1924  .addReg(DstLoReg, getKillRegState(DstIsKill))
1925  .addReg(DstLoReg, getKillRegState(DstIsKill));
1926 
1927  if (ImpIsDead)
1928  MIROL->getOperand(3).setIsDead();
1929  // SREG is always implicitly killed
1930  MIROL->getOperand(4).setIsKill();
1931 
1932  MI.eraseFromParent();
1933  return false;
1934 }
1935 
1936 bool AVRExpandPseudo::expandASRW15Rd(Block &MBB, BlockIt MBBI) {
1937  MachineInstr &MI = *MBBI;
1938  Register DstLoReg, DstHiReg;
1939  Register DstReg = MI.getOperand(0).getReg();
1940  bool DstIsDead = MI.getOperand(0).isDead();
1941  bool ImpIsDead = MI.getOperand(3).isDead();
1942  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1943 
1944  // lsl r25
1945  // sbc r25, r25
1946  // mov r24, r25
1947 
1948  // lsl r25 <=> add r25, r25
1949  buildMI(MBB, MBBI, AVR::ADDRdRr)
1950  .addReg(DstHiReg, RegState::Define)
1951  .addReg(DstHiReg, RegState::Kill)
1952  .addReg(DstHiReg, RegState::Kill);
1953 
1954  // sbc r25, r25
1955  auto MISBC =
1956  buildMI(MBB, MBBI, AVR::SBCRdRr)
1957  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1958  .addReg(DstHiReg, RegState::Kill)
1959  .addReg(DstHiReg, RegState::Kill);
1960  if (ImpIsDead)
1961  MISBC->getOperand(3).setIsDead();
1962  // SREG is always implicitly killed
1963  MISBC->getOperand(4).setIsKill();
1964 
1965  // mov r24, r25
1966  buildMI(MBB, MBBI, AVR::MOVRdRr)
1967  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1968  .addReg(DstHiReg);
1969 
1970  MI.eraseFromParent();
1971  return true;
1972 }
1973 
1974 template <>
1975 bool AVRExpandPseudo::expand<AVR::ASRWNRd>(Block &MBB, BlockIt MBBI) {
1976  MachineInstr &MI = *MBBI;
1977  unsigned Imm = MI.getOperand(2).getImm();
1978  switch (Imm) {
1979  case 7:
1980  return expandASRW7Rd(MBB, MBBI);
1981  case 8:
1982  return expandASRW8Rd(MBB, MBBI);
1983  case 14:
1984  return expandASRW14Rd(MBB, MBBI);
1985  case 15:
1986  return expandASRW15Rd(MBB, MBBI);
1987  default:
1988  llvm_unreachable("unimplemented asrwn");
1989  return false;
1990  }
1991 }
1992 
1993 bool AVRExpandPseudo::expandLSLB7Rd(Block &MBB, BlockIt MBBI) {
1994  MachineInstr &MI = *MBBI;
1995  Register DstReg = MI.getOperand(0).getReg();
1996  bool DstIsDead = MI.getOperand(0).isDead();
1997  bool DstIsKill = MI.getOperand(1).isKill();
1998  bool ImpIsDead = MI.getOperand(3).isDead();
1999 
2000  // ror r24
2001  // clr r24
2002  // ror r24
2003 
2004  buildMI(MBB, MBBI, AVR::RORRd)
2005  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2006  .addReg(DstReg, RegState::Kill)
2007  ->getOperand(3)
2008  .setIsUndef(true);
2009 
2010  buildMI(MBB, MBBI, AVR::EORRdRr)
2011  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2012  .addReg(DstReg, RegState::Kill)
2013  .addReg(DstReg, RegState::Kill);
2014 
2015  auto MIRRC =
2016  buildMI(MBB, MBBI, AVR::RORRd)
2017  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2018  .addReg(DstReg, getKillRegState(DstIsKill));
2019 
2020  if (ImpIsDead)
2021  MIRRC->getOperand(2).setIsDead();
2022 
2023  // SREG is always implicitly killed
2024  MIRRC->getOperand(3).setIsKill();
2025 
2026  MI.eraseFromParent();
2027  return true;
2028 }
2029 
2030 template <>
2031 bool AVRExpandPseudo::expand<AVR::LSLBNRd>(Block &MBB, BlockIt MBBI) {
2032  MachineInstr &MI = *MBBI;
2033  unsigned Imm = MI.getOperand(2).getImm();
2034  switch (Imm) {
2035  case 7:
2036  return expandLSLB7Rd(MBB, MBBI);
2037  default:
2038  llvm_unreachable("unimplemented lslbn");
2039  return false;
2040  }
2041 }
2042 
2043 bool AVRExpandPseudo::expandLSRB7Rd(Block &MBB, BlockIt MBBI) {
2044  MachineInstr &MI = *MBBI;
2045  Register DstReg = MI.getOperand(0).getReg();
2046  bool DstIsDead = MI.getOperand(0).isDead();
2047  bool DstIsKill = MI.getOperand(1).isKill();
2048  bool ImpIsDead = MI.getOperand(3).isDead();
2049 
2050  // rol r24
2051  // clr r24
2052  // rol r24
2053 
2054  buildMI(MBB, MBBI, AVR::ADCRdRr)
2055  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2056  .addReg(DstReg, RegState::Kill)
2057  .addReg(DstReg, RegState::Kill)
2058  ->getOperand(4)
2059  .setIsUndef(true);
2060 
2061  buildMI(MBB, MBBI, AVR::EORRdRr)
2062  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2063  .addReg(DstReg, RegState::Kill)
2064  .addReg(DstReg, RegState::Kill);
2065 
2066  auto MIRRC =
2067  buildMI(MBB, MBBI, AVR::ADCRdRr)
2068  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2069  .addReg(DstReg, getKillRegState(DstIsKill))
2070  .addReg(DstReg, getKillRegState(DstIsKill));
2071 
2072  if (ImpIsDead)
2073  MIRRC->getOperand(3).setIsDead();
2074 
2075  // SREG is always implicitly killed
2076  MIRRC->getOperand(4).setIsKill();
2077 
2078  MI.eraseFromParent();
2079  return true;
2080 }
2081 
2082 template <>
2083 bool AVRExpandPseudo::expand<AVR::LSRBNRd>(Block &MBB, BlockIt MBBI) {
2084  MachineInstr &MI = *MBBI;
2085  unsigned Imm = MI.getOperand(2).getImm();
2086  switch (Imm) {
2087  case 7:
2088  return expandLSRB7Rd(MBB, MBBI);
2089  default:
2090  llvm_unreachable("unimplemented lsrbn");
2091  return false;
2092  }
2093 }
2094 
2095 bool AVRExpandPseudo::expandASRB6Rd(Block &MBB, BlockIt MBBI) {
2096  MachineInstr &MI = *MBBI;
2097  Register DstReg = MI.getOperand(0).getReg();
2098  bool DstIsDead = MI.getOperand(0).isDead();
2099  bool DstIsKill = MI.getOperand(1).isKill();
2100 
2101  // bst r24, 6
2102  // lsl r24
2103  // sbc r24, r24
2104  // bld r24, 0
2105 
2106  buildMI(MBB, MBBI, AVR::BST)
2107  .addReg(DstReg)
2108  .addImm(6)
2109  ->getOperand(2)
2110  .setIsUndef(true);
2111 
2112  buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rd
2113  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2114  .addReg(DstReg, RegState::Kill)
2115  .addReg(DstReg, RegState::Kill);
2116 
2117  buildMI(MBB, MBBI, AVR::SBCRdRr)
2118  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2119  .addReg(DstReg, RegState::Kill)
2120  .addReg(DstReg, RegState::Kill);
2121 
2122  buildMI(MBB, MBBI, AVR::BLD)
2123  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2124  .addReg(DstReg, getKillRegState(DstIsKill))
2125  .addImm(0)
2126  ->getOperand(3)
2127  .setIsKill();
2128 
2129  MI.eraseFromParent();
2130  return true;
2131 }
2132 
2133 bool AVRExpandPseudo::expandASRB7Rd(Block &MBB, BlockIt MBBI) {
2134  MachineInstr &MI = *MBBI;
2135  Register DstReg = MI.getOperand(0).getReg();
2136  bool DstIsDead = MI.getOperand(0).isDead();
2137  bool DstIsKill = MI.getOperand(1).isKill();
2138  bool ImpIsDead = MI.getOperand(3).isDead();
2139 
2140  // lsl r24
2141  // sbc r24, r24
2142 
2143  buildMI(MBB, MBBI, AVR::ADDRdRr)
2144  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2145  .addReg(DstReg, RegState::Kill)
2146  .addReg(DstReg, RegState::Kill);
2147 
2148  auto MIRRC =
2149  buildMI(MBB, MBBI, AVR::SBCRdRr)
2150  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
2151  .addReg(DstReg, getKillRegState(DstIsKill))
2152  .addReg(DstReg, getKillRegState(DstIsKill));
2153 
2154  if (ImpIsDead)
2155  MIRRC->getOperand(3).setIsDead();
2156 
2157  // SREG is always implicitly killed
2158  MIRRC->getOperand(4).setIsKill();
2159 
2160  MI.eraseFromParent();
2161  return true;
2162 }
2163 
2164 template <>
2165 bool AVRExpandPseudo::expand<AVR::ASRBNRd>(Block &MBB, BlockIt MBBI) {
2166  MachineInstr &MI = *MBBI;
2167  unsigned Imm = MI.getOperand(2).getImm();
2168  switch (Imm) {
2169  case 6:
2170  return expandASRB6Rd(MBB, MBBI);
2171  case 7:
2172  return expandASRB7Rd(MBB, MBBI);
2173  default:
2174  llvm_unreachable("unimplemented asrbn");
2175  return false;
2176  }
2177 }
2178 
2179 template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {
2180  MachineInstr &MI = *MBBI;
2181  Register DstLoReg, DstHiReg;
2182  // sext R17:R16, R17
2183  // mov r16, r17
2184  // lsl r17
2185  // sbc r17, r17
2186  // sext R17:R16, R13
2187  // mov r16, r13
2188  // mov r17, r13
2189  // lsl r17
2190  // sbc r17, r17
2191  // sext R17:R16, R16
2192  // mov r17, r16
2193  // lsl r17
2194  // sbc r17, r17
2195  Register DstReg = MI.getOperand(0).getReg();
2196  Register SrcReg = MI.getOperand(1).getReg();
2197  bool DstIsDead = MI.getOperand(0).isDead();
2198  bool SrcIsKill = MI.getOperand(1).isKill();
2199  bool ImpIsDead = MI.getOperand(2).isDead();
2200  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2201 
2202  if (SrcReg != DstLoReg)
2203  buildMI(MBB, MBBI, AVR::MOVRdRr)
2204  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2205  .addReg(SrcReg);
2206 
2207  if (SrcReg != DstHiReg) {
2208  auto MOV = buildMI(MBB, MBBI, AVR::MOVRdRr)
2209  .addReg(DstHiReg, RegState::Define)
2210  .addReg(SrcReg);
2211  if (SrcReg != DstLoReg && SrcIsKill)
2212  MOV->getOperand(1).setIsKill();
2213  }
2214 
2215  buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr
2216  .addReg(DstHiReg, RegState::Define)
2217  .addReg(DstHiReg, RegState::Kill)
2218  .addReg(DstHiReg, RegState::Kill);
2219 
2220  auto SBC =
2221  buildMI(MBB, MBBI, AVR::SBCRdRr)
2222  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2223  .addReg(DstHiReg, RegState::Kill)
2224  .addReg(DstHiReg, RegState::Kill);
2225 
2226  if (ImpIsDead)
2227  SBC->getOperand(3).setIsDead();
2228 
2229  // SREG is always implicitly killed
2230  SBC->getOperand(4).setIsKill();
2231 
2232  MI.eraseFromParent();
2233  return true;
2234 }
2235 
2236 template <> bool AVRExpandPseudo::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) {
2237  MachineInstr &MI = *MBBI;
2238  Register DstLoReg, DstHiReg;
2239  // zext R25:R24, R20
2240  // mov R24, R20
2241  // eor R25, R25
2242  // zext R25:R24, R24
2243  // eor R25, R25
2244  // zext R25:R24, R25
2245  // mov R24, R25
2246  // eor R25, R25
2247  Register DstReg = MI.getOperand(0).getReg();
2248  Register SrcReg = MI.getOperand(1).getReg();
2249  bool DstIsDead = MI.getOperand(0).isDead();
2250  bool SrcIsKill = MI.getOperand(1).isKill();
2251  bool ImpIsDead = MI.getOperand(2).isDead();
2252  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2253 
2254  if (SrcReg != DstLoReg) {
2255  buildMI(MBB, MBBI, AVR::MOVRdRr)
2256  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2257  .addReg(SrcReg, getKillRegState(SrcIsKill));
2258  }
2259 
2260  auto EOR =
2261  buildMI(MBB, MBBI, AVR::EORRdRr)
2262  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2263  .addReg(DstHiReg, RegState::Kill | RegState::Undef)
2264  .addReg(DstHiReg, RegState::Kill | RegState::Undef);
2265 
2266  if (ImpIsDead)
2267  EOR->getOperand(3).setIsDead();
2268 
2269  MI.eraseFromParent();
2270  return true;
2271 }
2272 
2273 template <>
2274 bool AVRExpandPseudo::expand<AVR::SPREAD>(Block &MBB, BlockIt MBBI) {
2275  MachineInstr &MI = *MBBI;
2276  Register DstLoReg, DstHiReg;
2277  Register DstReg = MI.getOperand(0).getReg();
2278  bool DstIsDead = MI.getOperand(0).isDead();
2279  unsigned Flags = MI.getFlags();
2280  unsigned OpLo = AVR::INRdA;
2281  unsigned OpHi = AVR::INRdA;
2282  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
2283 
2284  // Low part
2285  buildMI(MBB, MBBI, OpLo)
2286  .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
2287  .addImm(0x3d)
2288  .setMIFlags(Flags);
2289 
2290  // High part
2291  buildMI(MBB, MBBI, OpHi)
2292  .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
2293  .addImm(0x3e)
2294  .setMIFlags(Flags);
2295 
2296  MI.eraseFromParent();
2297  return true;
2298 }
2299 
2300 template <>
2301 bool AVRExpandPseudo::expand<AVR::SPWRITE>(Block &MBB, BlockIt MBBI) {
2302  const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
2303  MachineInstr &MI = *MBBI;
2304  Register SrcLoReg, SrcHiReg;
2305  Register SrcReg = MI.getOperand(1).getReg();
2306  bool SrcIsKill = MI.getOperand(1).isKill();
2307  unsigned Flags = MI.getFlags();
2308  TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
2309 
2310  buildMI(MBB, MBBI, AVR::INRdA)
2311  .addReg(STI.getTmpRegister(), RegState::Define)
2312  .addImm(STI.getIORegSREG())
2313  .setMIFlags(Flags);
2314 
2315  buildMI(MBB, MBBI, AVR::BCLRs).addImm(0x07).setMIFlags(Flags);
2316 
2317  buildMI(MBB, MBBI, AVR::OUTARr)
2318  .addImm(0x3e)
2319  .addReg(SrcHiReg, getKillRegState(SrcIsKill))
2320  .setMIFlags(Flags);
2321 
2322  buildMI(MBB, MBBI, AVR::OUTARr)
2323  .addImm(STI.getIORegSREG())
2324  .addReg(STI.getTmpRegister(), RegState::Kill)
2325  .setMIFlags(Flags);
2326 
2327  buildMI(MBB, MBBI, AVR::OUTARr)
2328  .addImm(0x3d)
2329  .addReg(SrcLoReg, getKillRegState(SrcIsKill))
2330  .setMIFlags(Flags);
2331 
2332  MI.eraseFromParent();
2333  return true;
2334 }
2335 
2336 bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
2337  MachineInstr &MI = *MBBI;
2338  int Opcode = MBBI->getOpcode();
2339 
2340 #define EXPAND(Op) \
2341  case Op: \
2342  return expand<Op>(MBB, MI)
2343 
2344  switch (Opcode) {
2345  EXPAND(AVR::ADDWRdRr);
2346  EXPAND(AVR::ADCWRdRr);
2347  EXPAND(AVR::SUBWRdRr);
2348  EXPAND(AVR::SUBIWRdK);
2349  EXPAND(AVR::SBCWRdRr);
2350  EXPAND(AVR::SBCIWRdK);
2351  EXPAND(AVR::ANDWRdRr);
2352  EXPAND(AVR::ANDIWRdK);
2353  EXPAND(AVR::ORWRdRr);
2354  EXPAND(AVR::ORIWRdK);
2355  EXPAND(AVR::EORWRdRr);
2356  EXPAND(AVR::COMWRd);
2357  EXPAND(AVR::NEGWRd);
2358  EXPAND(AVR::CPWRdRr);
2359  EXPAND(AVR::CPCWRdRr);
2360  EXPAND(AVR::LDIWRdK);
2361  EXPAND(AVR::LDSWRdK);
2362  EXPAND(AVR::LDWRdPtr);
2363  EXPAND(AVR::LDWRdPtrPi);
2364  EXPAND(AVR::LDWRdPtrPd);
2365  case AVR::LDDWRdYQ: //: FIXME: remove this once PR13375 gets fixed
2366  EXPAND(AVR::LDDWRdPtrQ);
2367  EXPAND(AVR::LPMWRdZ);
2368  EXPAND(AVR::LPMWRdZPi);
2369  EXPAND(AVR::ELPMBRdZ);
2370  EXPAND(AVR::ELPMWRdZ);
2371  EXPAND(AVR::ELPMBRdZPi);
2372  EXPAND(AVR::ELPMWRdZPi);
2373  EXPAND(AVR::AtomicLoad8);
2374  EXPAND(AVR::AtomicLoad16);
2375  EXPAND(AVR::AtomicStore8);
2376  EXPAND(AVR::AtomicStore16);
2377  EXPAND(AVR::AtomicFence);
2378  EXPAND(AVR::STSWKRr);
2379  EXPAND(AVR::STWPtrRr);
2380  EXPAND(AVR::STWPtrPiRr);
2381  EXPAND(AVR::STWPtrPdRr);
2382  EXPAND(AVR::STDWPtrQRr);
2383  EXPAND(AVR::STDSPQRr);
2384  EXPAND(AVR::STDWSPQRr);
2385  EXPAND(AVR::INWRdA);
2386  EXPAND(AVR::OUTWARr);
2387  EXPAND(AVR::PUSHWRr);
2388  EXPAND(AVR::POPWRd);
2389  EXPAND(AVR::ROLBRd);
2390  EXPAND(AVR::RORBRd);
2391  EXPAND(AVR::LSLWRd);
2392  EXPAND(AVR::LSRWRd);
2393  EXPAND(AVR::RORWRd);
2394  EXPAND(AVR::ROLWRd);
2395  EXPAND(AVR::ASRWRd);
2396  EXPAND(AVR::LSLWHiRd);
2397  EXPAND(AVR::LSRWLoRd);
2398  EXPAND(AVR::ASRWLoRd);
2399  EXPAND(AVR::LSLWNRd);
2400  EXPAND(AVR::LSRWNRd);
2401  EXPAND(AVR::ASRWNRd);
2402  EXPAND(AVR::LSLBNRd);
2403  EXPAND(AVR::LSRBNRd);
2404  EXPAND(AVR::ASRBNRd);
2405  EXPAND(AVR::SEXT);
2406  EXPAND(AVR::ZEXT);
2407  EXPAND(AVR::SPREAD);
2408  EXPAND(AVR::SPWRITE);
2409  }
2410 #undef EXPAND
2411  return false;
2412 }
2413 
2414 } // end of anonymous namespace
2415 
2416 INITIALIZE_PASS(AVRExpandPseudo, "avr-expand-pseudo", AVR_EXPAND_PSEUDO_NAME,
2417  false, false)
2418 namespace llvm {
2419 
2420 FunctionPass *createAVRExpandPseudoPass() { return new AVRExpandPseudo(); }
2421 
2422 } // end of namespace llvm
llvm::MachineOperand::MO_BlockAddress
@ MO_BlockAddress
Address of a basic block.
Definition: MachineOperand.h:62
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:108
llvm::MachineOperand::MO_Immediate
@ MO_Immediate
Immediate operand.
Definition: MachineOperand.h:52
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::AArch64PACKey::ID
ID
Definition: AArch64BaseInfo.h:818
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
EXPAND
#define EXPAND(Op)
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::RegState::Define
@ Define
Register definition.
Definition: MachineInstrBuilder.h:44
INITIALIZE_PASS
INITIALIZE_PASS(AVRExpandPseudo, "avr-expand-pseudo", AVR_EXPAND_PSEUDO_NAME, false, false) namespace llvm
Definition: AVRExpandPseudoInsts.cpp:2416
llvm::getDeadRegState
unsigned getDeadRegState(bool B)
Definition: MachineInstrBuilder.h:549
llvm::AVRSubtarget::getIORegRAMPZ
int getIORegRAMPZ() const
Get I/O register addresses.
Definition: AVRSubtarget.h:96
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::getUndefRegState
unsigned getUndefRegState(bool B)
Definition: MachineInstrBuilder.h:552
MachineRegisterInfo.h
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::MachineOperand::MO_GlobalAddress
@ MO_GlobalAddress
Address of a global value.
Definition: MachineOperand.h:61
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::AVRSubtarget::getTmpRegister
Register getTmpRegister() const
Definition: AVRSubtarget.h:106
llvm::AVRSubtarget
A specific AVR target MCU.
Definition: AVRSubtarget.h:32
llvm::TargetFrameLowering::hasReservedCallFrame
virtual bool hasReservedCallFrame(const MachineFunction &MF) const
hasReservedCallFrame - Under normal circumstances, when a frame pointer is not required,...
Definition: TargetFrameLowering.h:292
llvm::MachineBasicBlock::eraseFromParent
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition: MachineBasicBlock.cpp:1347
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
LoopDeletionResult::Modified
@ Modified
llvm::AVRSubtarget::getInstrInfo
const AVRInstrInfo * getInstrInfo() const override
Definition: AVRSubtarget.h:42
llvm::initializeAVRExpandPseudoPass
void initializeAVRExpandPseudoPass(PassRegistry &)
AVR_EXPAND_PSEUDO_NAME
#define AVR_EXPAND_PSEUDO_NAME
Definition: AVRExpandPseudoInsts.cpp:27
llvm::AArch64ISD::SBC
@ SBC
Definition: AArch64ISelLowering.h:91
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::GlobalValue
Definition: GlobalValue.h:44
expand
static Expected< BitVector > expand(StringRef S, StringRef Original)
Definition: GlobPattern.cpp:27
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
llvm::AVRRegisterInfo
Utilities relating to AVR registers.
Definition: AVRRegisterInfo.h:24
MachineFunctionPass.h
llvm::SISrcMods::SEXT
@ SEXT
Definition: SIDefines.h:221
AVRTargetMachine.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:261
llvm::MachineOperand::CreateBA
static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, unsigned TargetFlags=0)
Definition: MachineOperand.h:875
AVRMCTargetDesc.h
llvm::AVRII::MO_NEG
@ MO_NEG
On a symbol operand, this represents it has to be negated.
Definition: AVRInstrInfo.h:58
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::BlockAddress
The address of a basic block.
Definition: Constants.h:849
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::AVRSubtarget::getFrameLowering
const TargetFrameLowering * getFrameLowering() const override
Definition: AVRSubtarget.h:43
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
AVR.h
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::getKillRegState
unsigned getKillRegState(bool B)
Definition: MachineInstrBuilder.h:546
llvm::AVRSubtarget::getRegisterInfo
const AVRRegisterInfo * getRegisterInfo() const override
Definition: AVRSubtarget.h:52
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:357
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:305
MachineInstrBuilder.h
AVRInstrInfo.h
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::AVRSubtarget::getIORegSREG
int getIORegSREG() const
Definition: AVRSubtarget.h:100
llvm::AVRII::MO_LO
@ MO_LO
On a symbol operand, this represents the lo part.
Definition: AVRInstrInfo.h:52
TargetRegisterInfo.h
llvm::createAVRExpandPseudoPass
FunctionPass * createAVRExpandPseudoPass()
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:307
llvm::AVRII::MO_HI
@ MO_HI
On a symbol operand, this represents the hi part.
Definition: AVRInstrInfo.h:55