LLVM  14.0.0git
ExpandPostRAPseudos.cpp
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1 //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
10 // instructions after register allocation.
11 //
12 //===----------------------------------------------------------------------===//
13 
18 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/InitializePasses.h"
23 #include "llvm/Support/Debug.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "postrapseudos"
29 
30 namespace {
31 struct ExpandPostRA : public MachineFunctionPass {
32 private:
33  const TargetRegisterInfo *TRI;
34  const TargetInstrInfo *TII;
35 
36 public:
37  static char ID; // Pass identification, replacement for typeid
38  ExpandPostRA() : MachineFunctionPass(ID) {}
39 
40  void getAnalysisUsage(AnalysisUsage &AU) const override {
41  AU.setPreservesCFG();
45  }
46 
47  /// runOnMachineFunction - pass entry point
48  bool runOnMachineFunction(MachineFunction&) override;
49 
50 private:
51  bool LowerSubregToReg(MachineInstr *MI);
52  bool LowerCopy(MachineInstr *MI);
53 
54  void TransferImplicitOperands(MachineInstr *MI);
55 };
56 } // end anonymous namespace
57 
58 char ExpandPostRA::ID = 0;
60 
62  "Post-RA pseudo instruction expansion pass", false, false)
63 
64 /// TransferImplicitOperands - MI is a pseudo-instruction, and the lowered
65 /// replacement instructions immediately precede it. Copy any implicit
66 /// operands from MI to the replacement instruction.
67 void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) {
69  --CopyMI;
70 
71  for (const MachineOperand &MO : MI->implicit_operands())
72  if (MO.isReg())
73  CopyMI->addOperand(MO);
74 }
75 
76 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
77  MachineBasicBlock *MBB = MI->getParent();
78  assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
79  MI->getOperand(1).isImm() &&
80  (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
81  MI->getOperand(3).isImm() && "Invalid subreg_to_reg");
82 
83  Register DstReg = MI->getOperand(0).getReg();
84  Register InsReg = MI->getOperand(2).getReg();
85  assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
86  unsigned SubIdx = MI->getOperand(3).getImm();
87 
88  assert(SubIdx != 0 && "Invalid index for insert_subreg");
89  Register DstSubReg = TRI->getSubReg(DstReg, SubIdx);
90 
92  "Insert destination must be in a physical register");
94  "Inserted value must be in a physical register");
95 
96  LLVM_DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
97 
98  if (MI->allDefsAreDead()) {
99  MI->setDesc(TII->get(TargetOpcode::KILL));
100  MI->RemoveOperand(3); // SubIdx
101  MI->RemoveOperand(1); // Imm
102  LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI);
103  return true;
104  }
105 
106  if (DstSubReg == InsReg) {
107  // No need to insert an identity copy instruction.
108  // Watch out for case like this:
109  // %rax = SUBREG_TO_REG 0, killed %eax, 3
110  // We must leave %rax live.
111  if (DstReg != InsReg) {
112  MI->setDesc(TII->get(TargetOpcode::KILL));
113  MI->RemoveOperand(3); // SubIdx
114  MI->RemoveOperand(1); // Imm
115  LLVM_DEBUG(dbgs() << "subreg: replace by: " << *MI);
116  return true;
117  }
118  LLVM_DEBUG(dbgs() << "subreg: eliminated!");
119  } else {
120  TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
121  MI->getOperand(2).isKill());
122 
123  // Implicitly define DstReg for subsequent uses.
125  --CopyMI;
126  CopyMI->addRegisterDefined(DstReg);
127  LLVM_DEBUG(dbgs() << "subreg: " << *CopyMI);
128  }
129 
130  LLVM_DEBUG(dbgs() << '\n');
131  MBB->erase(MI);
132  return true;
133 }
134 
135 bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
136 
137  if (MI->allDefsAreDead()) {
138  LLVM_DEBUG(dbgs() << "dead copy: " << *MI);
139  MI->setDesc(TII->get(TargetOpcode::KILL));
140  LLVM_DEBUG(dbgs() << "replaced by: " << *MI);
141  return true;
142  }
143 
144  MachineOperand &DstMO = MI->getOperand(0);
145  MachineOperand &SrcMO = MI->getOperand(1);
146 
147  bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg());
148  if (IdentityCopy || SrcMO.isUndef()) {
149  LLVM_DEBUG(dbgs() << (IdentityCopy ? "identity copy: " : "undef copy: ")
150  << *MI);
151  // No need to insert an identity copy instruction, but replace with a KILL
152  // if liveness is changed.
153  if (SrcMO.isUndef() || MI->getNumOperands() > 2) {
154  // We must make sure the super-register gets killed. Replace the
155  // instruction with KILL.
156  MI->setDesc(TII->get(TargetOpcode::KILL));
157  LLVM_DEBUG(dbgs() << "replaced by: " << *MI);
158  return true;
159  }
160  // Vanilla identity copy.
161  MI->eraseFromParent();
162  return true;
163  }
164 
165  LLVM_DEBUG(dbgs() << "real copy: " << *MI);
166  TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
167  DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
168 
169  if (MI->getNumOperands() > 2)
170  TransferImplicitOperands(MI);
171  LLVM_DEBUG({
173  dbgs() << "replaced by: " << *(--dMI);
174  });
175  MI->eraseFromParent();
176  return true;
177 }
178 
179 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
180 /// copies.
181 ///
182 bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
183  LLVM_DEBUG(dbgs() << "Machine Function\n"
184  << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
185  << "********** Function: " << MF.getName() << '\n');
187  TII = MF.getSubtarget().getInstrInfo();
188 
189  bool MadeChange = false;
190 
191  for (MachineBasicBlock &MBB : MF) {
193  // Only expand pseudos.
194  if (!MI.isPseudo())
195  continue;
196 
197  // Give targets a chance to expand even standard pseudos.
198  if (TII->expandPostRAPseudo(MI)) {
199  MadeChange = true;
200  continue;
201  }
202 
203  // Expand standard pseudos.
204  switch (MI.getOpcode()) {
205  case TargetOpcode::SUBREG_TO_REG:
206  MadeChange |= LowerSubregToReg(&MI);
207  break;
208  case TargetOpcode::COPY:
209  MadeChange |= LowerCopy(&MI);
210  break;
211  case TargetOpcode::DBG_VALUE:
212  continue;
213  case TargetOpcode::INSERT_SUBREG:
214  case TargetOpcode::EXTRACT_SUBREG:
215  llvm_unreachable("Sub-register pseudos should have been eliminated.");
216  }
217  }
218  }
219 
220  return MadeChange;
221 }
MI
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Definition: IRTranslator.cpp:105
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
DEBUG_TYPE
#define DEBUG_TYPE
Definition: ExpandPostRAPseudos.cpp:28
INITIALIZE_PASS
INITIALIZE_PASS(ExpandPostRA, DEBUG_TYPE, "Post-RA pseudo instruction expansion pass", false, false) void ExpandPostRA
TransferImplicitOperands - MI is a pseudo-instruction, and the lowered replacement instructions immed...
Definition: ExpandPostRAPseudos.cpp:61
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:92
llvm::ExpandPostRAPseudosID
char & ExpandPostRAPseudosID
ExpandPostRAPseudos - This pass expands pseudo instructions after register allocation.
Definition: ExpandPostRAPseudos.cpp:59
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
TargetInstrInfo.h
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MachineRegisterInfo.h
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instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1301
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachineOperand::isKill
bool isKill() const
Definition: MachineOperand.h:390
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::Register::isPhysicalRegister
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:65
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
Passes.h
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:634
llvm::MachineLoopInfoID
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Definition: MachineLoopInfo.cpp:44
llvm::MachineOperand::isUndef
bool isUndef() const
Definition: MachineOperand.h:395
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::make_early_inc_range
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:593
MachineFunctionPass.h
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:542
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::HexagonInstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
This function is called for all pseudo instructions that remain after register allocation.
Definition: HexagonInstrInfo.cpp:1000
llvm::AnalysisUsage::setPreservesCFG
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:253
llvm::AnalysisUsage::addPreservedID
AnalysisUsage & addPreservedID(const void *ID)
Definition: PassAnalysisSupport.h:88
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
TargetSubtargetInfo.h
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
MachineInstrBuilder.h
llvm::MachineDominatorsID
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
llvm::TargetRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: TargetRegisterInfo.h:1094
raw_ostream.h
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::HexagonInstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Emit instructions to copy a pair of physical registers.
Definition: HexagonInstrInfo.cpp:810
InitializePasses.h
TargetRegisterInfo.h
Debug.h
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unsigned ID
Definition: TargetTransformInfo.h:38