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22 #include "llvm/Config/llvm-config.h"
38 "Machine Natural Loop Construction",
true,
true)
46 calculate(getAnalysis<MachineDominatorTree>());
104 if (
const BasicBlock *PHeadBB = PHeadMBB->getBasicBlock())
105 if (
DebugLoc DL = PHeadBB->getTerminator()->getDebugLoc())
111 if (
const BasicBlock *HeadBB = HeadMBB->getBasicBlock())
112 return HeadBB->getTerminator()->getDebugLoc();
119 bool FindMultiLoopPreheader)
const {
123 if (!SpeculativePreheader)
142 if (!FindMultiLoopPreheader) {
147 if (
T &&
T->getHeader() ==
S)
167 if (
Reg == 0)
continue;
180 !
TII->isIgnorableUse(MO))
184 }
else if (!MO.isDead()) {
198 "Machine instr not mapped for this vreg?!");
210 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
This is an optimization pass for GlobalISel generic memory operations.
void calculate(MachineDominatorTree &MDT)
MachineLoop * getLoopFor(const MachineBasicBlock *BB) const
Return the innermost loop that BB lives in.
INITIALIZE_PASS_BEGIN(MachineLoopInfo, "machine-loops", "Machine Natural Loop Construction", true, true) INITIALIZE_PASS_END(MachineLoopInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Represents a single loop in the control flow graph.
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
bool contains(const MachineLoop *L) const
Return true if the specified loop is contained within in this loop.
MachineBasicBlock * findLoopPreheader(MachineLoop *L, bool SpeculativePreheader=false, bool FindMultiLoopPreheader=false) const
Find the block that either is the loop preheader, or could speculatively be used as the preheader.
Reg
All possible values of the reg field in the ModR/M byte.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MachineBasicBlock * getBottomBlock()
Return the "bottom" block in the loop, which is the last block in the linear layout,...
unsigned const TargetRegisterInfo * TRI
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
LLVM Basic Block Representation.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
unsigned pred_size() const
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
TargetInstrInfo - Interface to description of machine instruction set.
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Represent the analysis usage information of a pass.
MachineBasicBlock * findLoopControlBlock()
Find the block that contains the loop control variable and the loop test.
const HexagonInstrInfo * TII
MachineOperand class - Representation of each machine instruction operand.
MachineBasicBlock * getExitingBlock() const
If getExitingBlocks would return exactly one block, return that block.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
PassBuilder PB(Machine, PassOpts->PTO, None, &PIC)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Representation of each machine instruction.
void initializeMachineLoopInfoPass(PassRegistry &)
bool hasAddressTaken() const
Test whether this block is potentially the target of an indirect branch.
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
MachineBasicBlock * getLoopPreheader() const
If there is a preheader for this loop, return it.
machine Machine Natural Loop true
MachineBasicBlock * getLoopLatch() const
If there is a single latch block for this loop, return it.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< pred_iterator > predecessors()
iterator_range< succ_iterator > successors()
self_iterator getIterator()
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
void setPreservesAll()
Set by analyses that do not transform their input at all.
Iterator for intrusive lists based on ilist_node.
This class builds and contains all of the top-level loop structures in the specified function.
DebugLoc getStartLoc() const
Return the debug location of the start of this loop.
MachineBasicBlock * getHeader() const
machine Machine Natural Loop Construction
COFF::MachineTypes Machine
MachineDomTree & getBase()
MachineBasicBlock * getTopBlock()
Return the "top" block in the loop, which is the first block in the linear layout,...
bool isLoopExiting(const MachineBasicBlock *BB) const
True if terminator in the block can branch to another block that is outside of the current loop.
void print(raw_ostream &OS, bool Verbose=false, bool PrintNested=true, unsigned Depth=0) const
Print loop with all the BBs inside it.
AnalysisUsage & addRequired()
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
bool isLoopInvariant(MachineInstr &I) const
Returns true if the instruction is loop invariant.