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57 #define DEBUG_TYPE "hexagon-peephole"
61 cl::desc(
"Disable Peephole Optimization"));
65 cl::desc(
"Disable Optimization of PNotP"));
69 cl::desc(
"Disable Optimization of Sign/Zero Extends"));
73 cl::desc(
"Disable Optimization of extensions to i64."));
95 return "Hexagon optimize redundant zero and size extends";
110 if (skipFunction(MF.getFunction()))
113 QII =
static_cast<const HexagonInstrInfo *
>(MF.getSubtarget().getInstrInfo());
115 MRI = &MF.getRegInfo();
124 MBBb != MBBe; ++MBBb) {
127 PeepholeDoubleRegsMap.
clear();
131 NextI = std::next(
I);
146 PeepholeMap[DstReg] = SrcReg;
161 PeepholeMap[DstReg] = SrcReg;
169 if (
MI.getOpcode() == Hexagon::S2_lsr_i_p) {
178 PeepholeDoubleRegsMap[DstReg] =
179 std::make_pair(*&SrcReg, Hexagon::isub_hi);
194 PeepholeMap[DstReg] = SrcReg;
213 if (
unsigned PeepholeSrc = PeepholeMap.
lookup(SrcReg)) {
219 PeepholeDoubleRegsMap.
find(SrcReg);
220 if (DI != PeepholeDoubleRegsMap.
end()) {
221 std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
224 PeepholeSrc.first,
false ,
false ,
225 false ,
false ,
false ,
226 false , PeepholeSrc.second));
235 if (QII->isPredicated(
MI)) {
239 if (RC0->
getID() == Hexagon::PredRegsRegClassID) {
244 if (
unsigned PeepholeSrc = PeepholeMap.
lookup(Reg0)) {
246 MI.getOperand(0).setReg(PeepholeSrc);
248 int NewOp = QII->getInvertedPredicatedOpcode(
MI.getOpcode());
249 MI.setDesc(QII->get(NewOp));
258 unsigned Op =
MI.getOpcode();
260 unsigned PR = 1, S1 = 2, S2 = 3;
263 case Hexagon::C2_mux:
264 case Hexagon::C2_muxii:
267 case Hexagon::C2_muxri:
268 NewOp = Hexagon::C2_muxir;
270 case Hexagon::C2_muxir:
271 NewOp = Hexagon::C2_muxri;
276 if (
unsigned POrig = PeepholeMap.
lookup(PSrc)) {
278 QII->get(NewOp),
MI.getOperand(0).getReg())
280 .
add(
MI.getOperand(S2))
281 .
add(
MI.getOperand(S1));
283 MI.eraseFromParent();
296 return new HexagonPeephole();
unsigned getID() const
Return the register class ID number.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const MachineInstrBuilder & add(const MachineOperand &MO) const
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
static cl::opt< bool > DisablePNotP("disable-hexagon-pnotp", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Optimization of PNotP"))
INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole", false, false) bool HexagonPeephole
static cl::opt< bool > DisableOptSZExt("disable-hexagon-optszext", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Disable Optimization of Sign/Zero Extends"))
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Represent the analysis usage information of a pass.
MachineOperand class - Representation of each machine instruction operand.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
void clearKillFlags(Register Reg) const
clearKillFlags - Iterate over all the uses of the given register and clear the kill flag from the Mac...
Representation of each machine instruction.
initializer< Ty > init(const Ty &Val)
iterator find(const_arg_type_t< KeyT > Val)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Register getReg() const
getReg - Returns the register number.
StringRef - Represent a constant reference to a string, i.e.
static cl::opt< bool > DisableHexagonPeephole("disable-hexagon-peephole", cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Disable Peephole Optimization"))
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
unsigned getSubReg() const
Iterator for intrusive lists based on ilist_node.
void initializeHexagonPeepholePass(PassRegistry &)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
FunctionPass * createHexagonPeephole()
static cl::opt< bool > DisableOptExtTo64("disable-hexagon-opt-ext-to-64", cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Disable Optimization of extensions to i64."))
FunctionPass class - This class is used to implement most global optimizations.