LLVM 19.0.0git
HexagonPeephole.cpp
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1//===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7// This peephole pass optimizes in the following cases.
8// 1. Optimizes redundant sign extends for the following case
9// Transform the following pattern
10// %170 = SXTW %166
11// ...
12// %176 = COPY %170:isub_lo
13//
14// Into
15// %176 = COPY %166
16//
17// 2. Optimizes redundant negation of predicates.
18// %15 = CMPGTrr %6, %2
19// ...
20// %16 = NOT_p killed %15
21// ...
22// JMP_c killed %16, <%bb.1>, implicit dead %pc
23//
24// Into
25// %15 = CMPGTrr %6, %2;
26// ...
27// JMP_cNot killed %15, <%bb.1>, implicit dead %pc;
28//
29// Note: The peephole pass makes the instrucstions like
30// %170 = SXTW %166 or %16 = NOT_p killed %15
31// redundant and relies on some form of dead removal instructions, like
32// DCE or DIE to actually eliminate them.
33
34//===----------------------------------------------------------------------===//
35
36#include "Hexagon.h"
38#include "llvm/ADT/DenseMap.h"
39#include "llvm/ADT/Statistic.h"
44#include "llvm/CodeGen/Passes.h"
47#include "llvm/IR/Constants.h"
48#include "llvm/Pass.h"
50#include "llvm/Support/Debug.h"
53#include <algorithm>
54
55using namespace llvm;
56
57#define DEBUG_TYPE "hexagon-peephole"
58
59static cl::opt<bool>
60 DisableHexagonPeephole("disable-hexagon-peephole", cl::Hidden,
61 cl::desc("Disable Peephole Optimization"));
62
63static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp", cl::Hidden,
64 cl::desc("Disable Optimization of PNotP"));
65
66static cl::opt<bool>
67 DisableOptSZExt("disable-hexagon-optszext", cl::Hidden, cl::init(true),
68 cl::desc("Disable Optimization of Sign/Zero Extends"));
69
70static cl::opt<bool>
71 DisableOptExtTo64("disable-hexagon-opt-ext-to-64", cl::Hidden,
72 cl::init(true),
73 cl::desc("Disable Optimization of extensions to i64."));
74
75namespace llvm {
78}
79
80namespace {
81 struct HexagonPeephole : public MachineFunctionPass {
82 const HexagonInstrInfo *QII;
83 const HexagonRegisterInfo *QRI;
85
86 public:
87 static char ID;
88 HexagonPeephole() : MachineFunctionPass(ID) {
90 }
91
92 bool runOnMachineFunction(MachineFunction &MF) override;
93
94 StringRef getPassName() const override {
95 return "Hexagon optimize redundant zero and size extends";
96 }
97
98 void getAnalysisUsage(AnalysisUsage &AU) const override {
100 }
101 };
102}
103
104char HexagonPeephole::ID = 0;
105
106INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole",
107 false, false)
108
109bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
110 if (skipFunction(MF.getFunction()))
111 return false;
112
113 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
114 QRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
115 MRI = &MF.getRegInfo();
116
119
120 if (DisableHexagonPeephole) return false;
121
122 // Loop over all of the basic blocks.
123 for (MachineBasicBlock &MBB : MF) {
124 PeepholeMap.clear();
125 PeepholeDoubleRegsMap.clear();
126
127 // Traverse the basic block.
129 // Look for sign extends:
130 // %170 = SXTW %166
131 if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) {
132 assert(MI.getNumOperands() == 2);
133 MachineOperand &Dst = MI.getOperand(0);
134 MachineOperand &Src = MI.getOperand(1);
135 Register DstReg = Dst.getReg();
136 Register SrcReg = Src.getReg();
137 // Just handle virtual registers.
138 if (DstReg.isVirtual() && SrcReg.isVirtual()) {
139 // Map the following:
140 // %170 = SXTW %166
141 // PeepholeMap[170] = %166
142 PeepholeMap[DstReg] = SrcReg;
143 }
144 }
145
146 // Look for %170 = COMBINE_ir_V4 (0, %169)
147 // %170:DoublRegs, %169:IntRegs
148 if (!DisableOptExtTo64 && MI.getOpcode() == Hexagon::A4_combineir) {
149 assert(MI.getNumOperands() == 3);
150 MachineOperand &Dst = MI.getOperand(0);
151 MachineOperand &Src1 = MI.getOperand(1);
152 MachineOperand &Src2 = MI.getOperand(2);
153 if (Src1.getImm() != 0)
154 continue;
155 Register DstReg = Dst.getReg();
156 Register SrcReg = Src2.getReg();
157 PeepholeMap[DstReg] = SrcReg;
158 }
159
160 // Look for this sequence below
161 // %DoubleReg1 = LSRd_ri %DoubleReg0, 32
162 // %IntReg = COPY %DoubleReg1:isub_lo.
163 // and convert into
164 // %IntReg = COPY %DoubleReg0:isub_hi.
165 if (MI.getOpcode() == Hexagon::S2_lsr_i_p) {
166 assert(MI.getNumOperands() == 3);
167 MachineOperand &Dst = MI.getOperand(0);
168 MachineOperand &Src1 = MI.getOperand(1);
169 MachineOperand &Src2 = MI.getOperand(2);
170 if (Src2.getImm() != 32)
171 continue;
172 Register DstReg = Dst.getReg();
173 Register SrcReg = Src1.getReg();
174 PeepholeDoubleRegsMap[DstReg] =
175 std::make_pair(*&SrcReg, Hexagon::isub_hi);
176 }
177
178 // Look for P=NOT(P).
179 if (!DisablePNotP && MI.getOpcode() == Hexagon::C2_not) {
180 assert(MI.getNumOperands() == 2);
181 MachineOperand &Dst = MI.getOperand(0);
182 MachineOperand &Src = MI.getOperand(1);
183 Register DstReg = Dst.getReg();
184 Register SrcReg = Src.getReg();
185 // Just handle virtual registers.
186 if (DstReg.isVirtual() && SrcReg.isVirtual()) {
187 // Map the following:
188 // %170 = NOT_xx %166
189 // PeepholeMap[170] = %166
190 PeepholeMap[DstReg] = SrcReg;
191 }
192 }
193
194 // Look for copy:
195 // %176 = COPY %170:isub_lo
196 if (!DisableOptSZExt && MI.isCopy()) {
197 assert(MI.getNumOperands() == 2);
198 MachineOperand &Dst = MI.getOperand(0);
199 MachineOperand &Src = MI.getOperand(1);
200
201 // Make sure we are copying the lower 32 bits.
202 if (Src.getSubReg() != Hexagon::isub_lo)
203 continue;
204
205 Register DstReg = Dst.getReg();
206 Register SrcReg = Src.getReg();
207 if (DstReg.isVirtual() && SrcReg.isVirtual()) {
208 // Try to find in the map.
209 if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
210 // Change the 1st operand.
211 MI.removeOperand(1);
212 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
213 } else {
215 PeepholeDoubleRegsMap.find(SrcReg);
216 if (DI != PeepholeDoubleRegsMap.end()) {
217 std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
218 MI.removeOperand(1);
219 MI.addOperand(MachineOperand::CreateReg(
220 PeepholeSrc.first, false /*isDef*/, false /*isImp*/,
221 false /*isKill*/, false /*isDead*/, false /*isUndef*/,
222 false /*isEarlyClobber*/, PeepholeSrc.second));
223 }
224 }
225 }
226 }
227
228 // Look for Predicated instructions.
229 if (!DisablePNotP) {
230 bool Done = false;
231 if (QII->isPredicated(MI)) {
232 MachineOperand &Op0 = MI.getOperand(0);
233 Register Reg0 = Op0.getReg();
234 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
235 if (RC0->getID() == Hexagon::PredRegsRegClassID) {
236 // Handle instructions that have a prediate register in op0
237 // (most cases of predicable instructions).
238 if (Reg0.isVirtual()) {
239 // Try to find in the map.
240 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
241 // Change the 1st operand and, flip the opcode.
242 MI.getOperand(0).setReg(PeepholeSrc);
243 MRI->clearKillFlags(PeepholeSrc);
244 int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode());
245 MI.setDesc(QII->get(NewOp));
246 Done = true;
247 }
248 }
249 }
250 }
251
252 if (!Done) {
253 // Handle special instructions.
254 unsigned Op = MI.getOpcode();
255 unsigned NewOp = 0;
256 unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
257
258 switch (Op) {
259 case Hexagon::C2_mux:
260 case Hexagon::C2_muxii:
261 NewOp = Op;
262 break;
263 case Hexagon::C2_muxri:
264 NewOp = Hexagon::C2_muxir;
265 break;
266 case Hexagon::C2_muxir:
267 NewOp = Hexagon::C2_muxri;
268 break;
269 }
270 if (NewOp) {
271 Register PSrc = MI.getOperand(PR).getReg();
272 if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
273 BuildMI(MBB, MI.getIterator(), MI.getDebugLoc(), QII->get(NewOp),
274 MI.getOperand(0).getReg())
275 .addReg(POrig)
276 .add(MI.getOperand(S2))
277 .add(MI.getOperand(S1));
278 MRI->clearKillFlags(POrig);
279 MI.eraseFromParent();
280 }
281 } // if (NewOp)
282 } // if (!Done)
283
284 } // if (!DisablePNotP)
285
286 } // Instruction
287 } // Basic Block
288 return true;
289}
290
292 return new HexagonPeephole();
293}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
static const LLT S1
This file contains the declarations for the subclasses of Constant, which represent the different fla...
This file defines the DenseMap class.
static cl::opt< bool > DisableOptExtTo64("disable-hexagon-opt-ext-to-64", cl::Hidden, cl::init(true), cl::desc("Disable Optimization of extensions to i64."))
static cl::opt< bool > DisableHexagonPeephole("disable-hexagon-peephole", cl::Hidden, cl::desc("Disable Peephole Optimization"))
static cl::opt< bool > DisablePNotP("disable-hexagon-pnotp", cl::Hidden, cl::desc("Disable Optimization of PNotP"))
static cl::opt< bool > DisableOptSZExt("disable-hexagon-optszext", cl::Hidden, cl::init(true), cl::desc("Disable Optimization of Sign/Zero Extends"))
IRTranslator LLVM IR MI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
Represent the analysis usage information of a pass.
This class represents an Operation in the Expression.
ValueT lookup(const_arg_type_t< KeyT > Val) const
lookup - Return the entry for the specified key, or a default constructed value if no such entry exis...
Definition: DenseMap.h:202
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:155
iterator end()
Definition: DenseMap.h:84
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
int64_t getImm() const
Register getReg() const
getReg - Returns the register number.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
unsigned getID() const
Return the register class ID number.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
@ Done
Definition: Threading.h:61
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
Definition: STLExtras.h:665
FunctionPass * createHexagonPeephole()
void initializeHexagonPeepholePass(PassRegistry &)
DWARFExpression::Operation Op