LLVM  13.0.0git
InstCombineSimplifyDemanded.cpp
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1 //===- InstCombineSimplifyDemanded.cpp ------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains logic for simplifying instructions based on information
10 // about how they are used.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "InstCombineInternal.h"
17 #include "llvm/IR/IntrinsicInst.h"
18 #include "llvm/IR/PatternMatch.h"
19 #include "llvm/Support/KnownBits.h"
21 
22 using namespace llvm;
23 using namespace llvm::PatternMatch;
24 
25 #define DEBUG_TYPE "instcombine"
26 
27 /// Check to see if the specified operand of the specified instruction is a
28 /// constant integer. If so, check to see if there are any bits set in the
29 /// constant that are not demanded. If so, shrink the constant and return true.
30 static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
31  const APInt &Demanded) {
32  assert(I && "No instruction?");
33  assert(OpNo < I->getNumOperands() && "Operand index too large");
34 
35  // The operand must be a constant integer or splat integer.
36  Value *Op = I->getOperand(OpNo);
37  const APInt *C;
38  if (!match(Op, m_APInt(C)))
39  return false;
40 
41  // If there are no bits set that aren't demanded, nothing to do.
42  if (C->isSubsetOf(Demanded))
43  return false;
44 
45  // This instruction is producing bits that are not demanded. Shrink the RHS.
46  I->setOperand(OpNo, ConstantInt::get(Op->getType(), *C & Demanded));
47 
48  return true;
49 }
50 
51 
52 
53 /// Inst is an integer instruction that SimplifyDemandedBits knows about. See if
54 /// the instruction has any properties that allow us to simplify its operands.
56  unsigned BitWidth = Inst.getType()->getScalarSizeInBits();
57  KnownBits Known(BitWidth);
58  APInt DemandedMask(APInt::getAllOnesValue(BitWidth));
59 
60  Value *V = SimplifyDemandedUseBits(&Inst, DemandedMask, Known,
61  0, &Inst);
62  if (!V) return false;
63  if (V == &Inst) return true;
64  replaceInstUsesWith(Inst, V);
65  return true;
66 }
67 
68 /// This form of SimplifyDemandedBits simplifies the specified instruction
69 /// operand if possible, updating it in place. It returns true if it made any
70 /// change and false otherwise.
72  const APInt &DemandedMask,
73  KnownBits &Known, unsigned Depth) {
74  Use &U = I->getOperandUse(OpNo);
75  Value *NewVal = SimplifyDemandedUseBits(U.get(), DemandedMask, Known,
76  Depth, I);
77  if (!NewVal) return false;
78  if (Instruction* OpInst = dyn_cast<Instruction>(U))
79  salvageDebugInfo(*OpInst);
80 
81  replaceUse(U, NewVal);
82  return true;
83 }
84 
85 /// This function attempts to replace V with a simpler value based on the
86 /// demanded bits. When this function is called, it is known that only the bits
87 /// set in DemandedMask of the result of V are ever used downstream.
88 /// Consequently, depending on the mask and V, it may be possible to replace V
89 /// with a constant or one of its operands. In such cases, this function does
90 /// the replacement and returns true. In all other cases, it returns false after
91 /// analyzing the expression and setting KnownOne and known to be one in the
92 /// expression. Known.Zero contains all the bits that are known to be zero in
93 /// the expression. These are provided to potentially allow the caller (which
94 /// might recursively be SimplifyDemandedBits itself) to simplify the
95 /// expression.
96 /// Known.One and Known.Zero always follow the invariant that:
97 /// Known.One & Known.Zero == 0.
98 /// That is, a bit can't be both 1 and 0. Note that the bits in Known.One and
99 /// Known.Zero may only be accurate for those bits set in DemandedMask. Note
100 /// also that the bitwidth of V, DemandedMask, Known.Zero and Known.One must all
101 /// be the same.
102 ///
103 /// This returns null if it did not change anything and it permits no
104 /// simplification. This returns V itself if it did some simplification of V's
105 /// operands based on the information about what bits are demanded. This returns
106 /// some other non-null value if it found out that V is equal to another value
107 /// in the context where the specified bits are demanded, but not for all users.
109  KnownBits &Known,
110  unsigned Depth,
111  Instruction *CxtI) {
112  assert(V != nullptr && "Null pointer of Value???");
113  assert(Depth <= MaxAnalysisRecursionDepth && "Limit Search Depth");
114  uint32_t BitWidth = DemandedMask.getBitWidth();
115  Type *VTy = V->getType();
116  assert(
117  (!VTy->isIntOrIntVectorTy() || VTy->getScalarSizeInBits() == BitWidth) &&
118  Known.getBitWidth() == BitWidth &&
119  "Value *V, DemandedMask and Known must have same BitWidth");
120 
121  if (isa<Constant>(V)) {
122  computeKnownBits(V, Known, Depth, CxtI);
123  return nullptr;
124  }
125 
126  Known.resetAll();
127  if (DemandedMask.isNullValue()) // Not demanding any bits from V.
128  return UndefValue::get(VTy);
129 
131  return nullptr;
132 
133  if (isa<ScalableVectorType>(VTy))
134  return nullptr;
135 
136  Instruction *I = dyn_cast<Instruction>(V);
137  if (!I) {
138  computeKnownBits(V, Known, Depth, CxtI);
139  return nullptr; // Only analyze instructions.
140  }
141 
142  // If there are multiple uses of this value and we aren't at the root, then
143  // we can't do any simplifications of the operands, because DemandedMask
144  // only reflects the bits demanded by *one* of the users.
145  if (Depth != 0 && !I->hasOneUse())
146  return SimplifyMultipleUseDemandedBits(I, DemandedMask, Known, Depth, CxtI);
147 
148  KnownBits LHSKnown(BitWidth), RHSKnown(BitWidth);
149 
150  // If this is the root being simplified, allow it to have multiple uses,
151  // just set the DemandedMask to all bits so that we can try to simplify the
152  // operands. This allows visitTruncInst (for example) to simplify the
153  // operand of a trunc without duplicating all the logic below.
154  if (Depth == 0 && !V->hasOneUse())
155  DemandedMask.setAllBits();
156 
157  switch (I->getOpcode()) {
158  default:
159  computeKnownBits(I, Known, Depth, CxtI);
160  break;
161  case Instruction::And: {
162  // If either the LHS or the RHS are Zero, the result is zero.
163  if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) ||
164  SimplifyDemandedBits(I, 0, DemandedMask & ~RHSKnown.Zero, LHSKnown,
165  Depth + 1))
166  return I;
167  assert(!RHSKnown.hasConflict() && "Bits known to be one AND zero?");
168  assert(!LHSKnown.hasConflict() && "Bits known to be one AND zero?");
169 
170  Known = LHSKnown & RHSKnown;
171 
172  // If the client is only demanding bits that we know, return the known
173  // constant.
174  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
175  return Constant::getIntegerValue(VTy, Known.One);
176 
177  // If all of the demanded bits are known 1 on one side, return the other.
178  // These bits cannot contribute to the result of the 'and'.
179  if (DemandedMask.isSubsetOf(LHSKnown.Zero | RHSKnown.One))
180  return I->getOperand(0);
181  if (DemandedMask.isSubsetOf(RHSKnown.Zero | LHSKnown.One))
182  return I->getOperand(1);
183 
184  // If the RHS is a constant, see if we can simplify it.
185  if (ShrinkDemandedConstant(I, 1, DemandedMask & ~LHSKnown.Zero))
186  return I;
187 
188  break;
189  }
190  case Instruction::Or: {
191  // If either the LHS or the RHS are One, the result is One.
192  if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) ||
193  SimplifyDemandedBits(I, 0, DemandedMask & ~RHSKnown.One, LHSKnown,
194  Depth + 1))
195  return I;
196  assert(!RHSKnown.hasConflict() && "Bits known to be one AND zero?");
197  assert(!LHSKnown.hasConflict() && "Bits known to be one AND zero?");
198 
199  Known = LHSKnown | RHSKnown;
200 
201  // If the client is only demanding bits that we know, return the known
202  // constant.
203  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
204  return Constant::getIntegerValue(VTy, Known.One);
205 
206  // If all of the demanded bits are known zero on one side, return the other.
207  // These bits cannot contribute to the result of the 'or'.
208  if (DemandedMask.isSubsetOf(LHSKnown.One | RHSKnown.Zero))
209  return I->getOperand(0);
210  if (DemandedMask.isSubsetOf(RHSKnown.One | LHSKnown.Zero))
211  return I->getOperand(1);
212 
213  // If the RHS is a constant, see if we can simplify it.
214  if (ShrinkDemandedConstant(I, 1, DemandedMask))
215  return I;
216 
217  break;
218  }
219  case Instruction::Xor: {
220  if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) ||
221  SimplifyDemandedBits(I, 0, DemandedMask, LHSKnown, Depth + 1))
222  return I;
223  assert(!RHSKnown.hasConflict() && "Bits known to be one AND zero?");
224  assert(!LHSKnown.hasConflict() && "Bits known to be one AND zero?");
225 
226  Known = LHSKnown ^ RHSKnown;
227 
228  // If the client is only demanding bits that we know, return the known
229  // constant.
230  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
231  return Constant::getIntegerValue(VTy, Known.One);
232 
233  // If all of the demanded bits are known zero on one side, return the other.
234  // These bits cannot contribute to the result of the 'xor'.
235  if (DemandedMask.isSubsetOf(RHSKnown.Zero))
236  return I->getOperand(0);
237  if (DemandedMask.isSubsetOf(LHSKnown.Zero))
238  return I->getOperand(1);
239 
240  // If all of the demanded bits are known to be zero on one side or the
241  // other, turn this into an *inclusive* or.
242  // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
243  if (DemandedMask.isSubsetOf(RHSKnown.Zero | LHSKnown.Zero)) {
244  Instruction *Or =
245  BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1),
246  I->getName());
247  return InsertNewInstWith(Or, *I);
248  }
249 
250  // If all of the demanded bits on one side are known, and all of the set
251  // bits on that side are also known to be set on the other side, turn this
252  // into an AND, as we know the bits will be cleared.
253  // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
254  if (DemandedMask.isSubsetOf(RHSKnown.Zero|RHSKnown.One) &&
255  RHSKnown.One.isSubsetOf(LHSKnown.One)) {
257  ~RHSKnown.One & DemandedMask);
258  Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
259  return InsertNewInstWith(And, *I);
260  }
261 
262  // If the RHS is a constant, see if we can change it. Don't alter a -1
263  // constant because that's a canonical 'not' op, and that is better for
264  // combining, SCEV, and codegen.
265  const APInt *C;
266  if (match(I->getOperand(1), m_APInt(C)) && !C->isAllOnesValue()) {
267  if ((*C | ~DemandedMask).isAllOnesValue()) {
268  // Force bits to 1 to create a 'not' op.
269  I->setOperand(1, ConstantInt::getAllOnesValue(VTy));
270  return I;
271  }
272  // If we can't turn this into a 'not', try to shrink the constant.
273  if (ShrinkDemandedConstant(I, 1, DemandedMask))
274  return I;
275  }
276 
277  // If our LHS is an 'and' and if it has one use, and if any of the bits we
278  // are flipping are known to be set, then the xor is just resetting those
279  // bits to zero. We can just knock out bits from the 'and' and the 'xor',
280  // simplifying both of them.
281  if (Instruction *LHSInst = dyn_cast<Instruction>(I->getOperand(0))) {
282  ConstantInt *AndRHS, *XorRHS;
283  if (LHSInst->getOpcode() == Instruction::And && LHSInst->hasOneUse() &&
284  match(I->getOperand(1), m_ConstantInt(XorRHS)) &&
285  match(LHSInst->getOperand(1), m_ConstantInt(AndRHS)) &&
286  (LHSKnown.One & RHSKnown.One & DemandedMask) != 0) {
287  APInt NewMask = ~(LHSKnown.One & RHSKnown.One & DemandedMask);
288 
289  Constant *AndC =
290  ConstantInt::get(I->getType(), NewMask & AndRHS->getValue());
291  Instruction *NewAnd = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
292  InsertNewInstWith(NewAnd, *I);
293 
294  Constant *XorC =
295  ConstantInt::get(I->getType(), NewMask & XorRHS->getValue());
296  Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC);
297  return InsertNewInstWith(NewXor, *I);
298  }
299  }
300  break;
301  }
302  case Instruction::Select: {
303  Value *LHS, *RHS;
305  if (SPF == SPF_UMAX) {
306  // UMax(A, C) == A if ...
307  // The lowest non-zero bit of DemandMask is higher than the highest
308  // non-zero bit of C.
309  const APInt *C;
310  unsigned CTZ = DemandedMask.countTrailingZeros();
311  if (match(RHS, m_APInt(C)) && CTZ >= C->getActiveBits())
312  return LHS;
313  } else if (SPF == SPF_UMIN) {
314  // UMin(A, C) == A if ...
315  // The lowest non-zero bit of DemandMask is higher than the highest
316  // non-one bit of C.
317  // This comes from using DeMorgans on the above umax example.
318  const APInt *C;
319  unsigned CTZ = DemandedMask.countTrailingZeros();
320  if (match(RHS, m_APInt(C)) &&
321  CTZ >= C->getBitWidth() - C->countLeadingOnes())
322  return LHS;
323  }
324 
325  // If this is a select as part of any other min/max pattern, don't simplify
326  // any further in case we break the structure.
327  if (SPF != SPF_UNKNOWN)
328  return nullptr;
329 
330  if (SimplifyDemandedBits(I, 2, DemandedMask, RHSKnown, Depth + 1) ||
331  SimplifyDemandedBits(I, 1, DemandedMask, LHSKnown, Depth + 1))
332  return I;
333  assert(!RHSKnown.hasConflict() && "Bits known to be one AND zero?");
334  assert(!LHSKnown.hasConflict() && "Bits known to be one AND zero?");
335 
336  // If the operands are constants, see if we can simplify them.
337  // This is similar to ShrinkDemandedConstant, but for a select we want to
338  // try to keep the selected constants the same as icmp value constants, if
339  // we can. This helps not break apart (or helps put back together)
340  // canonical patterns like min and max.
341  auto CanonicalizeSelectConstant = [](Instruction *I, unsigned OpNo,
342  const APInt &DemandedMask) {
343  const APInt *SelC;
344  if (!match(I->getOperand(OpNo), m_APInt(SelC)))
345  return false;
346 
347  // Get the constant out of the ICmp, if there is one.
348  // Only try this when exactly 1 operand is a constant (if both operands
349  // are constant, the icmp should eventually simplify). Otherwise, we may
350  // invert the transform that reduces set bits and infinite-loop.
351  Value *X;
352  const APInt *CmpC;
353  ICmpInst::Predicate Pred;
354  if (!match(I->getOperand(0), m_ICmp(Pred, m_Value(X), m_APInt(CmpC))) ||
355  isa<Constant>(X) || CmpC->getBitWidth() != SelC->getBitWidth())
356  return ShrinkDemandedConstant(I, OpNo, DemandedMask);
357 
358  // If the constant is already the same as the ICmp, leave it as-is.
359  if (*CmpC == *SelC)
360  return false;
361  // If the constants are not already the same, but can be with the demand
362  // mask, use the constant value from the ICmp.
363  if ((*CmpC & DemandedMask) == (*SelC & DemandedMask)) {
364  I->setOperand(OpNo, ConstantInt::get(I->getType(), *CmpC));
365  return true;
366  }
367  return ShrinkDemandedConstant(I, OpNo, DemandedMask);
368  };
369  if (CanonicalizeSelectConstant(I, 1, DemandedMask) ||
370  CanonicalizeSelectConstant(I, 2, DemandedMask))
371  return I;
372 
373  // Only known if known in both the LHS and RHS.
374  Known = KnownBits::commonBits(LHSKnown, RHSKnown);
375  break;
376  }
377  case Instruction::ZExt:
378  case Instruction::Trunc: {
379  unsigned SrcBitWidth = I->getOperand(0)->getType()->getScalarSizeInBits();
380 
381  APInt InputDemandedMask = DemandedMask.zextOrTrunc(SrcBitWidth);
382  KnownBits InputKnown(SrcBitWidth);
383  if (SimplifyDemandedBits(I, 0, InputDemandedMask, InputKnown, Depth + 1))
384  return I;
385  assert(InputKnown.getBitWidth() == SrcBitWidth && "Src width changed?");
386  Known = InputKnown.zextOrTrunc(BitWidth);
387  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
388  break;
389  }
390  case Instruction::BitCast:
391  if (!I->getOperand(0)->getType()->isIntOrIntVectorTy())
392  return nullptr; // vector->int or fp->int?
393 
394  if (VectorType *DstVTy = dyn_cast<VectorType>(I->getType())) {
395  if (VectorType *SrcVTy =
396  dyn_cast<VectorType>(I->getOperand(0)->getType())) {
397  if (cast<FixedVectorType>(DstVTy)->getNumElements() !=
398  cast<FixedVectorType>(SrcVTy)->getNumElements())
399  // Don't touch a bitcast between vectors of different element counts.
400  return nullptr;
401  } else
402  // Don't touch a scalar-to-vector bitcast.
403  return nullptr;
404  } else if (I->getOperand(0)->getType()->isVectorTy())
405  // Don't touch a vector-to-scalar bitcast.
406  return nullptr;
407 
408  if (SimplifyDemandedBits(I, 0, DemandedMask, Known, Depth + 1))
409  return I;
410  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
411  break;
412  case Instruction::SExt: {
413  // Compute the bits in the result that are not present in the input.
414  unsigned SrcBitWidth = I->getOperand(0)->getType()->getScalarSizeInBits();
415 
416  APInt InputDemandedBits = DemandedMask.trunc(SrcBitWidth);
417 
418  // If any of the sign extended bits are demanded, we know that the sign
419  // bit is demanded.
420  if (DemandedMask.getActiveBits() > SrcBitWidth)
421  InputDemandedBits.setBit(SrcBitWidth-1);
422 
423  KnownBits InputKnown(SrcBitWidth);
424  if (SimplifyDemandedBits(I, 0, InputDemandedBits, InputKnown, Depth + 1))
425  return I;
426 
427  // If the input sign bit is known zero, or if the NewBits are not demanded
428  // convert this into a zero extension.
429  if (InputKnown.isNonNegative() ||
430  DemandedMask.getActiveBits() <= SrcBitWidth) {
431  // Convert to ZExt cast.
432  CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName());
433  return InsertNewInstWith(NewCast, *I);
434  }
435 
436  // If the sign bit of the input is known set or clear, then we know the
437  // top bits of the result.
438  Known = InputKnown.sext(BitWidth);
439  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
440  break;
441  }
442  case Instruction::Add:
443  if ((DemandedMask & 1) == 0) {
444  // If we do not need the low bit, try to convert bool math to logic:
445  // add iN (zext i1 X), (sext i1 Y) --> sext (~X & Y) to iN
446  Value *X, *Y;
448  m_OneUse(m_SExt(m_Value(Y))))) &&
449  X->getType()->isIntOrIntVectorTy(1) && X->getType() == Y->getType()) {
450  // Truth table for inputs and output signbits:
451  // X:0 | X:1
452  // ----------
453  // Y:0 | 0 | 0 |
454  // Y:1 | -1 | 0 |
455  // ----------
457  Builder.SetInsertPoint(I);
458  Value *AndNot = Builder.CreateAnd(Builder.CreateNot(X), Y);
459  return Builder.CreateSExt(AndNot, VTy);
460  }
461 
462  // add iN (sext i1 X), (sext i1 Y) --> sext (X | Y) to iN
463  // TODO: Relax the one-use checks because we are removing an instruction?
464  if (match(I, m_Add(m_OneUse(m_SExt(m_Value(X))),
465  m_OneUse(m_SExt(m_Value(Y))))) &&
466  X->getType()->isIntOrIntVectorTy(1) && X->getType() == Y->getType()) {
467  // Truth table for inputs and output signbits:
468  // X:0 | X:1
469  // -----------
470  // Y:0 | -1 | -1 |
471  // Y:1 | -1 | 0 |
472  // -----------
474  Builder.SetInsertPoint(I);
475  Value *Or = Builder.CreateOr(X, Y);
476  return Builder.CreateSExt(Or, VTy);
477  }
478  }
480  case Instruction::Sub: {
481  /// If the high-bits of an ADD/SUB are not demanded, then we do not care
482  /// about the high bits of the operands.
483  unsigned NLZ = DemandedMask.countLeadingZeros();
484  // Right fill the mask of bits for this ADD/SUB to demand the most
485  // significant bit and all those below it.
486  APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ));
487  if (ShrinkDemandedConstant(I, 0, DemandedFromOps) ||
488  SimplifyDemandedBits(I, 0, DemandedFromOps, LHSKnown, Depth + 1) ||
489  ShrinkDemandedConstant(I, 1, DemandedFromOps) ||
490  SimplifyDemandedBits(I, 1, DemandedFromOps, RHSKnown, Depth + 1)) {
491  if (NLZ > 0) {
492  // Disable the nsw and nuw flags here: We can no longer guarantee that
493  // we won't wrap after simplification. Removing the nsw/nuw flags is
494  // legal here because the top bit is not demanded.
495  BinaryOperator &BinOP = *cast<BinaryOperator>(I);
496  BinOP.setHasNoSignedWrap(false);
497  BinOP.setHasNoUnsignedWrap(false);
498  }
499  return I;
500  }
501 
502  // If we are known to be adding/subtracting zeros to every bit below
503  // the highest demanded bit, we just return the other side.
504  if (DemandedFromOps.isSubsetOf(RHSKnown.Zero))
505  return I->getOperand(0);
506  // We can't do this with the LHS for subtraction, unless we are only
507  // demanding the LSB.
508  if ((I->getOpcode() == Instruction::Add ||
509  DemandedFromOps.isOneValue()) &&
510  DemandedFromOps.isSubsetOf(LHSKnown.Zero))
511  return I->getOperand(1);
512 
513  // Otherwise just compute the known bits of the result.
514  bool NSW = cast<OverflowingBinaryOperator>(I)->hasNoSignedWrap();
515  Known = KnownBits::computeForAddSub(I->getOpcode() == Instruction::Add,
516  NSW, LHSKnown, RHSKnown);
517  break;
518  }
519  case Instruction::Shl: {
520  const APInt *SA;
521  if (match(I->getOperand(1), m_APInt(SA))) {
522  const APInt *ShrAmt;
523  if (match(I->getOperand(0), m_Shr(m_Value(), m_APInt(ShrAmt))))
524  if (Instruction *Shr = dyn_cast<Instruction>(I->getOperand(0)))
525  if (Value *R = simplifyShrShlDemandedBits(Shr, *ShrAmt, I, *SA,
526  DemandedMask, Known))
527  return R;
528 
529  uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
530  APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
531 
532  // If the shift is NUW/NSW, then it does demand the high bits.
533  ShlOperator *IOp = cast<ShlOperator>(I);
534  if (IOp->hasNoSignedWrap())
535  DemandedMaskIn.setHighBits(ShiftAmt+1);
536  else if (IOp->hasNoUnsignedWrap())
537  DemandedMaskIn.setHighBits(ShiftAmt);
538 
539  if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
540  return I;
541  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
542 
543  bool SignBitZero = Known.Zero.isSignBitSet();
544  bool SignBitOne = Known.One.isSignBitSet();
545  Known.Zero <<= ShiftAmt;
546  Known.One <<= ShiftAmt;
547  // low bits known zero.
548  if (ShiftAmt)
549  Known.Zero.setLowBits(ShiftAmt);
550 
551  // If this shift has "nsw" keyword, then the result is either a poison
552  // value or has the same sign bit as the first operand.
553  if (IOp->hasNoSignedWrap()) {
554  if (SignBitZero)
555  Known.Zero.setSignBit();
556  else if (SignBitOne)
557  Known.One.setSignBit();
558  if (Known.hasConflict())
559  return UndefValue::get(I->getType());
560  }
561  } else {
562  computeKnownBits(I, Known, Depth, CxtI);
563  }
564  break;
565  }
566  case Instruction::LShr: {
567  const APInt *SA;
568  if (match(I->getOperand(1), m_APInt(SA))) {
569  uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
570 
571  // Unsigned shift right.
572  APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
573 
574  // If the shift is exact, then it does demand the low bits (and knows that
575  // they are zero).
576  if (cast<LShrOperator>(I)->isExact())
577  DemandedMaskIn.setLowBits(ShiftAmt);
578 
579  if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
580  return I;
581  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
582  Known.Zero.lshrInPlace(ShiftAmt);
583  Known.One.lshrInPlace(ShiftAmt);
584  if (ShiftAmt)
585  Known.Zero.setHighBits(ShiftAmt); // high bits known zero.
586  } else {
587  computeKnownBits(I, Known, Depth, CxtI);
588  }
589  break;
590  }
591  case Instruction::AShr: {
592  // If this is an arithmetic shift right and only the low-bit is set, we can
593  // always convert this into a logical shr, even if the shift amount is
594  // variable. The low bit of the shift cannot be an input sign bit unless
595  // the shift amount is >= the size of the datatype, which is undefined.
596  if (DemandedMask.isOneValue()) {
597  // Perform the logical shift right.
598  Instruction *NewVal = BinaryOperator::CreateLShr(
599  I->getOperand(0), I->getOperand(1), I->getName());
600  return InsertNewInstWith(NewVal, *I);
601  }
602 
603  // If the sign bit is the only bit demanded by this ashr, then there is no
604  // need to do it, the shift doesn't change the high bit.
605  if (DemandedMask.isSignMask())
606  return I->getOperand(0);
607 
608  const APInt *SA;
609  if (match(I->getOperand(1), m_APInt(SA))) {
610  uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
611 
612  // Signed shift right.
613  APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
614  // If any of the high bits are demanded, we should set the sign bit as
615  // demanded.
616  if (DemandedMask.countLeadingZeros() <= ShiftAmt)
617  DemandedMaskIn.setSignBit();
618 
619  // If the shift is exact, then it does demand the low bits (and knows that
620  // they are zero).
621  if (cast<AShrOperator>(I)->isExact())
622  DemandedMaskIn.setLowBits(ShiftAmt);
623 
624  if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
625  return I;
626 
627  unsigned SignBits = ComputeNumSignBits(I->getOperand(0), Depth + 1, CxtI);
628 
629  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
630  // Compute the new bits that are at the top now plus sign bits.
631  APInt HighBits(APInt::getHighBitsSet(
632  BitWidth, std::min(SignBits + ShiftAmt - 1, BitWidth)));
633  Known.Zero.lshrInPlace(ShiftAmt);
634  Known.One.lshrInPlace(ShiftAmt);
635 
636  // If the input sign bit is known to be zero, or if none of the top bits
637  // are demanded, turn this into an unsigned shift right.
638  assert(BitWidth > ShiftAmt && "Shift amount not saturated?");
639  if (Known.Zero[BitWidth-ShiftAmt-1] ||
640  !DemandedMask.intersects(HighBits)) {
641  BinaryOperator *LShr = BinaryOperator::CreateLShr(I->getOperand(0),
642  I->getOperand(1));
643  LShr->setIsExact(cast<BinaryOperator>(I)->isExact());
644  return InsertNewInstWith(LShr, *I);
645  } else if (Known.One[BitWidth-ShiftAmt-1]) { // New bits are known one.
646  Known.One |= HighBits;
647  }
648  } else {
649  computeKnownBits(I, Known, Depth, CxtI);
650  }
651  break;
652  }
653  case Instruction::UDiv: {
654  // UDiv doesn't demand low bits that are zero in the divisor.
655  const APInt *SA;
656  if (match(I->getOperand(1), m_APInt(SA))) {
657  // If the shift is exact, then it does demand the low bits.
658  if (cast<UDivOperator>(I)->isExact())
659  break;
660 
661  // FIXME: Take the demanded mask of the result into account.
662  unsigned RHSTrailingZeros = SA->countTrailingZeros();
663  APInt DemandedMaskIn =
664  APInt::getHighBitsSet(BitWidth, BitWidth - RHSTrailingZeros);
665  if (SimplifyDemandedBits(I, 0, DemandedMaskIn, LHSKnown, Depth + 1))
666  return I;
667 
668  // Propagate zero bits from the input.
669  Known.Zero.setHighBits(std::min(
670  BitWidth, LHSKnown.Zero.countLeadingOnes() + RHSTrailingZeros));
671  } else {
672  computeKnownBits(I, Known, Depth, CxtI);
673  }
674  break;
675  }
676  case Instruction::SRem: {
677  ConstantInt *Rem;
678  if (match(I->getOperand(1), m_ConstantInt(Rem))) {
679  // X % -1 demands all the bits because we don't want to introduce
680  // INT_MIN % -1 (== undef) by accident.
681  if (Rem->isMinusOne())
682  break;
683  APInt RA = Rem->getValue().abs();
684  if (RA.isPowerOf2()) {
685  if (DemandedMask.ult(RA)) // srem won't affect demanded bits
686  return I->getOperand(0);
687 
688  APInt LowBits = RA - 1;
689  APInt Mask2 = LowBits | APInt::getSignMask(BitWidth);
690  if (SimplifyDemandedBits(I, 0, Mask2, LHSKnown, Depth + 1))
691  return I;
692 
693  // The low bits of LHS are unchanged by the srem.
694  Known.Zero = LHSKnown.Zero & LowBits;
695  Known.One = LHSKnown.One & LowBits;
696 
697  // If LHS is non-negative or has all low bits zero, then the upper bits
698  // are all zero.
699  if (LHSKnown.isNonNegative() || LowBits.isSubsetOf(LHSKnown.Zero))
700  Known.Zero |= ~LowBits;
701 
702  // If LHS is negative and not all low bits are zero, then the upper bits
703  // are all one.
704  if (LHSKnown.isNegative() && LowBits.intersects(LHSKnown.One))
705  Known.One |= ~LowBits;
706 
707  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
708  break;
709  }
710  }
711 
712  // The sign bit is the LHS's sign bit, except when the result of the
713  // remainder is zero.
714  if (DemandedMask.isSignBitSet()) {
715  computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1, CxtI);
716  // If it's known zero, our sign bit is also zero.
717  if (LHSKnown.isNonNegative())
718  Known.makeNonNegative();
719  }
720  break;
721  }
722  case Instruction::URem: {
723  KnownBits Known2(BitWidth);
725  if (SimplifyDemandedBits(I, 0, AllOnes, Known2, Depth + 1) ||
726  SimplifyDemandedBits(I, 1, AllOnes, Known2, Depth + 1))
727  return I;
728 
729  unsigned Leaders = Known2.countMinLeadingZeros();
730  Known.Zero = APInt::getHighBitsSet(BitWidth, Leaders) & DemandedMask;
731  break;
732  }
733  case Instruction::Call: {
734  bool KnownBitsComputed = false;
735  if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
736  switch (II->getIntrinsicID()) {
737  case Intrinsic::abs: {
738  if (DemandedMask == 1)
739  return II->getArgOperand(0);
740  break;
741  }
742  case Intrinsic::bswap: {
743  // If the only bits demanded come from one byte of the bswap result,
744  // just shift the input byte into position to eliminate the bswap.
745  unsigned NLZ = DemandedMask.countLeadingZeros();
746  unsigned NTZ = DemandedMask.countTrailingZeros();
747 
748  // Round NTZ down to the next byte. If we have 11 trailing zeros, then
749  // we need all the bits down to bit 8. Likewise, round NLZ. If we
750  // have 14 leading zeros, round to 8.
751  NLZ &= ~7;
752  NTZ &= ~7;
753  // If we need exactly one byte, we can do this transformation.
754  if (BitWidth-NLZ-NTZ == 8) {
755  unsigned ResultBit = NTZ;
756  unsigned InputBit = BitWidth-NTZ-8;
757 
758  // Replace this with either a left or right shift to get the byte into
759  // the right place.
760  Instruction *NewVal;
761  if (InputBit > ResultBit)
762  NewVal = BinaryOperator::CreateLShr(II->getArgOperand(0),
763  ConstantInt::get(I->getType(), InputBit-ResultBit));
764  else
765  NewVal = BinaryOperator::CreateShl(II->getArgOperand(0),
766  ConstantInt::get(I->getType(), ResultBit-InputBit));
767  NewVal->takeName(I);
768  return InsertNewInstWith(NewVal, *I);
769  }
770  break;
771  }
772  case Intrinsic::fshr:
773  case Intrinsic::fshl: {
774  const APInt *SA;
775  if (!match(I->getOperand(2), m_APInt(SA)))
776  break;
777 
778  // Normalize to funnel shift left. APInt shifts of BitWidth are well-
779  // defined, so no need to special-case zero shifts here.
780  uint64_t ShiftAmt = SA->urem(BitWidth);
781  if (II->getIntrinsicID() == Intrinsic::fshr)
782  ShiftAmt = BitWidth - ShiftAmt;
783 
784  APInt DemandedMaskLHS(DemandedMask.lshr(ShiftAmt));
785  APInt DemandedMaskRHS(DemandedMask.shl(BitWidth - ShiftAmt));
786  if (SimplifyDemandedBits(I, 0, DemandedMaskLHS, LHSKnown, Depth + 1) ||
787  SimplifyDemandedBits(I, 1, DemandedMaskRHS, RHSKnown, Depth + 1))
788  return I;
789 
790  Known.Zero = LHSKnown.Zero.shl(ShiftAmt) |
791  RHSKnown.Zero.lshr(BitWidth - ShiftAmt);
792  Known.One = LHSKnown.One.shl(ShiftAmt) |
793  RHSKnown.One.lshr(BitWidth - ShiftAmt);
794  KnownBitsComputed = true;
795  break;
796  }
797  default: {
798  // Handle target specific intrinsics
799  Optional<Value *> V = targetSimplifyDemandedUseBitsIntrinsic(
800  *II, DemandedMask, Known, KnownBitsComputed);
801  if (V.hasValue())
802  return V.getValue();
803  break;
804  }
805  }
806  }
807 
808  if (!KnownBitsComputed)
809  computeKnownBits(V, Known, Depth, CxtI);
810  break;
811  }
812  }
813 
814  // If the client is only demanding bits that we know, return the known
815  // constant.
816  if (DemandedMask.isSubsetOf(Known.Zero|Known.One))
817  return Constant::getIntegerValue(VTy, Known.One);
818  return nullptr;
819 }
820 
821 /// Helper routine of SimplifyDemandedUseBits. It computes Known
822 /// bits. It also tries to handle simplifications that can be done based on
823 /// DemandedMask, but without modifying the Instruction.
825  Instruction *I, const APInt &DemandedMask, KnownBits &Known, unsigned Depth,
826  Instruction *CxtI) {
827  unsigned BitWidth = DemandedMask.getBitWidth();
828  Type *ITy = I->getType();
829 
830  KnownBits LHSKnown(BitWidth);
831  KnownBits RHSKnown(BitWidth);
832 
833  // Despite the fact that we can't simplify this instruction in all User's
834  // context, we can at least compute the known bits, and we can
835  // do simplifications that apply to *just* the one user if we know that
836  // this instruction has a simpler value in that context.
837  switch (I->getOpcode()) {
838  case Instruction::And: {
839  // If either the LHS or the RHS are Zero, the result is zero.
840  computeKnownBits(I->getOperand(1), RHSKnown, Depth + 1, CxtI);
841  computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1,
842  CxtI);
843 
844  Known = LHSKnown & RHSKnown;
845 
846  // If the client is only demanding bits that we know, return the known
847  // constant.
848  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
849  return Constant::getIntegerValue(ITy, Known.One);
850 
851  // If all of the demanded bits are known 1 on one side, return the other.
852  // These bits cannot contribute to the result of the 'and' in this
853  // context.
854  if (DemandedMask.isSubsetOf(LHSKnown.Zero | RHSKnown.One))
855  return I->getOperand(0);
856  if (DemandedMask.isSubsetOf(RHSKnown.Zero | LHSKnown.One))
857  return I->getOperand(1);
858 
859  break;
860  }
861  case Instruction::Or: {
862  // We can simplify (X|Y) -> X or Y in the user's context if we know that
863  // only bits from X or Y are demanded.
864 
865  // If either the LHS or the RHS are One, the result is One.
866  computeKnownBits(I->getOperand(1), RHSKnown, Depth + 1, CxtI);
867  computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1,
868  CxtI);
869 
870  Known = LHSKnown | RHSKnown;
871 
872  // If the client is only demanding bits that we know, return the known
873  // constant.
874  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
875  return Constant::getIntegerValue(ITy, Known.One);
876 
877  // If all of the demanded bits are known zero on one side, return the
878  // other. These bits cannot contribute to the result of the 'or' in this
879  // context.
880  if (DemandedMask.isSubsetOf(LHSKnown.One | RHSKnown.Zero))
881  return I->getOperand(0);
882  if (DemandedMask.isSubsetOf(RHSKnown.One | LHSKnown.Zero))
883  return I->getOperand(1);
884 
885  break;
886  }
887  case Instruction::Xor: {
888  // We can simplify (X^Y) -> X or Y in the user's context if we know that
889  // only bits from X or Y are demanded.
890 
891  computeKnownBits(I->getOperand(1), RHSKnown, Depth + 1, CxtI);
892  computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1,
893  CxtI);
894 
895  Known = LHSKnown ^ RHSKnown;
896 
897  // If the client is only demanding bits that we know, return the known
898  // constant.
899  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
900  return Constant::getIntegerValue(ITy, Known.One);
901 
902  // If all of the demanded bits are known zero on one side, return the
903  // other.
904  if (DemandedMask.isSubsetOf(RHSKnown.Zero))
905  return I->getOperand(0);
906  if (DemandedMask.isSubsetOf(LHSKnown.Zero))
907  return I->getOperand(1);
908 
909  break;
910  }
911  case Instruction::AShr: {
912  // Compute the Known bits to simplify things downstream.
913  computeKnownBits(I, Known, Depth, CxtI);
914 
915  // If this user is only demanding bits that we know, return the known
916  // constant.
917  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
918  return Constant::getIntegerValue(ITy, Known.One);
919 
920  // If the right shift operand 0 is a result of a left shift by the same
921  // amount, this is probably a zero/sign extension, which may be unnecessary,
922  // if we do not demand any of the new sign bits. So, return the original
923  // operand instead.
924  const APInt *ShiftRC;
925  const APInt *ShiftLC;
926  Value *X;
927  unsigned BitWidth = DemandedMask.getBitWidth();
928  if (match(I,
929  m_AShr(m_Shl(m_Value(X), m_APInt(ShiftLC)), m_APInt(ShiftRC))) &&
930  ShiftLC == ShiftRC && ShiftLC->ult(BitWidth) &&
931  DemandedMask.isSubsetOf(APInt::getLowBitsSet(
932  BitWidth, BitWidth - ShiftRC->getZExtValue()))) {
933  return X;
934  }
935 
936  break;
937  }
938  default:
939  // Compute the Known bits to simplify things downstream.
940  computeKnownBits(I, Known, Depth, CxtI);
941 
942  // If this user is only demanding bits that we know, return the known
943  // constant.
944  if (DemandedMask.isSubsetOf(Known.Zero|Known.One))
945  return Constant::getIntegerValue(ITy, Known.One);
946 
947  break;
948  }
949 
950  return nullptr;
951 }
952 
953 /// Helper routine of SimplifyDemandedUseBits. It tries to simplify
954 /// "E1 = (X lsr C1) << C2", where the C1 and C2 are constant, into
955 /// "E2 = X << (C2 - C1)" or "E2 = X >> (C1 - C2)", depending on the sign
956 /// of "C2-C1".
957 ///
958 /// Suppose E1 and E2 are generally different in bits S={bm, bm+1,
959 /// ..., bn}, without considering the specific value X is holding.
960 /// This transformation is legal iff one of following conditions is hold:
961 /// 1) All the bit in S are 0, in this case E1 == E2.
962 /// 2) We don't care those bits in S, per the input DemandedMask.
963 /// 3) Combination of 1) and 2). Some bits in S are 0, and we don't care the
964 /// rest bits.
965 ///
966 /// Currently we only test condition 2).
967 ///
968 /// As with SimplifyDemandedUseBits, it returns NULL if the simplification was
969 /// not successful.
971  Instruction *Shr, const APInt &ShrOp1, Instruction *Shl,
972  const APInt &ShlOp1, const APInt &DemandedMask, KnownBits &Known) {
973  if (!ShlOp1 || !ShrOp1)
974  return nullptr; // No-op.
975 
976  Value *VarX = Shr->getOperand(0);
977  Type *Ty = VarX->getType();
978  unsigned BitWidth = Ty->getScalarSizeInBits();
979  if (ShlOp1.uge(BitWidth) || ShrOp1.uge(BitWidth))
980  return nullptr; // Undef.
981 
982  unsigned ShlAmt = ShlOp1.getZExtValue();
983  unsigned ShrAmt = ShrOp1.getZExtValue();
984 
985  Known.One.clearAllBits();
986  Known.Zero.setLowBits(ShlAmt - 1);
987  Known.Zero &= DemandedMask;
988 
991 
992  bool isLshr = (Shr->getOpcode() == Instruction::LShr);
993  BitMask1 = isLshr ? (BitMask1.lshr(ShrAmt) << ShlAmt) :
994  (BitMask1.ashr(ShrAmt) << ShlAmt);
995 
996  if (ShrAmt <= ShlAmt) {
997  BitMask2 <<= (ShlAmt - ShrAmt);
998  } else {
999  BitMask2 = isLshr ? BitMask2.lshr(ShrAmt - ShlAmt):
1000  BitMask2.ashr(ShrAmt - ShlAmt);
1001  }
1002 
1003  // Check if condition-2 (see the comment to this function) is satified.
1004  if ((BitMask1 & DemandedMask) == (BitMask2 & DemandedMask)) {
1005  if (ShrAmt == ShlAmt)
1006  return VarX;
1007 
1008  if (!Shr->hasOneUse())
1009  return nullptr;
1010 
1011  BinaryOperator *New;
1012  if (ShrAmt < ShlAmt) {
1013  Constant *Amt = ConstantInt::get(VarX->getType(), ShlAmt - ShrAmt);
1014  New = BinaryOperator::CreateShl(VarX, Amt);
1015  BinaryOperator *Orig = cast<BinaryOperator>(Shl);
1016  New->setHasNoSignedWrap(Orig->hasNoSignedWrap());
1017  New->setHasNoUnsignedWrap(Orig->hasNoUnsignedWrap());
1018  } else {
1019  Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt);
1020  New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
1021  BinaryOperator::CreateAShr(VarX, Amt);
1022  if (cast<BinaryOperator>(Shr)->isExact())
1023  New->setIsExact(true);
1024  }
1025 
1026  return InsertNewInstWith(New, *Shl);
1027  }
1028 
1029  return nullptr;
1030 }
1031 
1032 /// The specified value produces a vector with any number of elements.
1033 /// This method analyzes which elements of the operand are undef or poison and
1034 /// returns that information in UndefElts.
1035 ///
1036 /// DemandedElts contains the set of elements that are actually used by the
1037 /// caller, and by default (AllowMultipleUsers equals false) the value is
1038 /// simplified only if it has a single caller. If AllowMultipleUsers is set
1039 /// to true, DemandedElts refers to the union of sets of elements that are
1040 /// used by all callers.
1041 ///
1042 /// If the information about demanded elements can be used to simplify the
1043 /// operation, the operation is simplified, then the resultant value is
1044 /// returned. This returns null if no change was made.
1046  APInt DemandedElts,
1047  APInt &UndefElts,
1048  unsigned Depth,
1049  bool AllowMultipleUsers) {
1050  // Cannot analyze scalable type. The number of vector elements is not a
1051  // compile-time constant.
1052  if (isa<ScalableVectorType>(V->getType()))
1053  return nullptr;
1054 
1055  unsigned VWidth = cast<FixedVectorType>(V->getType())->getNumElements();
1056  APInt EltMask(APInt::getAllOnesValue(VWidth));
1057  assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!");
1058 
1059  if (isa<UndefValue>(V)) {
1060  // If the entire vector is undef or poison, just return this info.
1061  UndefElts = EltMask;
1062  return nullptr;
1063  }
1064 
1065  if (DemandedElts.isNullValue()) { // If nothing is demanded, provide poison.
1066  UndefElts = EltMask;
1067  return PoisonValue::get(V->getType());
1068  }
1069 
1070  UndefElts = 0;
1071 
1072  if (auto *C = dyn_cast<Constant>(V)) {
1073  // Check if this is identity. If so, return 0 since we are not simplifying
1074  // anything.
1075  if (DemandedElts.isAllOnesValue())
1076  return nullptr;
1077 
1078  Type *EltTy = cast<VectorType>(V->getType())->getElementType();
1079  Constant *Poison = PoisonValue::get(EltTy);
1081  for (unsigned i = 0; i != VWidth; ++i) {
1082  if (!DemandedElts[i]) { // If not demanded, set to poison.
1083  Elts.push_back(Poison);
1084  UndefElts.setBit(i);
1085  continue;
1086  }
1087 
1088  Constant *Elt = C->getAggregateElement(i);
1089  if (!Elt) return nullptr;
1090 
1091  Elts.push_back(Elt);
1092  if (isa<UndefValue>(Elt)) // Already undef or poison.
1093  UndefElts.setBit(i);
1094  }
1095 
1096  // If we changed the constant, return it.
1097  Constant *NewCV = ConstantVector::get(Elts);
1098  return NewCV != C ? NewCV : nullptr;
1099  }
1100 
1101  // Limit search depth.
1102  if (Depth == 10)
1103  return nullptr;
1104 
1105  if (!AllowMultipleUsers) {
1106  // If multiple users are using the root value, proceed with
1107  // simplification conservatively assuming that all elements
1108  // are needed.
1109  if (!V->hasOneUse()) {
1110  // Quit if we find multiple users of a non-root value though.
1111  // They'll be handled when it's their turn to be visited by
1112  // the main instcombine process.
1113  if (Depth != 0)
1114  // TODO: Just compute the UndefElts information recursively.
1115  return nullptr;
1116 
1117  // Conservatively assume that all elements are needed.
1118  DemandedElts = EltMask;
1119  }
1120  }
1121 
1122  Instruction *I = dyn_cast<Instruction>(V);
1123  if (!I) return nullptr; // Only analyze instructions.
1124 
1125  bool MadeChange = false;
1126  auto simplifyAndSetOp = [&](Instruction *Inst, unsigned OpNum,
1127  APInt Demanded, APInt &Undef) {
1128  auto *II = dyn_cast<IntrinsicInst>(Inst);
1129  Value *Op = II ? II->getArgOperand(OpNum) : Inst->getOperand(OpNum);
1130  if (Value *V = SimplifyDemandedVectorElts(Op, Demanded, Undef, Depth + 1)) {
1131  replaceOperand(*Inst, OpNum, V);
1132  MadeChange = true;
1133  }
1134  };
1135 
1136  APInt UndefElts2(VWidth, 0);
1137  APInt UndefElts3(VWidth, 0);
1138  switch (I->getOpcode()) {
1139  default: break;
1140 
1141  case Instruction::GetElementPtr: {
1142  // The LangRef requires that struct geps have all constant indices. As
1143  // such, we can't convert any operand to partial undef.
1144  auto mayIndexStructType = [](GetElementPtrInst &GEP) {
1145  for (auto I = gep_type_begin(GEP), E = gep_type_end(GEP);
1146  I != E; I++)
1147  if (I.isStruct())
1148  return true;;
1149  return false;
1150  };
1151  if (mayIndexStructType(cast<GetElementPtrInst>(*I)))
1152  break;
1153 
1154  // Conservatively track the demanded elements back through any vector
1155  // operands we may have. We know there must be at least one, or we
1156  // wouldn't have a vector result to get here. Note that we intentionally
1157  // merge the undef bits here since gepping with either an undef base or
1158  // index results in undef.
1159  for (unsigned i = 0; i < I->getNumOperands(); i++) {
1160  if (isa<UndefValue>(I->getOperand(i))) {
1161  // If the entire vector is undefined, just return this info.
1162  UndefElts = EltMask;
1163  return nullptr;
1164  }
1165  if (I->getOperand(i)->getType()->isVectorTy()) {
1166  APInt UndefEltsOp(VWidth, 0);
1167  simplifyAndSetOp(I, i, DemandedElts, UndefEltsOp);
1168  UndefElts |= UndefEltsOp;
1169  }
1170  }
1171 
1172  break;
1173  }
1174  case Instruction::InsertElement: {
1175  // If this is a variable index, we don't know which element it overwrites.
1176  // demand exactly the same input as we produce.
1177  ConstantInt *Idx = dyn_cast<ConstantInt>(I->getOperand(2));
1178  if (!Idx) {
1179  // Note that we can't propagate undef elt info, because we don't know
1180  // which elt is getting updated.
1181  simplifyAndSetOp(I, 0, DemandedElts, UndefElts2);
1182  break;
1183  }
1184 
1185  // The element inserted overwrites whatever was there, so the input demanded
1186  // set is simpler than the output set.
1187  unsigned IdxNo = Idx->getZExtValue();
1188  APInt PreInsertDemandedElts = DemandedElts;
1189  if (IdxNo < VWidth)
1190  PreInsertDemandedElts.clearBit(IdxNo);
1191 
1192  // If we only demand the element that is being inserted and that element
1193  // was extracted from the same index in another vector with the same type,
1194  // replace this insert with that other vector.
1195  // Note: This is attempted before the call to simplifyAndSetOp because that
1196  // may change UndefElts to a value that does not match with Vec.
1197  Value *Vec;
1198  if (PreInsertDemandedElts == 0 &&
1199  match(I->getOperand(1),
1200  m_ExtractElt(m_Value(Vec), m_SpecificInt(IdxNo))) &&
1201  Vec->getType() == I->getType()) {
1202  return Vec;
1203  }
1204 
1205  simplifyAndSetOp(I, 0, PreInsertDemandedElts, UndefElts);
1206 
1207  // If this is inserting an element that isn't demanded, remove this
1208  // insertelement.
1209  if (IdxNo >= VWidth || !DemandedElts[IdxNo]) {
1210  Worklist.push(I);
1211  return I->getOperand(0);
1212  }
1213 
1214  // The inserted element is defined.
1215  UndefElts.clearBit(IdxNo);
1216  break;
1217  }
1218  case Instruction::ShuffleVector: {
1219  auto *Shuffle = cast<ShuffleVectorInst>(I);
1220  assert(Shuffle->getOperand(0)->getType() ==
1221  Shuffle->getOperand(1)->getType() &&
1222  "Expected shuffle operands to have same type");
1223  unsigned OpWidth = cast<FixedVectorType>(Shuffle->getOperand(0)->getType())
1224  ->getNumElements();
1225  // Handle trivial case of a splat. Only check the first element of LHS
1226  // operand.
1227  if (all_of(Shuffle->getShuffleMask(), [](int Elt) { return Elt == 0; }) &&
1228  DemandedElts.isAllOnesValue()) {
1229  if (!isa<UndefValue>(I->getOperand(1))) {
1230  I->setOperand(1, UndefValue::get(I->getOperand(1)->getType()));
1231  MadeChange = true;
1232  }
1233  APInt LeftDemanded(OpWidth, 1);
1234  APInt LHSUndefElts(OpWidth, 0);
1235  simplifyAndSetOp(I, 0, LeftDemanded, LHSUndefElts);
1236  if (LHSUndefElts[0])
1237  UndefElts = EltMask;
1238  else
1239  UndefElts.clearAllBits();
1240  break;
1241  }
1242 
1243  APInt LeftDemanded(OpWidth, 0), RightDemanded(OpWidth, 0);
1244  for (unsigned i = 0; i < VWidth; i++) {
1245  if (DemandedElts[i]) {
1246  unsigned MaskVal = Shuffle->getMaskValue(i);
1247  if (MaskVal != -1u) {
1248  assert(MaskVal < OpWidth * 2 &&
1249  "shufflevector mask index out of range!");
1250  if (MaskVal < OpWidth)
1251  LeftDemanded.setBit(MaskVal);
1252  else
1253  RightDemanded.setBit(MaskVal - OpWidth);
1254  }
1255  }
1256  }
1257 
1258  APInt LHSUndefElts(OpWidth, 0);
1259  simplifyAndSetOp(I, 0, LeftDemanded, LHSUndefElts);
1260 
1261  APInt RHSUndefElts(OpWidth, 0);
1262  simplifyAndSetOp(I, 1, RightDemanded, RHSUndefElts);
1263 
1264  // If this shuffle does not change the vector length and the elements
1265  // demanded by this shuffle are an identity mask, then this shuffle is
1266  // unnecessary.
1267  //
1268  // We are assuming canonical form for the mask, so the source vector is
1269  // operand 0 and operand 1 is not used.
1270  //
1271  // Note that if an element is demanded and this shuffle mask is undefined
1272  // for that element, then the shuffle is not considered an identity
1273  // operation. The shuffle prevents poison from the operand vector from
1274  // leaking to the result by replacing poison with an undefined value.
1275  if (VWidth == OpWidth) {
1276  bool IsIdentityShuffle = true;
1277  for (unsigned i = 0; i < VWidth; i++) {
1278  unsigned MaskVal = Shuffle->getMaskValue(i);
1279  if (DemandedElts[i] && i != MaskVal) {
1280  IsIdentityShuffle = false;
1281  break;
1282  }
1283  }
1284  if (IsIdentityShuffle)
1285  return Shuffle->getOperand(0);
1286  }
1287 
1288  bool NewUndefElts = false;
1289  unsigned LHSIdx = -1u, LHSValIdx = -1u;
1290  unsigned RHSIdx = -1u, RHSValIdx = -1u;
1291  bool LHSUniform = true;
1292  bool RHSUniform = true;
1293  for (unsigned i = 0; i < VWidth; i++) {
1294  unsigned MaskVal = Shuffle->getMaskValue(i);
1295  if (MaskVal == -1u) {
1296  UndefElts.setBit(i);
1297  } else if (!DemandedElts[i]) {
1298  NewUndefElts = true;
1299  UndefElts.setBit(i);
1300  } else if (MaskVal < OpWidth) {
1301  if (LHSUndefElts[MaskVal]) {
1302  NewUndefElts = true;
1303  UndefElts.setBit(i);
1304  } else {
1305  LHSIdx = LHSIdx == -1u ? i : OpWidth;
1306  LHSValIdx = LHSValIdx == -1u ? MaskVal : OpWidth;
1307  LHSUniform = LHSUniform && (MaskVal == i);
1308  }
1309  } else {
1310  if (RHSUndefElts[MaskVal - OpWidth]) {
1311  NewUndefElts = true;
1312  UndefElts.setBit(i);
1313  } else {
1314  RHSIdx = RHSIdx == -1u ? i : OpWidth;
1315  RHSValIdx = RHSValIdx == -1u ? MaskVal - OpWidth : OpWidth;
1316  RHSUniform = RHSUniform && (MaskVal - OpWidth == i);
1317  }
1318  }
1319  }
1320 
1321  // Try to transform shuffle with constant vector and single element from
1322  // this constant vector to single insertelement instruction.
1323  // shufflevector V, C, <v1, v2, .., ci, .., vm> ->
1324  // insertelement V, C[ci], ci-n
1325  if (OpWidth ==
1326  cast<FixedVectorType>(Shuffle->getType())->getNumElements()) {
1327  Value *Op = nullptr;
1328  Constant *Value = nullptr;
1329  unsigned Idx = -1u;
1330 
1331  // Find constant vector with the single element in shuffle (LHS or RHS).
1332  if (LHSIdx < OpWidth && RHSUniform) {
1333  if (auto *CV = dyn_cast<ConstantVector>(Shuffle->getOperand(0))) {
1334  Op = Shuffle->getOperand(1);
1335  Value = CV->getOperand(LHSValIdx);
1336  Idx = LHSIdx;
1337  }
1338  }
1339  if (RHSIdx < OpWidth && LHSUniform) {
1340  if (auto *CV = dyn_cast<ConstantVector>(Shuffle->getOperand(1))) {
1341  Op = Shuffle->getOperand(0);
1342  Value = CV->getOperand(RHSValIdx);
1343  Idx = RHSIdx;
1344  }
1345  }
1346  // Found constant vector with single element - convert to insertelement.
1347  if (Op && Value) {
1349  Op, Value, ConstantInt::get(Type::getInt32Ty(I->getContext()), Idx),
1350  Shuffle->getName());
1351  InsertNewInstWith(New, *Shuffle);
1352  return New;
1353  }
1354  }
1355  if (NewUndefElts) {
1356  // Add additional discovered undefs.
1357  SmallVector<int, 16> Elts;
1358  for (unsigned i = 0; i < VWidth; ++i) {
1359  if (UndefElts[i])
1360  Elts.push_back(UndefMaskElem);
1361  else
1362  Elts.push_back(Shuffle->getMaskValue(i));
1363  }
1364  Shuffle->setShuffleMask(Elts);
1365  MadeChange = true;
1366  }
1367  break;
1368  }
1369  case Instruction::Select: {
1370  // If this is a vector select, try to transform the select condition based
1371  // on the current demanded elements.
1372  SelectInst *Sel = cast<SelectInst>(I);
1373  if (Sel->getCondition()->getType()->isVectorTy()) {
1374  // TODO: We are not doing anything with UndefElts based on this call.
1375  // It is overwritten below based on the other select operands. If an
1376  // element of the select condition is known undef, then we are free to
1377  // choose the output value from either arm of the select. If we know that
1378  // one of those values is undef, then the output can be undef.
1379  simplifyAndSetOp(I, 0, DemandedElts, UndefElts);
1380  }
1381 
1382  // Next, see if we can transform the arms of the select.
1383  APInt DemandedLHS(DemandedElts), DemandedRHS(DemandedElts);
1384  if (auto *CV = dyn_cast<ConstantVector>(Sel->getCondition())) {
1385  for (unsigned i = 0; i < VWidth; i++) {
1386  // isNullValue() always returns false when called on a ConstantExpr.
1387  // Skip constant expressions to avoid propagating incorrect information.
1388  Constant *CElt = CV->getAggregateElement(i);
1389  if (isa<ConstantExpr>(CElt))
1390  continue;
1391  // TODO: If a select condition element is undef, we can demand from
1392  // either side. If one side is known undef, choosing that side would
1393  // propagate undef.
1394  if (CElt->isNullValue())
1395  DemandedLHS.clearBit(i);
1396  else
1397  DemandedRHS.clearBit(i);
1398  }
1399  }
1400 
1401  simplifyAndSetOp(I, 1, DemandedLHS, UndefElts2);
1402  simplifyAndSetOp(I, 2, DemandedRHS, UndefElts3);
1403 
1404  // Output elements are undefined if the element from each arm is undefined.
1405  // TODO: This can be improved. See comment in select condition handling.
1406  UndefElts = UndefElts2 & UndefElts3;
1407  break;
1408  }
1409  case Instruction::BitCast: {
1410  // Vector->vector casts only.
1411  VectorType *VTy = dyn_cast<VectorType>(I->getOperand(0)->getType());
1412  if (!VTy) break;
1413  unsigned InVWidth = cast<FixedVectorType>(VTy)->getNumElements();
1414  APInt InputDemandedElts(InVWidth, 0);
1415  UndefElts2 = APInt(InVWidth, 0);
1416  unsigned Ratio;
1417 
1418  if (VWidth == InVWidth) {
1419  // If we are converting from <4 x i32> -> <4 x f32>, we demand the same
1420  // elements as are demanded of us.
1421  Ratio = 1;
1422  InputDemandedElts = DemandedElts;
1423  } else if ((VWidth % InVWidth) == 0) {
1424  // If the number of elements in the output is a multiple of the number of
1425  // elements in the input then an input element is live if any of the
1426  // corresponding output elements are live.
1427  Ratio = VWidth / InVWidth;
1428  for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1429  if (DemandedElts[OutIdx])
1430  InputDemandedElts.setBit(OutIdx / Ratio);
1431  } else if ((InVWidth % VWidth) == 0) {
1432  // If the number of elements in the input is a multiple of the number of
1433  // elements in the output then an input element is live if the
1434  // corresponding output element is live.
1435  Ratio = InVWidth / VWidth;
1436  for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
1437  if (DemandedElts[InIdx / Ratio])
1438  InputDemandedElts.setBit(InIdx);
1439  } else {
1440  // Unsupported so far.
1441  break;
1442  }
1443 
1444  simplifyAndSetOp(I, 0, InputDemandedElts, UndefElts2);
1445 
1446  if (VWidth == InVWidth) {
1447  UndefElts = UndefElts2;
1448  } else if ((VWidth % InVWidth) == 0) {
1449  // If the number of elements in the output is a multiple of the number of
1450  // elements in the input then an output element is undef if the
1451  // corresponding input element is undef.
1452  for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1453  if (UndefElts2[OutIdx / Ratio])
1454  UndefElts.setBit(OutIdx);
1455  } else if ((InVWidth % VWidth) == 0) {
1456  // If the number of elements in the input is a multiple of the number of
1457  // elements in the output then an output element is undef if all of the
1458  // corresponding input elements are undef.
1459  for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
1460  APInt SubUndef = UndefElts2.lshr(OutIdx * Ratio).zextOrTrunc(Ratio);
1461  if (SubUndef.countPopulation() == Ratio)
1462  UndefElts.setBit(OutIdx);
1463  }
1464  } else {
1465  llvm_unreachable("Unimp");
1466  }
1467  break;
1468  }
1469  case Instruction::FPTrunc:
1470  case Instruction::FPExt:
1471  simplifyAndSetOp(I, 0, DemandedElts, UndefElts);
1472  break;
1473 
1474  case Instruction::Call: {
1475  IntrinsicInst *II = dyn_cast<IntrinsicInst>(I);
1476  if (!II) break;
1477  switch (II->getIntrinsicID()) {
1478  case Intrinsic::masked_gather: // fallthrough
1479  case Intrinsic::masked_load: {
1480  // Subtlety: If we load from a pointer, the pointer must be valid
1481  // regardless of whether the element is demanded. Doing otherwise risks
1482  // segfaults which didn't exist in the original program.
1483  APInt DemandedPtrs(APInt::getAllOnesValue(VWidth)),
1484  DemandedPassThrough(DemandedElts);
1485  if (auto *CV = dyn_cast<ConstantVector>(II->getOperand(2)))
1486  for (unsigned i = 0; i < VWidth; i++) {
1487  Constant *CElt = CV->getAggregateElement(i);
1488  if (CElt->isNullValue())
1489  DemandedPtrs.clearBit(i);
1490  else if (CElt->isAllOnesValue())
1491  DemandedPassThrough.clearBit(i);
1492  }
1493  if (II->getIntrinsicID() == Intrinsic::masked_gather)
1494  simplifyAndSetOp(II, 0, DemandedPtrs, UndefElts2);
1495  simplifyAndSetOp(II, 3, DemandedPassThrough, UndefElts3);
1496 
1497  // Output elements are undefined if the element from both sources are.
1498  // TODO: can strengthen via mask as well.
1499  UndefElts = UndefElts2 & UndefElts3;
1500  break;
1501  }
1502  default: {
1503  // Handle target specific intrinsics
1504  Optional<Value *> V = targetSimplifyDemandedVectorEltsIntrinsic(
1505  *II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
1506  simplifyAndSetOp);
1507  if (V.hasValue())
1508  return V.getValue();
1509  break;
1510  }
1511  } // switch on IntrinsicID
1512  break;
1513  } // case Call
1514  } // switch on Opcode
1515 
1516  // TODO: We bail completely on integer div/rem and shifts because they have
1517  // UB/poison potential, but that should be refined.
1518  BinaryOperator *BO;
1519  if (match(I, m_BinOp(BO)) && !BO->isIntDivRem() && !BO->isShift()) {
1520  simplifyAndSetOp(I, 0, DemandedElts, UndefElts);
1521  simplifyAndSetOp(I, 1, DemandedElts, UndefElts2);
1522 
1523  // Any change to an instruction with potential poison must clear those flags
1524  // because we can not guarantee those constraints now. Other analysis may
1525  // determine that it is safe to re-apply the flags.
1526  if (MadeChange)
1528 
1529  // Output elements are undefined if both are undefined. Consider things
1530  // like undef & 0. The result is known zero, not undef.
1531  UndefElts &= UndefElts2;
1532  }
1533 
1534  // If we've proven all of the lanes undef, return an undef value.
1535  // TODO: Intersect w/demanded lanes
1536  if (UndefElts.isAllOnesValue())
1537  return UndefValue::get(I->getType());;
1538 
1539  return MadeChange ? I : nullptr;
1540 }
i
i
Definition: README.txt:29
llvm::APInt::setAllBits
void setAllBits()
Set every bit to 1.
Definition: APInt.h:1429
llvm::Constant::isAllOnesValue
bool isAllOnesValue() const
Return true if this is the value that would be returned by getAllOnesValue.
Definition: Constants.cpp:101
llvm::APInt::clearAllBits
void clearAllBits()
Set every bit to 0.
Definition: APInt.h:1515
llvm
Definition: AllocatorList.h:23
llvm::RecurKind::Or
@ Or
Bitwise or logical OR of integers.
llvm::Value::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this value.
Definition: Value.h:447
InstCombiner.h
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:722
llvm::KnownBits::resetAll
void resetAll()
Resets the known state of all bits.
Definition: KnownBits.h:66
IntrinsicInst.h
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:52
llvm::SelectPatternResult::Flavor
SelectPatternFlavor Flavor
Definition: ValueTracking.h:681
llvm::KnownBits::Zero
APInt Zero
Definition: KnownBits.h:24
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:131
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::PatternMatch::m_Add
BinaryOp_match< LHS, RHS, Instruction::Add > m_Add(const LHS &L, const RHS &R)
Definition: PatternMatch.h:959
llvm::Use::get
Value * get() const
Definition: Use.h:67
llvm::APInt::zextOrTrunc
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:948
llvm::Instruction::hasNoUnsignedWrap
bool hasNoUnsignedWrap() const
Determine whether the no unsigned wrap flag is set.
Definition: Instruction.cpp:132
llvm::MaxAnalysisRecursionDepth
constexpr unsigned MaxAnalysisRecursionDepth
Definition: ValueTracking.h:48
ValueTracking.h
llvm::InsertElementInst::Create
static InsertElementInst * Create(Value *Vec, Value *NewElt, Value *Idx, const Twine &NameStr="", Instruction *InsertBefore=nullptr)
Definition: Instructions.h:1928
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:34
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:46
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1581
llvm::Instruction::isShift
bool isShift() const
Definition: Instruction.h:167
llvm::SPF_UMAX
@ SPF_UMAX
Signed maximum.
Definition: ValueTracking.h:662
llvm::Instruction::setHasNoUnsignedWrap
void setHasNoUnsignedWrap(bool b=true)
Set or clear the nuw flag on this instruction, which must be an operator which supports this flag.
Definition: Instruction.cpp:120
llvm::Optional
Definition: APInt.h:33
llvm::PatternMatch::m_BinOp
class_match< BinaryOperator > m_BinOp()
Match an arbitrary binary operation and ignore it.
Definition: PatternMatch.h:84
llvm::PatternMatch::m_AShr
BinaryOp_match< LHS, RHS, Instruction::AShr > m_AShr(const LHS &L, const RHS &R)
Definition: PatternMatch.h:1104
llvm::ComputeNumSignBits
unsigned ComputeNumSignBits(const Value *Op, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return the number of times the sign bit of the register is replicated into the other bits.
Definition: ValueTracking.cpp:410
llvm::APInt::intersects
bool intersects(const APInt &RHS) const
This operation tests if there are any pairs of corresponding bits between this APInt and RHS that are...
Definition: APInt.h:1341
llvm::InstCombinerImpl::SimplifyDemandedInstructionBits
bool SimplifyDemandedInstructionBits(Instruction &Inst)
Tries to simplify operands to an integer instruction based on its demanded bits.
Definition: InstCombineSimplifyDemanded.cpp:55
llvm::APInt::lshr
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:987
llvm::OverflowingBinaryOperator::hasNoUnsignedWrap
bool hasNoUnsignedWrap() const
Test whether this operation is known to never undergo unsigned overflow, aka the nuw property.
Definition: Operator.h:90
llvm::matchSelectPattern
SelectPatternResult matchSelectPattern(Value *V, Value *&LHS, Value *&RHS, Instruction::CastOps *CastOp=nullptr, unsigned Depth=0)
Pattern match integer [SU]MIN, [SU]MAX and ABS idioms, returning the kind and providing the out param...
Definition: ValueTracking.cpp:6079
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:139
llvm::SelectPatternFlavor
SelectPatternFlavor
Specific patterns of select instructions we can match.
Definition: ValueTracking.h:657
llvm::InstCombinerImpl::SimplifyDemandedVectorElts
virtual Value * SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, APInt &UndefElts, unsigned Depth=0, bool AllowMultipleUsers=false) override
The specified value produces a vector with any number of elements.
Definition: InstCombineSimplifyDemanded.cpp:1045
llvm::Instruction::setIsExact
void setIsExact(bool b=true)
Set or clear the exact flag on this instruction, which must be an operator which supports this flag.
Definition: Instruction.cpp:128
llvm::Type::getInt32Ty
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:204
llvm::APInt::countPopulation
unsigned countPopulation() const
Count the number of bits set.
Definition: APInt.h:1726
KnownBits.h
llvm::gep_type_end
gep_type_iterator gep_type_end(const User *GEP)
Definition: GetElementPtrTypeIterator.h:146
llvm::UndefMaskElem
constexpr int UndefMaskElem
Definition: Instructions.h:1974
llvm::APInt::isSignMask
bool isSignMask() const
Check if the APInt's value is returned by getSignMask.
Definition: APInt.h:478
llvm::PatternMatch::m_OneUse
OneUse_match< T > m_OneUse(const T &SubPattern)
Definition: PatternMatch.h:67
llvm::Optional::hasValue
constexpr bool hasValue() const
Definition: Optional.h:286
llvm::APInt::setHighBits
void setHighBits(unsigned hiBits)
Set the top hiBits bits.
Definition: APInt.h:1510
llvm::PatternMatch::m_APInt
apint_match m_APInt(const APInt *&Res)
Match a ConstantInt or splatted ConstantVector, binding the specified pointer to the contained APInt.
Definition: PatternMatch.h:226
llvm::APInt::uge
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
Definition: APInt.h:1313
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:77
llvm::KnownBits::isNonNegative
bool isNonNegative() const
Returns true if this value is known to be non-negative.
Definition: KnownBits.h:99
llvm::Instruction::getOpcode
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:160
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1505
llvm::SPF_UNKNOWN
@ SPF_UNKNOWN
Definition: ValueTracking.h:658
llvm::SelectInst::getCondition
const Value * getCondition() const
Definition: Instructions.h:1762
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
llvm::APInt::setBit
void setBit(unsigned BitPosition)
Set a given bit to 1.
Definition: APInt.h:1442
InstCombineInternal.h
llvm::APInt::lshrInPlace
void lshrInPlace(unsigned ShiftAmt)
Logical right-shift this APInt by ShiftAmt in place.
Definition: APInt.h:994
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::Constant::isNullValue
bool isNullValue() const
Return true if this is the value that would be returned by getNullValue.
Definition: Constants.cpp:86
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::Instruction::setHasNoSignedWrap
void setHasNoSignedWrap(bool b=true)
Set or clear the nsw flag on this instruction, which must be an operator which supports this flag.
Definition: Instruction.cpp:124
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::KnownBits::One
APInt One
Definition: KnownBits.h:25
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::KnownBits::hasConflict
bool hasConflict() const
Returns true if there is conflicting information.
Definition: KnownBits.h:47
llvm::APInt::getLimitedValue
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
Definition: APInt.h:487
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:235
llvm::APInt::setLowBits
void setLowBits(unsigned loBits)
Set the bottom loBits bits.
Definition: APInt.h:1505
llvm::PatternMatch::m_ZExt
CastClass_match< OpTy, Instruction::ZExt > m_ZExt(const OpTy &Op)
Matches ZExt.
Definition: PatternMatch.h:1590
llvm::PatternMatch::m_c_Add
BinaryOp_match< LHS, RHS, Instruction::Add, true > m_c_Add(const LHS &L, const RHS &R)
Matches a Add with LHS and RHS in either order.
Definition: PatternMatch.h:2171
llvm::ShlOperator
Definition: Operator.h:438
llvm::Constant::getAllOnesValue
static Constant * getAllOnesValue(Type *Ty)
Definition: Constants.cpp:405
llvm::PatternMatch::m_ConstantInt
class_match< ConstantInt > m_ConstantInt()
Match an arbitrary ConstantInt and ignore it.
Definition: PatternMatch.h:101
llvm::Instruction
Definition: Instruction.h:45
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:154
llvm::APInt::getZExtValue
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1631
llvm::APInt::getHighBitsSet
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
Definition: APInt.h:655
llvm::UndefValue::get
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
Definition: Constants.cpp:1770
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:885
llvm::KnownBits::sext
KnownBits sext(unsigned BitWidth) const
Return known bits for a sign extension of the value we're tracking.
Definition: KnownBits.h:169
PatternMatch.h
llvm::APInt::countTrailingZeros
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.h:1700
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:154
llvm::Instruction::isIntDivRem
bool isIntDivRem() const
Definition: Instruction.h:166
llvm::APInt::setSignBit
void setSignBit()
Set the sign bit to 1.
Definition: APInt.h:1452
llvm::APInt::isAllOnesValue
bool isAllOnesValue() const
Determine if all bits are set.
Definition: APInt.h:401
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::PatternMatch::m_ExtractElt
TwoOps_match< Val_t, Idx_t, Instruction::ExtractElement > m_ExtractElt(const Val_t &Val, const Idx_t &Idx)
Matches ExtractElementInst.
Definition: PatternMatch.h:1453
llvm::APInt::ashr
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition: APInt.h:963
llvm::APInt::isSubsetOf
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
Definition: APInt.h:1349
llvm::PatternMatch::m_Shr
BinOpPred_match< LHS, RHS, is_right_shift_op > m_Shr(const LHS &L, const RHS &R)
Matches logical shift operations.
Definition: PatternMatch.h:1264
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:391
llvm::APInt::isOneValue
bool isOneValue() const
Determine if this is a value of 1.
Definition: APInt.h:416
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
ShrinkDemandedConstant
static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo, const APInt &Demanded)
Check to see if the specified operand of the specified instruction is a constant integer.
Definition: InstCombineSimplifyDemanded.cpp:30
llvm::InstCombinerImpl::SimplifyMultipleUseDemandedBits
Value * SimplifyMultipleUseDemandedBits(Instruction *I, const APInt &DemandedMask, KnownBits &Known, unsigned Depth, Instruction *CxtI)
Helper routine of SimplifyDemandedUseBits.
Definition: InstCombineSimplifyDemanded.cpp:824
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::GetElementPtrInst
an instruction for type-safe pointer arithmetic to access elements of arrays and structs
Definition: Instructions.h:905
llvm::computeKnownBits
void computeKnownBits(const Value *V, KnownBits &Known, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, OptimizationRemarkEmitter *ORE=nullptr, bool UseInstrInfo=true)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
Definition: ValueTracking.cpp:238
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::KnownBits::countMinLeadingZeros
unsigned countMinLeadingZeros() const
Returns the minimum number of leading zero bits.
Definition: KnownBits.h:229
llvm::SelectInst
This class represents the LLVM 'select' instruction.
Definition: Instructions.h:1715
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
llvm::KnownBits::computeForAddSub
static KnownBits computeForAddSub(bool Add, bool NSW, const KnownBits &LHS, KnownBits RHS)
Compute known bits resulting from adding LHS and RHS.
Definition: KnownBits.cpp:57
llvm::APInt::urem
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
Definition: APInt.cpp:1693
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:649
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::ZExtInst
This class represents zero extension of integer types.
Definition: Instructions.h:4730
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:70
llvm::PatternMatch::m_SExt
CastClass_match< OpTy, Instruction::SExt > m_SExt(const OpTy &Op)
Matches SExt.
Definition: PatternMatch.h:1584
llvm::PatternMatch::m_SpecificInt
specific_intval< false > m_SpecificInt(APInt V)
Match a specific integer value or vector with all elements equal to the value.
Definition: PatternMatch.h:836
llvm::BinaryOperator
Definition: InstrTypes.h:190
llvm::APInt::getAllOnesValue
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:567
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::Constant::getAggregateElement
Constant * getAggregateElement(unsigned Elt) const
For aggregates (struct/array/vector) return the constant that corresponds to the specified element if...
Definition: Constants.cpp:421
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:256
uint32_t
llvm::IRBuilderBase::InsertPointGuard
Definition: IRBuilder.h:367
llvm::ConstantInt::isMinusOne
bool isMinusOne() const
This function will return true iff every bit in this constant is set to true.
Definition: Constants.h:204
llvm::ConstantVector::get
static Constant * get(ArrayRef< Constant * > V)
Definition: Constants.cpp:1354
llvm::CastInst
This is the base class for all instructions that perform data casts.
Definition: InstrTypes.h:432
llvm::APInt::ult
bool ult(const APInt &RHS) const
Unsigned less than comparison.
Definition: APInt.h:1205
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:281
llvm::Value::getName
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:298
llvm::APInt::clearBit
void clearBit(unsigned BitPosition)
Set a given bit to 0.
Definition: APInt.h:1525
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:140
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:163
llvm::KnownBits::zextOrTrunc
KnownBits zextOrTrunc(unsigned BitWidth) const
Return known bits for a zero extension or truncation of the value we're tracking.
Definition: KnownBits.h:185
llvm::APInt::countLeadingZeros
unsigned countLeadingZeros() const
The APInt version of the countLeadingZeros functions in MathExtras.h.
Definition: APInt.h:1664
llvm::InstCombinerImpl::SimplifyDemandedBits
bool SimplifyDemandedBits(Instruction *I, unsigned Op, const APInt &DemandedMask, KnownBits &Known, unsigned Depth=0) override
This form of SimplifyDemandedBits simplifies the specified instruction operand if possible,...
Definition: InstCombineSimplifyDemanded.cpp:71
llvm::APInt::trunc
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:858
llvm::KnownBits
Definition: KnownBits.h:23
llvm::OverflowingBinaryOperator::hasNoSignedWrap
bool hasNoSignedWrap() const
Test whether this operation is known to never undergo signed overflow, aka the nsw property.
Definition: Operator.h:96
llvm::InstCombinerImpl::SimplifyDemandedUseBits
Value * SimplifyDemandedUseBits(Value *V, APInt DemandedMask, KnownBits &Known, unsigned Depth, Instruction *CxtI)
Attempts to replace V with a simpler value based on the demanded bits.
Definition: InstCombineSimplifyDemanded.cpp:108
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:314
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:53
llvm::Type::isIntOrIntVectorTy
bool isIntOrIntVectorTy() const
Return true if this is an integer type or a vector of integer types.
Definition: Type.h:208
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::salvageDebugInfo
void salvageDebugInfo(Instruction &I)
Assuming the instruction I is going to be deleted, attempt to salvage debug users of I by writing the...
Definition: Local.cpp:1799
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:184
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::APInt::abs
APInt abs() const
Get the absolute value;.
Definition: APInt.h:1868
llvm::APInt::isNullValue
bool isNullValue() const
Determine if all bits are clear.
Definition: APInt.h:411
llvm::APInt::getSignMask
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
Definition: APInt.h:560
llvm::Constant::getIntegerValue
static Constant * getIntegerValue(Type *Ty, const APInt &V)
Return the value for an integer or pointer constant, or a vector thereof, with the given scalar value...
Definition: Constants.cpp:388
llvm::PatternMatch::m_ICmp
CmpClass_match< LHS, RHS, ICmpInst, ICmpInst::Predicate > m_ICmp(ICmpInst::Predicate &Pred, const LHS &L, const RHS &R)
Definition: PatternMatch.h:1355
llvm::Instruction::hasNoSignedWrap
bool hasNoSignedWrap() const
Determine whether the no signed wrap flag is set.
Definition: Instruction.cpp:136
llvm::APInt::isSignBitSet
bool isSignBitSet() const
Determine if sign bit of this APInt is set.
Definition: APInt.h:376
llvm::SPF_UMIN
@ SPF_UMIN
Signed minimum.
Definition: ValueTracking.h:660
llvm::KnownBits::commonBits
static KnownBits commonBits(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits common to LHS and RHS.
Definition: KnownBits.h:284
llvm::APInt::getActiveBits
unsigned getActiveBits() const
Compute the number of active bits in the value.
Definition: APInt.h:1605
llvm::InstCombinerImpl::simplifyShrShlDemandedBits
Value * simplifyShrShlDemandedBits(Instruction *Shr, const APInt &ShrOp1, Instruction *Shl, const APInt &ShlOp1, const APInt &DemandedMask, KnownBits &Known)
Helper routine of SimplifyDemandedUseBits.
Definition: InstCombineSimplifyDemanded.cpp:970
TargetTransformInfo.h
llvm::PatternMatch
Definition: PatternMatch.h:47
llvm::APInt::getLowBitsSet
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
Definition: APInt.h:667
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:171
llvm::KnownBits::getBitWidth
unsigned getBitWidth() const
Get the bit width of this value.
Definition: KnownBits.h:40
llvm::Value::takeName
void takeName(Value *V)
Transfer the name from V to this value.
Definition: Value.cpp:376
llvm::APInt::shl
APInt shl(unsigned shiftAmt) const
Left-shift function.
Definition: APInt.h:1009
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1272
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::PatternMatch::m_Shl
BinaryOp_match< LHS, RHS, Instruction::Shl > m_Shl(const LHS &L, const RHS &R)
Definition: PatternMatch.h:1092
llvm::Instruction::dropPoisonGeneratingFlags
void dropPoisonGeneratingFlags()
Drops flags that may cause this instruction to evaluate to poison despite having non-poison inputs.
Definition: Instruction.cpp:140
llvm::KnownBits::makeNonNegative
void makeNonNegative()
Make this value non-negative.
Definition: KnownBits.h:113
llvm::Optional::getValue
constexpr const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:280
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::PoisonValue::get
static PoisonValue * get(Type *T)
Static factory methods - Return an 'poison' object of the specified type.
Definition: Constants.cpp:1789