LLVM  14.0.0git
InstCombineSimplifyDemanded.cpp
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1 //===- InstCombineSimplifyDemanded.cpp ------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains logic for simplifying instructions based on information
10 // about how they are used.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "InstCombineInternal.h"
17 #include "llvm/IR/IntrinsicInst.h"
18 #include "llvm/IR/PatternMatch.h"
19 #include "llvm/Support/KnownBits.h"
21 
22 using namespace llvm;
23 using namespace llvm::PatternMatch;
24 
25 #define DEBUG_TYPE "instcombine"
26 
27 /// Check to see if the specified operand of the specified instruction is a
28 /// constant integer. If so, check to see if there are any bits set in the
29 /// constant that are not demanded. If so, shrink the constant and return true.
30 static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
31  const APInt &Demanded) {
32  assert(I && "No instruction?");
33  assert(OpNo < I->getNumOperands() && "Operand index too large");
34 
35  // The operand must be a constant integer or splat integer.
36  Value *Op = I->getOperand(OpNo);
37  const APInt *C;
38  if (!match(Op, m_APInt(C)))
39  return false;
40 
41  // If there are no bits set that aren't demanded, nothing to do.
42  if (C->isSubsetOf(Demanded))
43  return false;
44 
45  // This instruction is producing bits that are not demanded. Shrink the RHS.
46  I->setOperand(OpNo, ConstantInt::get(Op->getType(), *C & Demanded));
47 
48  return true;
49 }
50 
51 
52 
53 /// Inst is an integer instruction that SimplifyDemandedBits knows about. See if
54 /// the instruction has any properties that allow us to simplify its operands.
56  unsigned BitWidth = Inst.getType()->getScalarSizeInBits();
57  KnownBits Known(BitWidth);
58  APInt DemandedMask(APInt::getAllOnes(BitWidth));
59 
60  Value *V = SimplifyDemandedUseBits(&Inst, DemandedMask, Known,
61  0, &Inst);
62  if (!V) return false;
63  if (V == &Inst) return true;
64  replaceInstUsesWith(Inst, V);
65  return true;
66 }
67 
68 /// This form of SimplifyDemandedBits simplifies the specified instruction
69 /// operand if possible, updating it in place. It returns true if it made any
70 /// change and false otherwise.
72  const APInt &DemandedMask,
73  KnownBits &Known, unsigned Depth) {
74  Use &U = I->getOperandUse(OpNo);
75  Value *NewVal = SimplifyDemandedUseBits(U.get(), DemandedMask, Known,
76  Depth, I);
77  if (!NewVal) return false;
78  if (Instruction* OpInst = dyn_cast<Instruction>(U))
79  salvageDebugInfo(*OpInst);
80 
81  replaceUse(U, NewVal);
82  return true;
83 }
84 
85 /// This function attempts to replace V with a simpler value based on the
86 /// demanded bits. When this function is called, it is known that only the bits
87 /// set in DemandedMask of the result of V are ever used downstream.
88 /// Consequently, depending on the mask and V, it may be possible to replace V
89 /// with a constant or one of its operands. In such cases, this function does
90 /// the replacement and returns true. In all other cases, it returns false after
91 /// analyzing the expression and setting KnownOne and known to be one in the
92 /// expression. Known.Zero contains all the bits that are known to be zero in
93 /// the expression. These are provided to potentially allow the caller (which
94 /// might recursively be SimplifyDemandedBits itself) to simplify the
95 /// expression.
96 /// Known.One and Known.Zero always follow the invariant that:
97 /// Known.One & Known.Zero == 0.
98 /// That is, a bit can't be both 1 and 0. Note that the bits in Known.One and
99 /// Known.Zero may only be accurate for those bits set in DemandedMask. Note
100 /// also that the bitwidth of V, DemandedMask, Known.Zero and Known.One must all
101 /// be the same.
102 ///
103 /// This returns null if it did not change anything and it permits no
104 /// simplification. This returns V itself if it did some simplification of V's
105 /// operands based on the information about what bits are demanded. This returns
106 /// some other non-null value if it found out that V is equal to another value
107 /// in the context where the specified bits are demanded, but not for all users.
109  KnownBits &Known,
110  unsigned Depth,
111  Instruction *CxtI) {
112  assert(V != nullptr && "Null pointer of Value???");
113  assert(Depth <= MaxAnalysisRecursionDepth && "Limit Search Depth");
114  uint32_t BitWidth = DemandedMask.getBitWidth();
115  Type *VTy = V->getType();
116  assert(
117  (!VTy->isIntOrIntVectorTy() || VTy->getScalarSizeInBits() == BitWidth) &&
118  Known.getBitWidth() == BitWidth &&
119  "Value *V, DemandedMask and Known must have same BitWidth");
120 
121  if (isa<Constant>(V)) {
122  computeKnownBits(V, Known, Depth, CxtI);
123  return nullptr;
124  }
125 
126  Known.resetAll();
127  if (DemandedMask.isZero()) // Not demanding any bits from V.
128  return UndefValue::get(VTy);
129 
131  return nullptr;
132 
133  if (isa<ScalableVectorType>(VTy))
134  return nullptr;
135 
136  Instruction *I = dyn_cast<Instruction>(V);
137  if (!I) {
138  computeKnownBits(V, Known, Depth, CxtI);
139  return nullptr; // Only analyze instructions.
140  }
141 
142  // If there are multiple uses of this value and we aren't at the root, then
143  // we can't do any simplifications of the operands, because DemandedMask
144  // only reflects the bits demanded by *one* of the users.
145  if (Depth != 0 && !I->hasOneUse())
146  return SimplifyMultipleUseDemandedBits(I, DemandedMask, Known, Depth, CxtI);
147 
148  KnownBits LHSKnown(BitWidth), RHSKnown(BitWidth);
149 
150  // If this is the root being simplified, allow it to have multiple uses,
151  // just set the DemandedMask to all bits so that we can try to simplify the
152  // operands. This allows visitTruncInst (for example) to simplify the
153  // operand of a trunc without duplicating all the logic below.
154  if (Depth == 0 && !V->hasOneUse())
155  DemandedMask.setAllBits();
156 
157  switch (I->getOpcode()) {
158  default:
159  computeKnownBits(I, Known, Depth, CxtI);
160  break;
161  case Instruction::And: {
162  // If either the LHS or the RHS are Zero, the result is zero.
163  if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) ||
164  SimplifyDemandedBits(I, 0, DemandedMask & ~RHSKnown.Zero, LHSKnown,
165  Depth + 1))
166  return I;
167  assert(!RHSKnown.hasConflict() && "Bits known to be one AND zero?");
168  assert(!LHSKnown.hasConflict() && "Bits known to be one AND zero?");
169 
170  Known = LHSKnown & RHSKnown;
171 
172  // If the client is only demanding bits that we know, return the known
173  // constant.
174  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
175  return Constant::getIntegerValue(VTy, Known.One);
176 
177  // If all of the demanded bits are known 1 on one side, return the other.
178  // These bits cannot contribute to the result of the 'and'.
179  if (DemandedMask.isSubsetOf(LHSKnown.Zero | RHSKnown.One))
180  return I->getOperand(0);
181  if (DemandedMask.isSubsetOf(RHSKnown.Zero | LHSKnown.One))
182  return I->getOperand(1);
183 
184  // If the RHS is a constant, see if we can simplify it.
185  if (ShrinkDemandedConstant(I, 1, DemandedMask & ~LHSKnown.Zero))
186  return I;
187 
188  break;
189  }
190  case Instruction::Or: {
191  // If either the LHS or the RHS are One, the result is One.
192  if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) ||
193  SimplifyDemandedBits(I, 0, DemandedMask & ~RHSKnown.One, LHSKnown,
194  Depth + 1))
195  return I;
196  assert(!RHSKnown.hasConflict() && "Bits known to be one AND zero?");
197  assert(!LHSKnown.hasConflict() && "Bits known to be one AND zero?");
198 
199  Known = LHSKnown | RHSKnown;
200 
201  // If the client is only demanding bits that we know, return the known
202  // constant.
203  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
204  return Constant::getIntegerValue(VTy, Known.One);
205 
206  // If all of the demanded bits are known zero on one side, return the other.
207  // These bits cannot contribute to the result of the 'or'.
208  if (DemandedMask.isSubsetOf(LHSKnown.One | RHSKnown.Zero))
209  return I->getOperand(0);
210  if (DemandedMask.isSubsetOf(RHSKnown.One | LHSKnown.Zero))
211  return I->getOperand(1);
212 
213  // If the RHS is a constant, see if we can simplify it.
214  if (ShrinkDemandedConstant(I, 1, DemandedMask))
215  return I;
216 
217  break;
218  }
219  case Instruction::Xor: {
220  if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) ||
221  SimplifyDemandedBits(I, 0, DemandedMask, LHSKnown, Depth + 1))
222  return I;
223  Value *LHS, *RHS;
224  if (DemandedMask == 1 &&
225  match(I->getOperand(0), m_Intrinsic<Intrinsic::ctpop>(m_Value(LHS))) &&
226  match(I->getOperand(1), m_Intrinsic<Intrinsic::ctpop>(m_Value(RHS)))) {
227  // (ctpop(X) ^ ctpop(Y)) & 1 --> ctpop(X^Y) & 1
229  Builder.SetInsertPoint(I);
230  auto *Xor = Builder.CreateXor(LHS, RHS);
231  return Builder.CreateUnaryIntrinsic(Intrinsic::ctpop, Xor);
232  }
233 
234  assert(!RHSKnown.hasConflict() && "Bits known to be one AND zero?");
235  assert(!LHSKnown.hasConflict() && "Bits known to be one AND zero?");
236 
237  Known = LHSKnown ^ RHSKnown;
238 
239  // If the client is only demanding bits that we know, return the known
240  // constant.
241  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
242  return Constant::getIntegerValue(VTy, Known.One);
243 
244  // If all of the demanded bits are known zero on one side, return the other.
245  // These bits cannot contribute to the result of the 'xor'.
246  if (DemandedMask.isSubsetOf(RHSKnown.Zero))
247  return I->getOperand(0);
248  if (DemandedMask.isSubsetOf(LHSKnown.Zero))
249  return I->getOperand(1);
250 
251  // If all of the demanded bits are known to be zero on one side or the
252  // other, turn this into an *inclusive* or.
253  // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
254  if (DemandedMask.isSubsetOf(RHSKnown.Zero | LHSKnown.Zero)) {
255  Instruction *Or =
256  BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1),
257  I->getName());
258  return InsertNewInstWith(Or, *I);
259  }
260 
261  // If all of the demanded bits on one side are known, and all of the set
262  // bits on that side are also known to be set on the other side, turn this
263  // into an AND, as we know the bits will be cleared.
264  // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
265  if (DemandedMask.isSubsetOf(RHSKnown.Zero|RHSKnown.One) &&
266  RHSKnown.One.isSubsetOf(LHSKnown.One)) {
268  ~RHSKnown.One & DemandedMask);
269  Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
270  return InsertNewInstWith(And, *I);
271  }
272 
273  // If the RHS is a constant, see if we can change it. Don't alter a -1
274  // constant because that's a canonical 'not' op, and that is better for
275  // combining, SCEV, and codegen.
276  const APInt *C;
277  if (match(I->getOperand(1), m_APInt(C)) && !C->isAllOnes()) {
278  if ((*C | ~DemandedMask).isAllOnes()) {
279  // Force bits to 1 to create a 'not' op.
280  I->setOperand(1, ConstantInt::getAllOnesValue(VTy));
281  return I;
282  }
283  // If we can't turn this into a 'not', try to shrink the constant.
284  if (ShrinkDemandedConstant(I, 1, DemandedMask))
285  return I;
286  }
287 
288  // If our LHS is an 'and' and if it has one use, and if any of the bits we
289  // are flipping are known to be set, then the xor is just resetting those
290  // bits to zero. We can just knock out bits from the 'and' and the 'xor',
291  // simplifying both of them.
292  if (Instruction *LHSInst = dyn_cast<Instruction>(I->getOperand(0))) {
293  ConstantInt *AndRHS, *XorRHS;
294  if (LHSInst->getOpcode() == Instruction::And && LHSInst->hasOneUse() &&
295  match(I->getOperand(1), m_ConstantInt(XorRHS)) &&
296  match(LHSInst->getOperand(1), m_ConstantInt(AndRHS)) &&
297  (LHSKnown.One & RHSKnown.One & DemandedMask) != 0) {
298  APInt NewMask = ~(LHSKnown.One & RHSKnown.One & DemandedMask);
299 
300  Constant *AndC =
301  ConstantInt::get(I->getType(), NewMask & AndRHS->getValue());
302  Instruction *NewAnd = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
303  InsertNewInstWith(NewAnd, *I);
304 
305  Constant *XorC =
306  ConstantInt::get(I->getType(), NewMask & XorRHS->getValue());
307  Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC);
308  return InsertNewInstWith(NewXor, *I);
309  }
310  }
311  break;
312  }
313  case Instruction::Select: {
314  Value *LHS, *RHS;
316  if (SPF == SPF_UMAX) {
317  // UMax(A, C) == A if ...
318  // The lowest non-zero bit of DemandMask is higher than the highest
319  // non-zero bit of C.
320  const APInt *C;
321  unsigned CTZ = DemandedMask.countTrailingZeros();
322  if (match(RHS, m_APInt(C)) && CTZ >= C->getActiveBits())
323  return LHS;
324  } else if (SPF == SPF_UMIN) {
325  // UMin(A, C) == A if ...
326  // The lowest non-zero bit of DemandMask is higher than the highest
327  // non-one bit of C.
328  // This comes from using DeMorgans on the above umax example.
329  const APInt *C;
330  unsigned CTZ = DemandedMask.countTrailingZeros();
331  if (match(RHS, m_APInt(C)) &&
332  CTZ >= C->getBitWidth() - C->countLeadingOnes())
333  return LHS;
334  }
335 
336  // If this is a select as part of any other min/max pattern, don't simplify
337  // any further in case we break the structure.
338  if (SPF != SPF_UNKNOWN)
339  return nullptr;
340 
341  if (SimplifyDemandedBits(I, 2, DemandedMask, RHSKnown, Depth + 1) ||
342  SimplifyDemandedBits(I, 1, DemandedMask, LHSKnown, Depth + 1))
343  return I;
344  assert(!RHSKnown.hasConflict() && "Bits known to be one AND zero?");
345  assert(!LHSKnown.hasConflict() && "Bits known to be one AND zero?");
346 
347  // If the operands are constants, see if we can simplify them.
348  // This is similar to ShrinkDemandedConstant, but for a select we want to
349  // try to keep the selected constants the same as icmp value constants, if
350  // we can. This helps not break apart (or helps put back together)
351  // canonical patterns like min and max.
352  auto CanonicalizeSelectConstant = [](Instruction *I, unsigned OpNo,
353  const APInt &DemandedMask) {
354  const APInt *SelC;
355  if (!match(I->getOperand(OpNo), m_APInt(SelC)))
356  return false;
357 
358  // Get the constant out of the ICmp, if there is one.
359  // Only try this when exactly 1 operand is a constant (if both operands
360  // are constant, the icmp should eventually simplify). Otherwise, we may
361  // invert the transform that reduces set bits and infinite-loop.
362  Value *X;
363  const APInt *CmpC;
364  ICmpInst::Predicate Pred;
365  if (!match(I->getOperand(0), m_ICmp(Pred, m_Value(X), m_APInt(CmpC))) ||
366  isa<Constant>(X) || CmpC->getBitWidth() != SelC->getBitWidth())
367  return ShrinkDemandedConstant(I, OpNo, DemandedMask);
368 
369  // If the constant is already the same as the ICmp, leave it as-is.
370  if (*CmpC == *SelC)
371  return false;
372  // If the constants are not already the same, but can be with the demand
373  // mask, use the constant value from the ICmp.
374  if ((*CmpC & DemandedMask) == (*SelC & DemandedMask)) {
375  I->setOperand(OpNo, ConstantInt::get(I->getType(), *CmpC));
376  return true;
377  }
378  return ShrinkDemandedConstant(I, OpNo, DemandedMask);
379  };
380  if (CanonicalizeSelectConstant(I, 1, DemandedMask) ||
381  CanonicalizeSelectConstant(I, 2, DemandedMask))
382  return I;
383 
384  // Only known if known in both the LHS and RHS.
385  Known = KnownBits::commonBits(LHSKnown, RHSKnown);
386  break;
387  }
388  case Instruction::Trunc: {
389  // If we do not demand the high bits of a right-shifted and truncated value,
390  // then we may be able to truncate it before the shift.
391  Value *X;
392  const APInt *C;
393  if (match(I->getOperand(0), m_OneUse(m_LShr(m_Value(X), m_APInt(C))))) {
394  // The shift amount must be valid (not poison) in the narrow type, and
395  // it must not be greater than the high bits demanded of the result.
396  if (C->ult(I->getType()->getScalarSizeInBits()) &&
397  C->ule(DemandedMask.countLeadingZeros())) {
398  // trunc (lshr X, C) --> lshr (trunc X), C
400  Builder.SetInsertPoint(I);
401  Value *Trunc = Builder.CreateTrunc(X, I->getType());
402  return Builder.CreateLShr(Trunc, C->getZExtValue());
403  }
404  }
405  }
407  case Instruction::ZExt: {
408  unsigned SrcBitWidth = I->getOperand(0)->getType()->getScalarSizeInBits();
409 
410  APInt InputDemandedMask = DemandedMask.zextOrTrunc(SrcBitWidth);
411  KnownBits InputKnown(SrcBitWidth);
412  if (SimplifyDemandedBits(I, 0, InputDemandedMask, InputKnown, Depth + 1))
413  return I;
414  assert(InputKnown.getBitWidth() == SrcBitWidth && "Src width changed?");
415  Known = InputKnown.zextOrTrunc(BitWidth);
416  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
417  break;
418  }
419  case Instruction::BitCast:
420  if (!I->getOperand(0)->getType()->isIntOrIntVectorTy())
421  return nullptr; // vector->int or fp->int?
422 
423  if (VectorType *DstVTy = dyn_cast<VectorType>(I->getType())) {
424  if (VectorType *SrcVTy =
425  dyn_cast<VectorType>(I->getOperand(0)->getType())) {
426  if (cast<FixedVectorType>(DstVTy)->getNumElements() !=
427  cast<FixedVectorType>(SrcVTy)->getNumElements())
428  // Don't touch a bitcast between vectors of different element counts.
429  return nullptr;
430  } else
431  // Don't touch a scalar-to-vector bitcast.
432  return nullptr;
433  } else if (I->getOperand(0)->getType()->isVectorTy())
434  // Don't touch a vector-to-scalar bitcast.
435  return nullptr;
436 
437  if (SimplifyDemandedBits(I, 0, DemandedMask, Known, Depth + 1))
438  return I;
439  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
440  break;
441  case Instruction::SExt: {
442  // Compute the bits in the result that are not present in the input.
443  unsigned SrcBitWidth = I->getOperand(0)->getType()->getScalarSizeInBits();
444 
445  APInt InputDemandedBits = DemandedMask.trunc(SrcBitWidth);
446 
447  // If any of the sign extended bits are demanded, we know that the sign
448  // bit is demanded.
449  if (DemandedMask.getActiveBits() > SrcBitWidth)
450  InputDemandedBits.setBit(SrcBitWidth-1);
451 
452  KnownBits InputKnown(SrcBitWidth);
453  if (SimplifyDemandedBits(I, 0, InputDemandedBits, InputKnown, Depth + 1))
454  return I;
455 
456  // If the input sign bit is known zero, or if the NewBits are not demanded
457  // convert this into a zero extension.
458  if (InputKnown.isNonNegative() ||
459  DemandedMask.getActiveBits() <= SrcBitWidth) {
460  // Convert to ZExt cast.
461  CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName());
462  return InsertNewInstWith(NewCast, *I);
463  }
464 
465  // If the sign bit of the input is known set or clear, then we know the
466  // top bits of the result.
467  Known = InputKnown.sext(BitWidth);
468  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
469  break;
470  }
471  case Instruction::Add:
472  if ((DemandedMask & 1) == 0) {
473  // If we do not need the low bit, try to convert bool math to logic:
474  // add iN (zext i1 X), (sext i1 Y) --> sext (~X & Y) to iN
475  Value *X, *Y;
477  m_OneUse(m_SExt(m_Value(Y))))) &&
478  X->getType()->isIntOrIntVectorTy(1) && X->getType() == Y->getType()) {
479  // Truth table for inputs and output signbits:
480  // X:0 | X:1
481  // ----------
482  // Y:0 | 0 | 0 |
483  // Y:1 | -1 | 0 |
484  // ----------
486  Builder.SetInsertPoint(I);
487  Value *AndNot = Builder.CreateAnd(Builder.CreateNot(X), Y);
488  return Builder.CreateSExt(AndNot, VTy);
489  }
490 
491  // add iN (sext i1 X), (sext i1 Y) --> sext (X | Y) to iN
492  // TODO: Relax the one-use checks because we are removing an instruction?
493  if (match(I, m_Add(m_OneUse(m_SExt(m_Value(X))),
494  m_OneUse(m_SExt(m_Value(Y))))) &&
495  X->getType()->isIntOrIntVectorTy(1) && X->getType() == Y->getType()) {
496  // Truth table for inputs and output signbits:
497  // X:0 | X:1
498  // -----------
499  // Y:0 | -1 | -1 |
500  // Y:1 | -1 | 0 |
501  // -----------
503  Builder.SetInsertPoint(I);
504  Value *Or = Builder.CreateOr(X, Y);
505  return Builder.CreateSExt(Or, VTy);
506  }
507  }
509  case Instruction::Sub: {
510  /// If the high-bits of an ADD/SUB are not demanded, then we do not care
511  /// about the high bits of the operands.
512  unsigned NLZ = DemandedMask.countLeadingZeros();
513  // Right fill the mask of bits for this ADD/SUB to demand the most
514  // significant bit and all those below it.
515  APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ));
516  if (ShrinkDemandedConstant(I, 0, DemandedFromOps) ||
517  SimplifyDemandedBits(I, 0, DemandedFromOps, LHSKnown, Depth + 1) ||
518  ShrinkDemandedConstant(I, 1, DemandedFromOps) ||
519  SimplifyDemandedBits(I, 1, DemandedFromOps, RHSKnown, Depth + 1)) {
520  if (NLZ > 0) {
521  // Disable the nsw and nuw flags here: We can no longer guarantee that
522  // we won't wrap after simplification. Removing the nsw/nuw flags is
523  // legal here because the top bit is not demanded.
524  BinaryOperator &BinOP = *cast<BinaryOperator>(I);
525  BinOP.setHasNoSignedWrap(false);
526  BinOP.setHasNoUnsignedWrap(false);
527  }
528  return I;
529  }
530 
531  // If we are known to be adding/subtracting zeros to every bit below
532  // the highest demanded bit, we just return the other side.
533  if (DemandedFromOps.isSubsetOf(RHSKnown.Zero))
534  return I->getOperand(0);
535  // We can't do this with the LHS for subtraction, unless we are only
536  // demanding the LSB.
537  if ((I->getOpcode() == Instruction::Add || DemandedFromOps.isOne()) &&
538  DemandedFromOps.isSubsetOf(LHSKnown.Zero))
539  return I->getOperand(1);
540 
541  // Otherwise just compute the known bits of the result.
542  bool NSW = cast<OverflowingBinaryOperator>(I)->hasNoSignedWrap();
543  Known = KnownBits::computeForAddSub(I->getOpcode() == Instruction::Add,
544  NSW, LHSKnown, RHSKnown);
545  break;
546  }
547  case Instruction::Shl: {
548  const APInt *SA;
549  if (match(I->getOperand(1), m_APInt(SA))) {
550  const APInt *ShrAmt;
551  if (match(I->getOperand(0), m_Shr(m_Value(), m_APInt(ShrAmt))))
552  if (Instruction *Shr = dyn_cast<Instruction>(I->getOperand(0)))
553  if (Value *R = simplifyShrShlDemandedBits(Shr, *ShrAmt, I, *SA,
554  DemandedMask, Known))
555  return R;
556 
557  uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
558  APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
559 
560  // If the shift is NUW/NSW, then it does demand the high bits.
561  ShlOperator *IOp = cast<ShlOperator>(I);
562  if (IOp->hasNoSignedWrap())
563  DemandedMaskIn.setHighBits(ShiftAmt+1);
564  else if (IOp->hasNoUnsignedWrap())
565  DemandedMaskIn.setHighBits(ShiftAmt);
566 
567  if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
568  return I;
569  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
570 
571  bool SignBitZero = Known.Zero.isSignBitSet();
572  bool SignBitOne = Known.One.isSignBitSet();
573  Known.Zero <<= ShiftAmt;
574  Known.One <<= ShiftAmt;
575  // low bits known zero.
576  if (ShiftAmt)
577  Known.Zero.setLowBits(ShiftAmt);
578 
579  // If this shift has "nsw" keyword, then the result is either a poison
580  // value or has the same sign bit as the first operand.
581  if (IOp->hasNoSignedWrap()) {
582  if (SignBitZero)
583  Known.Zero.setSignBit();
584  else if (SignBitOne)
585  Known.One.setSignBit();
586  if (Known.hasConflict())
587  return UndefValue::get(I->getType());
588  }
589  } else {
590  // This is a variable shift, so we can't shift the demand mask by a known
591  // amount. But if we are not demanding high bits, then we are not
592  // demanding those bits from the pre-shifted operand either.
593  if (unsigned CTLZ = DemandedMask.countLeadingZeros()) {
594  APInt DemandedFromOp(APInt::getLowBitsSet(BitWidth, BitWidth - CTLZ));
595  if (SimplifyDemandedBits(I, 0, DemandedFromOp, Known, Depth + 1)) {
596  // We can't guarantee that nsw/nuw hold after simplifying the operand.
597  I->dropPoisonGeneratingFlags();
598  return I;
599  }
600  }
601  computeKnownBits(I, Known, Depth, CxtI);
602  }
603  break;
604  }
605  case Instruction::LShr: {
606  const APInt *SA;
607  if (match(I->getOperand(1), m_APInt(SA))) {
608  uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
609 
610  // Unsigned shift right.
611  APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
612 
613  // If the shift is exact, then it does demand the low bits (and knows that
614  // they are zero).
615  if (cast<LShrOperator>(I)->isExact())
616  DemandedMaskIn.setLowBits(ShiftAmt);
617 
618  if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
619  return I;
620  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
621  Known.Zero.lshrInPlace(ShiftAmt);
622  Known.One.lshrInPlace(ShiftAmt);
623  if (ShiftAmt)
624  Known.Zero.setHighBits(ShiftAmt); // high bits known zero.
625  } else {
626  computeKnownBits(I, Known, Depth, CxtI);
627  }
628  break;
629  }
630  case Instruction::AShr: {
631  // If this is an arithmetic shift right and only the low-bit is set, we can
632  // always convert this into a logical shr, even if the shift amount is
633  // variable. The low bit of the shift cannot be an input sign bit unless
634  // the shift amount is >= the size of the datatype, which is undefined.
635  if (DemandedMask.isOne()) {
636  // Perform the logical shift right.
637  Instruction *NewVal = BinaryOperator::CreateLShr(
638  I->getOperand(0), I->getOperand(1), I->getName());
639  return InsertNewInstWith(NewVal, *I);
640  }
641 
642  // If the sign bit is the only bit demanded by this ashr, then there is no
643  // need to do it, the shift doesn't change the high bit.
644  if (DemandedMask.isSignMask())
645  return I->getOperand(0);
646 
647  const APInt *SA;
648  if (match(I->getOperand(1), m_APInt(SA))) {
649  uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
650 
651  // Signed shift right.
652  APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
653  // If any of the high bits are demanded, we should set the sign bit as
654  // demanded.
655  if (DemandedMask.countLeadingZeros() <= ShiftAmt)
656  DemandedMaskIn.setSignBit();
657 
658  // If the shift is exact, then it does demand the low bits (and knows that
659  // they are zero).
660  if (cast<AShrOperator>(I)->isExact())
661  DemandedMaskIn.setLowBits(ShiftAmt);
662 
663  if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
664  return I;
665 
666  unsigned SignBits = ComputeNumSignBits(I->getOperand(0), Depth + 1, CxtI);
667 
668  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
669  // Compute the new bits that are at the top now plus sign bits.
670  APInt HighBits(APInt::getHighBitsSet(
671  BitWidth, std::min(SignBits + ShiftAmt - 1, BitWidth)));
672  Known.Zero.lshrInPlace(ShiftAmt);
673  Known.One.lshrInPlace(ShiftAmt);
674 
675  // If the input sign bit is known to be zero, or if none of the top bits
676  // are demanded, turn this into an unsigned shift right.
677  assert(BitWidth > ShiftAmt && "Shift amount not saturated?");
678  if (Known.Zero[BitWidth-ShiftAmt-1] ||
679  !DemandedMask.intersects(HighBits)) {
680  BinaryOperator *LShr = BinaryOperator::CreateLShr(I->getOperand(0),
681  I->getOperand(1));
682  LShr->setIsExact(cast<BinaryOperator>(I)->isExact());
683  return InsertNewInstWith(LShr, *I);
684  } else if (Known.One[BitWidth-ShiftAmt-1]) { // New bits are known one.
685  Known.One |= HighBits;
686  }
687  } else {
688  computeKnownBits(I, Known, Depth, CxtI);
689  }
690  break;
691  }
692  case Instruction::UDiv: {
693  // UDiv doesn't demand low bits that are zero in the divisor.
694  const APInt *SA;
695  if (match(I->getOperand(1), m_APInt(SA))) {
696  // If the shift is exact, then it does demand the low bits.
697  if (cast<UDivOperator>(I)->isExact())
698  break;
699 
700  // FIXME: Take the demanded mask of the result into account.
701  unsigned RHSTrailingZeros = SA->countTrailingZeros();
702  APInt DemandedMaskIn =
703  APInt::getHighBitsSet(BitWidth, BitWidth - RHSTrailingZeros);
704  if (SimplifyDemandedBits(I, 0, DemandedMaskIn, LHSKnown, Depth + 1))
705  return I;
706 
707  // Propagate zero bits from the input.
708  Known.Zero.setHighBits(std::min(
709  BitWidth, LHSKnown.Zero.countLeadingOnes() + RHSTrailingZeros));
710  } else {
711  computeKnownBits(I, Known, Depth, CxtI);
712  }
713  break;
714  }
715  case Instruction::SRem: {
716  ConstantInt *Rem;
717  if (match(I->getOperand(1), m_ConstantInt(Rem))) {
718  // X % -1 demands all the bits because we don't want to introduce
719  // INT_MIN % -1 (== undef) by accident.
720  if (Rem->isMinusOne())
721  break;
722  APInt RA = Rem->getValue().abs();
723  if (RA.isPowerOf2()) {
724  if (DemandedMask.ult(RA)) // srem won't affect demanded bits
725  return I->getOperand(0);
726 
727  APInt LowBits = RA - 1;
728  APInt Mask2 = LowBits | APInt::getSignMask(BitWidth);
729  if (SimplifyDemandedBits(I, 0, Mask2, LHSKnown, Depth + 1))
730  return I;
731 
732  // The low bits of LHS are unchanged by the srem.
733  Known.Zero = LHSKnown.Zero & LowBits;
734  Known.One = LHSKnown.One & LowBits;
735 
736  // If LHS is non-negative or has all low bits zero, then the upper bits
737  // are all zero.
738  if (LHSKnown.isNonNegative() || LowBits.isSubsetOf(LHSKnown.Zero))
739  Known.Zero |= ~LowBits;
740 
741  // If LHS is negative and not all low bits are zero, then the upper bits
742  // are all one.
743  if (LHSKnown.isNegative() && LowBits.intersects(LHSKnown.One))
744  Known.One |= ~LowBits;
745 
746  assert(!Known.hasConflict() && "Bits known to be one AND zero?");
747  break;
748  }
749  }
750 
751  // The sign bit is the LHS's sign bit, except when the result of the
752  // remainder is zero.
753  if (DemandedMask.isSignBitSet()) {
754  computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1, CxtI);
755  // If it's known zero, our sign bit is also zero.
756  if (LHSKnown.isNonNegative())
757  Known.makeNonNegative();
758  }
759  break;
760  }
761  case Instruction::URem: {
762  KnownBits Known2(BitWidth);
763  APInt AllOnes = APInt::getAllOnes(BitWidth);
764  if (SimplifyDemandedBits(I, 0, AllOnes, Known2, Depth + 1) ||
765  SimplifyDemandedBits(I, 1, AllOnes, Known2, Depth + 1))
766  return I;
767 
768  unsigned Leaders = Known2.countMinLeadingZeros();
769  Known.Zero = APInt::getHighBitsSet(BitWidth, Leaders) & DemandedMask;
770  break;
771  }
772  case Instruction::Call: {
773  bool KnownBitsComputed = false;
774  if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
775  switch (II->getIntrinsicID()) {
776  case Intrinsic::abs: {
777  if (DemandedMask == 1)
778  return II->getArgOperand(0);
779  break;
780  }
781  case Intrinsic::ctpop: {
782  // Checking if the number of clear bits is odd (parity)? If the type has
783  // an even number of bits, that's the same as checking if the number of
784  // set bits is odd, so we can eliminate the 'not' op.
785  Value *X;
786  if (DemandedMask == 1 && VTy->getScalarSizeInBits() % 2 == 0 &&
787  match(II->getArgOperand(0), m_Not(m_Value(X)))) {
789  II->getModule(), Intrinsic::ctpop, II->getType());
790  return InsertNewInstWith(CallInst::Create(Ctpop, {X}), *I);
791  }
792  break;
793  }
794  case Intrinsic::bswap: {
795  // If the only bits demanded come from one byte of the bswap result,
796  // just shift the input byte into position to eliminate the bswap.
797  unsigned NLZ = DemandedMask.countLeadingZeros();
798  unsigned NTZ = DemandedMask.countTrailingZeros();
799 
800  // Round NTZ down to the next byte. If we have 11 trailing zeros, then
801  // we need all the bits down to bit 8. Likewise, round NLZ. If we
802  // have 14 leading zeros, round to 8.
803  NLZ &= ~7;
804  NTZ &= ~7;
805  // If we need exactly one byte, we can do this transformation.
806  if (BitWidth-NLZ-NTZ == 8) {
807  unsigned ResultBit = NTZ;
808  unsigned InputBit = BitWidth-NTZ-8;
809 
810  // Replace this with either a left or right shift to get the byte into
811  // the right place.
812  Instruction *NewVal;
813  if (InputBit > ResultBit)
814  NewVal = BinaryOperator::CreateLShr(II->getArgOperand(0),
815  ConstantInt::get(I->getType(), InputBit-ResultBit));
816  else
817  NewVal = BinaryOperator::CreateShl(II->getArgOperand(0),
818  ConstantInt::get(I->getType(), ResultBit-InputBit));
819  NewVal->takeName(I);
820  return InsertNewInstWith(NewVal, *I);
821  }
822  break;
823  }
824  case Intrinsic::fshr:
825  case Intrinsic::fshl: {
826  const APInt *SA;
827  if (!match(I->getOperand(2), m_APInt(SA)))
828  break;
829 
830  // Normalize to funnel shift left. APInt shifts of BitWidth are well-
831  // defined, so no need to special-case zero shifts here.
832  uint64_t ShiftAmt = SA->urem(BitWidth);
833  if (II->getIntrinsicID() == Intrinsic::fshr)
834  ShiftAmt = BitWidth - ShiftAmt;
835 
836  APInt DemandedMaskLHS(DemandedMask.lshr(ShiftAmt));
837  APInt DemandedMaskRHS(DemandedMask.shl(BitWidth - ShiftAmt));
838  if (SimplifyDemandedBits(I, 0, DemandedMaskLHS, LHSKnown, Depth + 1) ||
839  SimplifyDemandedBits(I, 1, DemandedMaskRHS, RHSKnown, Depth + 1))
840  return I;
841 
842  Known.Zero = LHSKnown.Zero.shl(ShiftAmt) |
843  RHSKnown.Zero.lshr(BitWidth - ShiftAmt);
844  Known.One = LHSKnown.One.shl(ShiftAmt) |
845  RHSKnown.One.lshr(BitWidth - ShiftAmt);
846  KnownBitsComputed = true;
847  break;
848  }
849  case Intrinsic::umax: {
850  // UMax(A, C) == A if ...
851  // The lowest non-zero bit of DemandMask is higher than the highest
852  // non-zero bit of C.
853  const APInt *C;
854  unsigned CTZ = DemandedMask.countTrailingZeros();
855  if (match(II->getArgOperand(1), m_APInt(C)) &&
856  CTZ >= C->getActiveBits())
857  return II->getArgOperand(0);
858  break;
859  }
860  case Intrinsic::umin: {
861  // UMin(A, C) == A if ...
862  // The lowest non-zero bit of DemandMask is higher than the highest
863  // non-one bit of C.
864  // This comes from using DeMorgans on the above umax example.
865  const APInt *C;
866  unsigned CTZ = DemandedMask.countTrailingZeros();
867  if (match(II->getArgOperand(1), m_APInt(C)) &&
868  CTZ >= C->getBitWidth() - C->countLeadingOnes())
869  return II->getArgOperand(0);
870  break;
871  }
872  default: {
873  // Handle target specific intrinsics
874  Optional<Value *> V = targetSimplifyDemandedUseBitsIntrinsic(
875  *II, DemandedMask, Known, KnownBitsComputed);
876  if (V.hasValue())
877  return V.getValue();
878  break;
879  }
880  }
881  }
882 
883  if (!KnownBitsComputed)
884  computeKnownBits(V, Known, Depth, CxtI);
885  break;
886  }
887  }
888 
889  // If the client is only demanding bits that we know, return the known
890  // constant.
891  if (DemandedMask.isSubsetOf(Known.Zero|Known.One))
892  return Constant::getIntegerValue(VTy, Known.One);
893  return nullptr;
894 }
895 
896 /// Helper routine of SimplifyDemandedUseBits. It computes Known
897 /// bits. It also tries to handle simplifications that can be done based on
898 /// DemandedMask, but without modifying the Instruction.
900  Instruction *I, const APInt &DemandedMask, KnownBits &Known, unsigned Depth,
901  Instruction *CxtI) {
902  unsigned BitWidth = DemandedMask.getBitWidth();
903  Type *ITy = I->getType();
904 
905  KnownBits LHSKnown(BitWidth);
906  KnownBits RHSKnown(BitWidth);
907 
908  // Despite the fact that we can't simplify this instruction in all User's
909  // context, we can at least compute the known bits, and we can
910  // do simplifications that apply to *just* the one user if we know that
911  // this instruction has a simpler value in that context.
912  switch (I->getOpcode()) {
913  case Instruction::And: {
914  // If either the LHS or the RHS are Zero, the result is zero.
915  computeKnownBits(I->getOperand(1), RHSKnown, Depth + 1, CxtI);
916  computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1,
917  CxtI);
918 
919  Known = LHSKnown & RHSKnown;
920 
921  // If the client is only demanding bits that we know, return the known
922  // constant.
923  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
924  return Constant::getIntegerValue(ITy, Known.One);
925 
926  // If all of the demanded bits are known 1 on one side, return the other.
927  // These bits cannot contribute to the result of the 'and' in this
928  // context.
929  if (DemandedMask.isSubsetOf(LHSKnown.Zero | RHSKnown.One))
930  return I->getOperand(0);
931  if (DemandedMask.isSubsetOf(RHSKnown.Zero | LHSKnown.One))
932  return I->getOperand(1);
933 
934  break;
935  }
936  case Instruction::Or: {
937  // We can simplify (X|Y) -> X or Y in the user's context if we know that
938  // only bits from X or Y are demanded.
939 
940  // If either the LHS or the RHS are One, the result is One.
941  computeKnownBits(I->getOperand(1), RHSKnown, Depth + 1, CxtI);
942  computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1,
943  CxtI);
944 
945  Known = LHSKnown | RHSKnown;
946 
947  // If the client is only demanding bits that we know, return the known
948  // constant.
949  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
950  return Constant::getIntegerValue(ITy, Known.One);
951 
952  // If all of the demanded bits are known zero on one side, return the
953  // other. These bits cannot contribute to the result of the 'or' in this
954  // context.
955  if (DemandedMask.isSubsetOf(LHSKnown.One | RHSKnown.Zero))
956  return I->getOperand(0);
957  if (DemandedMask.isSubsetOf(RHSKnown.One | LHSKnown.Zero))
958  return I->getOperand(1);
959 
960  break;
961  }
962  case Instruction::Xor: {
963  // We can simplify (X^Y) -> X or Y in the user's context if we know that
964  // only bits from X or Y are demanded.
965 
966  computeKnownBits(I->getOperand(1), RHSKnown, Depth + 1, CxtI);
967  computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1,
968  CxtI);
969 
970  Known = LHSKnown ^ RHSKnown;
971 
972  // If the client is only demanding bits that we know, return the known
973  // constant.
974  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
975  return Constant::getIntegerValue(ITy, Known.One);
976 
977  // If all of the demanded bits are known zero on one side, return the
978  // other.
979  if (DemandedMask.isSubsetOf(RHSKnown.Zero))
980  return I->getOperand(0);
981  if (DemandedMask.isSubsetOf(LHSKnown.Zero))
982  return I->getOperand(1);
983 
984  break;
985  }
986  case Instruction::AShr: {
987  // Compute the Known bits to simplify things downstream.
988  computeKnownBits(I, Known, Depth, CxtI);
989 
990  // If this user is only demanding bits that we know, return the known
991  // constant.
992  if (DemandedMask.isSubsetOf(Known.Zero | Known.One))
993  return Constant::getIntegerValue(ITy, Known.One);
994 
995  // If the right shift operand 0 is a result of a left shift by the same
996  // amount, this is probably a zero/sign extension, which may be unnecessary,
997  // if we do not demand any of the new sign bits. So, return the original
998  // operand instead.
999  const APInt *ShiftRC;
1000  const APInt *ShiftLC;
1001  Value *X;
1002  unsigned BitWidth = DemandedMask.getBitWidth();
1003  if (match(I,
1004  m_AShr(m_Shl(m_Value(X), m_APInt(ShiftLC)), m_APInt(ShiftRC))) &&
1005  ShiftLC == ShiftRC && ShiftLC->ult(BitWidth) &&
1006  DemandedMask.isSubsetOf(APInt::getLowBitsSet(
1007  BitWidth, BitWidth - ShiftRC->getZExtValue()))) {
1008  return X;
1009  }
1010 
1011  break;
1012  }
1013  default:
1014  // Compute the Known bits to simplify things downstream.
1015  computeKnownBits(I, Known, Depth, CxtI);
1016 
1017  // If this user is only demanding bits that we know, return the known
1018  // constant.
1019  if (DemandedMask.isSubsetOf(Known.Zero|Known.One))
1020  return Constant::getIntegerValue(ITy, Known.One);
1021 
1022  break;
1023  }
1024 
1025  return nullptr;
1026 }
1027 
1028 /// Helper routine of SimplifyDemandedUseBits. It tries to simplify
1029 /// "E1 = (X lsr C1) << C2", where the C1 and C2 are constant, into
1030 /// "E2 = X << (C2 - C1)" or "E2 = X >> (C1 - C2)", depending on the sign
1031 /// of "C2-C1".
1032 ///
1033 /// Suppose E1 and E2 are generally different in bits S={bm, bm+1,
1034 /// ..., bn}, without considering the specific value X is holding.
1035 /// This transformation is legal iff one of following conditions is hold:
1036 /// 1) All the bit in S are 0, in this case E1 == E2.
1037 /// 2) We don't care those bits in S, per the input DemandedMask.
1038 /// 3) Combination of 1) and 2). Some bits in S are 0, and we don't care the
1039 /// rest bits.
1040 ///
1041 /// Currently we only test condition 2).
1042 ///
1043 /// As with SimplifyDemandedUseBits, it returns NULL if the simplification was
1044 /// not successful.
1046  Instruction *Shr, const APInt &ShrOp1, Instruction *Shl,
1047  const APInt &ShlOp1, const APInt &DemandedMask, KnownBits &Known) {
1048  if (!ShlOp1 || !ShrOp1)
1049  return nullptr; // No-op.
1050 
1051  Value *VarX = Shr->getOperand(0);
1052  Type *Ty = VarX->getType();
1053  unsigned BitWidth = Ty->getScalarSizeInBits();
1054  if (ShlOp1.uge(BitWidth) || ShrOp1.uge(BitWidth))
1055  return nullptr; // Undef.
1056 
1057  unsigned ShlAmt = ShlOp1.getZExtValue();
1058  unsigned ShrAmt = ShrOp1.getZExtValue();
1059 
1060  Known.One.clearAllBits();
1061  Known.Zero.setLowBits(ShlAmt - 1);
1062  Known.Zero &= DemandedMask;
1063 
1064  APInt BitMask1(APInt::getAllOnes(BitWidth));
1065  APInt BitMask2(APInt::getAllOnes(BitWidth));
1066 
1067  bool isLshr = (Shr->getOpcode() == Instruction::LShr);
1068  BitMask1 = isLshr ? (BitMask1.lshr(ShrAmt) << ShlAmt) :
1069  (BitMask1.ashr(ShrAmt) << ShlAmt);
1070 
1071  if (ShrAmt <= ShlAmt) {
1072  BitMask2 <<= (ShlAmt - ShrAmt);
1073  } else {
1074  BitMask2 = isLshr ? BitMask2.lshr(ShrAmt - ShlAmt):
1075  BitMask2.ashr(ShrAmt - ShlAmt);
1076  }
1077 
1078  // Check if condition-2 (see the comment to this function) is satified.
1079  if ((BitMask1 & DemandedMask) == (BitMask2 & DemandedMask)) {
1080  if (ShrAmt == ShlAmt)
1081  return VarX;
1082 
1083  if (!Shr->hasOneUse())
1084  return nullptr;
1085 
1086  BinaryOperator *New;
1087  if (ShrAmt < ShlAmt) {
1088  Constant *Amt = ConstantInt::get(VarX->getType(), ShlAmt - ShrAmt);
1089  New = BinaryOperator::CreateShl(VarX, Amt);
1090  BinaryOperator *Orig = cast<BinaryOperator>(Shl);
1091  New->setHasNoSignedWrap(Orig->hasNoSignedWrap());
1092  New->setHasNoUnsignedWrap(Orig->hasNoUnsignedWrap());
1093  } else {
1094  Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt);
1095  New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
1096  BinaryOperator::CreateAShr(VarX, Amt);
1097  if (cast<BinaryOperator>(Shr)->isExact())
1098  New->setIsExact(true);
1099  }
1100 
1101  return InsertNewInstWith(New, *Shl);
1102  }
1103 
1104  return nullptr;
1105 }
1106 
1107 /// The specified value produces a vector with any number of elements.
1108 /// This method analyzes which elements of the operand are undef or poison and
1109 /// returns that information in UndefElts.
1110 ///
1111 /// DemandedElts contains the set of elements that are actually used by the
1112 /// caller, and by default (AllowMultipleUsers equals false) the value is
1113 /// simplified only if it has a single caller. If AllowMultipleUsers is set
1114 /// to true, DemandedElts refers to the union of sets of elements that are
1115 /// used by all callers.
1116 ///
1117 /// If the information about demanded elements can be used to simplify the
1118 /// operation, the operation is simplified, then the resultant value is
1119 /// returned. This returns null if no change was made.
1121  APInt DemandedElts,
1122  APInt &UndefElts,
1123  unsigned Depth,
1124  bool AllowMultipleUsers) {
1125  // Cannot analyze scalable type. The number of vector elements is not a
1126  // compile-time constant.
1127  if (isa<ScalableVectorType>(V->getType()))
1128  return nullptr;
1129 
1130  unsigned VWidth = cast<FixedVectorType>(V->getType())->getNumElements();
1131  APInt EltMask(APInt::getAllOnes(VWidth));
1132  assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!");
1133 
1134  if (match(V, m_Undef())) {
1135  // If the entire vector is undef or poison, just return this info.
1136  UndefElts = EltMask;
1137  return nullptr;
1138  }
1139 
1140  if (DemandedElts.isZero()) { // If nothing is demanded, provide poison.
1141  UndefElts = EltMask;
1142  return PoisonValue::get(V->getType());
1143  }
1144 
1145  UndefElts = 0;
1146 
1147  if (auto *C = dyn_cast<Constant>(V)) {
1148  // Check if this is identity. If so, return 0 since we are not simplifying
1149  // anything.
1150  if (DemandedElts.isAllOnes())
1151  return nullptr;
1152 
1153  Type *EltTy = cast<VectorType>(V->getType())->getElementType();
1154  Constant *Poison = PoisonValue::get(EltTy);
1156  for (unsigned i = 0; i != VWidth; ++i) {
1157  if (!DemandedElts[i]) { // If not demanded, set to poison.
1158  Elts.push_back(Poison);
1159  UndefElts.setBit(i);
1160  continue;
1161  }
1162 
1163  Constant *Elt = C->getAggregateElement(i);
1164  if (!Elt) return nullptr;
1165 
1166  Elts.push_back(Elt);
1167  if (isa<UndefValue>(Elt)) // Already undef or poison.
1168  UndefElts.setBit(i);
1169  }
1170 
1171  // If we changed the constant, return it.
1172  Constant *NewCV = ConstantVector::get(Elts);
1173  return NewCV != C ? NewCV : nullptr;
1174  }
1175 
1176  // Limit search depth.
1177  if (Depth == 10)
1178  return nullptr;
1179 
1180  if (!AllowMultipleUsers) {
1181  // If multiple users are using the root value, proceed with
1182  // simplification conservatively assuming that all elements
1183  // are needed.
1184  if (!V->hasOneUse()) {
1185  // Quit if we find multiple users of a non-root value though.
1186  // They'll be handled when it's their turn to be visited by
1187  // the main instcombine process.
1188  if (Depth != 0)
1189  // TODO: Just compute the UndefElts information recursively.
1190  return nullptr;
1191 
1192  // Conservatively assume that all elements are needed.
1193  DemandedElts = EltMask;
1194  }
1195  }
1196 
1197  Instruction *I = dyn_cast<Instruction>(V);
1198  if (!I) return nullptr; // Only analyze instructions.
1199 
1200  bool MadeChange = false;
1201  auto simplifyAndSetOp = [&](Instruction *Inst, unsigned OpNum,
1202  APInt Demanded, APInt &Undef) {
1203  auto *II = dyn_cast<IntrinsicInst>(Inst);
1204  Value *Op = II ? II->getArgOperand(OpNum) : Inst->getOperand(OpNum);
1205  if (Value *V = SimplifyDemandedVectorElts(Op, Demanded, Undef, Depth + 1)) {
1206  replaceOperand(*Inst, OpNum, V);
1207  MadeChange = true;
1208  }
1209  };
1210 
1211  APInt UndefElts2(VWidth, 0);
1212  APInt UndefElts3(VWidth, 0);
1213  switch (I->getOpcode()) {
1214  default: break;
1215 
1216  case Instruction::GetElementPtr: {
1217  // The LangRef requires that struct geps have all constant indices. As
1218  // such, we can't convert any operand to partial undef.
1219  auto mayIndexStructType = [](GetElementPtrInst &GEP) {
1220  for (auto I = gep_type_begin(GEP), E = gep_type_end(GEP);
1221  I != E; I++)
1222  if (I.isStruct())
1223  return true;;
1224  return false;
1225  };
1226  if (mayIndexStructType(cast<GetElementPtrInst>(*I)))
1227  break;
1228 
1229  // Conservatively track the demanded elements back through any vector
1230  // operands we may have. We know there must be at least one, or we
1231  // wouldn't have a vector result to get here. Note that we intentionally
1232  // merge the undef bits here since gepping with either an undef base or
1233  // index results in undef.
1234  for (unsigned i = 0; i < I->getNumOperands(); i++) {
1235  if (match(I->getOperand(i), m_Undef())) {
1236  // If the entire vector is undefined, just return this info.
1237  UndefElts = EltMask;
1238  return nullptr;
1239  }
1240  if (I->getOperand(i)->getType()->isVectorTy()) {
1241  APInt UndefEltsOp(VWidth, 0);
1242  simplifyAndSetOp(I, i, DemandedElts, UndefEltsOp);
1243  UndefElts |= UndefEltsOp;
1244  }
1245  }
1246 
1247  break;
1248  }
1249  case Instruction::InsertElement: {
1250  // If this is a variable index, we don't know which element it overwrites.
1251  // demand exactly the same input as we produce.
1252  ConstantInt *Idx = dyn_cast<ConstantInt>(I->getOperand(2));
1253  if (!Idx) {
1254  // Note that we can't propagate undef elt info, because we don't know
1255  // which elt is getting updated.
1256  simplifyAndSetOp(I, 0, DemandedElts, UndefElts2);
1257  break;
1258  }
1259 
1260  // The element inserted overwrites whatever was there, so the input demanded
1261  // set is simpler than the output set.
1262  unsigned IdxNo = Idx->getZExtValue();
1263  APInt PreInsertDemandedElts = DemandedElts;
1264  if (IdxNo < VWidth)
1265  PreInsertDemandedElts.clearBit(IdxNo);
1266 
1267  // If we only demand the element that is being inserted and that element
1268  // was extracted from the same index in another vector with the same type,
1269  // replace this insert with that other vector.
1270  // Note: This is attempted before the call to simplifyAndSetOp because that
1271  // may change UndefElts to a value that does not match with Vec.
1272  Value *Vec;
1273  if (PreInsertDemandedElts == 0 &&
1274  match(I->getOperand(1),
1275  m_ExtractElt(m_Value(Vec), m_SpecificInt(IdxNo))) &&
1276  Vec->getType() == I->getType()) {
1277  return Vec;
1278  }
1279 
1280  simplifyAndSetOp(I, 0, PreInsertDemandedElts, UndefElts);
1281 
1282  // If this is inserting an element that isn't demanded, remove this
1283  // insertelement.
1284  if (IdxNo >= VWidth || !DemandedElts[IdxNo]) {
1285  Worklist.push(I);
1286  return I->getOperand(0);
1287  }
1288 
1289  // The inserted element is defined.
1290  UndefElts.clearBit(IdxNo);
1291  break;
1292  }
1293  case Instruction::ShuffleVector: {
1294  auto *Shuffle = cast<ShuffleVectorInst>(I);
1295  assert(Shuffle->getOperand(0)->getType() ==
1296  Shuffle->getOperand(1)->getType() &&
1297  "Expected shuffle operands to have same type");
1298  unsigned OpWidth = cast<FixedVectorType>(Shuffle->getOperand(0)->getType())
1299  ->getNumElements();
1300  // Handle trivial case of a splat. Only check the first element of LHS
1301  // operand.
1302  if (all_of(Shuffle->getShuffleMask(), [](int Elt) { return Elt == 0; }) &&
1303  DemandedElts.isAllOnes()) {
1304  if (!match(I->getOperand(1), m_Undef())) {
1305  I->setOperand(1, PoisonValue::get(I->getOperand(1)->getType()));
1306  MadeChange = true;
1307  }
1308  APInt LeftDemanded(OpWidth, 1);
1309  APInt LHSUndefElts(OpWidth, 0);
1310  simplifyAndSetOp(I, 0, LeftDemanded, LHSUndefElts);
1311  if (LHSUndefElts[0])
1312  UndefElts = EltMask;
1313  else
1314  UndefElts.clearAllBits();
1315  break;
1316  }
1317 
1318  APInt LeftDemanded(OpWidth, 0), RightDemanded(OpWidth, 0);
1319  for (unsigned i = 0; i < VWidth; i++) {
1320  if (DemandedElts[i]) {
1321  unsigned MaskVal = Shuffle->getMaskValue(i);
1322  if (MaskVal != -1u) {
1323  assert(MaskVal < OpWidth * 2 &&
1324  "shufflevector mask index out of range!");
1325  if (MaskVal < OpWidth)
1326  LeftDemanded.setBit(MaskVal);
1327  else
1328  RightDemanded.setBit(MaskVal - OpWidth);
1329  }
1330  }
1331  }
1332 
1333  APInt LHSUndefElts(OpWidth, 0);
1334  simplifyAndSetOp(I, 0, LeftDemanded, LHSUndefElts);
1335 
1336  APInt RHSUndefElts(OpWidth, 0);
1337  simplifyAndSetOp(I, 1, RightDemanded, RHSUndefElts);
1338 
1339  // If this shuffle does not change the vector length and the elements
1340  // demanded by this shuffle are an identity mask, then this shuffle is
1341  // unnecessary.
1342  //
1343  // We are assuming canonical form for the mask, so the source vector is
1344  // operand 0 and operand 1 is not used.
1345  //
1346  // Note that if an element is demanded and this shuffle mask is undefined
1347  // for that element, then the shuffle is not considered an identity
1348  // operation. The shuffle prevents poison from the operand vector from
1349  // leaking to the result by replacing poison with an undefined value.
1350  if (VWidth == OpWidth) {
1351  bool IsIdentityShuffle = true;
1352  for (unsigned i = 0; i < VWidth; i++) {
1353  unsigned MaskVal = Shuffle->getMaskValue(i);
1354  if (DemandedElts[i] && i != MaskVal) {
1355  IsIdentityShuffle = false;
1356  break;
1357  }
1358  }
1359  if (IsIdentityShuffle)
1360  return Shuffle->getOperand(0);
1361  }
1362 
1363  bool NewUndefElts = false;
1364  unsigned LHSIdx = -1u, LHSValIdx = -1u;
1365  unsigned RHSIdx = -1u, RHSValIdx = -1u;
1366  bool LHSUniform = true;
1367  bool RHSUniform = true;
1368  for (unsigned i = 0; i < VWidth; i++) {
1369  unsigned MaskVal = Shuffle->getMaskValue(i);
1370  if (MaskVal == -1u) {
1371  UndefElts.setBit(i);
1372  } else if (!DemandedElts[i]) {
1373  NewUndefElts = true;
1374  UndefElts.setBit(i);
1375  } else if (MaskVal < OpWidth) {
1376  if (LHSUndefElts[MaskVal]) {
1377  NewUndefElts = true;
1378  UndefElts.setBit(i);
1379  } else {
1380  LHSIdx = LHSIdx == -1u ? i : OpWidth;
1381  LHSValIdx = LHSValIdx == -1u ? MaskVal : OpWidth;
1382  LHSUniform = LHSUniform && (MaskVal == i);
1383  }
1384  } else {
1385  if (RHSUndefElts[MaskVal - OpWidth]) {
1386  NewUndefElts = true;
1387  UndefElts.setBit(i);
1388  } else {
1389  RHSIdx = RHSIdx == -1u ? i : OpWidth;
1390  RHSValIdx = RHSValIdx == -1u ? MaskVal - OpWidth : OpWidth;
1391  RHSUniform = RHSUniform && (MaskVal - OpWidth == i);
1392  }
1393  }
1394  }
1395 
1396  // Try to transform shuffle with constant vector and single element from
1397  // this constant vector to single insertelement instruction.
1398  // shufflevector V, C, <v1, v2, .., ci, .., vm> ->
1399  // insertelement V, C[ci], ci-n
1400  if (OpWidth ==
1401  cast<FixedVectorType>(Shuffle->getType())->getNumElements()) {
1402  Value *Op = nullptr;
1403  Constant *Value = nullptr;
1404  unsigned Idx = -1u;
1405 
1406  // Find constant vector with the single element in shuffle (LHS or RHS).
1407  if (LHSIdx < OpWidth && RHSUniform) {
1408  if (auto *CV = dyn_cast<ConstantVector>(Shuffle->getOperand(0))) {
1409  Op = Shuffle->getOperand(1);
1410  Value = CV->getOperand(LHSValIdx);
1411  Idx = LHSIdx;
1412  }
1413  }
1414  if (RHSIdx < OpWidth && LHSUniform) {
1415  if (auto *CV = dyn_cast<ConstantVector>(Shuffle->getOperand(1))) {
1416  Op = Shuffle->getOperand(0);
1417  Value = CV->getOperand(RHSValIdx);
1418  Idx = RHSIdx;
1419  }
1420  }
1421  // Found constant vector with single element - convert to insertelement.
1422  if (Op && Value) {
1424  Op, Value, ConstantInt::get(Type::getInt32Ty(I->getContext()), Idx),
1425  Shuffle->getName());
1426  InsertNewInstWith(New, *Shuffle);
1427  return New;
1428  }
1429  }
1430  if (NewUndefElts) {
1431  // Add additional discovered undefs.
1432  SmallVector<int, 16> Elts;
1433  for (unsigned i = 0; i < VWidth; ++i) {
1434  if (UndefElts[i])
1435  Elts.push_back(UndefMaskElem);
1436  else
1437  Elts.push_back(Shuffle->getMaskValue(i));
1438  }
1439  Shuffle->setShuffleMask(Elts);
1440  MadeChange = true;
1441  }
1442  break;
1443  }
1444  case Instruction::Select: {
1445  // If this is a vector select, try to transform the select condition based
1446  // on the current demanded elements.
1447  SelectInst *Sel = cast<SelectInst>(I);
1448  if (Sel->getCondition()->getType()->isVectorTy()) {
1449  // TODO: We are not doing anything with UndefElts based on this call.
1450  // It is overwritten below based on the other select operands. If an
1451  // element of the select condition is known undef, then we are free to
1452  // choose the output value from either arm of the select. If we know that
1453  // one of those values is undef, then the output can be undef.
1454  simplifyAndSetOp(I, 0, DemandedElts, UndefElts);
1455  }
1456 
1457  // Next, see if we can transform the arms of the select.
1458  APInt DemandedLHS(DemandedElts), DemandedRHS(DemandedElts);
1459  if (auto *CV = dyn_cast<ConstantVector>(Sel->getCondition())) {
1460  for (unsigned i = 0; i < VWidth; i++) {
1461  // isNullValue() always returns false when called on a ConstantExpr.
1462  // Skip constant expressions to avoid propagating incorrect information.
1463  Constant *CElt = CV->getAggregateElement(i);
1464  if (isa<ConstantExpr>(CElt))
1465  continue;
1466  // TODO: If a select condition element is undef, we can demand from
1467  // either side. If one side is known undef, choosing that side would
1468  // propagate undef.
1469  if (CElt->isNullValue())
1470  DemandedLHS.clearBit(i);
1471  else
1472  DemandedRHS.clearBit(i);
1473  }
1474  }
1475 
1476  simplifyAndSetOp(I, 1, DemandedLHS, UndefElts2);
1477  simplifyAndSetOp(I, 2, DemandedRHS, UndefElts3);
1478 
1479  // Output elements are undefined if the element from each arm is undefined.
1480  // TODO: This can be improved. See comment in select condition handling.
1481  UndefElts = UndefElts2 & UndefElts3;
1482  break;
1483  }
1484  case Instruction::BitCast: {
1485  // Vector->vector casts only.
1486  VectorType *VTy = dyn_cast<VectorType>(I->getOperand(0)->getType());
1487  if (!VTy) break;
1488  unsigned InVWidth = cast<FixedVectorType>(VTy)->getNumElements();
1489  APInt InputDemandedElts(InVWidth, 0);
1490  UndefElts2 = APInt(InVWidth, 0);
1491  unsigned Ratio;
1492 
1493  if (VWidth == InVWidth) {
1494  // If we are converting from <4 x i32> -> <4 x f32>, we demand the same
1495  // elements as are demanded of us.
1496  Ratio = 1;
1497  InputDemandedElts = DemandedElts;
1498  } else if ((VWidth % InVWidth) == 0) {
1499  // If the number of elements in the output is a multiple of the number of
1500  // elements in the input then an input element is live if any of the
1501  // corresponding output elements are live.
1502  Ratio = VWidth / InVWidth;
1503  for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1504  if (DemandedElts[OutIdx])
1505  InputDemandedElts.setBit(OutIdx / Ratio);
1506  } else if ((InVWidth % VWidth) == 0) {
1507  // If the number of elements in the input is a multiple of the number of
1508  // elements in the output then an input element is live if the
1509  // corresponding output element is live.
1510  Ratio = InVWidth / VWidth;
1511  for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
1512  if (DemandedElts[InIdx / Ratio])
1513  InputDemandedElts.setBit(InIdx);
1514  } else {
1515  // Unsupported so far.
1516  break;
1517  }
1518 
1519  simplifyAndSetOp(I, 0, InputDemandedElts, UndefElts2);
1520 
1521  if (VWidth == InVWidth) {
1522  UndefElts = UndefElts2;
1523  } else if ((VWidth % InVWidth) == 0) {
1524  // If the number of elements in the output is a multiple of the number of
1525  // elements in the input then an output element is undef if the
1526  // corresponding input element is undef.
1527  for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1528  if (UndefElts2[OutIdx / Ratio])
1529  UndefElts.setBit(OutIdx);
1530  } else if ((InVWidth % VWidth) == 0) {
1531  // If the number of elements in the input is a multiple of the number of
1532  // elements in the output then an output element is undef if all of the
1533  // corresponding input elements are undef.
1534  for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
1535  APInt SubUndef = UndefElts2.lshr(OutIdx * Ratio).zextOrTrunc(Ratio);
1536  if (SubUndef.countPopulation() == Ratio)
1537  UndefElts.setBit(OutIdx);
1538  }
1539  } else {
1540  llvm_unreachable("Unimp");
1541  }
1542  break;
1543  }
1544  case Instruction::FPTrunc:
1545  case Instruction::FPExt:
1546  simplifyAndSetOp(I, 0, DemandedElts, UndefElts);
1547  break;
1548 
1549  case Instruction::Call: {
1550  IntrinsicInst *II = dyn_cast<IntrinsicInst>(I);
1551  if (!II) break;
1552  switch (II->getIntrinsicID()) {
1553  case Intrinsic::masked_gather: // fallthrough
1554  case Intrinsic::masked_load: {
1555  // Subtlety: If we load from a pointer, the pointer must be valid
1556  // regardless of whether the element is demanded. Doing otherwise risks
1557  // segfaults which didn't exist in the original program.
1558  APInt DemandedPtrs(APInt::getAllOnes(VWidth)),
1559  DemandedPassThrough(DemandedElts);
1560  if (auto *CV = dyn_cast<ConstantVector>(II->getOperand(2)))
1561  for (unsigned i = 0; i < VWidth; i++) {
1562  Constant *CElt = CV->getAggregateElement(i);
1563  if (CElt->isNullValue())
1564  DemandedPtrs.clearBit(i);
1565  else if (CElt->isAllOnesValue())
1566  DemandedPassThrough.clearBit(i);
1567  }
1568  if (II->getIntrinsicID() == Intrinsic::masked_gather)
1569  simplifyAndSetOp(II, 0, DemandedPtrs, UndefElts2);
1570  simplifyAndSetOp(II, 3, DemandedPassThrough, UndefElts3);
1571 
1572  // Output elements are undefined if the element from both sources are.
1573  // TODO: can strengthen via mask as well.
1574  UndefElts = UndefElts2 & UndefElts3;
1575  break;
1576  }
1577  default: {
1578  // Handle target specific intrinsics
1579  Optional<Value *> V = targetSimplifyDemandedVectorEltsIntrinsic(
1580  *II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
1581  simplifyAndSetOp);
1582  if (V.hasValue())
1583  return V.getValue();
1584  break;
1585  }
1586  } // switch on IntrinsicID
1587  break;
1588  } // case Call
1589  } // switch on Opcode
1590 
1591  // TODO: We bail completely on integer div/rem and shifts because they have
1592  // UB/poison potential, but that should be refined.
1593  BinaryOperator *BO;
1594  if (match(I, m_BinOp(BO)) && !BO->isIntDivRem() && !BO->isShift()) {
1595  simplifyAndSetOp(I, 0, DemandedElts, UndefElts);
1596  simplifyAndSetOp(I, 1, DemandedElts, UndefElts2);
1597 
1598  // Output elements are undefined if both are undefined. Consider things
1599  // like undef & 0. The result is known zero, not undef.
1600  UndefElts &= UndefElts2;
1601  }
1602 
1603  // If we've proven all of the lanes undef, return an undef value.
1604  // TODO: Intersect w/demanded lanes
1605  if (UndefElts.isAllOnes())
1606  return UndefValue::get(I->getType());;
1607 
1608  return MadeChange ? I : nullptr;
1609 }
i
i
Definition: README.txt:29
llvm::APInt::setAllBits
void setAllBits()
Set every bit to 1.
Definition: APInt.h:1270
llvm::Constant::isAllOnesValue
bool isAllOnesValue() const
Return true if this is the value that would be returned by getAllOnesValue.
Definition: Constants.cpp:91
llvm::APInt::clearAllBits
void clearAllBits()
Set every bit to 0.
Definition: APInt.h:1348
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
llvm::RecurKind::Or
@ Or
Bitwise or logical OR of integers.
llvm::Value::hasOneUse
bool hasOneUse() const
Return true if there is exactly one use of this value.
Definition: Value.h:434
InstCombiner.h
llvm::Intrinsic::getDeclaration
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
Definition: Function.cpp:1399
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:721
llvm::KnownBits::resetAll
void resetAll()
Resets the known state of all bits.
Definition: KnownBits.h:66
IntrinsicInst.h
llvm::Function
Definition: Function.h:62
llvm::IntrinsicInst::getIntrinsicID
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:52
llvm::SelectPatternResult::Flavor
SelectPatternFlavor Flavor
Definition: ValueTracking.h:700
llvm::PatternMatch::m_LShr
BinaryOp_match< LHS, RHS, Instruction::LShr > m_LShr(const LHS &L, const RHS &R)
Definition: PatternMatch.h:1127
llvm::KnownBits::Zero
APInt Zero
Definition: KnownBits.h:24
llvm::ConstantInt::getValue
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:133
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1177
llvm::PatternMatch::m_Add
BinaryOp_match< LHS, RHS, Instruction::Add > m_Add(const LHS &L, const RHS &R)
Definition: PatternMatch.h:988
llvm::Use::get
Value * get() const
Definition: Use.h:67
llvm::APInt::zextOrTrunc
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
Definition: APInt.cpp:970
llvm::Instruction::hasNoUnsignedWrap
bool hasNoUnsignedWrap() const
Determine whether the no unsigned wrap flag is set.
Definition: Instruction.cpp:136
llvm::MaxAnalysisRecursionDepth
constexpr unsigned MaxAnalysisRecursionDepth
Definition: ValueTracking.h:47
llvm::APInt::isOne
bool isOne() const
Determine if this is a value of 1.
Definition: APInt.h:371
ValueTracking.h
llvm::InsertElementInst::Create
static InsertElementInst * Create(Value *Vec, Value *NewElt, Value *Idx, const Twine &NameStr="", Instruction *InsertBefore=nullptr)
Definition: Instructions.h:1954
llvm::Depth
@ Depth
Definition: SIMachineScheduler.h:36
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::APInt::getBitWidth
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1412
llvm::Instruction::isShift
bool isShift() const
Definition: Instruction.h:167
llvm::SPF_UMAX
@ SPF_UMAX
Signed maximum.
Definition: ValueTracking.h:681
llvm::Instruction::setHasNoUnsignedWrap
void setHasNoUnsignedWrap(bool b=true)
Set or clear the nuw flag on this instruction, which must be an operator which supports this flag.
Definition: Instruction.cpp:124
llvm::Optional
Definition: APInt.h:33
llvm::PatternMatch::m_BinOp
class_match< BinaryOperator > m_BinOp()
Match an arbitrary binary operation and ignore it.
Definition: PatternMatch.h:84
llvm::PatternMatch::m_AShr
BinaryOp_match< LHS, RHS, Instruction::AShr > m_AShr(const LHS &L, const RHS &R)
Definition: PatternMatch.h:1133
llvm::ComputeNumSignBits
unsigned ComputeNumSignBits(const Value *Op, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Return the number of times the sign bit of the register is replicated into the other bits.
Definition: ValueTracking.cpp:391
llvm::RegState::Undef
@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
llvm::APInt::intersects
bool intersects(const APInt &RHS) const
This operation tests if there are any pairs of corresponding bits between this APInt and RHS that are...
Definition: APInt.h:1182
llvm::InstCombinerImpl::SimplifyDemandedInstructionBits
bool SimplifyDemandedInstructionBits(Instruction &Inst)
Tries to simplify operands to an integer instruction based on its demanded bits.
Definition: InstCombineSimplifyDemanded.cpp:55
llvm::APInt::lshr
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:815
RHS
Value * RHS
Definition: X86PartialReduction.cpp:74
llvm::OverflowingBinaryOperator::hasNoUnsignedWrap
bool hasNoUnsignedWrap() const
Test whether this operation is known to never undergo unsigned overflow, aka the nuw property.
Definition: Operator.h:95
llvm::matchSelectPattern
SelectPatternResult matchSelectPattern(Value *V, Value *&LHS, Value *&RHS, Instruction::CastOps *CastOp=nullptr, unsigned Depth=0)
Pattern match integer [SU]MIN, [SU]MAX and ABS idioms, returning the kind and providing the out param...
Definition: ValueTracking.cpp:6115
llvm::gep_type_begin
gep_type_iterator gep_type_begin(const User *GEP)
Definition: GetElementPtrTypeIterator.h:123
llvm::PatternMatch::m_Not
BinaryOp_match< ValTy, cst_pred_ty< is_all_ones >, Instruction::Xor, true > m_Not(const ValTy &V)
Matches a 'Not' as 'xor V, -1' or 'xor -1, V'.
Definition: PatternMatch.h:2287
llvm::SelectPatternFlavor
SelectPatternFlavor
Specific patterns of select instructions we can match.
Definition: ValueTracking.h:676
llvm::InstCombinerImpl::SimplifyDemandedVectorElts
virtual Value * SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, APInt &UndefElts, unsigned Depth=0, bool AllowMultipleUsers=false) override
The specified value produces a vector with any number of elements.
Definition: InstCombineSimplifyDemanded.cpp:1120
llvm::Instruction::setIsExact
void setIsExact(bool b=true)
Set or clear the exact flag on this instruction, which must be an operator which supports this flag.
Definition: Instruction.cpp:132
llvm::Type::getInt32Ty
static IntegerType * getInt32Ty(LLVMContext &C)
Definition: Type.cpp:241
llvm::APIntOps::umin
const APInt & umin(const APInt &A, const APInt &B)
Determine the smaller of two APInts considered to be unsigned.
Definition: APInt.h:2133
llvm::APInt::countPopulation
unsigned countPopulation() const
Count the number of bits set.
Definition: APInt.h:1567
KnownBits.h
llvm::gep_type_end
gep_type_iterator gep_type_end(const User *GEP)
Definition: GetElementPtrTypeIterator.h:130
llvm::UndefMaskElem
constexpr int UndefMaskElem
Definition: Instructions.h:2000
llvm::APInt::isSignMask
bool isSignMask() const
Check if the APInt's value is returned by getSignMask.
Definition: APInt.h:447
llvm::PatternMatch::m_OneUse
OneUse_match< T > m_OneUse(const T &SubPattern)
Definition: PatternMatch.h:67
llvm::Optional::hasValue
constexpr bool hasValue() const
Definition: Optional.h:289
llvm::APInt::setHighBits
void setHighBits(unsigned hiBits)
Set the top hiBits bits.
Definition: APInt.h:1343
llvm::PatternMatch::m_APInt
apint_match m_APInt(const APInt *&Res)
Match a ConstantInt or splatted ConstantVector, binding the specified pointer to the contained APInt.
Definition: PatternMatch.h:270
llvm::APInt::uge
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
Definition: APInt.h:1154
LHS
Value * LHS
Definition: X86PartialReduction.cpp:73
llvm::ConstantInt
This is the shared class of boolean and integer constants.
Definition: Constants.h:79
llvm::KnownBits::isNonNegative
bool isNonNegative() const
Returns true if this value is known to be non-negative.
Definition: KnownBits.h:99
llvm::Instruction::getOpcode
unsigned getOpcode() const
Returns a member of one of the enums like Instruction::Add.
Definition: Instruction.h:160
llvm::all_of
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1649
llvm::SPF_UNKNOWN
@ SPF_UNKNOWN
Definition: ValueTracking.h:677
llvm::SelectInst::getCondition
const Value * getCondition() const
Definition: Instructions.h:1788
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
llvm::APInt::setBit
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
Definition: APInt.h:1281
InstCombineInternal.h
llvm::ISD::CTLZ
@ CTLZ
Definition: ISDOpcodes.h:668
llvm::APInt::lshrInPlace
void lshrInPlace(unsigned ShiftAmt)
Logical right-shift this APInt by ShiftAmt in place.
Definition: APInt.h:822
llvm::PatternMatch::match
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
llvm::Constant::isNullValue
bool isNullValue() const
Return true if this is the value that would be returned by getNullValue.
Definition: Constants.cpp:74
llvm::APInt::isZero
bool isZero() const
Determine if this value is zero, i.e. all bits are clear.
Definition: APInt.h:359
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::Instruction::setHasNoSignedWrap
void setHasNoSignedWrap(bool b=true)
Set or clear the nsw flag on this instruction, which must be an operator which supports this flag.
Definition: Instruction.cpp:128
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::KnownBits::One
APInt One
Definition: KnownBits.h:25
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::CallInst::Create
static CallInst * Create(FunctionType *Ty, Value *F, const Twine &NameStr="", Instruction *InsertBefore=nullptr)
Definition: Instructions.h:1521
llvm::APInt::getAllOnes
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
Definition: APInt.h:214
llvm::KnownBits::hasConflict
bool hasConflict() const
Returns true if there is conflicting information.
Definition: KnownBits.h:47
llvm::APInt::getLimitedValue
uint64_t getLimitedValue(uint64_t Limit=UINT64_MAX) const
If this value is smaller than the specified limit, return it, otherwise return the limit value.
Definition: APInt.h:456
llvm::Type::isVectorTy
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:226
llvm::APInt::setLowBits
void setLowBits(unsigned loBits)
Set the bottom loBits bits.
Definition: APInt.h:1340
llvm::PatternMatch::m_ZExt
CastClass_match< OpTy, Instruction::ZExt > m_ZExt(const OpTy &Op)
Matches ZExt.
Definition: PatternMatch.h:1639
llvm::PatternMatch::m_c_Add
BinaryOp_match< LHS, RHS, Instruction::Add, true > m_c_Add(const LHS &L, const RHS &R)
Matches a Add with LHS and RHS in either order.
Definition: PatternMatch.h:2235
llvm::ShlOperator
Definition: Operator.h:454
llvm::Constant::getAllOnesValue
static Constant * getAllOnesValue(Type *Ty)
Definition: Constants.cpp:405
llvm::PatternMatch::m_ConstantInt
class_match< ConstantInt > m_ConstantInt()
Match an arbitrary ConstantInt and ignore it.
Definition: PatternMatch.h:145
llvm::Instruction
Definition: Instruction.h:45
llvm::Type::getScalarSizeInBits
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
Definition: Type.cpp:191
llvm::APInt::isAllOnes
bool isAllOnes() const
Determine if all bits are set. This is true for zero-width values.
Definition: APInt.h:347
llvm::APInt::getZExtValue
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1467
llvm::APInt::getHighBitsSet
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Constructs an APInt value that has the top hiBitsSet bits set.
Definition: APInt.h:279
llvm::UndefValue::get
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
Definition: Constants.cpp:1782
llvm::ConstantInt::get
static Constant * get(Type *Ty, uint64_t V, bool IsSigned=false)
If Ty is a vector type, return a Constant with a splat of the given value.
Definition: Constants.cpp:932
llvm::KnownBits::sext
KnownBits sext(unsigned BitWidth) const
Return known bits for a sign extension of the value we're tracking.
Definition: KnownBits.h:171
PatternMatch.h
llvm::APInt::countTrailingZeros
unsigned countTrailingZeros() const
Count the number of trailing zero bits.
Definition: APInt.h:1539
llvm::MCID::Call
@ Call
Definition: MCInstrDesc.h:153
llvm::Instruction::isIntDivRem
bool isIntDivRem() const
Definition: Instruction.h:166
llvm::APInt::setSignBit
void setSignBit()
Set the sign bit to 1.
Definition: APInt.h:1291
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::PatternMatch::m_ExtractElt
TwoOps_match< Val_t, Idx_t, Instruction::ExtractElement > m_ExtractElt(const Val_t &Val, const Idx_t &Idx)
Matches ExtractElementInst.
Definition: PatternMatch.h:1502
llvm::APInt::ashr
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
Definition: APInt.h:791
llvm::APInt::isSubsetOf
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
Definition: APInt.h:1190
llvm::PatternMatch::m_Shr
BinOpPred_match< LHS, RHS, is_right_shift_op > m_Shr(const LHS &L, const RHS &R)
Matches logical shift operations.
Definition: PatternMatch.h:1313
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
ShrinkDemandedConstant
static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo, const APInt &Demanded)
Check to see if the specified operand of the specified instruction is a constant integer.
Definition: InstCombineSimplifyDemanded.cpp:30
uint64_t
llvm::InstCombinerImpl::SimplifyMultipleUseDemandedBits
Value * SimplifyMultipleUseDemandedBits(Instruction *I, const APInt &DemandedMask, KnownBits &Known, unsigned Depth, Instruction *CxtI)
Helper routine of SimplifyDemandedUseBits.
Definition: InstCombineSimplifyDemanded.cpp:899
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::GetElementPtrInst
an instruction for type-safe pointer arithmetic to access elements of arrays and structs
Definition: Instructions.h:933
llvm::computeKnownBits
void computeKnownBits(const Value *V, KnownBits &Known, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, OptimizationRemarkEmitter *ORE=nullptr, bool UseInstrInfo=true)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
Definition: ValueTracking.cpp:224
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::KnownBits::countMinLeadingZeros
unsigned countMinLeadingZeros() const
Returns the minimum number of leading zero bits.
Definition: KnownBits.h:236
llvm::SelectInst
This class represents the LLVM 'select' instruction.
Definition: Instructions.h:1741
RA
SI optimize exec mask operations pre RA
Definition: SIOptimizeExecMaskingPreRA.cpp:71
llvm::KnownBits::computeForAddSub
static KnownBits computeForAddSub(bool Add, bool NSW, const KnownBits &LHS, KnownBits RHS)
Compute known bits resulting from adding LHS and RHS.
Definition: KnownBits.cpp:57
llvm::APInt::urem
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
Definition: APInt.cpp:1658
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:650
llvm::PatternMatch::m_Value
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:76
llvm::ZExtInst
This class represents zero extension of integer types.
Definition: Instructions.h:4812
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::PatternMatch::m_SExt
CastClass_match< OpTy, Instruction::SExt > m_SExt(const OpTy &Op)
Matches SExt.
Definition: PatternMatch.h:1633
llvm::PatternMatch::m_SpecificInt
specific_intval< false > m_SpecificInt(APInt V)
Match a specific integer value or vector with all elements equal to the value.
Definition: PatternMatch.h:863
llvm::BinaryOperator
Definition: InstrTypes.h:190
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::PatternMatch::m_Undef
auto m_Undef()
Match an arbitrary undef constant.
Definition: PatternMatch.h:136
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::Constant::getAggregateElement
Constant * getAggregateElement(unsigned Elt) const
For aggregates (struct/array/vector) return the constant that corresponds to the specified element if...
Definition: Constants.cpp:420
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
uint32_t
llvm::IRBuilderBase::InsertPointGuard
Definition: IRBuilder.h:367
llvm::ConstantInt::isMinusOne
bool isMinusOne() const
This function will return true iff every bit in this constant is set to true.
Definition: Constants.h:206
llvm::ConstantVector::get
static Constant * get(ArrayRef< Constant * > V)
Definition: Constants.cpp:1402
llvm::CastInst
This is the base class for all instructions that perform data casts.
Definition: InstrTypes.h:431
llvm::APInt::ult
bool ult(const APInt &RHS) const
Unsigned less than comparison.
Definition: APInt.h:1044
LLVM_FALLTHROUGH
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:290
llvm::Value::getName
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:309
llvm::APInt::clearBit
void clearBit(unsigned BitPosition)
Set a given bit to 0.
Definition: APInt.h:1358
llvm::ConstantInt::getZExtValue
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:142
llvm::MCID::Select
@ Select
Definition: MCInstrDesc.h:162
llvm::KnownBits::zextOrTrunc
KnownBits zextOrTrunc(unsigned BitWidth) const
Return known bits for a zero extension or truncation of the value we're tracking.
Definition: KnownBits.h:187
llvm::APIntOps::umax
const APInt & umax(const APInt &A, const APInt &B)
Determine the larger of two APInts considered to be unsigned.
Definition: APInt.h:2138
llvm::APInt::countLeadingZeros
unsigned countLeadingZeros() const
The APInt version of the countLeadingZeros functions in MathExtras.h.
Definition: APInt.h:1500
llvm::InstCombinerImpl::SimplifyDemandedBits
bool SimplifyDemandedBits(Instruction *I, unsigned Op, const APInt &DemandedMask, KnownBits &Known, unsigned Depth=0) override
This form of SimplifyDemandedBits simplifies the specified instruction operand if possible,...
Definition: InstCombineSimplifyDemanded.cpp:71
llvm::APInt::trunc
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:883
llvm::KnownBits
Definition: KnownBits.h:23
llvm::OverflowingBinaryOperator::hasNoSignedWrap
bool hasNoSignedWrap() const
Test whether this operation is known to never undergo signed overflow, aka the nsw property.
Definition: Operator.h:101
llvm::InstCombinerImpl::SimplifyDemandedUseBits
Value * SimplifyDemandedUseBits(Value *V, APInt DemandedMask, KnownBits &Known, unsigned Depth, Instruction *CxtI)
Attempts to replace V with a simpler value based on the demanded bits.
Definition: InstCombineSimplifyDemanded.cpp:108
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::Type::isIntOrIntVectorTy
bool isIntOrIntVectorTy() const
Return true if this is an integer type or a vector of integer types.
Definition: Type.h:196
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::salvageDebugInfo
void salvageDebugInfo(Instruction &I)
Assuming the instruction I is going to be deleted, attempt to salvage debug users of I by writing the...
Definition: Local.cpp:1745
llvm::MCID::Add
@ Add
Definition: MCInstrDesc.h:183
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:45
llvm::APInt::abs
APInt abs() const
Get the absolute value.
Definition: APInt.h:1682
llvm::APInt::getSignMask
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
Definition: APInt.h:209
llvm::Constant::getIntegerValue
static Constant * getIntegerValue(Type *Ty, const APInt &V)
Return the value for an integer or pointer constant, or a vector thereof, with the given scalar value...
Definition: Constants.cpp:388
llvm::PatternMatch::m_ICmp
CmpClass_match< LHS, RHS, ICmpInst, ICmpInst::Predicate > m_ICmp(ICmpInst::Predicate &Pred, const LHS &L, const RHS &R)
Definition: PatternMatch.h:1404
llvm::Instruction::hasNoSignedWrap
bool hasNoSignedWrap() const
Determine whether the no signed wrap flag is set.
Definition: Instruction.cpp:140
llvm::APInt::isSignBitSet
bool isSignBitSet() const
Determine if sign bit of this APInt is set.
Definition: APInt.h:324
llvm::SPF_UMIN
@ SPF_UMIN
Signed minimum.
Definition: ValueTracking.h:679
llvm::KnownBits::commonBits
static KnownBits commonBits(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits common to LHS and RHS.
Definition: KnownBits.h:308
llvm::APInt::getActiveBits
unsigned getActiveBits() const
Compute the number of active bits in the value.
Definition: APInt.h:1436
llvm::InstCombinerImpl::simplifyShrShlDemandedBits
Value * simplifyShrShlDemandedBits(Instruction *Shr, const APInt &ShrOp1, Instruction *Shl, const APInt &ShlOp1, const APInt &DemandedMask, KnownBits &Known)
Helper routine of SimplifyDemandedUseBits.
Definition: InstCombineSimplifyDemanded.cpp:1045
TargetTransformInfo.h
llvm::PatternMatch
Definition: PatternMatch.h:47
llvm::APInt::getLowBitsSet
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
Definition: APInt.h:289
GEP
Hexagon Common GEP
Definition: HexagonCommonGEP.cpp:172
llvm::KnownBits::getBitWidth
unsigned getBitWidth() const
Get the bit width of this value.
Definition: KnownBits.h:40
llvm::Value::takeName
void takeName(Value *V)
Transfer the name from V to this value.
Definition: Value.cpp:382
llvm::APInt::shl
APInt shl(unsigned shiftAmt) const
Left-shift function.
Definition: APInt.h:837
llvm::User::getOperand
Value * getOperand(unsigned i) const
Definition: User.h:169
llvm::abs
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Definition: APFloat.h:1282
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::PatternMatch::m_Shl
BinaryOp_match< LHS, RHS, Instruction::Shl > m_Shl(const LHS &L, const RHS &R)
Definition: PatternMatch.h:1121
llvm::KnownBits::makeNonNegative
void makeNonNegative()
Make this value non-negative.
Definition: KnownBits.h:115
llvm::Optional::getValue
constexpr const T & getValue() const LLVM_LVALUE_FUNCTION
Definition: Optional.h:283
llvm::RecurKind::Xor
@ Xor
Bitwise or logical XOR of integers.
llvm::Use
A Use represents the edge between a Value definition and its users.
Definition: Use.h:44
llvm::PoisonValue::get
static PoisonValue * get(Type *T)
Static factory methods - Return an 'poison' object of the specified type.
Definition: Constants.cpp:1801